Circuit board, light-emitting base plate, backlight module and display device

Abstract

A circuit board comprises a substrate, a first electrically conductive layer, a first insulation layer and a second electrically conductive layer. The first electrically conductive layer is arranged on one side of the substrate. The first electrically conductive layer comprises a plurality of signal lines and a plurality of first electrically conductive portions. The first insulation layer is provided with a first via hole penetrating the first insulation layer. The second electrically conductive layer comprises a plurality of second electrically conductive portions; the second electrically conductive portions are in electric contact with the first electrically conductive portions by means of the first via hole; and each second electrically conductive portion comprises a bonding pad, which is the part of the second electrically conductive portion that is exposed from the first via hole in the first insulation layer. The first electrically conductive layer and the second electrically conductive layer each comprise at least one main electrically conductive layer; the main electrically conductive layer and solder can form a first intermetallic compound; at least one of the first electrically conductive layer and the second electrically conductive layer further comprises a stop layer; the stop layer is arranged between two adjacent main electrically conductive layers, and the stop layer and the solder can form a second intermetallic compound; and the rate of reaction between the stop layer and the solder is less than the rate of reaction between the main electrically conductive layer and the solder.

Description

Circuit board, light-emitting substrate, backlight module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a circuit board, a light-emitting substrate, a backlight module, and a display device. Background Art

[0002] With the development of light-emitting diode (LED) technology, backlight sources using submillimeter (micro) or even micron-scale light-emitting diodes (LEDs) have become widely used. This not only allows products using these backlights, such as liquid crystal displays (LCDs), to achieve contrast levels comparable to those of organic light-emitting diode (OLED) displays, but also allows these products to retain the technical advantages of LCDs, thereby improving display quality and providing users with a superior visual experience.

[0003] Summary of the Invention

[0004] In one aspect, a circuit board is provided, comprising a substrate, a first conductive layer, a first insulating layer, and a second conductive layer.

[0005] The first conductive layer is disposed on one side of the substrate. The first conductive layer includes multiple signal lines and multiple first conductive portions. The first insulating layer is disposed on a side of the first conductive layer away from the substrate; the first insulating layer is provided with a first via extending through the first insulating layer. The second conductive layer is disposed on a side of the first insulating layer away from the substrate; the second conductive layer includes multiple second conductive portions; the second conductive portions are in electrical contact with the first conductive portions through the first vias, and the second conductive portions include pads, which are portions of the second conductive portions exposed by the first vias in the first insulating layer.

[0006] Among them, the first conductive layer and the second conductive layer each include at least one main conductive layer, and the main conductive layer can form a first intermetallic compound with the solder; at least one of the first conductive layer and the second conductive layer also includes a stop layer, which is arranged between two adjacent main conductive layers and can form a second intermetallic compound with the solder, and the reaction rate of the stop layer with the solder is lower than the reaction rate of the main conductive layer with the solder.

[0007] In some embodiments, the material of the stop layer includes any one of nickel, a copper alloy containing more than 40 atomic percent of copper, and a nickel alloy containing more than 40 atomic percent of nickel.

[0008] In some embodiments, the thickness of the stop layer is

[0009] In some embodiments, the circuit board further includes an anti-oxidation layer, which is disposed on a side of the second conductive layer away from the substrate, and the anti-oxidation layer can form a third intermetallic compound with the solder.

[0010] In some embodiments, the anti-oxidation layer covers the traces and the second conductive portion located in the second conductive layer.

[0011] In some embodiments, the material of the oxidation protection layer includes nickel or a nickel alloy with a nickel atomic percentage greater than 40%.

[0012] In some embodiments, the thickness of the anti-oxidation layer is

[0013] In some embodiments, the first conductive layer further includes an adhesive layer, the adhesive layer being disposed between the main conductive layer of the first conductive layer and the substrate, and the adhesive layer being incapable of reacting with the solder.

[0014] In some embodiments, the material of the adhesion layer includes any one of titanium, molybdenum, molybdenum-niobium alloy, molybdenum-titanium alloy, molybdenum-tungsten alloy, molybdenum-tantalum alloy, and molybdenum-niobium-titanium alloy.

[0015] In some embodiments, the thickness of the adhesive layer is

[0016] In some embodiments, the area of ​​the orthographic projection of the first conductive portion on the substrate is larger than the area of ​​the orthographic projection of the pad on the substrate, and the orthographic projection of the pad on the substrate is within the range of the orthographic projection of the first conductive portion on the substrate.

[0017] In some embodiments, the first conductive layer includes a main conductive layer and a stop layer, and the second conductive layer includes a main conductive layer and a stop layer; the two stop layers are located between the main conductive layer of the first conductive layer and the main conductive layer of the second conductive layer. Alternatively, the first conductive layer includes a main conductive layer, and the second conductive layer includes a main conductive layer and a stop layer; the stop layer is located between the main conductive layer of the first conductive layer and the main conductive layer of the second conductive layer. Alternatively, the first conductive layer includes a main conductive layer and a stop layer, and the second conductive layer includes a main conductive layer; the stop layer is located between the main conductive layer of the first conductive layer and the main conductive layer of the second conductive layer.

[0018] In some embodiments, the plurality of second conductive portions are divided into a plurality of device conductive portion groups and a plurality of chip conductive portion groups. The device conductive portion groups are configured to connect to light-emitting devices, and the chip conductive portion groups are configured to connect to microchips. The circuit board includes a plurality of drive units arranged in an array, each of the drive units including a plurality of device conductive portion groups. The circuit board also includes connecting wires, electrically connecting the plurality of device conductive portion groups within a single drive unit via the connecting wires; the connecting wires are located on the first conductive layer and / or the second conductive layer.

[0019] In some embodiments, the plurality of second conductive portions are divided into a plurality of device conductive portion groups and a plurality of chip conductive portion groups. The signal lines include a first signal line and a second signal line, the first signal line being electrically connected to the device conductive portion group; the second signal line being electrically connected to the chip conductive portion group. The first insulating layer further comprises a second via extending through the first insulating layer. The circuit board further comprises a plurality of device adapter wires and a plurality of chip adapter wires.

[0020] The plurality of device breakout wires are located in the second conductive layer; one end of each device breakout wire is electrically connected to the first signal line through the second via, and the other end is electrically connected to the second conductive portion of the device conductive portion group. The plurality of chip breakout wires are located in the second conductive layer; one end of each chip breakout wire is electrically connected to the second signal line through the second via, and the other end is electrically connected to the second conductive portion of the chip conductive portion group.

[0021] In some embodiments, the circuit board further includes a first passivation layer and a second passivation layer. The first passivation layer is disposed between the first conductive layer and the first insulating layer and exposes at least a portion of the first conductive portion. The second passivation layer is disposed between the first insulating layer and the second conductive layer and exposes at least a portion of the first conductive portion. Multiple pads electrically connected to the same electronic component are exposed by the same first via, such that the first insulating layer is not present in the region between the multiple pads electrically connected to the same electronic component.

[0022] In some embodiments, the circuit board further comprises a third passivation layer and a second insulating layer. The third passivation layer is disposed on a side of the second conductive layer away from the substrate and at least exposes the pads. The second insulating layer is disposed on a side of the third passivation layer away from the substrate and at least exposes the pads. The third passivation layer and / or the second insulating layer further expose an area between multiple pads electrically connected to the same electronic component, such that the third passivation layer and / or the second insulating layer are not present in the area between the multiple pads electrically connected to the same electronic component.

[0023] In another aspect, a light-emitting substrate is provided. The light-emitting substrate includes a circuit board and an electronic component, wherein the circuit board is the circuit board as described in any of the above embodiments. The pins of the electronic component are electrically connected to the pads on the circuit board via solder.

[0024] In some embodiments, the circuit board includes an anti-oxidation layer that covers the traces and the second conductive portion located on the second conductive layer. The light-emitting substrate further includes a reflective layer that is disposed on a side of the anti-oxidation layer away from the substrate and in contact with the anti-oxidation layer. The reflective layer has a plurality of openings, through which the pins of the electronic component are electrically connected to the solder and the pads.

[0025] In another aspect, a backlight module is provided. The backlight module includes a light-emitting substrate as described in any of the above embodiments and a plurality of optical films. The light-emitting substrate has a light-emitting side and a non-light-emitting side opposite to each other. The plurality of optical films are disposed on the light-emitting side of the light-emitting substrate.

[0026] In another aspect, a display device is provided, comprising the backlight module and a display panel as described above, wherein the display panel is disposed on a side of the plurality of optical films in the backlight module away from the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] FIG1 is a structural diagram of a display device according to some embodiments;

[0029] FIG2 is a cross-sectional view of a display device according to some embodiments;

[0030] FIG3 is a circuit diagram of a light emitting substrate according to some embodiments;

[0031] FIG4A is a top view of the light-emitting substrate shown in FIG3 ;

[0032] FIG4B is a structural diagram of a circuit board shown in FIG4A ;

[0033] FIG4C is a structural diagram of another circuit board shown in FIG4A ;

[0034] FIG4D is a structural diagram of another circuit board shown in FIG4A;

[0035] FIG5 is a partial enlarged view of point A in FIG4B ;

[0036] FIG6A is a cross-sectional view along section line XX′ in FIG4B ;

[0037] FIG6B is another cross-sectional view along section line YY′ in FIG4B ;

[0038] FIG7A is a cross-sectional view along section line AA′ in FIG5 ;

[0039] FIG7B is another cross-sectional view along section line AA′ in FIG5 ;

[0040] FIG8A is another cross-sectional view along section line BB′ in FIG5 ;

[0041] FIG8B is another cross-sectional view along section line BB′ in FIG5 ;

[0042] FIG9A is another cross-sectional view along section line BB′ in FIG5 ;

[0043] FIG9B is another cross-sectional view along section line BB′ in FIG5 ;

[0044] FIG10A is another cross-sectional view along section line BB′ in FIG5 ;

[0045] FIG10B is another cross-sectional view along section line BB′ in FIG5 ;

[0046] FIG. 11 is a cross-sectional view of a circuit board covered with a reflective layer according to some embodiments. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0054] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0055] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0058] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] In this article, compounds formed between metals or metals and metalloids (such as hydrogen, boron, nitrogen, sulfur, phosphorus, carbon, and silicon) are called intermetallic compounds (IMCs). The elements in an IMC are bound together by metallic bonds, maintaining metallic properties. IMCs are the product of interfacial reactions.

[0061] 1 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays images, whether in motion (eg, video) or stationary (eg, still images), and whether textual or graphic.

[0062] Exemplarily, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, or a virtual reality (VR) device.

[0063] In some embodiments, the display device 1000 may be a liquid crystal display device.

[0064] As shown in FIG. 2 , the display device 1000 may include a display panel 100 , a backlight module 200 and a glass cover 300 .

[0065] The display panel 100 includes a light-emitting side and a non-light-emitting side that are arranged opposite to each other. The light-emitting side refers to the side of the display panel 100 used for displaying images (the upper side of the display panel 100 in FIG2 ), and the non-light-emitting side refers to the side opposite the light-emitting side (the lower side of the display panel 100 in FIG2 ).

[0066] The backlight module 200 is disposed on the non-light-emitting side of the display panel 100 , and is used to provide light source for the display panel 100 .

[0067] The glass cover 300 is disposed on the light-emitting side of the display panel 100 and is used to protect the display panel 100. For example, the glass cover 300 can be made of rigid materials such as glass, quartz, and plastic, or flexible materials such as polymer resin.

[0068] In some examples, please continue to refer to FIG. 2 , the backlight module 200 may include a light-emitting substrate 210 and a plurality of optical films 220 .

[0069] The light-emitting substrate 210 has a light-emitting side and a non-light-emitting side relative to each other. The light-emitting side refers to the side of the light-emitting substrate 210 that provides a light source (the upper side of the light-emitting substrate 210 in Figure 2), and the non-light-emitting side refers to the other side opposite to the light-emitting side (the lower side of the light-emitting substrate 210 in Figure 2).

[0070] A plurality of optical films 220 are disposed on the light emitting side of the light emitting substrate 210 .

[0071] The light-emitting substrate 210 can directly emit white light, which is then homogenized by the multiple optical films 220 and then emitted toward the display panel 100. Alternatively, the light-emitting substrate 210 can also emit light of other colors (e.g., blue light), which is then color-converted and homogenized by the multiple optical films 220 and then emitted toward the display panel 100.

[0072] For example, referring to FIG. 2 , along a direction away from the light emitting substrate 210 , the plurality of optical films 220 include a diffuser plate 221 , a quantum dot film 222 , a diffuser 223 and a composite film 224 that are sequentially arranged.

[0073] The diffuser 221 blurs the light emitted by the light-emitting substrate 210 and provides support for the quantum dot film 222, diffuser 223, and composite film 224. The quantum dot film 222, when stimulated by light of a certain color emitted by the light-emitting substrate 210, converts that light into white light, thereby improving the utilization of the light energy of the light-emitting substrate 210. The diffuser 223 evens out the light passing through it. The composite film 224 improves the light extraction efficiency of the backlight module 200, thereby increasing the display brightness of the display device 1000.

[0074] It should be noted that the composite film 224 may include a brightness enhancement film (BEF) and a reflective polarized brightness enhancement film (DBEF), which utilizes the principles of total reflection, refraction, and polarization to increase the light flux within a certain angle range to improve the brightness of the display device 1000.

[0075] For example, the light-emitting substrate 210 emits blue light in a direction away from the light-emitting substrate 210. The quantum dot film 222 may include a red quantum dot material, a green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 210 passes through the red quantum dot material, it is converted into red light; when the blue light passes through the green quantum dot material, it is converted into green light; the blue light can directly pass through the transparent material; then, the blue light, red light, and green light are mixed and superimposed in a certain proportion to present white light. Finally, the diffuser 221 and the diffuser sheet 223 can mix the white light evenly to improve the light shadow produced by the light-emitting substrate 210 and improve the display quality of the display device 1000.

[0076] In some embodiments, referring to FIG. 2 , the light emitting substrate 210 includes a circuit board 10 , an electronic component 20 , and a reflective layer 30 .

[0077] As shown in FIG. 2 , the circuit board 10 includes a functional area 10A and a peripheral area 10B. The functional area 10A is configured to place electronic components 20 , and the peripheral area 10B is configured to bind circuit boards.

[0078] 2 , reflective layer 30 is disposed on circuit board 10 . Furthermore, the boundary of reflective layer 30 may coincide with the boundary of functional area 10A of circuit board 10 , meaning that reflective layer 30 may not be disposed in peripheral area 10B of circuit board 10 .

[0079] As shown in FIG2 , the reflective layer 30 is provided with a plurality of openings 301 . The pins of the electronic component 20 can be electrically connected to the solder and the pads on the circuit board 10 through the openings 301 , so as to be fixed to the circuit board 10 .

[0080] The reflectivity of the reflective layer 30 is greater than or equal to 90%. For example, the material of the reflective layer 30 may include white ink and / or silicone white glue. For example, the material of the reflective layer 30 may include resin (e.g., epoxy resin, polytetrafluoroethylene resin), titanium dioxide, and an organic solvent (e.g., dipropylene glycol methyl ether).

[0081] As shown in FIG. 2 , the electronic component 20 may include a light emitting device 21 and / or a microchip 22 .

[0082] As shown in FIG2 , the light emitting device 21 may include a Micro LED and a Mini LED. The size (e.g., length) of the Micro LED is less than 50 microns, for example, 10 to 50 microns. The size (e.g., length) of the Mini LED is 50 to 150 microns, for example, 80 to 120 microns.

[0083] As shown in FIG2 , the microchip 22 may include a sensor chip and a driver chip. The sensor chip may be, for example, a photosensor chip or a thermal sensor chip. The driver chip is used to provide a driving signal to the light-emitting device 21. The following uses the example of the microchip 22 including the driver chip to exemplify the embodiment of the present disclosure.

[0084] In the related art, during the repair process of the light-emitting substrate, it is necessary to remove the faulty electronic components. When removing the electronic components from the circuit board, the surface structure of the pads will most likely be damaged, resulting in the inability to weld and fix the pads of the circuit board to the electronic components again. The product's repairability and yield are low.

[0085] Based on this, as shown in FIG6A , some embodiments of the present disclosure provide a circuit board 10 , which includes a substrate 11 , a first conductive layer 12 , a first insulating layer 172 , and a second conductive layer 13 .

[0086] In some examples, the ratio of the thickness of the first conductive layer 12 to the second conductive layer 13 in a direction perpendicular to the plane of the substrate 11 is between 1:5 and 5:1. For example, the thickness of the first conductive layer 12 is the same as the thickness of the second conductive layer 13, or the thickness of the first conductive layer 12 is 0.2 times, 0.5 times, 0.7 times, 1.1 times, 1.2 times, 1.5 times, 2 times, 2.5 times, 3 times, 4.5 times, 5 times, etc., of the thickness of the second conductive layer 13, which is not limited in the present disclosure.

[0087] In some examples, the substrate 11 may be a flexible substrate, for example, the flexible substrate may be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0088] In other examples, the substrate 11 may be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0089] As shown in FIG6A , the first conductive layer 12 is disposed on one side of the substrate 11 , the first insulating layer 172 is disposed on the side of the first conductive layer 12 away from the substrate 11 , and the second conductive layer 13 is disposed on the side of the first insulating layer 172 away from the substrate 11 .

[0090] As shown in FIG. 5 and FIG. 6A , the first insulating layer 172 is provided with a first via hole H1 penetrating the first insulating layer 172 .

[0091] It should be noted that the material of the first insulating layer 172 includes a resin, such as epoxy resin. The thickness of the first insulating layer 172 is 2 μm to 10 μm. For example, the thickness of the first insulating layer 172 is any one of 2 μm, 3 μm, 4 μm, 5 μm, 7 μm, 8 μm, and 10 μm.

[0092] 3 , 4A , and 5 , first conductive layer 12 includes a plurality of signal lines 120 and a plurality of first conductive portions 151. Second conductive layer 13 includes a plurality of second conductive portions 152. Second conductive portions 152 are electrically connected to first conductive portions 151 through first vias H1. Second conductive portions 152 include pads P, which are portions of second conductive portions 152 exposed by first vias H1 in first insulating layer 172. Electronic component 20 is soldered to pads P to be secured to circuit board 10. The solder may comprise tin, for example.

[0093] It should be noted that the area of ​​the orthographic projection of the first conductive portion 151 on the substrate 11 may be the same as or different from the area of ​​the orthographic projection of the pad P on the substrate 11. For example, the area of ​​the orthographic projection of the first conductive portion 151 on the substrate 11 is larger than the area of ​​the orthographic projection of the pad P on the substrate 11, and the orthographic projection of the pad P on the substrate 11 is located within the orthographic projection of the first conductive portion 151 on the substrate 11, which is conducive to the flatness of the upper surface of the pad P.

[0094] It should be understood that the first conductive layer 12 can be formed by multiple deposition and photolithography processes, and the second conductive layer 13 can be formed by multiple deposition and photolithography processes, that is, the above-mentioned first conductive layer 12 and second conductive layer 13 can be a stacked structure formed by stacking multiple conductive material layers.

[0095] For example, referring to FIG6A , the first conductive layer 12 and the second conductive layer 13 each include at least one main conductive layer 141. The main conductive layer 141 can form a first intermetallic compound with the solder. For ease of distinction, the main conductive layer 141 in the first conductive layer 12 is hereinafter referred to as the first main conductive layer 121, and the main conductive layer 141 in the second conductive layer 13 is hereinafter referred to as the second main conductive layer 131.

[0096] 6A , the thickness of the first main conductive layer 121 is 0.6 μm to 4 μm. For example, the thickness of the first main conductive layer 121 is any one of 0.6 μm, 0.9 μm, 1.8 μm, 2.7 μm, 3.6 μm, and 4 μm.

[0097] 6A , the thickness of the second main conductive layer 131 is ~1.8μm. For example, the thickness of the second main conductive layer 131 is Any one of 1.2 μm, 1.5 μm and 1.8 μm.

[0098] It should be noted that the material of the main conductive layer 141 includes metal, for example, the material of the main conductive layer 141 includes copper or silver.

[0099] In addition, at least one of the first conductive layer 12 and the second conductive layer 13 further includes a stop layer 142, which is disposed between two adjacent main conductive layers 141. In this case, in the region where any pad P is located, there are at least two main conductive layers 141 and a stop layer 142 located between the two adjacent main conductive layers 141. For ease of distinction, the stop layer 142 in the first conductive layer 12 is hereinafter referred to as the first stop layer 122, and the stop layer 142 in the second conductive layer 13 is hereinafter referred to as the second stop layer 132.

[0100] 5 and 9A , the first conductive layer 12 includes a first main conductive layer 121 and a first stop layer 122, and the second conductive layer 13 includes a second main conductive layer 131. The first stop layer 122 is located between the first main conductive layer 121 and the second main conductive layer 131.

[0101] In this case, the first conductive portion 151 includes a first main conductive layer 121 and a first stop layer 122, and the second conductive portion 152 includes a second main conductive layer 131. That is, in the region where the pad P is located, there are two main conductive layers 141 and a stop layer 142 located between the two main conductive layers 141.

[0102] 5 and 9B , the first conductive layer 12 includes a first main conductive layer 121 , and the second conductive layer 13 includes a second main conductive layer 131 and a second stop layer 132 . The second stop layer 132 is located between the first main conductive layer 121 and the second main conductive layer 131 .

[0103] In this case, the first conductive portion 151 includes a first main conductive layer 121, and the second conductive portion 152 includes a second main conductive layer 131 and a second stop layer 132. That is, in the region where the pad P is located, there are two main conductive layers 141 and a stop layer 142 located between the two main conductive layers 141.

[0104] 5 and 8A , the first conductive layer 12 includes a first main conductive layer 121 and a first stop layer 122, and the second conductive layer 13 includes a second main conductive layer 131 and a second stop layer 132. The first stop layer 122 and the second stop layer 132 are both located between the first main conductive layer 121 and the second main conductive layer 131.

[0105] In this case, the first conductive portion 151 includes a first main conductive layer 121 and a first stop layer 122, and the second conductive portion 152 includes a second main conductive layer 131 and a second stop layer 132. That is, in the region where the pad P is located, there are two main conductive layers 141 and two stop layers 142 located between the two main conductive layers 141.

[0106] It should be noted that, in addition to the above embodiments, the first conductive layer 12 and the second conductive layer 13 may also include a multi-layer main conductive layer 141 and a multi-layer stop layer 142 , which can be specifically set according to actual conditions and are not listed one by one in the embodiments of the present disclosure.

[0107] The stop layer 142 can form a second intermetallic compound with the solder, and the reaction rate between the stop layer 142 and the solder is lower than the reaction rate between the main conductive layer 141 and the solder.

[0108] Here, the material of the stop layer 142 includes a single metal or an alloy. The single metal may include nickel. The alloy may include a copper alloy with a copper atomic percentage greater than 40% or a nickel alloy with a nickel atomic percentage greater than 40%. Exemplarily, the copper alloy may include a binary or ternary alloy of copper, such as any one of a nickel-copper alloy, a nickel-copper-aluminum alloy, a copper-magnesium-aluminum alloy, and a copper-titanium alloy. Exemplarily, the nickel alloy may include a binary or ternary alloy of nickel, such as any one of a nickel-aluminum alloy, a nickel-molybdenum alloy, a nickel-tungsten alloy, a nickel-titanium alloy, and a nickel-copper alloy.

[0109] In addition, when the material of the stop layer 142 includes a nickel alloy with a nickel atomic percentage greater than 40%, the content of nickel atoms in the stop layer 142 can be gradually reduced from the stop layer 142 to the substrate 11, so that the reaction rate of the stop layer 142 closer to the substrate 11 and the solder is lower than the reaction rate of the stop layer 142 farther away from the substrate 11 and the solder.

[0110] It should be noted that the thickness of the stop layer 142 is For example, the thickness of the stop layer 142 is and Any of .

[0111] In this case, when soldering the electronic component 20 to the pad P, the solder is first heated and melted. The metal atoms then diffuse and form a first intermetallic compound with metal atoms in the primary conductive layer 141, and a fourth intermetallic compound with metal atoms in the pins of the electronic component 20, thereby achieving soldering. By adjusting the thickness of the primary conductive layer 141, a reliable connection between the pins of the electronic component 20 and the pad P can be achieved.

[0112] It is understood that as the solder continues to diffuse, the metal atoms in the solder may further form a second intermetallic compound with the metal atoms in the stop layer 142. Since the reaction rate between the stop layer 142 and the solder is relatively slow, the stop layer 142 can slow down the diffusion rate of the solder, thereby making it easier to stop the diffusion of the solder at the stop layer 142.

[0113] In this way, when the electronic component 20 is removed during repair, at most the main conductive layer 141 and stop layer 142 that react with the electronic component 20's pins will be removed. On the side of the stop layer 142 near the substrate 11, at least one layer of the main conductive layer 141 remains unreacted with the solder. In other words, after the electronic component 20 is removed, the area where the solder pads P were removed can be re-soldered, thereby improving the repairability of the light-emitting substrate 210.

[0114] It should be noted that each main conductive layer 141 in the first conductive portion 151 and the second conductive portion 152 can be soldered once. That is, the sum of the main conductive layers 141 in the first conductive portion 151 and the second conductive portion 152 is equal to the total number of times the electronic component 20 can be repeatedly soldered. In other words, the number of main conductive layers 141 in the first conductive layer 12 and the second conductive layer 13 can be set, for example, based on the number of required repairs.

[0115] In some embodiments, as shown in Figures 5 and 7A, circuit board 10 further includes an anti-oxidation layer 143. Anti-oxidation layer 143 is disposed on a side of second conductive layer 13 away from substrate 11 to prevent oxidation of the traces on second conductive layer 13 and the exposed upper surface of second conductive portion 152. Furthermore, anti-oxidation layer 143 can form a third intermetallic compound with solder, allowing the solder to diffuse into main conductive layer 141 for soldering.

[0116] In some examples, as shown in Figures 6A, 7A, and 8A, the anti-oxidation layer 143 is located on the second conductive layer 13, away from the surface of the second conductive portion 152. That is, the anti-oxidation layer 143 covers the exposed upper surfaces of the second conductive layer 13 and the second conductive portion 152. In this way, the anti-oxidation layer 143 can be formed using the same mask as the second conductive layer 13 through a single etching process, simplifying the process.

[0117] It should be noted that the wiring located in the second conductive layer 13 may be specifically described below, and will not be elaborated herein in detail in the embodiment of the present disclosure.

[0118] In other exemplary embodiments, as shown in Figures 6B, 7B, and 8B, the anti-oxidation layer 143 covers the traces and the second conductive portion 152 located in the second conductive layer 13. That is, the anti-oxidation layer 143 covers the exposed top and side surfaces of the traces and pads P located in the second conductive layer 13. In this case, the anti-oxidation layer 143 covers the exposed top and side surfaces of the traces and pads P, completely covering the exposed surfaces of the traces and pads P.

[0119] Based on this, no other anti-oxidation insulating layers, such as passivation layers and resins, are required on circuit board 10. Specifically, referring to Figures 2, 5, and 6B, if circuit board 10 includes anti-oxidation layer 143, which covers the traces on second conductive layer 13 and second conductive portion 152, as shown in Figure 11, the reflective layer 30 can be disposed on a side of anti-oxidation layer 143 away from substrate 11, and in contact with anti-oxidation layer 143.

[0120] Setting it up in this way can simplify the process flow and reduce mass production costs; at the same time, it avoids the etching process in the process of forming the passivation layer and resin, which causes the surface roughness of the pad P to decrease, thereby adversely affecting the reaction between the solder and the pad P, and avoids the stress of the passivation layer and the resin causing the pad P to bulge and unable to form an effective weld.

[0121] The material of the anti-oxidation layer 143 may be the same as or different from that of the stop layer 142. When the material of the anti-oxidation layer 143 is the same as that of the stop layer 142, the second intermetallic compound is the same as the third intermetallic compound.

[0122] Exemplarily, the material of the anti-oxidation layer 143 includes nickel or a nickel alloy having a nickel atomic percentage greater than 40%. For example, the material of the anti-oxidation layer 143 includes a binary or ternary nickel alloy, such as any one of a nickel-aluminum alloy, a nickel-molybdenum alloy, a nickel-tungsten alloy, a nickel-titanium alloy, and a nickel-copper alloy.

[0123] It should be noted that the thickness of the anti-oxidation layer 143 is For example, the thickness of the anti-oxidation layer 143 is and Any of .

[0124] In some embodiments, as shown in FIG. 6A , the first conductive layer 12 further includes an adhesive layer 144 . The adhesive layer 144 is disposed between the main conductive layer 141 of the first conductive layer 12 and the substrate 11 to improve adhesion between the main conductive layer 141 and the substrate 11 .

[0125] Adhesion layer 144 is non-reactive with the solder, thereby preventing the solder from diffusing into substrate 11 and damaging it. Exemplarily, the material of adhesion layer 144 includes a single metal or a metal alloy. Exemplarily, the single metal includes titanium or molybdenum. For example, the metal alloy includes any one of a molybdenum-niobium alloy, a molybdenum-titanium alloy, a molybdenum-tungsten alloy, a molybdenum-tantalum alloy, and a molybdenum-niobium-titanium alloy.

[0126] It should be noted that the thickness of the adhesive layer 144 is For example, the thickness of the adhesive layer 144 is and Any of .

[0127] 3 and 4A , the electronic component 20 includes a light emitting device 21 and a microchip 22. The light emitting substrate 210 includes a plurality of driving units 110 arranged in an array, each driving unit 110 including a plurality of light emitting devices 21 connected in series and / or in parallel.

[0128] For example, as shown in FIG4A , each driving unit 110 includes four light-emitting devices 21 connected in series. Of course, each driving unit 110 may also include four, five, seven, or eight light-emitting devices 21, and the connection mode of the multiple light-emitting devices 21 in the driving unit 110 is not limited to series connection, but may also be parallel connection, but the embodiments of the present disclosure are not limited thereto.

[0129] Based on the above, as shown in Figures 4A, 4B and 5, the multiple second conductive parts 152 can form a multiple device conductive part groups 1520, and the device conductive part groups 1520 are configured to connect the light-emitting device 21, that is, the surface of the device conductive part group 1520 away from the substrate 11 is at least partially exposed to form a pad P so as to achieve reliable electrical connection with the pins of the light-emitting device 21 through solder.

[0130] As shown in FIG. 4B and FIG. 5 , the device conductive portion group 1520 includes an anode conductive portion 1521 and a cathode conductive portion 1522 .

[0131] On this basis, referring to Figures 4A, 4B, 5 and 6B, the above-mentioned circuit board 10 also includes a connecting line 161, and the multiple light-emitting devices 21 in the same driving unit 110 are electrically connected through the connecting line 161; that is, the multiple device conductive part groups 1520 in the same driving unit 110 are electrically connected through the connecting line 161.

[0132] 4B , 4C, 4D and 5 , one end of the connection line 161 is electrically connected to the cathode conductive portion 1522 of one device conductive portion group 1520 , and the other end is electrically connected to the anode conductive portion 1521 of another device conductive portion group 1520 .

[0133] The connecting line 161 is located in the first conductive layer 12 and / or the second conductive layer 13 .

[0134] For example, as shown in FIG4C , the connection line 161 is located in the first conductive layer 12. For another example, as shown in FIG4B , the connection line 161 is located in the second conductive layer 13. For another example, referring to FIG4D , the connection line 161 includes a first connection pattern and a second connection pattern stacked together, the first connection pattern being located in the first conductive layer 12 and the second connection pattern being located in the second conductive layer 13.

[0135] It should be noted that the area of ​​the first connection pattern can be the same as or different from the area of ​​the second connection pattern. For example, the area of ​​the first connection pattern is larger than the area of ​​the second connection pattern, and the orthographic projection of the second connection pattern on the substrate 11 is located within the orthographic projection of the first connection pattern on the substrate 11, which is conducive to flattening the upper surface of the connection line 161.

[0136] The microchip 22 may be a driver chip, for example, to drive the plurality of light-emitting devices 21 to emit light. Here, one microchip 22 may only drive the plurality of light-emitting devices 21 in one driver unit 110 to emit light, or one microchip 22 may drive the plurality of light-emitting devices 21 in a plurality of driver units 110 to emit light.

[0137] 3 and 4A , each of four driving units 110 is electrically connected to a microchip 22 , and the microchip 22 is electrically connected to the multiple light-emitting devices 21 in the four driving units 110 , respectively, to drive the multiple light-emitting devices 21 in the four driving units 110 to emit light.

[0138] Based on the above, as shown in Figures 4A and 4B, the plurality of second conductive portions 152 further include a plurality of chip conductive portion groups 1530. The chip conductive portion groups 1530 are configured to connect to the microchip 22. That is, the surface of the chip conductive portion groups 1530 away from the substrate 11 is at least partially exposed to form pads P, so as to achieve reliable electrical connection with the pins of the microchip 22 via solder.

[0139] As shown in FIG3 , FIG4A and FIG4B , the chip conductive portion group 1530 includes a data conductive portion DataP, a clock conductive portion CLKP, an address conductive portion Di_in, a relay conductive portion Di_out, a chip power conductive portion VCCP, a ground conductive portion GNDP and an output conductive portion OutP.

[0140] Among them, the number of data conductive parts DataP can be one; the number of clock conductive parts CLKP can be one; the number of address conductive parts Di_in can be one; the number of relay conductive parts Di_out can be one; the number of chip power conductive parts VCCP can be one; the number of ground conductive parts GNDP can be one; the number of output conductive parts OutP can be an even number, for example, the number of output conductive parts OutP is four.

[0141] 3 , 4A and 4B , the plurality of signal lines 120 may include, for example, a first signal line 1210 and a second signal line 1220 . The first signal line 1210 is electrically connected to the device conductive portion group 1520 ; the second signal line 1220 is electrically connected to the chip conductive portion group 1530 .

[0142] On this basis, referring to Figures 4A and 6A, first insulating layer 172 is further provided with a second via H2 extending through first insulating layer 172. Circuit board 10 further includes a plurality of device connection wires 133 and a plurality of chip connection wires 130. Device connection wires 133 are located on second conductive layer 13, and chip connection wires 130 are located on second conductive layer 13.

[0143] 3, 4B, 5, and 6A, one end of the device connection wire 133 electrically contacts the first signal line 1210 through the second via H2, and the other end electrically contacts the second conductive portion 152 of the device conductive portion group 1520. One end of the chip connection wire 130 electrically contacts the second signal line 1220 through the second via H2, and the other end electrically contacts the second conductive portion 152 of the chip conductive portion group 1530, thereby minimizing the footprint of circuit traces and preventing short circuits at intersections of circuit traces.

[0144] 3 , the first signal line 1210 may include a device power signal line 123 , and the second signal line 1220 may include a common voltage line 124 , a data signal line 125 , a clock signal line 126 , a feedback signal line 127 , an address signal line 128 and a chip power signal line 129 .

[0145] As shown in Figures 3, 4A, and 5, the device power signal line 123 is electrically connected to the anode conductive portion 1521 of the first light-emitting device 21 in the driving unit 110 via the device adapter 133. The common voltage line 124 is electrically connected to the ground conductive portion GNDP via the chip adapter 130. The data signal line 125 is electrically connected to the data conductive portion DataP via the chip adapter 130. The clock signal line 126 is electrically connected to the clock conductive portion CLKP via the chip adapter 130. The feedback signal line 127 is electrically connected to the relay conductive portion Di_out via the chip adapter 130. The address signal line 128 is electrically connected to the address conductive portion Di_in via the chip adapter 130. The chip power signal line 129 is electrically connected to the chip power conductive portion VCCP via the chip adapter 130.

[0146] In some embodiments, referring to Figures 4A, 4B, and 6A, the circuit board 10 further includes connecting adapter wires 134. Multiple connecting adapter wires 134 are located on the second conductive layer 13. One end of the connecting adapter wire 134 electrically contacts the second conductive portion 152 of the device conductive portion group 1520 (see Figure 5) through the second via H2, and the other end electrically contacts the second conductive portion 152 of the chip conductive portion group 1530 (see Figure 5) through the second via H2.

[0147] In some embodiments, referring to FIG. 10A , the circuit board 10 further includes a first passivation layer 171 and a second passivation layer 173 .

[0148] Here, the materials of the first passivation layer 171 and the second passivation layer 173 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the materials of the first passivation layer 171 and the second passivation layer 173 both include SiN. The thickness of the first passivation layer 171 and the second passivation layer 173 is For example, the thickness of the first passivation layer 171 and the second passivation layer 173 is and Any of .

[0149] 10A , the first passivation layer 171 is disposed between the first conductive layer 12 and the first insulating layer 172 , and the second passivation layer 173 is disposed between the first insulating layer 172 and the second conductive layer 13 .

[0150] On this basis, as shown in FIG. 10A , multiple pads P electrically connected to the same electronic component 20 are exposed by the same first via H1 , so that the first insulating layer 172 does not exist in the area between the multiple pads P electrically connected to the same electronic component 20 .

[0151] In this case, the number of film layers between the multiple pads P electrically connected to the same electronic component 20 is reduced, thereby reducing the height difference of the welding surfaces of the multiple pads P electrically connected to the same electronic component 20 and improving the flatness of the electronic component 20 after being fixed. For example, the flatness of the surface of the light-emitting side of the light-emitting device 21 is improved, and the light output is more uniform.

[0152] In some embodiments, referring to FIG. 10A , the circuit board 10 further includes a third passivation layer 174 and a second insulating layer 175 .

[0153] Here, the material of the third passivation layer 174 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the material of the third passivation layer 174 includes SiN. The thickness of the third passivation layer 174 is For example, the thickness of the third passivation layer 174 is and Any of .

[0154] The second insulating layer 175 may be made of a resin such as epoxy resin. The thickness of the second insulating layer 175 may be 2 μm to 10 μm. For example, the thickness of the second insulating layer 175 may be any one of 2 μm, 3 μm, 4 μm, 5 μm, 7 μm, 8 μm, and 10 μm.

[0155] 10A , the third passivation layer 174 is disposed on a side of the second conductive layer 13 away from the substrate 11 and at least exposes the pad P. The second insulating layer 175 is disposed on a side of the third passivation layer 174 away from the substrate 11 and at least exposes the pad P.

[0156] On this basis, the third passivation layer 174 and / or the second insulating layer 175 also exposes the area between multiple pads P electrically connected to the same electronic component 20, so that the third passivation layer 174 and / or the second insulating layer 175 does not exist in the area between multiple pads P electrically connected to the same electronic component 20.

[0157] 10B , the second insulating layer 175 further exposes regions between the plurality of pads P electrically connected to the same electronic component 20 , so that the second insulating layer 175 does not exist in the regions between the plurality of pads P electrically connected to the same electronic component 20 .

[0158] In some embodiments, as shown in FIG. 11 , the circuit board 10 further includes a marking layer 18 and a fourth passivation layer 19 .

[0159] Here, the material of the marking layer 18 includes metal. For example, the material of the marking layer 18 includes at least one of molybdenum, titanium, copper and niobium. The thickness of the marking layer 18 is For example, the thickness of the marking layer 18 is and Any of .

[0160] In addition, the material of the fourth passivation layer 19 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the material of the fourth passivation layer 19 includes SiN. The thickness of the fourth passivation layer 19 is For example, the thickness of the fourth passivation layer 19 is and Any of .

[0161] As shown in Figure 11, the marking layer 18 is disposed between the substrate 11 and the first conductive layer 12, and the fourth passivation layer 19 is disposed between the marking layer 18 and the first conductive layer 12. The marking layer 18 includes at least one alignment mark 181, so that alignment can be performed by capturing an image of the alignment mark 181 during the process.

[0162] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A circuit board comprising: substrate; A first conductive layer is provided on one side of the substrate; the first conductive layer includes a plurality of signal lines and a plurality of first conductive parts; a first insulating layer, disposed on a side of the first conductive layer away from the substrate; the first insulating layer is provided with a first via hole penetrating the first insulating layer; a second conductive layer disposed on a side of the first insulating layer away from the substrate; the second conductive layer comprising a plurality of second conductive portions; the second conductive portions being in electrical contact with the first conductive portions through the first vias, the second conductive portions comprising pads, the pads being portions of the second conductive portions exposed by the first vias of the first insulating layer; Among them, the first conductive layer and the second conductive layer each include at least one main conductive layer, and the main conductive layer can form a first intermetallic compound with the solder; at least one of the first conductive layer and the second conductive layer also includes a stop layer, which is arranged between two adjacent main conductive layers and can form a second intermetallic compound with the solder, and the reaction rate of the stop layer with the solder is lower than the reaction rate of the main conductive layer with the solder.

2. The circuit board according to claim 1, wherein The material of the stop layer includes any one of nickel, a copper alloy with a copper atomic percentage greater than 40%, and a nickel alloy with a nickel atomic percentage greater than 40%.

3. The circuit board according to claim 1 or 2, wherein: The thickness of the stop layer is 4 . The circuit board according to claim 1 , further comprising an anti-oxidation layer, wherein the anti-oxidation layer is disposed on a side of the second conductive layer away from the substrate, and the anti-oxidation layer can form a third intermetallic compound with the solder.

5. The circuit board according to claim 4, wherein: The anti-oxidation layer covers the wiring and the second conductive portion located on the second conductive layer.

6. The circuit board according to claim 4 or 5, wherein: The material of the anti-oxidation layer includes nickel or a nickel alloy with a nickel atomic percentage greater than 40%.

7. The circuit board according to any one of claims 4 to 6, wherein: The thickness of the anti-oxidation layer is 8. The circuit board according to any one of claims 1 to 7, wherein: The first conductive layer further includes an adhesive layer, which is disposed between the main conductive layer of the first conductive layer and the substrate, and the adhesive layer cannot react with the solder.

9. The circuit board according to claim 8, wherein: The material of the adhesive layer includes any one of titanium, molybdenum, molybdenum-niobium alloy, molybdenum-titanium alloy, molybdenum-tungsten alloy, molybdenum-tantalum alloy and molybdenum-niobium-titanium alloy.

10. The circuit board according to claim 8 or 9, wherein the thickness of the adhesive layer is 11. The circuit board according to any one of claims 1 to 10, wherein: The area of ​​the orthographic projection of the first conductive portion on the substrate is larger than the area of ​​the orthographic projection of the pad on the substrate, and the orthographic projection of the pad on the substrate is within the range of the orthographic projection of the first conductive portion on the substrate.

12. The circuit board according to any one of claims 1 to 11, wherein: The first conductive layer includes a main conductive layer and a stop layer, and the second conductive layer includes a main conductive layer and a stop layer; the two stop layers are located between the main conductive layer of the first conductive layer and the main conductive layer of the second conductive layer; Alternatively, the first conductive layer includes a main conductive layer, and the second conductive layer includes a main conductive layer and a stop layer; the stop layer is located between the main conductive layer of the first conductive layer and the main conductive layer of the second conductive layer; Alternatively, the first conductive layer includes a main conductive layer and a stop layer, and the second conductive layer includes a main conductive layer; the stop layer is located between the main conductive layer of the first conductive layer and the main conductive layer of the second conductive layer.

13. The circuit board according to any one of claims 1 to 12, wherein: The plurality of second conductive portions are divided into a plurality of device conductive portion groups and a plurality of chip conductive portion groups; the device conductive portion groups are configured to connect to light-emitting devices, and the chip conductive portion groups are configured to connect to microchips; The circuit board includes a plurality of drive units arranged in an array, each of the drive units includes a plurality of device conductive portion groups, and the circuit board further includes: A connecting line is used to electrically connect multiple device conductive portion groups in the same driving unit; the connecting line is located in the first conductive layer and / or the second conductive layer.

14. The circuit board according to any one of claims 1 to 13, wherein: The plurality of second conductive portions are divided into a plurality of device conductive portion groups and a plurality of chip conductive portion groups; The signal line includes a first signal line and a second signal line, the first signal line is electrically connected to the device conductive portion group; the second signal line is electrically connected to the chip conductive portion group; the first insulating layer is further provided with a second via hole penetrating the first insulating layer; The circuit board also includes: a plurality of device transfer wires located in the second conductive layer; one end of the device transfer wire is in electrical contact with the first signal line through the second via hole, and the other end is in electrical contact with the second conductive portion of the device conductive portion group; A plurality of chip transfer wires are located in the second conductive layer; one end of the chip transfer wire is electrically connected to the second signal line through the second via hole, and the other end is electrically connected to the second conductive portion of the chip conductive portion group.

15. The circuit board according to any one of claims 1 to 14, further comprising: a first passivation layer, disposed between the first conductive layer and the first insulating layer and exposing at least a portion of the first conductive portion; a second passivation layer, disposed between the first insulating layer and the second conductive layer, and exposing at least a portion of the first conductive portion; The plurality of pads electrically connected to the same electronic component are exposed by the same first via hole, so that the first insulating layer does not exist in the area between the plurality of pads electrically connected to the same electronic component.

16. The circuit board according to any one of claims 1 to 15, further comprising: a third passivation layer, disposed on a side of the second conductive layer away from the substrate and exposing at least the pad; a second insulating layer, disposed on a side of the third passivation layer away from the substrate and exposing at least the pad; In which, the third passivation layer and / or the second insulating layer also exposes the area between multiple pads electrically connected to the same electronic component, so that the third passivation layer and / or the second insulating layer does not exist in the area between multiple pads electrically connected to the same electronic component.

17. A light-emitting substrate, comprising: A circuit board, wherein the circuit board is the circuit board according to any one of claims 1 to 16; An electronic component, wherein the pins of the electronic component are electrically connected to the pads on the circuit board through solder.

18. The light-emitting substrate according to claim 17, wherein The circuit board includes an anti-oxidation layer, and the anti-oxidation layer covers the wiring and the second conductive part located on the second conductive layer; The light-emitting substrate further includes a reflective layer, which is arranged on a side of the anti-oxidation layer away from the substrate and in contact with the anti-oxidation layer; the reflective layer is provided with a plurality of openings, and the pins of the electronic component are electrically connected to the solder and the pads through the openings.

19. A backlight module, comprising: The light-emitting substrate according to claim 17 or 18, wherein the light-emitting substrate has a light-emitting side and a non-light-emitting side opposite to each other; A plurality of optical films are arranged on the light-emitting side of the light-emitting substrate.

20. A display device comprising: The backlight module according to claim 19; The display panel is arranged on a side of the plurality of optical films in the backlight module away from the light-emitting substrate.