Method for Testing an Input Channel for PWM Signals of an Electronic Circuit

Abstract

An input channel 4 for a pulse width modulated (PWM) signal input to an electronic circuit 2 is tested by applying a test PWM signal 12 to an input module 6 of the circuit. The input module contains a

Description

The present invention relates to a method for testing an input channel for PWM signals of an electronic circuit and to a computing unit and a computer program for performing same. Background of the invention In order to assist a processing unit, such as e.g. a CPU (Central Processing Unit) with time-related and position-related processes, so-called timers, i.e. timer units or timer modules, are known. Such timer modules can be designed as individual components or as peripheral modules of the processing unit and thereby provide more or less important functions for signal recording and generation in temporal dependence upon one or more internal clocks of the timer module. In particular, input channels can be provided which receive PWM signals and detect the level transitions thereof, e.g. in relation to an internal clock. Disclosure of the invention In accordance with the invention, a method for testing an input channel for PWM signals of an electronic circuit as claimed in claim 1, a computing unit as claimed in claim 11 and a computer program as claimed in claim 15 for performing same, having the features of the independent claims are provided. Advantageous embodiments are described in the dependent claims and the description hereinafter. The invention makes use of the measure of switching to the reception of a predetermined test PWM signal for a test time interval whilst an external PWM signal is received on the input channel or during reception of an external PWM signal by means of the input channel, and of determining at least one test value based upon the test PWM signal received during the test time interval, said test value being compared to at least one corresponding reference value in order to recognise that a malfunction of the input channel is present in the event that a difference between the at least one test value and the at least one reference value exceeds a specified or specifiable threshold value, in particular the at least one test value does not correspond to the at least one reference value. This measure is advantageous because one and the same input channel is used both for reception of the external PWM signal and for reception of the test PWM signal. In particular, no second input channel is necessary, e.g. for redundant reception of the external PWM signal. Switching an input channel can be understood to mean terminating, in particular interrupting or postponing, reception of a first PWM signal and commencing, in particular continuing with, reception of a second PWM signal. In the present case, switching the input channel can be understood to mean in particular terminating, in particular interrupting or postponing, reception of the external PWM signal and commencing reception of the test PWM signal. Furthermore, in the present case, switching-back the input channel can be understood to mean in particular terminating reception of the test PWM signal and commencing, in particular continuing with, reception of the external PWM signal. In this case, the input channel is preferably adapted to receive in an alternating manner a first PWM signal, in particular the external PWM signal, and a second PWM signal, in particular the test PWM signal. Pulse width modulation is also referred to as pulse duration modulation or pulse length modulation. In the further description, the usual abbreviation of PWM is used to refer to pulse width modulation. The malfunction can be considered to be a potential malfunction of the input channel because other elements which are used in the method can also have a fault. Such faults can be recognised or eliminated by suitable testing methods for these other elements. Preferably, the at least one test value includes a cycle duration and / or a pulse duty factor or duty cycle of the test PWM signal. The duty cycle designates the time duration within a period, during which a high signal level is present. The pulse duty factor is also referred to as the pulse control factor and is determined as usual as the quotient of the duty cycle and cycle duration. Preferably, the test time interval is shorter than a cycle duration of the external PWM signal, more preferably shorter than half a cycle duration of the external PWM signal. The testing of the input channel thus has only a slight effect or no effect at all upon the accuracy of values (e.g. pulse duty factor) determined (processed) from the external PWM signal. Preferably, the test time interval is the same as or longer than two cycle durations of the test PWM signal. More preferably, the test time interval includes at least two complete periods of the test PWM signal. Within the scope of the present invention, a complete period of a PWM signal is to be understood preferably to mean a temporal portion of the PWM signal which commences with a rising flank, i.e. a level transition from a low level to a high level, and is followed by a falling flank, i.e. a level transition from the high level to the low level. A complete period of a PWM signal can be ascertained based upon a number of level transitions from a low / high signal level to a high / low signal level. A low signal level can correspond e.g. to a voltage of 0 V, a high signal level can correspond e.g. to a voltage of 5 V. These measures can serve to ensure that the at least one test value can be determined with sufficient accuracy. Preferably, the external PWM signal is processed in order to determine a processed value which is interrogated and / or used in intervals, wherein the test time interval is shorter than 20%, preferably shorter than 10%, even more preferably shorter than 5%, of a temporal length of the intervals. Therefore, it is possible to ensure that the processed value, which corresponds to a sensor measurement value, for instance in the case of an external PWM signal from a sensor, is not falsified by the testing of the input channel. The intervals, e.g. regular intervals, are approximately between points in time when the processed value is interrogated or used (e.g. in a closed-loop control). Such intervals can be e.g. in the range of 1 ms to 20 ms. Analogously, provision could be made that a temporal proportion of the test time interval or, if the method is performed repeatedly, the test time intervals in relation to the total time (i.e. the time in which the external PWM signal is received, plus the time in which the test PWM signal is received) is less than 20%, preferably less than 10%, more preferably less than 5%. Preferably, the switching of the input channel from reception of the external PWM signal to reception of the test PWM signal is effected in response to a trigger signal. The trigger signal can be e.g. an interrupt which is recognised at an interrupt module of the electronic circuit. Preferably, the test PWM signal is generated by means of the electronic circuit. In particular, an output module of the electronic circuit can be used for this purpose. The test PWM signal can be guided from the output module to the input module or input channel externally (outside the electronic circuit) via a corresponding line. Alternatively, if corresponding lines are provided in the electronic circuit, the test PWM signal can be guided from the output module to the input module or input channel internally. In an advantageous manner, the method comprises a step of outputting a signal, in particular by means of the computing unit, based upon the step of comparing the at least one test value to at least one corresponding predetermined reference value. It is feasible for a signal to be output only in the case in which it has been determined that a malfunction of the input channel is present. It is also feasible for a signal to be output in addition also in the case in which the difference between the at least one test value and the at least one reference value is less than or equal to the specified or specifiable threshold value. The signal can include malfunction information in relation to the presence or non-presence of the malfunction of the input channel. In response to the output signal and / or using the output signal, the malfunction information can be transmitted wirelessly or in a wired manner to an output unit, e.g. a display unit, in order to output, in particular display, information in relation to the malfunction, e.g. the presence of a malfunction, by means of the output unit. Furthermore, it is feasible that, in response to the output signal and / or using the output signal, the malfunction information is relayed wirelessly or in a wired manner to a further signal processing unit which is physically spaced apart from the computing unit, in order to further process the malfunction information by means of the signal processing unit and / or to initiate and / or control engagement into the electronic circuit. A computing unit in accordance with the invention, e.g. a control device of a motor vehicle, comprises an electronic circuit having an input channel for PWM signals and is adapted, in particular in terms of program technology, to perform a method in accordance with the invention. The computing unit comprises the electronic circuit or is connected thereto (in particular for exchanging data and / or signals). The electronic circuit comprises an input module, wherein the input channel is provided in the input module. The electronic circuit preferably comprises an output module which is connected to the input module and is configured or can be configured to generate the test PWM signal. The configuration can be effected e.g. by registers. Preferably, the input module has at least two inputs and a selection element, by means of which each of the inputs can be selectively connected to the input channel. The selection element can be produced e.g. by switching element(s) and / or multiplexers or the like. The implementation of a method in accordance with the invention in the form of a computer program or computer program product having program code for performing all of the method steps is also advantageous because this gives rise to particularly low costs, in particular when an executing control device is also used for further tasks and therefore is already present. Finally, a machine-readable storage medium is provided having a computer program stored thereon, as described above. Suitable storage media or data carriers for providing the computer program are in particular magnetic, optical and electronic storage devices, such as hard disks, flash memories, EEPROMs, DVDs amongst others. A download of a program via computer networks (Internet, Intranet etc.) is possible. Such a download can be effected in a wired or cabled manner or wirelessly (e.g. via a WLAN network, a 3G, 4G, 5G or 6G connection etc.). Further advantages and embodiments of the invention are apparent from the description and the accompanying drawing. The invention is illustrated schematically in the drawing using exemplified embodiments and is described hereinafter with reference to the drawing. Brief description of the drawings Figure 1 shows an exemplary electronic circuit having an input channel which can be tested in accordance with the invention. Figure 2 shows a flow diagram according to a preferred embodiment. Figures 3 A, 3B show signal progressions of external PWM signals and test PWM signals corresponding to preferred embodiments. Embodiment(s) of the invention Figure 1 shows an exemplary electronic circuit 2 having an input channel 4 which can be tested in accordance with the invention. The electronic circuit is, in particular, a generic timer module (GTM), as described e.g. in EP 2 553 540 Al. The input channel 4 is provided by way of example in an input module 6 (or timer input module) which has at least two inputs, wherein the input channel 4 can be selectively connected to one of the inputs, for which reason a selection element 8, e.g. a multiplexer and / or semiconductor switch, is provided. An external PWM signal 10 is provided at one of the inputs of the input module 6 and a test PWM signal 12 is provided at another of the inputs of the input module 6. By means of the selection element 8, one of these two PWM signals can be selectively relayed to the input channel 4. In general, the input module 6 can have a plurality of input channels and / or a plurality of input modules can be provided, as shown. The input module 6 or the input channel 4 preferably comprises analysis elements or filter elements (not illustrated), with which in particular predetermined properties of signals, which are received, can be recognised. This includes e.g. level transitions (flanks) of a received PWM signal and / or cycle durations of a received PWM signal and / or the pulse duty factor (pulse control factor) or the duty cycle (i.e. the duration during a period in which a high level of the PWM signal is present) of a received PWM signal. In addition, in the case of the level transitions a distinction can be provided between the direction, i.e. whether a level transition from a low signal level to a high signal level (rising flank) or from a high signal level to a low signal level (falling flank) is present. In addition or in order to be able to determine the aforementioned properties, one or more counting elements and / or one or more register elements can be provided as analysis elements, with which one or more numbers of clock cycles, in particular between level transitions can be counted and / or detected (in particular intermediately stored). Furthermore, the electronic circuit 2 preferably comprises a timer circuit (or a clock signal module) 14 which is adapted to provide one or more clock signals (at possibly different frequencies) for the other elements or modules of the electronic circuit 2 (generic timer module). The input module 6 or the input channel 4 can be configured in particular to use or select one of these clock signals and to synchronise signals, in particular PWM signals, received on the input channel 4 with this clock signal. In the case of PWM signals, the temporal length between level transitions is thus characterised or given by a specific number of clock cycles of the clock signal. It is understood that the electronic circuit 2 can optionally also have different modules, not shown. By way of example, an (external) communication interface 16 (or bus interface) is provided in the electronic circuit 2, which permits data communication with other computing units and / or processors. In particular, properties (cycle duration, pulse duty factor) which are determined by the input channel 4 or by the analysis elements can be communicated via the communication interface 16 to other computing units and can be used thereby. For example, the external PWM signal could be a signal of a sensor, wherein the measurement value is coded as a pulse duty factor and the measurement value is used by a closed-loop controller which is implemented by the other computing unit. The test PWM signal 12 is generated preferably by means of an output module 18 (or timer output module) and is communicated to the input module 6. Accordingly, the output module 18 is configured or can be configured to generate the test PWM signal 12 with a determined or determinable period length and a determined or determinable pulse duty factor and to provide said signal to an output which is connected to the input of the input module, at which the test PWM signal 12 is provided. In contrast, it would also be conceivable for the test PWM signal 12 to be generated by an electronic unit outside the electronic circuit. It is expedient to generate said signal by means of the output module 18 of the electronic circuit 2 because the output module 18 and the input module 6 are supplied with clock signals from the same clock source, e.g. the timer circuit 14. In general, a plurality of output modules can be included in the electronic circuit 2, as shown. The configuration of the output module 18, the input module 6 and, where appropriate, other elements or modules of the electronic circuit 2 can be effected e.g. by setting corresponding configuration registers. Further elements which are shown by way of example and can be included in the electronic circuit 2 are an (internal) general interface unit 20 (routing unit) which connects individual modules of the electronic circuit 2 for data communication, one or more computing modules 22 which are adapted to perform computing operations and for this purpose each have for instance a computing core and a storage device, an interrupt module 24, via which interrupts can be triggered in the electronic circuit 2 and / or interrupts of the electronic circuit 2 can be recognised, and interface-connected output modules 26 which, unlike the output module 18, are connected to the interface unit 20. An interface-connected output module 26 could likewise be used for generating the test PWM signal 12. The interrupt module 24 can be connected to other computing units via data lines or signal lines. Individual method steps can be performed at least in part by one of the computing modules 22 of the electronic circuit, in particular the step of comparing the at least one test value to the predetermined reference value and / or of determining that a malfunction of the input channel is possibly present can be performed by a computing module. In addition or alternatively, it is also feasible for the switching of the input channel from reception of the external PWM signal to reception of the test PWM signal and the switching-back after the test time interval to be triggered or instigated by a computing module (e.g. by corresponding activation of the selection element or by setting a corresponding register). For this purpose, one or more computer programs or computer program modules can be provided which are executed in a computing module. Likewise, these method steps can be performed at least in part by another computing unit which e.g. (if present) are connected to the electronic circuit 2 by means of the communication interface 16 and / or the interrupt module 24. The term “another computing unit” is intended to refer to a computing unit which is different from the electronic circuit. For example, the electronic circuit 2 can be arranged together with the other computing unit on a circuit board or integrated in a chip. The combined computing unit thus obtained can be contained for instance in a control device of a machine and / or a vehicle in order to perform control functions. Figure 2 shows a flow diagram according to one embodiment of the method for testing an input channel of an electronic circuit, for instance the electronic circuit 2 shown in figure 1. A state is assumed in which the external PWM signal is received by the input channel, step 110. In step 120, the input channel is switched from reception of the external PWM signal to reception of a test PWM signal. In step 130, at least one test value is determined based upon the received test PWM signal. For this purpose, in particular level transitions and the points in time thereof (typically measured in clock cycles) are detected. Then, in step 140, after the test time interval (starting with step 120), a switch back is effected, i.e. a switch from reception of a test PWM signal to reception of the external PWM signal. Step 130 can be performed in part after step 140, in particular provision can be made that the at least one test value is calculated after the switching-back, e.g. the calculation is performed using values which have been detected during the test time interval. After step 140, the state at step 110 is then restored. Provision can be made that the testing of the input channel is repeated, e.g. performed at specific intervals. Step 120 can be considered to be the beginning of the test time interval and step 140 can be considered to be the end of the test time interval. The test PWM signal is generated in step 100 with a determined cycle duration and a determined pulse duty factor (pulse control factor). This step can be performed continuously independently of other steps (for instance, as in figure 1 by means of an output module which is independent of the input channel). Alternatively, it is also feasible for the test PWM signal not to be generated continuously but instead only in specific time periods which include the test time interval or, if the test is performed repeatedly, the test time intervals. For the generated test PWM signal, at least one value which is designated as a reference value and corresponds to at least one test value is known or predetermined. That is to say that if the input channel is fault-free, a difference between the at 1 east one test value and the at least one reference value should be less than or equal to a specified or specifiable threshold value, in particular the at least one test value should be equal to the at least one reference value (if a fault is not present in another element, except the input channel). In step 150, the at least one test value, which is determined in step 130, is compared to the corresponding at least one known or predetermined reference value. If a difference between the at least one test value and the at least one reference value exceeds a specified or specifiable threshold value, in particular if the at least one test value is not equal to the at least one reference value, in step 160 a malfunction of the input channel is determined or recognised. More specifically, a possible or potential malfunction of the input channel is determined because another element involved in the method could possibly also have a malfunction. Such malfunctions of other elements can be eliminated by suitable (other) testing methods. If the (potential) malfunction is determined, provision can be made that a corresponding fault message is generated and / or communicated. Likewise, further use of the external PWM signal or data based thereon or processed values could be avoided. If the difference between the at least one test value and the at least one reference value does not exceed a specified or specifiable threshold value, in particular if the at least one test value is equal to the at least one reference value, preferably in step 170 a fault-free state of the input channel is determined or recognised. Provision can be made that for instance after a specific waiting time, renewed testing of the input channel is performed, i.e. the procedure skips back to step 120. Typically, in step 120 the processing of the external PWM signal is interrupted. For example, level transitions which, after step 120, are in the test time interval are not taken into consideration in the determination of processed variables, e.g. the pulse duty factor of the external PWM signal. Only after switching back to step 140 is the processing of the external PWM signal continued. Preferably, provision is made that the processing of the external PWM signal is not continued directly at the end of the test time interval (step 140), but instead in step 180 there is initially a wait until a complete or valid period of the external PWM signal has elapsed. This can be recognised from the level transitions. Preferably, in step 190, after the complete period of the external PWM signal has elapsed, the processing of the external PWM signal is continued. If step 180 is not provided, the processing can be continued for instance at the end of the test time interval. Step 180 is expedient because the determination of processed values from the external PWM signal is more accurate. In an optional step 200 which is performed in particular in cycles (e.g. in intervals in the range of 1 ms to 20 ms), provision can be made to interrogate and / or use (for instance in a closed-loop control method) a processed value (for instance pulse duty factor) determined from the external PWM signal. With a suitable (brief) selection of the test time interval, the testing of the input channel has no effect or only a very slight effect upon the accuracy of processed values of the external PWM signal. For instance, if the testing is performed repeatedly, the waiting time in step 170 can be greater than a cycle time of step 200. In general, provision can be made for the test time interval and optionally the waiting time from step 170 to be selected such that processing of the external PWM signal can be performed for at least 80%, preferably at least 90%, more preferably at least 95% of the total time. That is to say that the time in which the processing is interrupted (between step 120 and step 190 or 140) should proportionally be, in particular, less than 20%, preferably less than 10%, more preferably less than 5%. Figures 3A, 3B show signal progressions of external PWM signals and test PWM signals according to preferred embodiments. Both figures each include three graphs in which signal progressions or levels P of signals are plotted over time t. The top graph 52 shows the signal progression of an external PWM signal. The middle graph 54 shows the signal progression of a test PWM signal. The bottom graph 56 shows the signal progression of a signal which is received on the input channel whilst the testing method is being performed. The signal progression in graph 56 has three temporal ranges. Firstly, until the commencement 56 of the test time interval 60, the signal received on the input channel corresponds to the external PWM signal from graph 52. During the test time interval 60, the signal received on the input channel corresponds to the test PWM signal from graph 54. After the end 62 of the test time interval 60, the signal received on the input channel corresponds again to the external PWM signal from graph 52. Since no temporal correlation exists between the external PWM signal and the test PWM signal, the test time interval 62 can correspond to different time windows related to the periods of the external PWM signal, for instance according to figure 3A or according to figure 3B. Furthermore, both figures indicate a point in time 64 when a complete period of the external PWM signal after the end 62 of the test time interval 60 has elapsed. This can be recognised from the number of level transitions (flanks) which are present after the end 62 of the test time interval 60 or which are detected by means of the input channel. It is assumed that a period of a PWM signal commences with a rising flank, i.e. the level transition from the low level to the high level. The temporal length of the high level is variable corresponding to the pulse duty factor. In figure 3A, at the end 62 of the test time interval 60 a high signal level of the signal received on the input channel is present. In this case, the passage of a complete period of the external PWM signal can be recognised with the fourth level transition 74. As the four level transitions 71, 72, 73, 74 are detected, it is thus possible to determine that the complete period 66 of the external PWM signal after the end 62 of the test time interval 60 has elapsed. 5 In figure 3B, at the end 62 of the test time interval 60 a low signal level of the signal received on the input channel is present. In this case, the passage of a complete period of the external PWM signal can be recognised with the third level transition 83. As the four level transitions 81, 82, 83 are detected, it is thus possible to determine that the complete period 66 of the external PWM signal after the end 62 of the test time interval 60 has elapsed. 10

Claims

1. Method for testing an input channel (4) for pulse width modulation, PWM, signals of an electronic circuit (2) whilst an external PWM signal (10) is received (110), comprisinggenerating (100) a predetermined test PWM signal (12) having a predetermined cycle duration;switching (120) the input channel from reception of the external PWM signal (10) to reception of the test PWM signal (12);determining (130) at least one test value during reception of the test PWM signal (12);switching back (140), after a test time interval (60), the input channel from reception of the test PWM signal (12) to reception of the external PWM signal (10);comparing (150) the at least one test value to at least one corresponding predetermined reference value;determining (160) that a malfunction of the input channel is present, if a difference between the at least one test value and the at least one reference value exceeds a specified or specifiable threshold value.

2. Method as claimed in claim 1, wherein the at least one test value includes a cycle duration and / or a pulse duty factor or duty cycle of the test PWM signal.

3. Method as claimed in any one of the preceding claims, wherein the test time interval (60) is shorter than a cycle duration of the external PWM signal, preferably shorter than half a cycle duration of the external PWM signal.

4. Method as claimed in any one of the preceding claims, wherein the test time interval (60) is the same as or longer than two cycle durations of the test PWM signal, wherein preferably the test time interval includes at least two complete periods of the test PWM signal.

5. Method as claimed in any one of the preceding claims, wherein at the beginning (58) of the test time interval (60) processing of the external PWM signal is interrupted and after the end (62)of the test time interval the processing of the external PWM signal is continued (190).

6. Method as claimed in claim 5, wherein the processing of the external PWM signal is continued (190) after the end (62) of the test time interval (60), after a complete period (66) of the external PWM signal after the end of the test time interval has elapsed.

7. Method as claimed in claim 6, wherein it is determined that the complete period (66) of the external PWM signal after the end (62) of the test time interval (60) has elapsed, in that:if a high signal level is present at the end of the test time interval, it is determined that four level transitions (71, 72, 73, 74) of the external PWM signal are present after the end of the test time interval; and / or,if a low signal level is present at the end of the test time interval, it is determined that three level transitions (81, 82, 83) of the external PWM signal are present after the end of the test time interval.

8. Method as claimed in any one of the preceding claims, wherein the external PWM signal (10) is processed in order to determine a processed value which is interrogated and / or used at intervals, wherein the test time interval is shorter than 20%, preferably shorter than 10%, even more preferably shorter than 5% of a temporal length of the intervals.

9. Method as claimed in any one of the preceding claims, wherein the switching (120) of the input channel from reception of the external PWM signal to reception of the test PWM signal is effected in response to a trigger signal.

10. Method as claimed in any one of the preceding claims, wherein the test PWM signal (12) is generated by means of the electronic circuit (2).

11. Computing unit which is adapted to perform and / or instigate the performance of all of the method steps of a method as claimed in any one of the preceding claims, wherein the computing unit comprises the electronic circuit (2) or is connected thereto; and wherein the electronic circuit(2) comprises an input module (6), wherein the input channel (4) is provided in the input module (6).

12. Computing unit as claimed in claim 11, wherein the electronic circuit (2) comprises an output module (18) which is connected to the input module (6) and which is configured or can be configured to generate the test PWM signal.

13. Computing unit as claimed in any one of claims 11 or 12, wherein the input module (6) has at last two inputs and one selection element (8), by means of which each of the inputs can be selectively connected to the input channel (4).

14. Computing unit as claimed in any one of claims 11 to 13, wherein the input channel (4) comprises at least one analysis element in order to recognise signal transitions of received PWM signals and / or to determine a cycle duration of received PWM signals and / or to determine a pulse duty factor or a duty cycle of received PWM signals.

15. Computer program which instigates a computing unit as claimed in any one of claims 11 to 14 to perform all of the method steps of a method as claimed in any one of claims 1 to 10 when said computer program is executed on the computing unit.

16. Machine-readable storage medium comprising a computer program as claimed in claim 15 stored thereon.

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