Shift register unit, gate driving circuit, and display apparatus

Abstract

Provided are a shift register unit, a gate driving circuit and a display apparatus, belonging to the technical field of display. In the shift register unit, an input circuit can control the potential of a first node (N1) and the potential of a third node (N3) on the basis of a clock signal provided by a clock end, a power supply signal provided by a power supply end and the potential of a second node (N2). A control circuit can control the potential of a fourth node (N4) and the potential of a fifth node (N5) on the basis of the clock signal, the power supply signal, and the potential of the first node (N1), the second node (N2) and the third node (N3). An output circuit can transmit to an output end a first power supply signal or a second power supply signal on the basis of the potential of the fourth node (N4) and the potential of the fifth node (N5). Thus, by flexibly setting signals provided by each signal end, signals of required potentials can be reliably transmitted to the fourth node (N4) and the fifth node (N5), allowing the output circuit to be fully and quickly turned on or off, thereby avoiding steps forming during jumping of signals transmitted to the output end, that is, a trailing phenomenon.

Description

Shift register unit, gate drive circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AM OLED) display devices are widely used in various products due to their advantages such as flexibility, high contrast and low power consumption.

[0003] In related art, an AMOLED display device typically includes an AMOLED display panel and a gate drive circuit. The AMOLED display panel includes multiple rows of pixels. The gate drive circuit includes multiple cascaded shift register units. Each shift register unit is coupled to a row of pixels and is used to transmit a gate drive signal to that row of pixels to drive that row of pixels to emit light. The multiple cascaded shift register units enable progressive scanning of the multiple rows of pixels, allowing the AMOLED display panel to display an image.

[0004] However, due to the influence of the threshold voltage of the transistors in the shift register unit, the potential of the gate drive signal transmitted by the shift register unit in the related art may have multiple steps when jumping, that is, signal tailing occurs. As a result, the output stability of the shift register unit is poor.

[0005] Summary of the Invention

[0006] Provided are a shift register unit, a gate drive circuit, and a display device. The technical solution is as follows:

[0007] In one aspect, a shift register unit is provided, comprising:

[0008] a first input circuit coupled to a first clock terminal, an input terminal, a first node, and a second node, respectively, and configured to control the connection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal, and to control the connection between the second node and the first node in response to a potential of the second node;

[0009] a second input circuit, coupled to the first node, the first clock terminal, the first power terminal, and the third node, respectively, and configured to control the connection and disconnection between the first clock terminal and the third node in response to the potential of the first node, and to control the connection and disconnection between the first power terminal and the third node in response to the first clock signal;

[0010] a first control circuit, coupled to the input terminal, the first clock terminal, the second node, the second power terminal, the second clock terminal, and the third node, respectively, and configured to control the connection between the input terminal and the second node in response to the first clock signal, control the connection between the second power terminal and the second node in response to the potential of the third node, and control the connection between the second clock terminal and the second node in response to the potential of the second node;

[0011] a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, the fourth node, and the fifth node, respectively, and configured to control the connection between the second clock terminal and the fourth node in response to the potential of the third node and a second clock signal provided by the second clock terminal, control the connection between the second power terminal and the fourth node in response to the potential of the first node, and control the connection between the first node and the fifth node in response to the first power signal provided by the first power terminal;

[0012] The output circuit is coupled to the fourth node, the fifth node, the first power supply terminal, the second power supply terminal and the output terminal, respectively, and is used to control the connection and disconnection between the second power supply terminal and the output terminal in response to the potential of the fourth node, and to control the connection and disconnection between the first power supply terminal and the output terminal in response to the potential of the fifth node.

[0013] Optionally, the first input circuit includes: a first input sub-circuit and a second input sub-circuit;

[0014] The first input sub-circuit is coupled to the first clock terminal, the input terminal and the first node respectively, and is used to control the connection and disconnection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal;

[0015] The second input sub-circuit is coupled to the second node and the first node respectively, and is used to control the connection and disconnection between the second node and the first node in response to the potential of the second node.

[0016] Optionally, the first input sub-circuit includes: a first transistor; the second input sub-circuit includes: a second transistor;

[0017] The gate of the first transistor is coupled to the first clock terminal, the first electrode of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the first node;

[0018] The gate and the first electrode of the second transistor are both coupled to the second node, and the second electrode of the second transistor is coupled to the first node.

[0019] Optionally, the second input circuit includes: a third input sub-circuit and a fourth input sub-circuit;

[0020] The third input sub-circuit is coupled to the first node, the first clock terminal and the third node respectively, and is used to control the connection and disconnection between the first clock terminal and the third node in response to the potential of the first node;

[0021] The fourth input sub-circuit is coupled to the first clock terminal, the first power terminal and the third node respectively, and is used to control the connection and disconnection of the first power terminal and the third node in response to the first clock signal.

[0022] Optionally, the third input sub-circuit includes: a third transistor; the fourth input sub-circuit includes: a fourth transistor;

[0023] The gate of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first clock terminal, and the second electrode of the third transistor is coupled to the third node;

[0024] A gate of the fourth transistor is coupled to the first clock terminal, a first electrode of the fourth transistor is coupled to the first power supply terminal, and a second electrode of the fourth transistor is coupled to the third node.

[0025] Optionally, the first control circuit includes:

[0026] a first control subcircuit, coupled to the first clock terminal, the input terminal, and the second node, respectively, and configured to control the connection and disconnection between the input terminal and the second node in response to the first clock signal;

[0027] a second control subcircuit, coupled to the second node, the second power supply terminal, the third node, the second clock terminal, and the sixth node, respectively, and configured to control the connection and disconnection between the second power supply terminal and the sixth node in response to the potential of the third node, and to control the connection and disconnection between the second clock terminal and the sixth node in response to the potential of the second node;

[0028] The potential regulating subcircuit is coupled to the second node and the sixth node respectively, and is used to regulate the potential of the second node and the potential of the sixth node.

[0029] Optionally, the first control subcircuit includes: a fifth transistor; the second control subcircuit includes: a sixth transistor and a seventh transistor; the potential adjustment subcircuit includes: a first capacitor;

[0030] The gate of the fifth transistor is coupled to the first clock terminal, the first electrode of the fifth transistor is coupled to the input terminal, and the second electrode of the fifth transistor is coupled to the second node;

[0031] The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the second power supply terminal, and the second electrode of the sixth transistor is coupled to the sixth node;

[0032] The gate of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is coupled to the second clock terminal, and the second electrode of the seventh transistor is coupled to the sixth node;

[0033] A first terminal of the first capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the sixth node.

[0034] Optionally, the shift register unit further includes:

[0035] a third control circuit, coupled to the first power terminal, the seventh node, and the second node, respectively, and configured to control the seventh node to be conductive with the second node in response to the first power signal;

[0036] The seventh node is coupled to the first control sub-circuit.

[0037] Optionally, the third control circuit includes: an eighth transistor;

[0038] A gate of the eighth transistor is coupled to the first power supply terminal, a first electrode of the eighth transistor is coupled to the seventh node, and a second electrode of the eighth transistor is coupled to the second node.

[0039] Optionally, the second control circuit includes:

[0040] a third control subcircuit, coupled to the third node, the second clock terminal, the second power terminal, the first node, and the fourth node, respectively, and configured to control the connection and disconnection between the second clock terminal and the fourth node in response to the potential of the third node and the second clock signal, and to control the connection and disconnection between the second power terminal and the fourth node in response to the potential of the first node;

[0041] The fourth control sub-circuit is coupled to the first power supply terminal, the first node and the fifth node respectively, and is used to control the first node and the fifth node to be conductive in response to the first power supply signal.

[0042] Optionally, the third control subcircuit includes: a ninth transistor, a tenth transistor, an eleventh transistor and a second capacitor; the fourth control subcircuit includes: a twelfth transistor;

[0043] The gate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor and the gate of the tenth transistor are both coupled to the second clock terminal, the second electrode of the ninth transistor is coupled to the first electrode of the tenth transistor, and the second electrode of the tenth transistor is coupled to the fourth node;

[0044] The gate of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the second power supply terminal, and the second electrode of the eleventh transistor is coupled to the fourth node;

[0045] A first terminal of the second capacitor is coupled to the gate of the ninth transistor, and a second terminal of the second capacitor is coupled to the second electrode of the ninth transistor;

[0046] A gate of the twelfth transistor is coupled to the first power supply terminal, a first electrode of the twelfth transistor is coupled to the first node, and a second electrode of the twelfth transistor is coupled to the fifth node.

[0047] Optionally, the output circuit includes: a first output sub-circuit and a second output sub-circuit;

[0048] The first output sub-circuit is coupled to the fourth node, the second power supply terminal and the output terminal respectively, and is used to control the connection and disconnection between the second power supply terminal and the output terminal in response to the potential of the fourth node;

[0049] The second output sub-circuit is coupled to the fifth node, the first power supply terminal and the output terminal respectively, and is used to control the connection and disconnection of the first power supply terminal and the output terminal in response to the potential of the fifth node.

[0050] Optionally, the first output sub-circuit includes: a thirteenth transistor and a third capacitor; the second output sub-circuit includes: a fourteenth transistor;

[0051] The gate of the thirteenth transistor is coupled to the fourth node, the first electrode of the thirteenth transistor is coupled to the second power supply terminal, and the second electrode of the thirteenth transistor is coupled to the output terminal;

[0052] A first terminal of the third capacitor is coupled to the gate of the thirteenth transistor, and a second terminal of the third capacitor is coupled to the first electrode of the thirteenth transistor;

[0053] A gate of the fourteenth transistor is coupled to the fifth node, a first electrode of the fourteenth transistor is coupled to the first power supply terminal, and a second electrode of the fourteenth transistor is coupled to the output terminal.

[0054] Optionally, the shift register unit further includes: a fourth control circuit;

[0055] The fourth control circuit is coupled to the discharge control terminal, the second power supply terminal and the first node respectively, and is used to control the connection and disconnection between the second power supply terminal and the first node in response to a discharge control signal provided by the discharge control terminal.

[0056] Optionally, the fifth control circuit includes: a fifteenth transistor;

[0057] A gate of the fifteenth transistor is coupled to the discharge control terminal, a first electrode of the fifteenth transistor is coupled to the second power supply terminal, and a second electrode of the fifteenth transistor is coupled to the first node.

[0058] Optionally, the shift register unit further includes:

[0059] a fifth control circuit, coupled to the first power terminal, the third node, and the eighth node, respectively, and configured to control the third node and the eighth node to be conductive in response to the first power signal;

[0060] The eighth node is coupled to the second input circuit, or the eighth node is coupled to the second control circuit.

[0061] Optionally, the fifth control circuit includes: a sixteenth transistor;

[0062] A gate of the sixteenth transistor is coupled to the first power supply terminal, a first electrode of the sixteenth transistor is coupled to the eighth node, and a second electrode of the sixteenth transistor is coupled to the third node.

[0063] In another aspect, a shift register unit is provided, comprising:

[0064] a first input transistor, having a gate coupled to the first clock terminal, a first electrode coupled to the input terminal, and a second electrode coupled to the first node, for controlling the connection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal;

[0065] a second input transistor, wherein the gate and the first electrode are both coupled to the second node, the second electrode is coupled to the first node, and is configured to control the connection and disconnection between the second node and the first node in response to the potential of the second node;

[0066] a second input circuit coupled to the first node, the first clock terminal, and a third node, respectively, and configured to control the connection between the first clock terminal and the third node in response to the potential of the first node;

[0067] a first control circuit, coupled to the input terminal, the first clock terminal, and the second node, respectively, and configured to control the connection and disconnection between the input terminal and the second node in response to the first clock signal;

[0068] a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the fourth node, and the fifth node, respectively, and configured to control the connection between the second clock terminal and the fourth node in response to the potential of the third node and a second clock signal provided by the second clock terminal, and to control the connection between the first node and the fifth node in response to the first power signal provided by the first power terminal;

[0069] The output circuit is coupled to the fourth node, the fifth node, the first power supply terminal, the second power supply terminal and the output terminal, respectively, and is used to control the connection and disconnection between the second power supply terminal and the output terminal in response to the potential of the fourth node, and to control the connection and disconnection between the first power supply terminal and the output terminal in response to the potential of the fifth node.

[0070] Optionally, the second input circuit is further coupled to the first power supply terminal, and is configured to control the connection and disconnection between the first power supply terminal and the third node in response to the first clock signal;

[0071] The second input circuit includes: a third transistor and a fourth transistor;

[0072] The gate of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first clock terminal, and the second electrode of the third transistor is coupled to the third node;

[0073] A gate of the fourth transistor is coupled to the first clock terminal, a first electrode of the fourth transistor is coupled to the first power supply terminal, and a second electrode of the fourth transistor is coupled to the third node.

[0074] Optionally, the first control circuit is further coupled to the second power supply terminal, the second clock terminal, and the third node, respectively, and is configured to control the connection and disconnection between the second power supply terminal and the second node in response to the potential of the third node, and to control the connection and disconnection between the second clock terminal and the second node in response to the potential of the second node;

[0075] The first control circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor;

[0076] The gate of the fifth transistor is coupled to the first clock terminal, the first electrode of the fifth transistor is coupled to the input terminal, and the second electrode of the fifth transistor is coupled to the second node;

[0077] The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the second power supply terminal, and the second electrode of the sixth transistor is coupled to the second electrode of the seventh transistor;

[0078] The gate of the seventh transistor is coupled to the second node, and the first electrode of the seventh transistor is coupled to the second clock terminal;

[0079] A first terminal of the first capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the second electrode of the seventh transistor.

[0080] Optionally, the second control circuit is further coupled to the second power supply terminal, and is configured to control the connection and disconnection between the second power supply terminal and the fourth node in response to the potential of the first node;

[0081] The second control circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor;

[0082] The gate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor and the gate of the tenth transistor are both coupled to the second clock terminal, the second electrode of the ninth transistor is coupled to the first electrode of the tenth transistor, and the second electrode of the tenth transistor is coupled to the fourth node;

[0083] The gate of the eleventh transistor is coupled to the first node, the first electrode of the eleventh transistor is coupled to the second power supply terminal, and the second electrode of the eleventh transistor is coupled to the fourth node;

[0084] A first terminal of the second capacitor is coupled to the gate of the ninth transistor, and a second terminal of the second capacitor is coupled to the second electrode of the ninth transistor;

[0085] A gate of the twelfth transistor is coupled to the first power supply terminal, a first electrode of the twelfth transistor is coupled to the first node, and a second electrode of the twelfth transistor is coupled to the fifth node.

[0086] Optionally, the output circuit includes: a thirteenth transistor, a fourteenth transistor, and a third capacitor;

[0087] The gate of the thirteenth transistor is coupled to the fourth node, the first electrode of the thirteenth transistor is coupled to the second power supply terminal, and the second electrode of the thirteenth transistor is coupled to the output terminal;

[0088] A first terminal of the third capacitor is coupled to the gate of the thirteenth transistor, and a second terminal of the third capacitor is coupled to the first electrode of the thirteenth transistor;

[0089] A gate of the fourteenth transistor is coupled to the fifth node, a first electrode of the fourteenth transistor is coupled to the first power supply terminal, and a second electrode of the fourteenth transistor is coupled to the output terminal.

[0090] In another aspect, a gate driving circuit is provided, comprising: at least two cascaded shift register units as described in the first and second aspects above;

[0091] Among them, the input end of the first-level shift register unit is coupled to the input start end, and in the shift register units of other levels except the first-level shift register unit, the input end of each level of the shift register unit is coupled to the output end of the cascaded shift register unit of the previous level.

[0092] In another aspect, a display device is provided, comprising: a display panel, and the gate driving circuit as described in the above-mentioned further aspect;

[0093] The display panel includes a plurality of pixels. The gate driving circuit is coupled to the plurality of pixels and is configured to transmit a gate driving signal to the plurality of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0095] FIG1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure;

[0096] FIG2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0097] FIG3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0098] FIG4 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0099] FIG5 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0100] FIG6 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0101] FIG7 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0102] FIG8 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0103] FIG9 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0104] FIG10 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0105] FIG11 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0106] FIG12 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0107] FIG13 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0108] FIG14 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0109] FIG15 is a timing diagram of signal terminals coupled to a shift register unit according to an embodiment of the present disclosure;

[0110] FIG16 is a timing diagram of signal terminals coupled to another shift register unit provided by an embodiment of the present disclosure;

[0111] FIG17 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure;

[0112] FIG18 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0114] The transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode, and the drain is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the control electrode, which can also be referred to as the gate, the signal input end is designated as the source electrode, and the signal output end is designated as the drain electrode. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two state variables and do not imply that the first potential or the second potential has a specific value throughout the text.

[0115] FIG1 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure. As shown in FIG1 , the shift register unit includes: a first input circuit 01 , a second input circuit 02 , a first control circuit 03 , a second control circuit 04 , and an output circuit 05 .

[0116] Among them, the first input circuit 01 is coupled (i.e., electrically connected) to the first clock terminal CK1, the input terminal IN, the first node N1 and the second node N2, respectively, and is used to control the connection and disconnection between the input terminal IN and the first node N1 in response to the first clock signal provided by the first clock terminal CK1, and to control the connection and disconnection between the second node N2 and the first node N1 in response to the potential of the second node N2.

[0117] For example, the first input circuit 01 can control the input terminal IN to be connected to the first node N1 when the potential of the first clock signal provided by the first clock terminal CK1 is the first potential. At this time, the input signal provided by the input terminal IN can be transmitted (also referred to as "written") to the first node N1. And, the first input circuit 01 can control the input terminal IN to be disconnected from the first node N1 when the potential of the first clock signal is the second potential. Similarly, the first input circuit 01 can control the second node N2 to be connected to the first node N1 when the potential of the second node N2 is the first potential. At this time, the potential of the second node N2 can be further transmitted to the first node N1. And, the first input circuit 01 can control the second node N2 to be disconnected from the first node N1 when the potential of the second node N2 is the second potential. That is, the first input circuit 01 can not only control the potential of the first node N1 based on the first clock signal and the input signal, but also control the potential of the first node N1 based on the potential of the second node N2.

[0118] Optionally, in the embodiment of the present disclosure, the first potential may be an effective potential, and the second potential may be an ineffective potential. Furthermore, the first potential may be a low potential, and the second potential may be a high potential, i.e., the first potential is smaller than the second potential. The transistor in the circuit corresponding to this potential may be a P-type transistor. If the transistor in the circuit is an N-type transistor, the first potential may be a high potential, and the second potential may be a low potential, i.e., the first potential is larger than the second potential. The following embodiments will not be described in detail.

[0119] The second input circuit 02 is coupled to the first node N1, the first clock terminal CK1, the first power supply terminal VGL and the third node N3 respectively, and is used to control the connection and disconnection of the first clock terminal CK1 and the third node N3 in response to the potential of the first node N1, and to control the connection and disconnection of the first power supply terminal VGL and the third node N3 in response to the first clock signal.

[0120] For example, the second input circuit 02 can control the first clock terminal CK1 to be conductive with the third node N3 when the potential of the first node N1 is a first potential. In this case, the first clock signal provided by the first clock terminal CK1 can be transmitted to the third node N3. Furthermore, the second input circuit 02 can control the first clock terminal CK1 to be decoupled from the third node N3 when the potential of the first node N1 is a second potential.

[0121] Similarly, the second input circuit 02 can control the first power supply terminal VGL to be conductive with the third node N3 when the potential of the first clock signal is the first potential. In this case, the first power supply signal provided by the first power supply terminal VGL can be transmitted to the third node N3. Furthermore, the second input circuit 02 can control the first power supply terminal VGL to be decoupled from the third node N3 when the potential of the first clock signal is the second potential. Optionally, in the disclosed embodiment, the potential of the first power supply signal can be a low potential.

[0122] The first control circuit 03 is coupled to the input terminal IN, the first clock terminal CK1, the second node N2, the second power supply terminal VGH, the second clock terminal CK2 and the third node N3, respectively, and is used to control the connection and disconnection of the input terminal IN and the second node N2 in response to the first clock signal, control the connection and disconnection of the second power supply terminal VGH and the second node N2 in response to the potential of the third node N3, and control the connection and disconnection of the second clock terminal CK2 and the second node N2 in response to the potential of the second node N2.

[0123] For example, the first control circuit 03 can control the input terminal IN to be conductively coupled to the second node N2 when the potential of the first clock signal is a first potential. In this case, the input signal provided by the input terminal IN can be transmitted to the second node N2. Similarly, the first control circuit 03 can control the input terminal IN to be decoupled from the second node N2 when the potential of the first clock signal is a second potential.

[0124] Similarly, the first control circuit 03 can control the second power supply terminal VGH to be conductive with the third node N3 when the potential of the third node N3 is a first potential. In this case, the second power supply signal provided by the second power supply terminal VGH can be transmitted to the third node N3. Furthermore, the first control circuit 03 can control the second power supply terminal VGH to be decoupled from the third node N3 when the potential of the third node N3 is a second potential. Optionally, in the embodiment of the present disclosure, the potential of the second power supply signal can be a high potential.

[0125] Furthermore, the first control circuit 03 can control the second clock terminal CK2 to be conductive with the second node N2 when the potential of the second node N2 is the first potential. In this case, the second clock signal provided by the second clock terminal CK2 can be transmitted to the second node N2. Furthermore, the first control circuit 03 can control the second clock terminal CK2 to be decoupled from the second node N2 when the potential of the second node N2 is the second potential.

[0126] The second control circuit O4 is coupled to the third node N3, the second clock terminal CK2, the first node N1, the first power supply terminal VGL, the second power supply terminal VGH, the fourth node N4, and the fifth node N5, respectively. The second control circuit O4 is configured to control the connection between the second clock terminal CK2 and the fourth node N4 in response to the potential of the third node N3 and the second clock signal provided by the second clock terminal CK2, control the connection between the second power supply terminal VGH and the fourth node N4 in response to the potential of the first node N1, and control the connection between the first node N1 and the fifth node N5 in response to the first power supply signal provided by the first power supply terminal VGL. That is, the fifth node N5 is connected to the first node N1.

[0127] For example, the second control circuit 04 can control the second clock terminal CK2 to be conductive with the fourth node N4 when the potential of the third node N3 is the first potential and the potential of the second clock signal provided by the second clock terminal CK2 is the first potential. In this case, the second clock signal provided by the second clock terminal CK2 can be transmitted to the fourth node N4. Furthermore, the second control circuit 04 can control the second clock terminal CK2 to be decoupled from the fourth node N4 when the potential of the third node N3 is the second potential and / or the potential of the second clock signal is the second potential.

[0128] Similarly, the second control circuit 04 can control the second power supply terminal VGH to be conductively coupled to the fourth node N4 when the potential of the first node N1 is at the first potential. In this case, the second power supply signal provided by the second power supply terminal VGH can be transmitted to the fourth node N4. Furthermore, the second control circuit 04 can control the second power supply terminal VGH to be decoupled from the fourth node N4 when the potential of the first node N1 is at the second potential.

[0129] The output circuit 05 is coupled to the fourth node N4, the fifth node N5, the first power supply terminal VGL, the second power supply terminal VGH and the output terminal OUT, respectively, and is used to control the connection and disconnection of the second power supply terminal VGH and the output terminal OUT in response to the potential of the fourth node N4, and to control the connection and disconnection of the first power supply terminal VGL and the output terminal OUT in response to the potential of the fifth node N5.

[0130] For example, the output circuit 05 can control the second power supply terminal VGH to be conductively coupled to the output terminal OUT when the potential of the fourth node N4 is at a first potential. In this case, the second power supply signal provided by the second power supply terminal VGH can be transmitted to the output terminal OUT. Furthermore, the output circuit 05 can control the second power supply terminal VGH to be decoupled from the output terminal OUT when the potential of the fourth node N4 is at a second potential.

[0131] In summary, an embodiment of the present disclosure provides a shift register unit, which includes two input circuits, two control circuits and an output circuit. The input circuit can control the potential of the first node and the potential of the third node based on the clock signal provided by the coupled clock terminal, the power signal provided by the power terminal and the potential of the second node. The control circuit can control the potential of the fourth node and the fifth node based on the clock signal provided by the coupled clock terminal, the power signal provided by the power terminal, and the potentials of the first node, the second node and the third node. The output circuit can transmit the first power signal or the second power signal to the output terminal based on the potential of the fourth node and the fifth node. In this way, by flexibly setting the signals provided by each signal terminal, the signals of the required potential can be reliably transmitted to the fourth node and the fifth node, thereby making the output circuit fully and quickly turned on or off, avoiding the potential jump of the signal transmitted to the output terminal to appear steps, that is, avoiding the tailing phenomenon of the output signal, and ensuring better output stability.

[0132] FIG2 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG2 , the first input circuit 01 described in the embodiment of the present disclosure may include: a first input sub-circuit 011 and a second input sub-circuit 012 .

[0133] The first input sub-circuit 011 can be coupled to the first clock terminal CK1, the input terminal IN and the first node N1 respectively, and can be used to control the connection between the input terminal IN and the first node N1 in response to the first clock signal provided by the first clock terminal CK1.

[0134] For example, the first input sub-circuit 011 can control the input terminal IN to be connected to the first node N1 when the potential of the first clock signal provided by the first clock terminal CK1 is the first potential, and can control the input terminal IN to be disconnected from the first node N1 when the potential of the first clock signal is the second potential.

[0135] The second input sub-circuit 012 can be coupled to the second node N2 and the first node N1, respectively, and can be used to control the connection between the second node N2 and the first node N1 in response to the potential of the second node N2. In other words, the second input sub-circuit 012 can be connected in series between the second node N2 and the first node N1, and the potential of the first node N1 can be controlled according to the potential of the second node N2.

[0136] For example, the second input sub-circuit 012 can control the second node N2 to be conductive with the first node N1 when the potential of the second node N2 is the first potential, and can control the second node N2 to be decoupled from the first node N1 when the potential of the second node N2 is the second potential.

[0137] FIG3 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG3 , the second input circuit 02 described in the embodiment of the present disclosure may include: a third input sub-circuit 021 and a fourth input sub-circuit 022 .

[0138] The third input sub-circuit 021 can be coupled to the first node N1, the first clock terminal CK1 and the third node N3 respectively, and can be used to control the connection between the first clock terminal CK1 and the third node N3 in response to the potential of the first node N1.

[0139] For example, the third input sub-circuit 021 can control the first clock terminal CK1 to be conductive with the third node N3 when the potential of the first node N1 is the first potential, and can control the first clock terminal CK1 to be decoupled from the third node N3 when the potential of the first node N1 is the second potential.

[0140] The fourth input sub-circuit 022 may be coupled to the first clock terminal CK1 , the first power terminal VGL and the third node N3 respectively, and may be used to control the connection and disconnection between the first power terminal VGL and the third node N3 in response to the first clock signal.

[0141] For example, the fourth input sub-circuit 022 can control the first power supply terminal VGL and the third node N3 to be conductive when the potential of the first clock signal is the first potential, and can control the first power supply terminal VGL and the third node N3 to be disconnected when the potential of the first clock signal is the second potential.

[0142] FIG4 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG4 , the first control circuit 03 described in the embodiment of the present disclosure may include: a first control subcircuit 031 , a second control subcircuit 032 , and a potential adjustment subcircuit 033 .

[0143] The first control sub-circuit 031 may be coupled to the first clock terminal CK1, the input terminal IN and the second node N2 respectively, and may be used to control the connection and disconnection between the input terminal IN and the second node N2 in response to the first clock signal.

[0144] For example, the first control subcircuit 031 can control the input terminal IN to be connected to the second node N2 when the potential of the first clock signal is the first potential, and can control the input terminal IN to be disconnected from the second node N2 when the potential of the first clock signal is the second potential.

[0145] The second control sub-circuit 032 can be coupled to the second node N2, the second power supply terminal VGH, the third node N3, the second clock terminal CK2 and the sixth node N6 respectively, and can be used to control the connection and disconnection of the second power supply terminal VGH and the sixth node N6 in response to the potential of the third node N3, and can control the connection and disconnection of the second clock terminal CK2 and the sixth node N6 in response to the potential of the second node N2.

[0146] For example, the second control sub-circuit 032 can control the second power supply terminal VGH to be conductively coupled to the sixth node N6 when the potential of the third node N3 is at a first potential. In this case, the second power supply signal provided by the second power supply terminal VGH can be transmitted to the sixth node N6. Furthermore, the second control sub-circuit 032 can control the second power supply terminal VGH to be decoupled from the sixth node N6 when the potential of the third node N3 is at a second potential.

[0147] Similarly, the second control sub-circuit 032 can control the second clock terminal CK2 to be conductive with the sixth node N6 when the potential of the second node N2 is the first potential. In this case, the second clock signal provided by the second clock terminal CK2 can be transmitted to the sixth node N6. Furthermore, the second control sub-circuit 032 can control the second clock terminal CK2 to be decoupled from the sixth node N6 when the potential of the second node N2 is the second potential.

[0148] The potential adjustment sub-circuit 033 may be coupled to the second node N2 and the sixth node N6 respectively, and may be used to adjust the potential of the second node N2 and the potential of the sixth node N6.

[0149] FIG5 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG5 , the second control circuit 04 described in the embodiment of the present disclosure may include: a third control sub-circuit 041 and a fourth control sub-circuit 042 .

[0150] Among them, the third control sub-circuit 041 can be coupled to the third node N3, the second clock terminal CK2, the second power supply terminal VGH, the first node N1 and the fourth node N4 respectively, and can be used to control the on and off of the second clock terminal CK2 and the fourth node N4 in response to the potential of the third node N3 and the second clock signal, and can control the on and off of the second power supply terminal VGH and the fourth node N4 in response to the potential of the first node N1.

[0151] For example, the third control sub-circuit 041 can control the second clock terminal CK2 to be conductively coupled to the fourth node N4 when the potential of the third node and the potential of the second clock signal are both at the first potential. Furthermore, the third control sub-circuit 041 can control the second clock terminal CK2 to be decoupled from the fourth node N4 when the potential of the third node N3 is at the second potential and / or the potential of the second clock signal is at the second potential. Similarly, the third control sub-circuit 041 can control the second power supply terminal VGH to be conductively coupled to the fourth node N4 when the potential of the first node N1 is at the first potential, and can control the second power supply terminal VGH to be decoupled from the fourth node N4 when the potential of the first node N1 is at the second potential.

[0152] The fourth control sub-circuit 042 may be coupled to the first power terminal VGL, the first node N1 and the fifth node N5 respectively, and may be configured to control the first node N1 and the fifth node N5 to be conductive in response to the first power signal.

[0153] FIG6 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG6 , the output circuit 05 described in the embodiment of the present disclosure may include: a first output sub-circuit 051 and a second output sub-circuit 052 .

[0154] The first output sub-circuit 051 can be coupled to the fourth node N4, the second power supply terminal VGH and the output terminal OUT respectively, and can be used to control the connection and disconnection of the second power supply terminal VGH and the output terminal OUT in response to the potential of the fourth node N4.

[0155] For example, the first output sub-circuit 051 can control the second power supply terminal VGH and the output terminal OUT to be connected when the potential of the fourth node N4 is the first potential, and can control the second power supply terminal VGH and the output terminal OUT to be disconnected when the potential of the fourth node N4 is the second potential.

[0156] The second output sub-circuit 052 can be coupled to the fifth node N5, the first power supply terminal VGL and the output terminal OUT respectively, and can be used to control the connection and disconnection of the first power supply terminal VGL and the output terminal OUT in response to the potential of the fifth node N5.

[0157] For example, the second output sub-circuit 052 can control the first power supply terminal VGL and the output terminal OUT to be connected when the potential of the fifth node N5 is the first potential, and can control the first power supply terminal VGL and the output terminal OUT to be disconnected when the potential of the fifth node N5 is the second potential.

[0158] FIG7 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG5 , the shift register unit described in the embodiment of the present disclosure may further include: a third control circuit 06 .

[0159] The third control circuit 06 can be coupled to the first power terminal VGL, the seventh node N7, and the second node N2, respectively, and can be used to control the seventh node N7 and the second node N2 to be conductive in response to the first power signal. The seventh node N7 can be coupled to the first control sub-circuit 031. That is, the third control circuit 06 can be connected in series between the first control sub-circuit 031 and the second node N2.

[0160] FIG8 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG8 , the shift register unit described in the embodiment of the present disclosure may further include: a fourth control circuit 07 .

[0161] The fourth control circuit 07 can be coupled to the discharge control terminal NCX, the second power terminal VGH and the first node N1 respectively, and can be used to control the connection and disconnection between the second power terminal VGH and the first node N1 in response to a discharge control signal provided by the discharge control terminal NCX.

[0162] For example, when the discharge control signal provided by the discharge control terminal NCX has a first potential, the fourth control circuit 07 can control the second power supply terminal VGH to be electrically connected to the first node N1. In this case, the second power signal provided by the second power supply terminal VGH can be transmitted to the first node N1. Furthermore, when the discharge control signal has a second potential, the fourth control circuit 07 can control the second power supply terminal VGH to be disconnected from the first node N1.

[0163] FIG9 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG9 , the shift register unit described in the embodiment of the present disclosure may further include: a fifth control circuit 08 .

[0164] The fifth control circuit 08 can be coupled to the first power terminal VGL, the third node N3 and the eighth node N8 respectively, and can be used to control the third node N3 and the eighth node N8 to be conductive in response to the first power signal.

[0165] Optionally, as an optional implementation, referring to Figure 9 , the eighth node N8 may be coupled to the second input circuit 02. That is, the fifth control circuit 08 may be connected in series between the second input circuit 02 and the third node N3.

[0166] Alternatively, as another optional implementation, referring to another shift register unit shown in FIG10 , it can be seen that the eighth node N8 can be coupled to the second control circuit 04. That is, the fifth control circuit 08 can be connected in series between the second control circuit 04 and the third node N3.

[0167] Taking the above shift register unit as an example, Figures 11 to 14 respectively show schematic structural diagrams of four different shift register units. As shown in Figures 9 and 10, the first input subcircuit 011 may include: a first transistor T1; the second input subcircuit 012 may include: a second transistor T2.

[0168] A gate of the first transistor T1 may be coupled to the first clock terminal CK1 , a first electrode of the first transistor T1 may be coupled to the input terminal IN, and a second electrode of the first transistor T1 may be coupled to the first node N1 .

[0169] A gate electrode and a first electrode of the second transistor T2 may both be coupled to the second node N2 , and a second electrode of the second transistor T2 may be coupled to the first node N1 .

[0170] Based on the above embodiments, it can be seen that in the disclosed embodiments, the second input sub-circuit 012 (i.e., the second transistor T2) can be coupled between the second node N2 and the first node N1, and can be in the form of a diode coupled in a direction from the first node N1 to the second node N2. Therefore, no current can flow from the second node N2 to the first node N1. Based on this, when the potential of the second node N2 is greater than the potential of the first node N1, the second transistor T2 is in a reverse diode coupling state, and the potential of the first node N1 can remain relatively constant. When the potential of the input signal provided by the input terminal IN is the second potential (i.e., a high potential), because the second transistor T2 acts as a reverse diode, the potential of the second node N2 does not affect the potential of the first node N1, thereby ensuring a good potential stability of the first node N1. When the potential of the first node N1 remains stable, the potential stability of the fifth node N5, which is continuously connected to the first node N1, can also be good. Furthermore, the tailing phenomenon can be reliably avoided when the second output sub-circuit 052 transmits the first power supply signal to the output terminal OUT based on the potential of the fifth node N5.

[0171] Furthermore, the second transistor T2, acting as a diode, is coupled between the second node N2 and the first node N1 and can function as a charge pump. For example, the potential of the second node N2, which is in the form of an AC signal, can be converted into a DC signal at the first node N1 by the second transistor T2. Based on this, it can be further seen that regardless of how the potential of the second node N2 changes, the potential of the first node N1 can still be maintained at a constant potential due to the charge pump operation of the second transistor T2, thus providing good stability.

[0172] Continuing to refer to FIG. 11 to FIG. 14 , it can be seen that the third input sub-circuit 021 may include: a third transistor T3 ; and the fourth input sub-circuit 022 may include: a fourth transistor T4 .

[0173] A gate of the third transistor T3 may be coupled to the first node N1 , a first electrode of the third transistor T3 may be coupled to the first clock terminal CK1 , and a second electrode of the third transistor T3 may be coupled to the third node N3 .

[0174] A gate of the fourth transistor T4 may be coupled to the first clock terminal CK1 , a first terminal of the fourth transistor T4 may be coupled to the first power supply terminal VGL, and a second terminal of the fourth transistor T4 may be coupled to the third node N3 .

[0175] 11 to 14 , it can be seen that the first control subcircuit 031 may include a fifth transistor T5 ; the second control subcircuit 032 may include a sixth transistor T6 and a seventh transistor T7 ; and the potential adjustment subcircuit 033 may include a first capacitor C1 .

[0176] A gate of the fifth transistor T5 may be coupled to the first clock terminal CK1 , a first electrode of the fifth transistor T5 may be coupled to the input terminal IN, and a second electrode of the fifth transistor T5 may be coupled to the second node N2 .

[0177] A gate of the sixth transistor T6 may be coupled to the third node N3 , a first electrode of the sixth transistor T6 may be coupled to the second power supply terminal VGH, and a second electrode of the sixth transistor T6 may be coupled to the sixth node N6 .

[0178] A gate of the seventh transistor T7 may be coupled to the second node N2 , a first electrode of the seventh transistor T7 may be coupled to the second clock terminal CK2 , and a second electrode of the seventh transistor T7 may be coupled to the sixth node N6 .

[0179] A first terminal of the first capacitor C1 may be coupled to the second node N2 , and a second terminal of the first capacitor C1 may be coupled to the sixth node N6 .

[0180] Among them, when the sixth transistor T6 is turned on, the second power supply signal of the second potential (i.e., high potential) provided by the second power supply terminal VGH can be transmitted to the sixth node N6. In this way, the coupling effect (or boosting effect) of the first capacitor C1 can be further improved. When the potential of the input signal provided by the input terminal IN is the first potential (i.e., low potential) and the low potential input signal is transmitted to the second node N2, the seventh transistor T7 can remain in the on state, and the potential of the sixth node N6 can change with the change of the potential of the second clock signal provided by the second clock terminal CK2. In addition, the first capacitor C1 is coupled between the second node N2 and the sixth node N6, and can be coupled to the first capacitor C1 according to the change of the potential of the sixth node N6. The potential of the second node N2 can swing within a certain potential range, and it can be seen that the potential of the second node N2 can change with the change of the potential of the second clock signal, thereby achieving flexible and reliable control of the potential of the second node N2.

[0181] 11 to 14 , it can be seen that the third control sub-circuit 041 may include: a ninth transistor T9 , a tenth transistor T10 , an eleventh transistor T11 and a second capacitor C2 ; and the fourth control sub-circuit 042 may include: a twelfth transistor T12 .

[0182] The gate of the ninth transistor T9 can be coupled to the third node N3, the first electrode of the ninth transistor T9 and the gate of the tenth transistor T10 can both be coupled to the second clock terminal CK2, the second electrode of the ninth transistor T9 can be coupled to the first electrode of the tenth transistor T10, and the second electrode of the tenth transistor T10 can be coupled to the fourth node N4.

[0183] A gate of the eleventh transistor T11 may be coupled to the first node N1 , a first electrode of the eleventh transistor T11 may be coupled to the second power supply terminal VGH, and a second electrode of the eleventh transistor T11 may be coupled to the fourth node N4 .

[0184] A first terminal of the second capacitor C2 may be coupled to the gate of the ninth transistor T9 , and a second terminal of the second capacitor C2 may be coupled to the second electrode of the ninth transistor T9 .

[0185] A gate of the twelfth transistor T12 may be coupled to the first power supply terminal VGL, a first electrode of the twelfth transistor T12 may be coupled to the first node N1 , and a second electrode of the twelfth transistor T12 may be coupled to the fifth node N5 .

[0186] Among them, the fourth control subcircuit 042 (i.e., the twelfth transistor T12) can be in a normally on state, which can limit the potential drop of the first node N1 and the potential drop of the fifth node N5. For example, in some embodiments, when the potential drop of the fifth node N5 is large, the twelfth transistor T12 can be used as a resistor to divide the potential between the first node N1 and the fifth node N5. In this way, even if the potential of the fifth node N5 changes greatly, the sudden increase of the source-drain voltage of the first transistor T1 can be reduced or prevented, and thus the first transistor T1 coupled to the first node N1 can be protected. When the potential of the fifth node N5 drops below the potential of the first power supply signal, the twelfth transistor T12 can divide the voltage, and the potential of the first node N1 can remain relatively stable. For example, the potential of the first node N1 can be no lower than the potential of the first power supply signal, and the bias stress that may be applied to the first transistor T1 can be alleviated. Thus, the potential of the first node N1 can be reliably stabilized at the desired first potential, so that the potential of the fifth node N5 can also be reliably stabilized at the desired first potential, and thus the transistor included in the second output sub-circuit 052 can be reliably, timely and quickly turned on to transmit the first power supply signal of the first potential to the output terminal OUT, avoiding the tailing phenomenon of the transmitted first power supply signal, that is, ensuring better output stability.

[0187] Continuing to refer to FIG. 11 to FIG. 14 , it can be seen that the first output sub-circuit 051 may include: a thirteenth transistor T13 and a third capacitor C3 ; and the second output sub-circuit 052 includes: a fourteenth transistor T14 .

[0188] A gate of the thirteenth transistor T13 may be coupled to the fourth node N4, a first electrode of the thirteenth transistor T13 may be coupled to the second power supply terminal VGH, and a second electrode of the thirteenth transistor T13 may be coupled to the output terminal OUT;

[0189] A first terminal of the third capacitor C3 may be coupled to the gate of the thirteenth transistor T13, and a second terminal of the third capacitor C3 may be coupled to the first electrode of the thirteenth transistor T13;

[0190] A gate of the fourteenth transistor T14 may be coupled to the fifth node N5 , a first electrode of the fourteenth transistor T14 may be coupled to the first power supply terminal VGL, and a second electrode of the fourteenth transistor T14 may be coupled to the output terminal OUT.

[0191] Continuing to refer to FIG. 11 to FIG. 14 , it can be seen that the fourth control circuit 07 may include: a fifteenth transistor T15 .

[0192] A gate of the fifteenth transistor T15 may be coupled to the discharge control terminal NCX, a first electrode of the fifteenth transistor T15 may be coupled to the second power supply terminal VGH, and a second electrode of the fifteenth transistor T15 may be coupled to the first node N1.

[0193] For example, at the moment of power-on, the potential of the discharge control signal provided by the discharge control terminal NCX can be set to the first potential, so that the fifteenth transistor T15 can be reliably turned on, and the second power supply terminal VGH transmits the second power supply signal of the second potential (i.e., high potential) to the first node N1 (i.e., to the fifth node N5) through the fifteenth transistor T15, so that the fourteenth transistor T14 can be reliably turned off, and the signal output by the output terminal OUT maintains the potential of the previous stage, or remains at a high potential, thereby solving the problem of screen flashing when power is on.

[0194] Continuing to refer to FIG. 12 and FIG. 13 , it can be seen that the fifth control circuit 08 may include: a sixteenth transistor T16 .

[0195] A gate of the sixteenth transistor T16 may be coupled to the first power supply terminal VGL, a first electrode of the sixteenth transistor T16 may be coupled to the eighth node N8 , and a second electrode of the sixteenth transistor T16 may be coupled to the third node N3 .

[0196] As an optional implementation, for the structure shown in FIG12 , it can be seen that the eighth node N8 is coupled to the third control sub-circuit 041, specifically, to the gate of the ninth transistor T9. Alternatively, as another optional implementation, for the structure shown in FIG12 , it can be seen that the eighth node N8 is coupled to the third input sub-circuit 021, specifically, to the second electrode of the third transistor T3.

[0197] Like the twelfth transistor T12, the sixteenth transistor T16 included in the fifth control circuit 08 can also be in a normally on state. On this basis, when the potential of the eighth node N8 drops significantly (e.g., drops to a potential lower than the potential of the first power supply signal) through the coupling effect of the second capacitor C2, the sixteenth transistor T16 can be used as a resistor to keep the potential of the third node N3 relatively stable, for example, so that the potential of the third node N3 is not lower than the potential of the first power supply signal. Furthermore, the bias stress that may be applied to the third transistor T3 and the fourth transistor T4 coupled to the third node N3 can be alleviated. Therefore, the third transistor T3 and the fourth transistor T4 can be protected from the influence of the potential change at the eighth node N8. That is, the third transistor T3 and the fourth transistor T4 can be protected.

[0198] Optionally, referring to FIG14 , it can be seen that the third control circuit 06 may include an eighth transistor T8 . FIG14 further illustrates a shift register unit based on FIG12 .

[0199] The gate of the eighth transistor T8 can be coupled to the first power supply terminal VGL, the first electrode of the eighth transistor T8 can be coupled to the seventh node N7, and the second electrode of the eighth transistor T8 can be coupled to the second node N2. The seventh node N7 is coupled to the first control sub-circuit O31, specifically, to the second electrode of the fifth transistor T5.

[0200] Like the twelfth transistor T12 and the sixteenth transistor T16, the eighth transistor T8 can also have a normally-on state. Furthermore, when the potential of the second node N2 drops to a level lower than the potential of the first power supply signal, the eighth transistor T8 can divide the potential of the second node N2 so that the potential of the coupling node between the fifth transistor T5 and the eighth transistor T8 (i.e., the seventh node N7) can remain relatively stable. For example, the potential of the seventh node N7, which can also be considered as the potential of the second electrode of the fifth transistor T5, is not lower than the potential of the first power supply signal. Thus, the bias stress that may have been applied to the fifth transistor T5 can also be reduced. That is, the eighth transistor T8 can perform the same function as the twelfth transistor T12 and the sixteenth transistor T16, protecting the fifth transistor T5 from the influence of the potential change at the second node N2.

[0201] Optionally, as described in the above embodiment, the transistors included in the shift register unit protected by the embodiment of the present disclosure (e.g., the first transistor T1 to the sixteenth transistor T16 shown in FIG14 ) can all be P-type transistors. On this basis, as described in the above embodiment, the first potential (i.e., the effective potential) can be a low potential, and the second potential (i.e., the ineffective potential) can be a high potential.

[0202] Optionally, taking the shift register unit shown in FIG14 , in which each transistor is a P-type transistor and correspondingly, the first potential is a low potential and the second potential is a high potential as an example, the working principle of the shift register unit described in the embodiment of the present disclosure is described as follows:

[0203] As can be seen from the timing simulation diagrams shown in Figures 15 and 16, in the disclosed embodiment, during the same time period, the first clock signal provided by the first clock terminal CK1 and the second clock signal provided by the second clock terminal CK2 can be opposite. Furthermore, within a cycle, the first potential of the first clock signal and the second clock signal are shorter than the duration of the second potential. Furthermore, it can be seen that the first potential of one of the first and second clock signals is within the time period of the second potential of the other clock signal. The second potential of the input signal provided by the input terminal IN can correspond to the potential of the second power signal, and the first potential of the input signal can correspond to the potential of the first power signal. Simultaneously, the low potential of the fifth node N5 can be similar to the value obtained by adding the absolute value of the threshold voltage of the twelfth transistor T12 to the potential of the first power signal. However, because the threshold voltage of the twelfth transistor T12 is very small compared to the potential of the first power signal, it can be assumed that the low potential of the fifth node N5, the potential of the first power signal, and the low potential of the input signal are substantially the same or similar to each other, thus avoiding the output step phenomenon.

[0204] The input terminal IN can provide a high-potential input signal, the potential of the first clock signal is a low potential, and the potential of the second clock signal is a high potential. Furthermore, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on. The tenth transistor T10 is turned off. Accordingly, the high-potential input signal can be transmitted to the first node N1 via the first transistor T1 and to the seventh node N7 via the fifth transistor T5. Because the twelfth transistor T12 and the eighth transistor T8 are normally on, the high-potential input signal transmitted to the first node N1 can be further transmitted to the fifth node N5 via the twelfth transistor T12, and the high-potential input signal transmitted to the seventh node N7 can be further transmitted to the second node N2 via the eighth transistor T8. Furthermore, the second transistor T2, the third transistor T3, the seventh transistor T7, and the eleventh transistor T11 are all turned off. In addition, the low-potential first power supply signal can be transmitted to the third node N3 via the fourth transistor T4. Because the sixteenth transistor T16 is normally on, the low-level first power signal transmitted to the third node N3 can be further transmitted to the eighth node N8 via the sixteenth transistor T16. The ninth transistor T9 and the sixth transistor T6 are both turned on, and the high-level second power signal can be transmitted to the seventh node N7 via the sixth transistor T6, thereby ensuring that the potential of the second node N2 is high. Subsequently, the potential of the second clock signal can jump to a low level, and the potential of the first clock signal can jump to a high level. On this basis, the tenth transistor T10 can be turned on, and the low-level second clock signal can be transmitted to the fourth node N4 via the tenth transistor T10. Furthermore, the thirteenth transistor T13 is turned on, and the high-level second power signal is transmitted to the output terminal OUT via the thirteenth transistor T13, and this continues until the potential of the input signal jumps to a low level.

[0205] When the potential of the input signal jumps to a low potential, and the potential of the first clock signal is a low potential, and the potential of the second clock signal is a high potential, the first transistor T1, the fifth transistor T5, and the fourth transistor T4 are turned on, and the tenth transistor T10 is turned off. Accordingly, the low-potential input signal can be transmitted to the first node N1 through the first transistor T1, and then transmitted to the fifth node N5 through the normally-on twelfth transistor T12, and the fourteenth transistor T14 is turned on. Furthermore, the low-potential first power supply signal can be transmitted to the output terminal OUT through the fourteenth transistor T14. In addition, the low-potential input signal can also be transmitted to the second node N2 through the fifth transistor T5 and the normally-on eighth transistor T8, the second transistor T2 and the seventh transistor T7 are turned on, and the high-potential second clock signal can be transmitted to the seventh node N7 through the seventh transistor T7, thereby adjusting the potential of the second node N2 to a high potential, and the second transistor T2 is turned off again, so that the potential of the first node N1 is not affected. In addition, the eleventh transistor T11 is turned on, and the high-voltage second power supply signal can be transmitted to the fourth node N4 via the eleventh transistor T11, ensuring that the thirteenth transistor T13 is reliably turned off. Furthermore, the third transistor T3 is turned on, and the low-voltage first clock signal is transmitted to the third node N3 via the third transistor T3, and the low-voltage first power supply signal is transmitted to the third node N3 via the fourth transistor T4, and then the normally-on sixteenth transistor T16 transmits the signal to the eighth node N8, and the ninth transistor T9 is turned on. However, because the tenth transistor T10 is turned off, it does not affect the voltage of the fourth node N4.

[0206] It should be noted that Figures 15 and 16 do not show the potential of the input signal, but both show the simulation schematic diagrams of the first clock signal provided by the first clock terminal CK1, the second clock signal provided by the second clock terminal CK2, and the signal output by the output terminal OUT of the adjacent two-stage shift register unit. In addition, Figure 16 also shows a potential simulation diagram of each node in the shift register unit. Among them, the ninth node N9 refers to the coupling node of the ninth transistor T9 and the tenth transistor T10. The horizontal axis refers to time, and the unit can be minutes (m); the vertical axis refers to voltage, and the unit can be volts (V). The horizontal and vertical axes are not shown in the figure. With reference to Figures 15 and 16, it can be seen that the signal output by the output terminal OUT of the shift register unit provided in the embodiment of the present disclosure has no steps in the process of jumping from a high potential to a low potential, that is, there is no tailing phenomenon, and the output stability of the shift register unit is good.

[0207] In summary, an embodiment of the present disclosure provides a shift register unit, which includes two input circuits, two control circuits and an output circuit. The input circuit can control the potential of the first node and the potential of the third node based on the clock signal provided by the coupled clock terminal, the power signal provided by the power terminal and the potential of the second node. The control circuit can control the potential of the fourth node and the fifth node based on the clock signal provided by the coupled clock terminal, the power signal provided by the power terminal, and the potentials of the first node, the second node and the third node. The output circuit can transmit the first power signal or the second power signal to the output terminal based on the potential of the fourth node and the fifth node. In this way, by flexibly setting the signals provided by each signal terminal, the signals of the required potential can be reliably transmitted to the fourth node and the fifth node, thereby making the output circuit fully and quickly turned on or off, avoiding the potential jump of the signal transmitted to the output terminal to appear steps, that is, avoiding the tailing phenomenon of the output signal, and ensuring better output stability.

[0208] FIG17 is a schematic diagram of the structure of a gate driving circuit provided by an embodiment of the present disclosure. As shown in FIG17 , the gate driving circuit includes: at least two cascaded shift register units 00 as shown in any one of FIG1 to FIG14 .

[0209] Among them, the input terminal IN of the first-stage shift register unit 00 can be coupled to the input start terminal STV, and in the other-stage shift register units 00 except the first-stage shift register unit 00, the input terminal IN of each stage shift register unit 00 can be coupled to the output terminal OUT of the cascaded previous-stage shift register unit 00.

[0210] FIG18 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG18 , the display device can include a display panel 100 and a gate driving circuit 000 as shown in FIG17 .

[0211] The display panel 100 may include a plurality of pixels (not shown in the figure), and the gate driving circuit 000 may be coupled to the pixel and may be used to transmit a gate driving signal to the plurality of pixels.

[0212] Optionally, as described in the above embodiment, the pixel circuit P1 may include a plurality of transistors, and the plurality of transistors may all be N-type oxide transistors.

[0213] Optionally, the display device may be any product or component with a display function, such as an AMOLED display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, or a navigation device.

[0214] It should be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0215] For example, the words "first", "second" or "third" and similar terms used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0216] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0217] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0218] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection.

[0219] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0220] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the gate drive circuit, shift register unit, each circuit and each sub-circuit described above can refer to the corresponding processes in the method embodiment and will not be repeated here.

[0221] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A shift register unit, comprising:a first input circuit (01), coupled to a first clock terminal (CK1), an input terminal (IN), a first node (Nl) and a second node (N2), and configured to control connection or disconnection between the input terminal (IN) and the first node (Nl) in response to a first clock signal provided by the first clock terminal (CK1), and control connection or disconnection between the second node (N2) and the first node (Nl) in response to a potential at the second node (N2);a second input circuit (02), coupled to the first node (Nl), the first clock terminal (CK1), a first power terminal (VGL) and a third node (N3), and configured to control connection or disconnection between the first clock terminal (CK1) and the third node (N3) in response to a potential at the first node (Nl), and control connection or disconnection between the first power terminal (VGL) and the third node (N3) in response to the first clock signal;a first control circuit (03), coupled to the input terminal (IN), the first clock terminal (CK1), the second node (N2), a second power terminal (VGH), a second clock terminal (CK2) and the third node (N3), and configured to control connection or disconnection between the input terminal (IN) and the second node (N2) in response to the first clock signal, control connection or disconnection between the second power terminal (VGH) and the second node (N2) in response to a potential at the third node (N3), and control connection or disconnection between the second clock terminal (CK2) and the second node (N2) in response to the potential at the second node (N2);a second control circuit (04), coupled to the third node (N3), the second clock terminal (CK2), the first node (Nl), the first power terminal (VGL), the second power terminal (VGH), a fourth node (N4) and a fifth node (N5), and configured to control connection or disconnection between the second clock terminal (CK2) and the fourth node (N4) in response to the potential at the third node (N3) and a second clock signal provided by the second clock terminal (CK2), control connection or disconnection between the second power terminal (VGH) and the fourth node (N4) in response to the potential at the first node (Nl), and control the first node (Nl) to be connected to the fifth node (N5) in response to a first power signal provided by the first power terminal (VGL); andan output circuit (05), coupled to the fourth node (N4), the fifth node (N5), the first power terminal (VGL), the second power terminal (VGH) and an output terminal (OUT), and configured to control connection or disconnection between the second power terminal (VGH) and the output terminal (OUT) in response to a potential at the fourth node (N4), and control connection or disconnection between the first power terminal (VGL) and the output terminal (OUT) in responseto a potential at the fifth node (N5).

2. The shift register unit according to claim 1, wherein the first input circuit (01) comprises: a first input sub-circuit (Oil) and a second input sub-circuit (012); whereinthe first input sub-circuit (Oil) is coupled to the first clock terminal (CK1), the input terminal (IN) and the first node (Nl), and is configured to control the connection or disconnection between the input terminal (IN) and the first node (Nl) in response to the first clock signal provided by the first clock terminal (CK1); andthe second input sub-circuit (012) is coupled to the second node (N2) and the first node (Nl), and is configured to control the connection or disconnection between the second node (N2) and the first node (Nl) in response to the potential at the second node (N2).

3. The shift register unit according to claim 2, wherein the first input sub-circuit (Oil) comprises a first transistor (Tl); and the second input sub-circuit (012) comprises a second transistor (T2); whereina gate of the first transistor (Tl) is coupled to the first clock terminal (CK1), a first electrode of the first transistor (Tl) is coupled to the input terminal (IN), and a second electrode of the first transistor (Tl) is coupled to the first node (Nl), anda gate and a first electrode of the second transistor (T2) are both coupled to the second node (N2), and a second electrode of the second transistor (T2) is coupled to the first node (Nl).

4. The shift register unit according to any one of claims 1 to 3, wherein the second input circuit (02) comprises: a third input sub-circuit (021) and a fourth input sub-circuit (022); whereinthe third input sub-circuit (021) is coupled to the first node (Nl), the first clock terminal (CK1) and the third node (N3), and is configured to control the connection or disconnection between the first clock terminal (CK1) and the third node (N3) in response to the potential at the first node (Nl); andthe fourth input sub-circuit (022) is coupled to the first clock terminal (CK1), the first power terminal (VGL) and the third node (N3), and is configured to control the connection or disconnection between the first power terminal (VGL) and the third node (N3) in response to the first clock signal.

5. The shift register unit according to claim 4, wherein the third input sub-circuit (021) comprises a third transistor (T3); and the fourth input sub-circuit (022) comprises a fourth transistor (T4); whereina gate of the third transistor (T3) is coupled to the first node (Nl), a first electrode of the third transistor (T3) is coupled to the first clock terminal (CK1), and a second electrode of the third transistor (T3) is coupled to the third node (N3); anda gate of the fourth transistor (T4) is coupled to the first clock terminal (CK1), a first electrode of the fourth transistor (T4) is coupled to the first power terminal (VGL), and a second electrode of the fourth transistor (T4) is coupled to the third node (N3).

6. The shift register unit according to any one of claims 1 to 5, wherein the first control circuit (03) comprises:a first control sub-circuit (031), coupled to the first clock terminal (CK1), the input terminal (IN) and the second node (N2), and configured to control the connection or disconnection between the input terminal (IN) and the second node (N2) in response to the first clock signal;a second control sub-circuit (032), coupled to the second node (N2), the second power terminal (VGH), the third node (N3), the second clock terminal (CK2) and a sixth node (N6), and configured to control connection or disconnection between the second power terminal (VGH) and the sixth node (N6) in response to the potential at the third node (N3), and control connection or disconnection between the second clock terminal (CK2) and the sixth node (N6) in response to the potential at the second node (N2); anda potential adjustment sub-circuit (033), coupled to the second node (N2) and the sixth node (N6), and configured to adjust the potential at the second node (N2) and a potential at the sixth node (N6).

7. The shift register unit according to claim 6, wherein the first control sub-circuit (031) comprises a fifth transistor (T5); the second control sub-circuit (032) comprises a sixth transistor (T6) and a seventh transistor (T7); and the potential adjustment sub-circuit (033) comprises a first capacitor (Cl); whereina gate of the fifth transistor (T5) is coupled to the first clock terminal (CK1), a first electrode of the fifth transistor (T5) is coupled to the input terminal (IN), and a second electrode of the fifth transistor (T5) is coupled to the second node (N2);a gate of the sixth transistor (T6) is coupled to the third node (N3), a first electrode of the sixth transistor (T6) is coupled to the second power terminal (VGH), and a second electrode of the sixth transistor (T6) is coupled to the sixth node (N6);a gate of the seventh transistor (T7) is coupled to the second node (N2), a first electrode of the seventh transistor (T7) is coupled to the second clock terminal (CK2), and a second electrode of the seventh transistor (T7) is coupled to the sixth node (N6); anda first terminal of the first capacitor (Cl) is coupled to the second node (N2), and a second terminal of the first capacitor (Cl) is coupled to the sixth node (N6).

8. The shift register unit according to claim 6, further comprising:a third control circuit (06), coupled to the first power terminal (VGL), a seventh node (N7) and the second node (N2), and configured to control the seventh node (N7) to be connected to the second node (N2) in response to the first power signal;wherein the seventh node (N7) is coupled to the first control sub-circuit (031).

9. The shift register unit according to claim 8, wherein the third control circuit (06) comprises an eighth transistor (T8); whereina gate of the eighth transistor (T8) is coupled to the first power terminal (VGL), a first electrode of the eighth transistor (T8) is coupled to the seventh node (N7), and a second electrode of the eighth transistor (T8) is coupled to the second node (N2).

10. The shift register unit according to any one of claims 1 to 9, wherein the second control circuit (04) comprises:a third control sub-circuit (041), coupled to the third node (N3), the second clock terminal (CK2), the second power terminal (VGH), the first node (Nl) and the fourth node (N4), and configured to control the connection or disconnection between the second clock terminal (CK2) and the fourth node (N4) in response to the potential at the third node (N3) and the second clock signal, and control the connection or disconnection between the second power terminal (VGH) and the fourth node (N4) in response to the potential at the first node (Nl); anda fourth control sub-circuit (042), coupled to the first power terminal (VGL), the first node (Nl) and the fifth node (N5), and configured to control the first node (Nl) to be connected to the fifth node (N5) in response to the first power signal.

11. The shift register unit according to claim 10, wherein the third control sub-circuit (041) comprises a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (Til) and a second capacitor (C2); and the fourth control sub-circuit (042) comprises a twelfth transistor (T12); whereina gate of the ninth transistor (T9) is coupled to the third node (N3), a first electrode of the ninth transistor (T9) and a gate of the tenth transistor (T10) are both coupled to the second clock terminal (CK2), a second electrode of the ninth transistor (T9) is coupled to a first electrode of the tenth transistor (T10), and a second electrode of the tenth transistor (T10) is coupled to the fourthnode (N4);a gate of the eleventh transistor (T11) is coupled to the first node (Nl), a first electrode of the eleventh transistor (Til) is coupled to the second power terminal (VGH), and a second electrode of the eleventh transistor (T11) is coupled to the fourth node (N4);a first terminal of the second capacitor (C2) is coupled to the gate of the ninth transistor (T9), and a second terminal of the second capacitor (C2) is coupled to the second electrode of the ninth transistor (T9); anda gate of the twelfth transistor (T12) is coupled to the first power terminal (VGL), a first electrode of the twelfth transistor (T12) is coupled to the first node (Nl), and a second electrode of the twelfth transistor (T12) is coupled to the fifth node (N5).

12. The shift register unit according to any one of claims 1 to 11, wherein the output circuit (05) comprises: a first output sub-circuit (051) and a second output sub-circuit (052); whereinthe first output sub-circuit (051) is coupled to the fourth node (N4), the second power terminal (VGH) and the output terminal (OUT), and is configured to control the connection or disconnection between the second power terminal (VGH) and the output terminal (OUT) in response to the potential at the fourth node (N4); andthe second output sub-circuit (052) is coupled to the fifth node (N5), the first power terminal (VGL) and the output terminal (OUT), and is configured to control the connection or disconnection between the first power terminal (VGL) and the output terminal (OUT) in response to the potential at the fifth node (N5).

13. The shift register unit according to claim 12, wherein the first output sub-circuit (051) comprises a thirteenth transistor (T13) and a third capacitor (C3); and the second output sub-circuit (052) comprises a fourteenth transistor (T14); whereina gate of the thirteenth transistor (T13) is coupled to the fourth node (N4), a first electrode of the thirteenth transistor (T13) is coupled to the second power terminal (VGH), and a second electrode of the thirteenth transistor (T13) is coupled to the output terminal (OUT);a first terminal of the third capacitor (C3) is coupled to the gate of the thirteenth transistor (T13), and a second terminal of the third capacitor (C3) is coupled to the first electrode of the thirteenth transistor (T13); anda gate of the fourteenth transistor (T14) is coupled to the fifth node (N5), a first electrode of the fourteenth transistor (T14) is coupled to the first power terminal (VGL), and a second electrode of the fourteenth transistor (T14) is coupled to the output terminal (OUT).

14. The shift register unit according to any one of claims 1 to 13, further comprising: a fourth control circuit (07); whereinthe fourth control circuit (07) is coupled to a discharge control terminal (NCX), the second power terminal (VGH) and the first node (Nl), and is configured to control connection or disconnection between the second power terminal (VGH) and the first node (Nl) in response to a discharge control signal provided by the discharge control terminal (NCX).

15. The shift register unit according to claim 14, wherein the fifth control circuit (06) comprises: a fifteenth transistor (T15); whereina gate of the fifteenth transistor (T15) is coupled to the discharge control terminal (NCX), a first electrode of the fifteenth transistor (T15) is coupled to the second power terminal (VGH), and a second electrode of the fifteenth transistor (T15) is coupled to the first node (Nl).

16. The shift register unit according to any one of claims 1 to 15, further comprising:a fifth control circuit (08), coupled to the first power terminal (VGL), the third node (N3) and an eighth node (N8), and configured to control the third node (N3) to be connected to the eighth node (N8) in response to the first power signal;wherein the eighth node (N8) is coupled to the second input circuit (02), or the eighth node (N8) is coupled to the second control circuit (04).

17. The shift register unit according to claim 16, wherein the fifth control circuit (08) comprises: a sixteenth transistor (T16); whereina gate of the sixteenth transistor (T16) is coupled to the first power terminal (VGL), a first electrode of the sixteenth transistor (T16) is coupled to the eighth node (N8), and a second electrode of the sixteenth transistor (T16) is coupled to the third node (N3).

18. A shift register unit, comprising:a first input transistor (Tl), wherein a gate of the first input transistor (Tl) is coupled to a first clock terminal (CK1), a first electrode of the first input transistor (Tl) is coupled to an input terminal (IN), and a second electrode of the first input transistor (Tl) is coupled to a first node (Nl), and the first input transistor (Tl) is configured to control connection or disconnection between the input terminal (IN) and the first node (Nl) in response to a first clock signal provided by the first clock terminal (CK1);a second input transistor (T2), wherein a gate and a first electrode of the second input transistor (T2) are coupled to a second node (N2), and a second electrode of the second inputtransistor (T2) is coupled to the first node (Nl), and the second input transistor (T2) is configured to control connection or disconnection between the second node (N2) and the first node (Nl) in response to a potential at the second node (N2),a second input circuit (02), coupled to the first node (Nl), the first clock terminal (CK1) and a third node (N3), and configured to control connection or disconnection between the first clock terminal (CK1) and the third node (N3) in response to a potential at the first node (Nl);a first control circuit (03), coupled to the input terminal (IN), the first clock terminal (CK1) and the second node (N2), and configured to control connection or disconnection between the input terminal (IN) and the second node (N2) in response to the first clock signal;a second control circuit (04), coupled to the third node (N3), a second clock terminal (CK2), the first node (Nl), a first power terminal (VGL), a fourth node (N4) and a fifth node (N5), and configured to control connection or disconnection between the second clock terminal (CK2) and the fourth node (N4) in response to a potential at the third node (N3) and a second clock signal provided by the second clock terminal (CK2), and control the first node (Nl) to be connected to the fifth node (N5) in response to a first power signal provided by the first power terminal (VGL); andan output circuit (05), coupled to the fourth node (N4), the fifth node (N5), the first power terminal (VGL), a second power terminal (VGH) and an output terminal (OUT), and configured to control connection or disconnection between the second power terminal (VGH) and the output terminal (OUT) in response to a potential at the fourth node (N4), and control connection or disconnection between the first power terminal (VGL) and the output terminal (OUT) in response to a potential at the fifth node (N5).

19. The shift register unit according to claim 18, whereinthe second input circuit (02) is further coupled to the first power terminal (VGL), and is configured to control connection or disconnection between the first power terminal (VGL) and the third node (N3) in response to the first clock signal;the second input circuit (02) comprises a third transistor (T3) and a fourth transistor (T4); whereina gate of the third transistor (T3) is coupled to the first node (Nl), a first electrode of the third transistor (T3) is coupled to the first clock terminal (CK1), and a second electrode of the third transistor (T3) is coupled to the third node (N3); anda gate of the fourth transistor (T4) is coupled to the first clock terminal (CK1), a first electrode of the fourth transistor (T4) is coupled to the first power terminal (VGL), and a second electrode of the fourth transistor (T4) is coupled to the third node (N3).

20. The shift register unit according to claim 18 or 19, whereinthe first control circuit (03) is further coupled to the second power terminal (VGH), the second clock terminal (CK2) and the third node (N3), and is configured to control connection or disconnection between the second power terminal (VGH) and the second node (N2) in response to the potential at the third node (N3), and control connection or disconnection between the second clock terminal (CK2) and the second node (N2) in response to the potential at the second node (N2);the first control circuit (03) comprises a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a first capacitor (Cl); whereina gate of the fifth transistor (T5) is coupled to the first clock terminal (CK1), a first electrode of the fifth transistor (T5) is coupled to the input terminal (IN), and a second electrode of the fifth transistor (T5) is coupled to the second node (N2);a gate of the sixth transistor (T6) is coupled to the third node (N3), a first electrode of the sixth transistor (T6) is coupled to the second power terminal (VGH), and a second electrode of the sixth transistor (T6) is coupled to a second electrode of the seventh transistor (T7);a gate of the seventh transistor (T7) is coupled to the second node (N2), and a first electrode of the seventh transistor (T7) is coupled to the second clock terminal (CK2); anda first terminal of the first capacitor (Cl) is coupled to the second node (N2), and a second terminal of the first capacitor (Cl) is coupled to the second electrode of the seventh transistor (T7).

21. The shift register unit according to any one of claims 18 to 20, whereinthe second control circuit (04) is further coupled to the second power terminal (VGH), and is configured to control connection or disconnection between the second power terminal (VGH) and the fourth node (N4) in response to the potential at the first node (Nl);the second control circuit (04) comprises a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a twelfth transistor (T12), and a second capacitor (C2); whereina gate of the ninth transistor (T9) is coupled to the third node (N3), a first electrode of the ninth transistor (T9) and a gate of the tenth transistor (T10) are both coupled to the second clock terminal (CK2), a second electrode of the ninth transistor (T9) is coupled to a first electrode of the tenth transistor (T10), and a second electrode of the tenth transistor (T10) is coupled to the fourth node (N4);a gate of the eleventh transistor (Til) is coupled to the first node (Nl), a first electrode of the eleventh transistor (Til) is coupled to the second power terminal (VGH), and a secondelectrode of the eleventh transistor (Til) is coupled to the fourth node (N4);a first terminal of the second capacitor (C2) is coupled to the gate of the ninth transistor (T9), and a second terminal of the second capacitor (C2) is coupled to the second electrode of the ninth transistor (T9); anda gate of the twelfth transistor (T12) is coupled to the first power terminal (VGL), a first electrode of the twelfth transistor (T12) is coupled to the first node (Nl), and a second electrode of the twelfth transistor (T12) is coupled to the fifth node (N5).

22. The shift register unit according to any one of claims 18 to 21, wherein the output circuit (05) comprises: a thirteenth transistor (T13), a fourteenth transistor (T14), and a third capacitor (C3); whereina gate of the thirteenth transistor (T13) is coupled to the fourth node (N4), a first electrode of the thirteenth transistor (T13) is coupled to the second power terminal (VGH), and a second electrode of the thirteenth transistor (T13) is coupled to the output terminal (OUT);a first terminal of the third capacitor (C3) is coupled to the gate of the thirteenth transistor (T13), and a second terminal of the third capacitor (C3) is coupled to the first electrode of the thirteenth transistor (T13); anda gate of the fourteenth transistor (T14) is coupled to the fifth node (N5), a first electrode of the fourteenth transistor (T14) is coupled to the first power terminal (VGL), and a second electrode of the fourteenth transistor (T14) is coupled to the output terminal (OUT).

23. A gate driver circuit, comprising: at least two cascaded shift register units according to any one of claims 1 to 22; whereinan input terminal (IN) of a first stage of shift register unit (00) is coupled to an input enable terminal (STV), and in other stages of shift register units (00) other than the first stage of shift register unit (00), an input terminal (IN) of each stage of shift register unit (00) is coupled to an output terminal (OUT) of a cascaded previous stage of shift register unit (00).

24. A display device, comprising: a display panel (100) and the gate driver circuit (000) according to claim 23; whereinthe display panel (100) comprises a plurality of pixels, and the gate driver circuit (000) is coupled to the plurality of pixels and configured to transmit gate driving signals to the plurality of pixels.

Images