Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises a first region which comprises a plurality of rows of pixel circuits; the second area comprises a first start control line, a first driving circuit and a plurality of clock signal lines, the first start control line is electrically connected with the first driving circuit, and the first driving circuit comprises multiple stages of shift register units; in the shift register unit, a plurality of clock ends are electrically connected with a plurality of clock signal lines respectively, and N shift output ends are electrically connected with adjacent N rows of pixel circuits respectively; in a first working mode, a plurality of clock ends in the shift register unit receive different clock signals, so that N shift output ends output gate driving signals in a time-sharing manner; and in the second working mode, two clock ends in the shift register unit receive the same clock signal, so that the N shift output ends simultaneously output gate driving signals. In the invention, the display panel adopts the second working mode, so that the charging time of each row of pixel circuits can be prolonged, or the refresh rate can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of display technology, displays can switch between high resolution and low resolution.

[0003] In a display, the driving circuit set in the non-display area is an indispensable circuit structure, which is used to realize the display, touch and other functions of the display panel. At present, the high and low resolution switching of the display is mainly based on pattern change, and the working condition of the driving circuit in the non-display area does not change.

[0004] Therefore, existing displays can no longer meet the demand for higher refresh rates. Summary of the invention

[0005] The present invention provides a display panel and a display device to solve the problem that the display cannot meet the demand for a higher refresh rate.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising: a first area and a second area;

[0007] The first region includes a plurality of rows of pixel circuits;

[0008] The second area includes a first start control line, a first drive circuit and a plurality of clock signal lines, the first start control line is electrically connected to the first drive circuit, the first drive circuit includes a multi-stage shift register unit; the shift register unit includes a plurality of clock terminals and N shift output terminals, the plurality of clock terminals are electrically connected to the plurality of clock signal lines respectively, the N shift output terminals are electrically connected to adjacent N rows of pixel circuits respectively, N≥2;

[0009] The display panel includes a first operating mode and a second operating mode;

[0010] In the first working mode, the multiple clock terminals in the shift register unit receive different clock signals provided by the multiple clock signal lines, so that the N shift output terminals of the shift register unit output gate driving signals in time division;

[0011] In the second working mode, there are two clock terminals in the shift register unit to receive the same clock signal provided by the two clock signal lines, so that the N shift output terminals of the shift register unit output gate driving signals simultaneously.

[0012] According to another aspect of the present invention, a display device is provided, comprising: the display panel as described above.

[0013] In the present invention, the N shift output terminals of the shift register unit are electrically connected to the adjacent N rows of pixel circuits respectively; in the first working mode, a plurality of clock signal lines provide different clock signals, so that the N shift output terminals of the shift register unit output gate drive signals in time division, and the pixel circuits of each row in the first area are scanned row by row; in the second working mode, there are two clock terminals in the shift register unit that receive the same clock signal provided by the two clock signal lines, so that the N shift output terminals of the shift register unit simultaneously output gate drive signals, and the N rows of pixel circuits electrically connected to the shift register unit are scanned simultaneously. Based on this, no matter what resolution the display panel is at, the display panel adopts the second working mode, which can increase the charging time of each row of pixel circuits, which is beneficial to improving the pixel charging rate and reducing the power consumption of the display panel; or, adopting the second working mode is beneficial to improving the refresh rate of the display panel, so that the display panel can be compatible with a higher refresh rate at a low resolution.

[0014] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 yes Figure 1 A timing diagram of the display panel shown;

[0018] Figure 3 is a schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0019] Figure 4 yes Figure 3 A timing diagram of the shift register unit shown;

[0020] Figure 5 is a schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 7 yes Figure 6 A timing diagram of the display panel in the first working mode;

[0023] Figure 8 yes Figure 6 A timing diagram of the display panel in the second working mode;

[0024] Fig. 9 is a schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0025] Fig.10 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.11 yes Fig.10 A timing diagram of the display panel in the first working mode;

[0027] Fig.12 yes Fig.10 A timing diagram of the display panel in the second working mode;

[0028] Fig.13 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, such as Figure 1The display panel shown includes: a first area 101 and a second area 102; the first area 101 includes a plurality of rows of pixel circuits 103; the second area 102 includes a first start control line STV, a first drive circuit 104 and a plurality of clock signal lines CKL, the first start control line STV is electrically connected to the first drive circuit 104, the first drive circuit 104 includes a multi-stage shift register unit 105; the shift register unit 105 includes a plurality of clock terminals CK and N shift output terminals Gout, the plurality of clock terminals CK are electrically connected to the plurality of clock signal lines CKL, and the N shift output terminals Gout are electrically connected to the respective N adjacent rows of pixel circuits 103, N ≥ 2; the display panel includes a first working mode and a second working mode; in the first working mode, multiple clock terminals CK in the shift register unit 105 receive different clock signals provided by multiple clock signal lines CKL, so that the N shift output terminals Gout of the shift register unit 105 output gate drive signals in a time-sharing manner; in the second working mode, there are two clock terminals CK in the shift register unit 105 that receive the same clock signal provided by two clock signal lines CKL, so that the N shift output terminals Gout of the shift register unit 105 simultaneously output gate drive signals.

[0032] In this embodiment, the display panel may be a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, a quantum dot light emitting diode display panel, etc. The display panel may be a 2D display panel or a 3D display panel. The present invention does not limit the light emitting type and structure of the display panel. The display panel includes a first area 101 and a second area 102. The first area 101 may be a display area of ​​the display panel, and the second area 102 may be a non-display area outside the display area.

[0033] The first area 101 is used for display, and accordingly, the first area 101 includes a plurality of pixel circuits 103, and the pixel circuits 103 are electrically connected to the light-emitting element or the display electrode (not shown) to realize the driving of the light-emitting element or the display electrode to ensure the display of the light-emitting element or the display electrode. Optionally, a plurality of pixel circuits 103 in the first area 101 are arranged in a row along the row direction to form a row of pixel circuits 103, and a plurality of pixel circuits 103 are arranged in a column along the column direction to form a column of pixel circuits 103. However, the arrangement of the pixel circuits in the first area can also be other arrangement methods, not limited to the array arrangement method. The light-emitting element in the first area 101 can be an organic light-emitting display unit, a micro light-emitting diode display unit, or other types of display units, without specific restrictions.

[0034] The second area 102 includes a circuit structure for driving the pixel circuit 103 in the first area 101. Specifically, the second area 102 includes at least a first driving circuit 104. The first driving circuit 104 is used to drive the pixel circuit 103 in the first area 101 to drive the light-emitting element or the display electrode, so that the first area 101 can display. The first driving circuit 104 in the second area 102 is used to control the scanning of multiple rows of pixel circuits 103 in the first area 101.

[0035] The second area 102 further includes a plurality of signal lines, and the plurality of signal lines in the second area 102 are electrically connected to the first driving circuit 104. The plurality of signal lines electrically connected to the first driving circuit 104 at least include a first start control line STV and a plurality of clock signal lines CKL. Figure 1 1 shows that the second area 102 includes at least four clock signal lines CKL, which are marked as the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, and the fourth clock signal line CKL4. The first start control line STV is electrically connected to the first drive circuit 104, and is used to provide a start control signal to the first drive circuit 104 to trigger the first drive circuit 104 to work. The clock signal line CKL is electrically connected to the first drive circuit 104, and is used to provide a clock signal to the first drive circuit 104. Specifically, the first drive circuit 104 scans and drives the pixel circuits 103 of each row in the first area 101 in response to the control of the start control signal provided by the first start control line STV and the clock signals provided by the multiple clock signal lines CKL. Among them, the start control signal provided by the first start control line STV controls the start working time of the first drive circuit 104, and the clock signal provided by each clock signal line CKL controls the scanning drive mode of the first drive circuit 104 to the pixel circuits 103 of each row in the first area 101.

[0036] The first driving circuit 104 includes a multi-stage shift register unit 105; the shift register unit 105 includes multiple clock terminals CK and N shift output terminals Gout, the multiple clock terminals CK are electrically connected to multiple clock signal lines CKL respectively, and the N shift output terminals Gout are electrically connected to adjacent N rows of pixel circuits 103 respectively, N≥2. Figure 1 , it is shown that the shift register unit 105 includes four clock terminals CK, which are respectively marked as a clock terminal CK1, a clock terminal CK2, a clock terminal CK3, and a clock terminal CK4. Figure 1It is shown that the shift register unit 105 includes two shift output terminals Gout, which are marked as shift output terminal Gout1 and shift output terminal Gout2 respectively. A clock terminal CK in the shift register unit 105 is connected to a clock signal line CKL to receive a clock signal. The two clock signal lines CKL connected to the same clock terminal CK (such as CK1) of two different shift register units 105 may be the same or different. Under the condition of ensuring the normal operation of the product, the connection relationship between the clock terminal CK and the clock signal line CKL in the shift register unit 105 can be reasonably designed to meet the product requirements.

[0037] The N shift output terminals Gout of the shift register unit 105 are respectively electrically connected to the adjacent N rows of pixel circuits 103, where N≥2. Exemplarily, the first driving circuit 104 includes a first-stage shift register unit VSR(1), a second-stage shift register unit VSR(2), ..., sequentially arranged along the column direction, and the first area 101 includes a first-row pixel circuit 131, a second-row pixel circuit 132, a third-row pixel circuit 133, a fourth-row pixel circuit 134, ..., sequentially arranged along the column direction. The first start control line STV is electrically connected to the first-stage shift register unit VSR(1) for providing a start control signal to the first-stage shift register unit VSR(1) to trigger the first driving circuit 104 to operate. The two shift output terminals Gout of the first-stage shift register unit VSR(1) are respectively electrically connected to the adjacent first-row pixel circuit 131 and second-row pixel circuit 132, wherein the shift output terminal Gout1 is electrically connected to the first-row pixel circuit 131, and the shift output terminal Gout2 is electrically connected to the second-row pixel circuit 132; the two shift output terminals Gout of the second-stage shift register unit VSR(2) are respectively electrically connected to the adjacent third-row pixel circuit 133 and fourth-row pixel circuit 134, wherein the shift output terminal Gout1 is electrically connected to the third-row pixel circuit 133, and the shift output terminal Gout2 is electrically connected to the fourth-row pixel circuit 134; and so on. In other embodiments, according to the structure of different shift register units, the number of clock terminals of the shift register unit is not limited to 4, and the number of shift output terminals of the shift register unit is not limited to 2; according to the display requirements of the display panel, the N rows of pixel circuits electrically connected to the N shift output terminals of the shift register unit can be adjacent N rows or can be spaced apart; there is no specific restriction.

[0038] Based on the above display panel structure, the display panel includes two different working modes, namely the first working mode and the second working mode. The working mode of the display panel can be set independently, and the working mode of the display panel can be switched by controlling the timing of multiple clock signal lines in the second area 102.

[0039] When the display panel is in the first working mode, the multiple clock terminals CK in the shift register unit 105 receive different clock signals provided by the multiple clock signal lines CKL, so that the N shift output terminals Gout of the shift register unit 105 output gate drive signals in time division, that is, the multiple clock signal lines CKL are controlled to transmit clock signals corresponding to the first working mode, so that the first drive circuit 104 can work in the first working mode, and the corresponding control of the scanning driving mode of each row of pixel circuits 103 in the first area 101 is row-by-row scanning. Accordingly, in the first working mode, the scanning driving mode of the N rows of pixel circuits 103 electrically connected to the shift register unit 105 is row-by-row scanning.

[0040] When the display panel is in the second working mode, there are two clock terminals CK in the shift register unit 105 to receive the same clock signal provided by two clock signal lines CKL, so that the N shift output terminals Gout of the shift register unit 105 simultaneously output gate drive signals, that is, the multiple clock signal lines CKL are controlled to transmit the clock signal corresponding to the second working mode, so that the first drive circuit 104 can work in the second working mode, and the corresponding control shift register unit 105 corresponds to the scanning drive mode of the electrically connected N rows of pixel circuits 103 for simultaneous scanning.

[0041] As described above, in the second working mode, the scanning driving mode of the N rows of pixel circuits 103 electrically connected to the shift register unit 105 is simultaneous scanning. The display panel switches the resolution. For example, the display panel switches from high resolution to low resolution, and the display panel executes the second working mode. If the total scanning driving time for displaying a frame of the picture in the second working mode is consistent with the first working mode, the charging time of each row of pixel circuits 103 can be increased in the second working mode, which is conducive to improving the pixel charging rate, and the scanning driving times of the clock signal provided by the clock signal line can be reduced, which is conducive to reducing the power consumption of the display panel, and realizing the increase of pixel charging time at low resolution. Alternatively, if the charging time of each row of pixel circuits 103 in the second working mode is consistent with the first working mode, the total scanning driving time for displaying a frame of the picture in the second working mode is reduced, which is conducive to improving the refresh rate of the display panel, so that the display panel can be compatible with a higher refresh rate at low resolution.

[0042] It can be understood that the second area also includes a driving chip, which provides the required electrical signals to each signal line in the second area, thereby controlling the display panel to display. Figure 1 The driver chip is not shown.

[0043] In the present invention, the N shift output terminals of the shift register unit are electrically connected to the adjacent N rows of pixel circuits respectively; in the first working mode, a plurality of clock signal lines provide different clock signals, so that the N shift output terminals of the shift register unit output gate drive signals in time division, and the pixel circuits of each row in the first area are scanned row by row; in the second working mode, there are two clock terminals in the shift register unit that receive the same clock signal provided by the two clock signal lines, so that the N shift output terminals of the shift register unit simultaneously output gate drive signals, and the N rows of pixel circuits electrically connected to the shift register unit are scanned simultaneously. Based on this, no matter what resolution the display panel is at, the display panel adopts the second working mode, which can increase the charging time of each row of pixel circuits, which is beneficial to improving the pixel charging rate and reducing the power consumption of the display panel; or, adopting the second working mode is beneficial to improving the refresh rate of the display panel, so that the display panel can be compatible with a higher refresh rate at a low resolution.

[0044] Optionally, in the first working mode, the effective pulse width of the gate drive signal is H, and H is equal to the scanning time of a row of pixel circuits in the display panel. Optionally, in the second working mode, the effective pulse width of the gate drive signal is N*H, and H is equal to the scanning time of a row of pixel circuits in the display panel. Exemplarily, the first drive circuit is electrically connected to Na rows of pixel circuits, and Na is greater than N.

[0045] In this embodiment, in the first working mode, multiple clock signal lines provide different clock signals to multiple clock terminals in the shift register unit, so that the N shift output terminals of the shift register unit output gate drive signals in time-sharing, and the pixel circuits in each row in the first area are scanned row by row, and the N rows of pixel circuits electrically connected to the 1-level shift register unit are scanned row by row, then the total scanning drive time for displaying a frame of the picture is Na*H, and the number of scanning drives of the clock signal provided by the clock signal line is Na.

[0046] In the second working mode, there are two clock ends in the shift register unit that receive the same clock signal provided by two clock signal lines, so that the N shift output ends of the shift register unit simultaneously output gate drive signals, and the N rows of pixel circuits electrically connected to the corresponding one-level shift register unit are scanned simultaneously. Then, the total scanning drive time for displaying a frame of the picture is (Na / N)*N*H=Na*H, and the number of scanning drives of the clock signal provided by the clock signal line is (Na / N).

[0047] As described above, when the total scanning drive time for displaying a frame of picture remains consistent, the charging time of each row of pixel circuits can be increased in the second working mode, which is beneficial to improving the pixel charging rate. In addition, the number of scanning drives of the display panel can be reduced, which is beneficial to reducing the power consumption of the display panel.

[0048] In other embodiments, according to product requirements, the total scanning drive time for displaying a frame of picture in the first working mode can be designed to be different from the total scanning drive time for displaying a frame of picture in the second working mode; or, in the first working mode, the effective pulse width of the gate drive signal can be designed to be greater than or equal to H; or, in the second working mode, the effective pulse width of the gate drive signal can be designed to be less than or equal to N*H.

[0049] Figure 2 yes Figure 1 A timing diagram of the display panel is shown in FIG. Figure 2 As shown, the optional second area 102 includes Ya clock signal lines CKL, Ya≥4; among the Ya clock signal lines CKL, the frequencies of the clock signals provided by any two clock signal lines CKL are the same.

[0050] In this embodiment, the second area 102 includes a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, and a fourth clock signal line CKL4. The frequencies of the clock signals of the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, and the fourth clock signal line CKL4 are all the same.

[0051] In the first operation mode, the phases of the clock signals of the first clock signal line CKL1 , the second clock signal line CKL2 , the third clock signal line CKL3 , and the fourth clock signal line CKL4 are different.

[0052] In the second working mode, among the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3 and the fourth clock signal line CKL4, at least two clock signal lines CKL have the same clock signal phase. Exemplarily, the phase of the clock signal of the first clock signal line CKL1 is the same as the phase of the clock signal of the second clock signal line CKL2, and the phase of the clock signal of the third clock signal line CKL3 is the same as the phase of the clock signal of the fourth clock signal line CKL4.

[0053] Understandably, Figure 2 The timing of the four clock signal lines CKL shown is only an example. If required by the product, the frequency and phase of the clock signal provided by each clock signal line CKL can be reasonably adjusted.

[0054] like Figure 2As shown, the optional second area 102 includes the 1st clock signal line to the Yath clock signal line, Ya≥4; in the first working mode, the phase of the clock signal provided by the jth clock signal line is earlier than the phase of the clock signal provided by the (j+1)th clock signal line, and the phase difference between the two is a*H, 1≤j≤Ya; in the second working mode, the clock signal provided by the (2j-1)th clock signal line is the same as the clock signal provided by the (2j)th clock signal line, and the phase difference between the clock signal provided by the (2j-2)th clock signal line and the clock signal provided by the (2j)th clock signal line is b*H, 1≤2j≤Ya; a and b are both positive integers, and H is equal to the scanning time of a row of pixel circuits in the display panel.

[0055] In this embodiment, the optional second area 102 includes a first clock signal line CKL1 to a fourth clock signal line CKL4 .

[0056] In the first working mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is a*H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is a*H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is a*H; the phase of the clock signal provided by the fourth clock signal line CKL4 and the phase of the clock signal provided by the first clock signal line CKL1, the phase difference between the two is a*H. Optional a=1, if the product requires, the value of a can be reasonably adjusted, but not limited to this.

[0057] In the second working mode, the clock signal provided by the first clock signal line CKL1 is the same as the clock signal provided by the second clock signal line CKL2, the clock signal provided by the third clock signal line CKL3 is the same as the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the clock signal provided by the second clock signal line CKL2 and the clock signal provided by the fourth clock signal line CKL4 is b*H. b=N is optional, and the value of b can be reasonably adjusted if the product requires it, but it is not limited thereto.

[0058] Figure 3 is a schematic diagram of a shift register unit provided by an embodiment of the present invention, such as Figure 3As shown, the optional shift register unit 105 includes: a node control module 151, electrically connected to the input terminal IN, the first input clock terminal CKA, the second input clock terminal CKB, the first node Q1 and the second node Q2, for controlling the signals of the first node Q1 and the second node Q2; N shift output modules 152, the i-th shift output module 152 is electrically connected to the first node Q1, the second node Q2, the i-th control clock terminal CKO, the first level signal terminal VG1 and the i-th shift output terminal Gout, for controlling the signal of the i-th shift output terminal Gout, 1≤i≤N. Figure 3 N=2 can be selected, then the shift register unit 105 includes two shift output modules 152, namely the first shift output module 152(1) and the second shift output module 152(2). Correspondingly, the shift register unit 105 includes two control clock terminals CKO, namely the control clock terminal CKO(1) electrically connected to the first shift output module 152(1), and the control clock terminal CKO(2) electrically connected to the second shift output module 152(2). The shift register unit 105 also includes two shift output terminals Gout, namely the shift output terminal Gout1 electrically connected to the first shift output module 152(1), and the shift output terminal Gout2 electrically connected to the second shift output module 152(2).

[0059] In this embodiment, the shift register unit 105 includes a node control module 151. The node control module 151 is electrically connected to an input terminal IN, a first input clock terminal CKA, and a second input clock terminal CKB. The input terminal IN provides an input signal, wherein the input signal of the input terminal IN of the first-stage shift register unit VSR(1) in the first driving circuit 104 is a start control signal provided by the first start control line STV. The first input clock terminal CKA is a clock terminal CK of the shift register unit 105, which is used to receive a clock signal provided by a clock signal line CKL. The second input clock terminal CKB is another clock terminal CK of the shift register unit 105, which is used to receive a clock signal provided by a clock signal line CKL.

[0060] The node control module 151 is also electrically connected to the first node Q1 and the second node Q2, respectively. In response to the control of the signal provided by the input terminal IN, the clock signal provided by the first input clock terminal CKA, and the clock signal provided by the second input clock terminal CKB, the node control module 151 controls the signal of the first node Q1 so that the signal of the first node Q1 jumps to a corresponding high level or low level, and also controls the signal of the second node Q2 so that the signal of the second node Q2 jumps to a corresponding high level or low level.

[0061] The shift register unit 105 includes N shift output modules 152. The shift output module 152 is electrically connected to the first node Q1, the second node Q2, the control clock terminal CKO and the first level signal terminal VG1 respectively. The control clock terminal CKO in the shift output module 152 is a clock terminal CK of the shift register unit 105, which is used to receive a clock signal provided by a clock signal line CKL. The first level signal terminal VG1 provides a first level signal, which can be reasonably designed as a fixed high level or a fixed low level according to the scanning drive mode of the display panel. Of course, if the product requires it, the first level signal can also be reasonably designed as an electrical signal with high and low level jumps.

[0062] The shift output module 152 is also electrically connected to the shift output terminal Gout. The shift output module 152 controls the signal of the shift output terminal Gout in response to the signal provided by the first node Q1, the signal provided by the second node Q2, the clock signal provided by the control clock terminal CKO, and the first level signal provided by the first level signal terminal VG1, so that the signal of the shift output terminal Gout jumps to a corresponding high level or low level.

[0063] Specifically, the shift register unit 105 scans and drives the N rows of pixel circuits 103 in response to the clock signals provided by the multiple clock signal lines CKL and the signals provided by other terminals. In the first working mode, the multiple clock signal lines CKL provide different clock signals, so that the N shift output terminals Gout of the shift register unit 105 output gate drive signals in time division, thereby realizing the row-by-row scanning of the N rows of pixel circuits 103. In the second working mode, at least two clock signal lines CKL provide the same clock signal, so that there are two clock terminals CK in the shift register unit 105 that receive the same clock signal, and then the N shift output terminals Gout of the shift register unit 105 simultaneously output gate drive signals, thereby realizing the simultaneous scanning of the N rows of pixel circuits 103.

[0064] As described above, the display panel adopts the second working mode, which can increase the charging time of each row of pixel circuits, which is beneficial to improving the pixel charging rate and reducing the power consumption of the display panel; it is also beneficial to increase the refresh rate of the display panel, making the display panel compatible with a higher refresh rate.

[0065] Figure 4 yes Figure 3 A timing diagram of the shift register unit shown in FIG. Figure 4As shown, in the second working mode, in the shift register unit 105, the first input clock terminal CKA and the second input clock terminal CKB receive the same input clock signal, and the N control clock terminals CKO receive the same control clock signal; the input clock signal is different from the control clock signal. In the first working mode, in the shift register unit 105, the first input clock terminal CKA, the second input clock terminal CKB, and the N control clock terminals CKO receive different clock signals.

[0066] In this embodiment, in the first working mode, the clock signal received by the first input clock terminal CKA, the clock signal received by the second input clock terminal CKB, the clock signal received by the control clock terminal CKO(1) and the clock signal received by the control clock terminal CKO(2) in the shift register unit 105 are different. In this way, the shift register unit 105 responds to the control of multiple clock signals, and its shift output terminal Gout1 and the shift output terminal Gout2 output the gate drive signal in a time-sharing manner.

[0067] In the second working mode, the clock signal received by the first input clock terminal CKA and the clock signal received by the second input clock terminal CKB in the shift register unit 105 are the same, and the clock signal received by the control clock terminal CKO(1) and the clock signal received by the control clock terminal CKO(2) are the same. However, the input clock signal received by the first input clock terminal CKA is different from the control clock signal received by the control clock terminal CKO. In this way, the shift register unit 105 responds to the control of multiple clock signals, and its shift output terminal Gout1 and shift output terminal Gout2 simultaneously output gate drive signals.

[0068] As described above, the effective level width output by the shift output terminal Gout in the second working mode may be greater than the effective level width output by the shift output terminal Gout in the first working mode, so that the charging time of a row of pixel circuits 103 in the second working mode may be increased.

[0069] In other embodiments, if the effective level width output by the shift output terminal Gout in the second working mode is equal to the effective level width output by the shift output terminal Gout in the first working mode, then the total scanning drive time of a frame of the picture in the second working mode is reduced, thereby improving the refresh rate of the display panel.

[0070] Figure 5 is a schematic diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 5As shown, the optional node control module 151 includes: a first node sub-module 153, electrically connected to the second node Q2, the first input clock terminal CKA and the first node Q1, for controlling the signal of the first node Q1; a second node sub-module 154, electrically connected to the second input clock terminal CKB, the input terminal IN and the second node Q2, for controlling the signal of the second node Q2; a third node sub-module 155, electrically connected to the first input clock terminal CKA, the second level signal terminal VG2 and the first node Q1, for controlling the signal of the first node Q1.

[0071] In this embodiment, the node control module 151 includes a first node submodule 153 , a second node submodule 154 and a third node submodule 155 .

[0072] The first node submodule 153 is electrically connected to the second node Q2, the first input clock terminal CKA and the first node Q1 respectively. The control terminal of the optional first node submodule 153 is electrically connected to the second node Q2, the input terminal of the first node submodule 153 is electrically connected to the first input clock terminal CKA, and the output terminal of the first node submodule 153 is electrically connected to the first node Q1. The first node submodule 153 is turned on or off in response to the control of the signal of the second node Q2, so as to control the signal of the first node Q1 according to the clock signal provided by the first input clock terminal CKA. Specifically, if the signal of the second node Q2 is the on level (i.e., the valid level) that turns on the first node submodule 153, the first node submodule 153 is turned on, the clock signal provided by the first input clock terminal CKA is written into the first node Q1, and the signal of the first node Q1 changes with the high and low level jump of the clock signal provided by the first input clock terminal CKA; if the signal of the second node Q2 is the off level (i.e., the invalid level) that turns off the first node submodule 153, the first node submodule 153 is turned off.

[0073] The second node submodule 154 is electrically connected to the second input clock terminal CKB, the input terminal IN, and the second node Q2, respectively. The control terminal of the optional second node submodule 154 is electrically connected to the second input clock terminal CKB, the input terminal of the second node submodule 154 is electrically connected to the input terminal IN, and the output terminal of the second node submodule 154 is electrically connected to the second node Q2. The second node submodule 154 is turned on or off in response to the control of the clock signal of the second input clock terminal CKB, thereby controlling the signal of the second node Q2 according to the input signal provided by the input terminal IN. Specifically, if the clock signal of the second input clock terminal CKB is a turn-on level that turns on the second node submodule 154, the second node submodule 154 is turned on, and the input signal provided by the input terminal IN is written into the second node Q2; if the clock signal of the second input clock terminal CKB is a turn-off level that turns off the second node submodule 154, the second node submodule 154 is turned off.

[0074] The third node submodule 155 is electrically connected to the first input clock terminal CKA, the second level signal terminal VG2 and the first node Q1 respectively. The control terminal of the optional third node submodule 155 is electrically connected to the first input clock terminal CKA, the input terminal of the third node submodule 155 is electrically connected to the second level signal terminal VG2, the output terminal of the third node submodule 155 is electrically connected to the first node Q1, and the third node submodule 155 is turned on or off in response to the control of the clock signal of the first input clock terminal CKA, so as to control the signal of the first node Q1 according to the second level signal provided by the second level signal terminal VG2. Specifically, if the clock signal of the first input clock terminal CKA is the on level that turns on the third node submodule 155, the third node submodule 155 is turned on, and the second level signal provided by the second level signal terminal VG2 is written into the first node Q1; if the clock signal of the first input clock terminal CKA is the off level that turns off the third node submodule 155, the third node submodule 155 is turned off. The second level signal terminal VG2 provides a second level signal, which can be reasonably designed as a fixed high level or a fixed low level according to the scanning driving mode of the display panel. Of course, if the product requires, the second level signal can also be reasonably designed as an electrical signal with high and low level jumps.

[0075] In this embodiment, the optional first node submodule 153 includes a transistor M11, and the gate of the transistor M11 is electrically connected to the second node Q2. The second node submodule 154 includes a transistor M12, and the gate of the transistor M12 is electrically connected to the second input clock terminal CKB. The third node submodule 155 includes a transistor M13, and the gate of the transistor M13 is electrically connected to the first input clock terminal CKA. The optional transistor M11, the transistor M12 and the transistor M13 can all be NMOS.

[0076] like Figure 5 As shown, the optional shift output module 152 includes: a first output submodule 156, electrically connected to the first node Q1, the first level signal terminal VG1 and the shift output terminal Gout, used to control the signal of the shift output terminal Gout; a second output submodule 157, electrically connected to the second node Q2, the control clock terminal CKO and the shift output terminal Gout, used to control the signal of the shift output terminal Gout.

[0077] In this embodiment, the shift output module 152 includes a first output submodule 156 and a second output submodule 157 .

[0078] The first output submodule 156 is electrically connected to the first node Q1, the first level signal terminal VG1 and the shift output terminal Gout, respectively. The control terminal of the optional first output submodule 156 is electrically connected to the first node Q1, the input terminal of the first output submodule 156 is electrically connected to the first level signal terminal VG1, and the output terminal of the first output submodule 156 is electrically connected to the shift output terminal Gout. The first output submodule 156 is turned on or off in response to the control of the signal of the first node Q1, so as to control the signal of the shift output terminal Gout according to the first level signal provided by the first level signal terminal VG1. Specifically, if the signal of the first node Q1 is the on-level that turns on the first output submodule 156, the first output submodule 156 is turned on, and the first level signal provided by the first level signal terminal VG1 is written into the shift output terminal Gout; if the signal of the first node Q1 is the off-level that turns off the first output submodule 156, the first output submodule 156 is turned off.

[0079] The second output submodule 157 is electrically connected to the second node Q2, the control clock terminal CKO and the shift output terminal Gout, respectively. The control terminal of the optional second output submodule 157 is electrically connected to the second node Q2, the input terminal of the second output submodule 157 is electrically connected to the control clock terminal CKO, the output terminal of the second output submodule 157 is electrically connected to the shift output terminal Gout, and the second output submodule 157 is turned on or off in response to the control of the signal of the second node Q2, thereby controlling the signal of the shift output terminal Gout according to the clock signal provided by the control clock terminal CKO. Specifically, if the signal of the second node Q2 is the on-level that turns on the second output submodule 157, the second output submodule 157 is turned on, the clock signal provided by the control clock terminal CKO is written to the shift output terminal Gout, and the signal of the shift output terminal Gout changes with the high and low level jump of the clock signal provided by the control clock terminal CKO; if the signal of the second node Q2 is the off-level that turns off the second output submodule 157, the second output submodule 157 is turned off.

[0080] like Figure 5 As shown, the optional shift output module 152 includes: a potential holding submodule 158, and the second output submodule 157 is electrically connected to the second node Q2 through the potential holding submodule 158; the potential holding submodule 158 is also electrically connected to the second level signal terminal VG2, which is used to control the signal of the second node Q2 to be transmitted to the second output submodule 157.

[0081] In this embodiment, the control end of the optional potential maintaining submodule 158 is electrically connected to the second level signal terminal VG2, the input end of the potential maintaining submodule 158 is electrically connected to the second node Q2, and the output end of the potential maintaining submodule 158 is electrically connected to the control end of the second output submodule 157. The potential maintaining submodule 158 is turned on or off in response to the control of the second level signal of the second level signal terminal VG2, thereby controlling the conduction or shutdown of the second output submodule 157 according to the signal provided by the second node Q2. Specifically, if the second level signal of the second level signal terminal VG2 is the on-level that turns on the potential holding submodule 158, the potential holding submodule 158 is turned on, and the signal provided by the second node Q2 is written into the control end of the second output submodule 157, and the second output submodule 157 is turned on or off in response to the signal control of the second node Q2; if the second level signal of the second level signal terminal VG2 is the off-level that turns off the potential holding submodule 158, the potential holding submodule 158 is turned off, and the second output submodule 157 maintains the on state or the off state in response to the signal control of the output terminal Q21 of the potential holding submodule 158.

[0082] As described above, the second level signal of the optional second level signal terminal VG2 is a fixed level signal, and the second level signal is the on-level for turning on the potential holding submodule 158. During the operation of the first drive circuit 104, the potential holding submodule 158 remains in the on state, and the second output submodule 157 is turned on or off in response to the signal control of the second node Q2.

[0083] In this embodiment, in the optional shift output module 152 (1), the first output submodule 156 includes a transistor M14, the gate of which is electrically connected to the first node Q1, the second output submodule 157 includes a transistor M15, the gate of which is electrically connected to the node Q21, and the potential holding submodule 158 includes a transistor M16, the gate of which is electrically connected to the second level signal terminal VG2. In the optional shift output module 152 (2), the first output submodule 156 includes a transistor M17, the gate of which is electrically connected to the first node Q1, the second output submodule 157 includes a transistor M18, the gate of which is electrically connected to the node Q21, and the potential holding submodule 158 includes a transistor M19, the gate of which is electrically connected to the second level signal terminal VG2. The optional transistors M14, M15, M16, M17, M18, and M19 may all be NMOS.

[0084] like Figure 5As shown, the optional shift register unit 105 also includes: a first coupling submodule 159, electrically connected between the first node Q1 and the first level signal terminal VG1; the shift output module 152 includes: a second coupling submodule 160, electrically connected between the output terminal Q21 of the potential holding submodule 158 and the shift output terminal Gout.

[0085] In this embodiment, the optional first coupling submodule 159 includes a capacitor C11, the second coupling submodule 160 in the shift output module 152 (1) includes a capacitor C12, and the second coupling submodule 160 in the shift output module 152 (2) includes a capacitor C13.

[0086] like Figure 5 As shown, the optional node control module 151 includes: at least one of a forward scan control submodule 161 and a reverse scan control submodule 162; the forward scan control submodule 161 is electrically connected to the first forward scan signal terminal SZA, the second forward scan signal terminal SZB and the input terminal IN, and is used to control the signal of the input terminal IN; the reverse scan control submodule 162 is electrically connected to the first reverse scan signal terminal SFA, the second reverse scan signal terminal SFB and the input terminal IN, and is used to control the signal of the input terminal IN; the forward scan control submodule 161 and the reverse scan control submodule 162 are turned on in time sharing.

[0087] In this embodiment, the optional node control module 151 includes a forward scanning control submodule 161 and a reverse scanning control submodule 162, and the first drive circuit 104 can perform forward scanning and reverse scanning. When the first drive circuit 104 performs forward scanning, the forward scanning control submodule 161 remains turned on and the reverse scanning control submodule 162 remains turned off. When the first drive circuit 104 performs reverse scanning, the forward scanning control submodule 161 remains turned off and the reverse scanning control submodule 162 remains turned on.

[0088] The input end of the optional forward scanning control submodule 161 is electrically connected to the first forward scanning signal end SZA, the control end of the forward scanning control submodule 161 is electrically connected to the second forward scanning signal end SZB, and the output end of the forward scanning control submodule 161 is electrically connected to the input end IN. When the first driving circuit 104 performs forward scanning, the forward scanning control submodule 161 remains turned on, and the signal received by the first forward scanning signal end SZA is transmitted to the input end IN.

[0089] The input end of the optional reverse scan control submodule 162 is electrically connected to the first reverse scan signal end SFA, the control end of the reverse scan control submodule 162 is electrically connected to the second reverse scan signal end SFB, and the output end of the reverse scan control submodule 162 is electrically connected to the input end IN. When the first driving circuit 104 performs reverse scanning, the reverse scan control submodule 162 remains turned on, and the signal received by the first reverse scan signal end SFA is transmitted to the input end IN.

[0090] In other embodiments, the node control module may optionally include a forward sweep control submodule, or the node control module may include a reverse sweep control submodule, or the node control module may include neither a forward sweep control submodule nor a reverse sweep control submodule.

[0091] like Figure 5 As shown, the optional forward scan control submodule 161 includes a transistor M20, the gate of which is electrically connected to the second forward scan signal terminal SZB, and the reverse scan control submodule 162 includes a transistor M21, the gate of which is electrically connected to the second reverse scan signal terminal SFB. The optional transistors M21 and M22 may both be NMOS.

[0092] It is optional that one of the first level signal terminal and the second level signal terminal has the same signal as the second positive scanning signal terminal; and the other of the first level signal terminal and the second level signal terminal has the same signal as the second reverse scanning signal terminal. Figure 5 As shown, when the scanning order of the display panel is forward scanning, the signal of the optional first level signal terminal VG1 and the signal of the second reverse scanning signal terminal SFB are the same, both are low level; the signal of the second level signal terminal VG2 and the signal of the second forward scanning signal terminal SZB are the same, both are high level, so that the forward scanning control submodule 161 is turned on. Of course, when the scanning order of the display panel changes, such as switching to reverse scanning, the signal of the optional second level signal terminal VG2 and the signal of the second reverse scanning signal terminal SFB are the same, both are high level, so that the reverse scanning control submodule 162 is turned on; the signal of the first level signal terminal VG1 and the signal of the second forward scanning signal terminal SZB are the same, both are low level.

[0093] It can be understood that, when required by the product, the type of transistors in the shift register unit can be reasonably designed and is not limited to NMOS; illustratively, the multiple transistors in the shift register unit may include at least one NMOS transistor and at least one PMOS transistor, or, the multiple transistors in the shift register unit may all be PMOS transistors, or, the multiple transistors in the shift register unit may all be NMOS transistors.

[0094] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention, which may be Figure 6 The structure of the shift register unit 105 is as follows: Figure 5 As shown. The first forward scan signal terminal SZA of the Mth shift register unit 105 can be electrically connected to the first shift output terminal Gout of the (M-1)th shift register unit 105; the first reverse scan signal terminal SFA of the Mth shift register unit 105 can be electrically connected to the Nth shift output terminal Gout of the (M+1)th shift register unit 105. N=2 is optional.

[0095] For the first-stage shift register unit VSR1, the first forward scan signal terminal SZA of the first-stage shift register unit VSR1 is electrically connected to the first start control line STV, and the first reverse scan signal terminal SFA of the first-stage shift register unit VSR1 is electrically connected to the second shift output terminal Gout2 of the second-stage shift register unit VSR2 to receive the gate drive signal Gout(4).

[0096] For the second-stage shift register unit VSR2, the first positive scan signal terminal SZA of the second-stage shift register unit VSR2 is electrically connected to the first shift output terminal Gout1 of the first-stage shift register unit VSR1 to receive the gate drive signal Gout(1), and the first negative scan signal terminal SFA of the second-stage shift register unit VSR2 is electrically connected to the second shift output terminal Gout2 of the third-stage shift register unit VSR3 to receive the gate drive signal Gout(6).

[0097] For the third-stage shift register unit VSR3, the first forward scan signal terminal SZA of the third-stage shift register unit VSR3 is electrically connected to the first shift output terminal Gout1 of the second-stage shift register unit VSR2 to receive the gate drive signal Gout(3), and the first reverse scan signal terminal SFA of the third-stage shift register unit VSR3 is electrically connected to the second shift output terminal Gout2 of the fourth-stage shift register unit VSR4 to receive the gate drive signal Gout(8). And so on.

[0098] like Figure 6 As shown, N=2 is optional; the second area 102 includes the first clock signal line CKL1 to the fourth clock signal line CKL4; the first driving circuit 104 includes a multi-stage shift register circuit 106, the shift register circuit 106 includes a 2-stage shift register unit 105, and the shift register circuit 106 satisfies the following conditions: the first input clock terminal CKA of the first stage shift register unit (for example, VSR1) is electrically connected to the second clock signal line CKL2, the second input clock terminal CKB is electrically connected to the first clock signal line CKL1, and the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the third The clock signal line CKL3, the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the fourth clock signal line CKL4; the first input clock terminal CKA of the second-stage shift register unit (e.g., VSR2) is electrically connected to the fourth clock signal line CKL4, the second input clock terminal CKB is electrically connected to the third clock signal line CKL3, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the first clock signal line CKL1, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the second clock signal line CKL2.

[0099] Figure 7 yes Figure 6The timing diagram of the display panel in the first working mode is shown. Here, the first driving circuit can be selected to be forward scanning. The shift register circuit 106 composed of the third-stage shift register unit VSR3 and the fourth-stage shift register unit VSR4 is taken as an example to describe the working process of the forward scanning. The working process of the shift register circuit 106 is as follows:

[0100] In stage t11, the gate drive signal Gout(3) outputted from the first shift output terminal Gout1 of the second-stage shift register unit VSR2 is at a high level, and the clock signal provided by the first clock signal line CKL1 is at a high level; then in the third-stage shift register unit VSR3, the transistor M13 is turned off, the transistor M12 is turned on, the second node Q2 is at a high level to turn on the transistors M11, M15 and M18, the first node Q1 is at a low level to turn off the transistors M14 and M17, the gate drive signal Gout(5) outputted from the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(6) outputted from the shift output terminal Gout2 is at a low level.

[0101] In the t12 stage, the clock signal provided by the second clock signal line CKL2 is at a high level; then in the third-stage shift register unit VSR3, the transistor M13 is turned on, the transistor M12 is turned off, the second node Q2 maintains a high level to turn on the transistors M11, M15 and M18, the first node Q1 is at a high level to turn on the transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level.

[0102] In the t13 stage, the clock signal provided by the third clock signal line CKL3 is at a high level; then in the third-stage shift register unit VSR3, the transistors M13 and M12 are turned off, the second node Q2 maintains a high level to turn on the transistors M11, M15 and M18, the first node Q1 is at a low level to turn off the transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level.

[0103] In the t14 stage, the clock signal provided by the fourth clock signal line CKL4 is at a high level; then in the third-stage shift register unit VSR3, the transistors M13 and M12 are turned off, the second node Q2 maintains a high level to turn on the transistors M11, M15 and M18, the first node Q1 maintains a low level to turn off the transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level.

[0104] After stage t14, in the third-stage shift register unit VSR3, the gate driving signal Gout(5) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(6) outputted from the shift output terminal Gout2 is at a low level.

[0105] Similarly, for the fourth-stage shift register unit VSR4, at stage t13, the transistor M12 is turned on, the second node Q2 is at a high level, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level; at stage t15, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level; at stage t16, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a high level. After stage t16, in the fourth-stage shift register unit VSR4, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level.

[0106] Figure 8 yes Figure 6 The timing diagram of the display panel in the second working mode is shown. Here, the first driving circuit can be selected to be forward scanning. The shift register circuit 106 composed of the third-stage shift register unit VSR3 and the fourth-stage shift register unit VSR4 is taken as an example to describe the working process of the forward scanning. The working process of the shift register circuit 106 is as follows:

[0107] In the stage from t21 to t22, the gate drive signal Gout(3) outputted from the first shift output terminal Gout1 of the second-stage shift register unit VSR2 is at a high level, the clock signal provided by the first clock signal line CKL1 is at a high level, and the clock signal provided by the second clock signal line CKL2 is at a high level; then in the third-stage shift register unit VSR3, the transistors M13 and M12 are turned on, the second node Q2 is at a high level to turn on the transistors M11, M15 and M18, the first node Q1 is at a high level to turn on the transistors M14 and M17, the gate drive signal Gout(5) outputted from the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(6) outputted from the shift output terminal Gout2 is at a low level.

[0108] In the stage from t23 to t24, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; then in the third-stage shift register unit VSR3, the transistors M13 and M12 are turned off, the second node Q2 maintains a high level to turn on the transistors M11, M15 and M18, the first node Q1 is at a low level to turn off the transistors M14 and M17, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level.

[0109] After stage t24, in the third-stage shift register unit VSR3, the gate driving signal Gout(5) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(6) outputted from the shift output terminal Gout2 is at a low level.

[0110] Similarly, for the fourth-stage shift register unit VSR4, during the period from t23 to t24, the first node Q1 is at a high level, the second node Q2 is at a high level, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level; during the period from t25 to t26, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a high level. After the period from t26, in the fourth-stage shift register unit VSR4, the gate drive signal Gout(7) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(8) output by the shift output terminal Gout2 is at a low level.

[0111] In this embodiment, in the first working mode, multiple clock signal lines provide different clock signals, so that the N shift output terminals of the shift register unit output gate drive signals in time division, and the pixel circuits of each row in the first area are scanned row by row; in the second working mode, there are two clock terminals in the shift register unit that receive the same clock signal provided by two clock signal lines, so that the N shift output terminals of the shift register unit simultaneously output gate drive signals, and the N rows of pixel circuits electrically connected to the shift register unit are scanned simultaneously. Based on this, the display panel adopts the second working mode, which can increase the charging time of each row of pixel circuits, which is beneficial to improve the pixel charging rate and reduce the power consumption of the display panel; or, adopting the second working mode is beneficial to improve the refresh rate of the display panel, so that the display panel can be compatible with a higher refresh rate.

[0112] Fig. 9 is a schematic diagram of another shift register unit provided by an embodiment of the present invention, and Figure 5 There are differences. The following only describes Fig. 9 Different from Figure 5 part, Fig. 9 Zhongyu Figure 5 The same structure will not be described again here.

[0113] like Fig. 9 As shown, the optional node control module 151 includes: a first node submodule 201, electrically connected to the second node Q2, the first level signal terminal VG1 and the first node Q1, for controlling the signal of the first node Q1; a second node submodule 202, electrically connected to the first node Q1, the first level signal terminal VG1 and the second node Q2, for controlling the signal of the second node Q2; a third node submodule 203, electrically connected to the first input clock terminal CKA, the second input clock terminal CKB, the second level signal terminal VG2 and the first node Q1, for controlling the signal of the first node Q1; the input terminal IN is the second node Q2.

[0114] In this embodiment, the control end of the first node submodule 201 is electrically connected to the second node Q2, and the first node submodule 201 responds to the control of the signal of the second node Q2 to turn on or off the transmission path between the first level signal end VG1 and the first node Q1. The control end of the second node submodule 202 is electrically connected to the first node Q1, and the second node submodule 202 responds to the control of the signal of the first node Q1 to turn on or off the transmission path between the first level signal end VG1 and the second node Q2.

[0115] The optional third node submodule 203 includes: a first control subunit 204, electrically connected to the first control signal terminal VC1, the first input clock terminal CKA and the third node Q3, for controlling the signal of the third node Q3; a second control subunit 205, electrically connected to the second control signal terminal VC2, the second input clock terminal CKB and the third node Q3, for controlling the signal of the third node Q3; a third control subunit 206, electrically connected to the third node Q3, the second level signal terminal VG2 and the first node Q1, for controlling the signal of the first node Q1.

[0116] In this embodiment, the control end of the first control subunit 204 is electrically connected to the first control signal end VC1. The first control subunit 204 turns on or off the transmission path between the first input clock end CKA and the third node Q3 in response to the control of the signal of the first control signal end VC1.

[0117] The control end of the second control subunit 205 is electrically connected to the second control signal end VC2. The second control subunit 205 switches on or off the transmission path between the second input clock end CKB and the third node Q3 in response to the control of the signal of the second control signal end VC2.

[0118] The control end of the third control subunit 206 is electrically connected to the third node Q3. The third control subunit 206 turns on or off the transmission path between the second level signal terminal VG2 and the first node Q1 in response to the control of the signal of the third node Q3.

[0119] In this embodiment, the optional first node submodule 201 includes a transistor M31, and the gate of the transistor M31 is electrically connected to the second node Q2. The second node submodule 202 includes a transistor M32, and the gate of the transistor M32 is electrically connected to the first node Q1. The first control subunit 204 includes a transistor M33, and the gate of the transistor M33 is electrically connected to the first control signal terminal VC1. The second control subunit 205 includes a transistor M34, and the gate of the transistor M34 is electrically connected to the second control signal terminal VC2. The third control subunit 206 includes a transistor M35, and the gate of the transistor M35 is electrically connected to the third node Q3.

[0120] Fig. 9 The structure of the shift output module 152 is Figure 5 The same structure is not repeated here, and the same structure is used Figure 5 's reference numerals.

[0121] It is optional that one of the first level signal terminal and the second level signal terminal has the same signal as the first control signal terminal; and the other of the first level signal terminal and the second level signal terminal has the same signal as the second control signal terminal. Fig. 9As shown, the optional second level signal terminal VG2 has the same signal as the first control signal terminal VC1, both of which are high level; the first level signal terminal VG1 has the same signal as the second control signal terminal VC1, both of which are low level.

[0122] like Fig. 9 As shown, the optional node control module 151 includes: at least one of a forward scan control submodule 207 and a reverse scan control submodule 208; the forward scan control submodule 207 is electrically connected to the first forward scan signal terminal SZA, the second forward scan signal terminal SZB and the input terminal IN, and is used to control the signal of the input terminal IN; the reverse scan control submodule 208 is electrically connected to the first reverse scan signal terminal SFA, the second reverse scan signal terminal SFB and the input terminal IN, and is used to control the signal of the input terminal IN; the forward scan control submodule 207 and the reverse scan control submodule are turned on in time sharing.

[0123] Fig. 9 The center scanning control submodule 207 and Figure 5 The difference is that Fig. 9 The control end of the forward scanning control submodule 207 is electrically connected to the first forward scanning signal end SZA, the input end of the forward scanning control submodule 207 is electrically connected to the second forward scanning signal end SZB, and the output end of the forward scanning control submodule 207 is electrically connected to the input end IN. When the first driving circuit 104 performs forward scanning, the forward scanning control submodule 207 is turned on accordingly, and the signal of the second forward scanning signal end SZB is transmitted to the input end IN.

[0124] Fig. 9 The reverse scan control submodule 208 and Figure 5 The difference is that Fig. 9 The control end of the reverse scan control submodule 208 is electrically connected to the first reverse scan signal end SFA, the input end of the reverse scan control submodule 208 is electrically connected to the second reverse scan signal end SFB, and the output end of the reverse scan control submodule 208 is electrically connected to the input end IN. When the first driving circuit 104 performs reverse scanning, the reverse scan control submodule 208 is turned on accordingly, and the signal of the second reverse scan signal end SFB is transmitted to the input end IN.

[0125] like Fig. 9 As shown, the optional forward scan control submodule 207 includes a transistor M36, the gate of which is electrically connected to the first forward scan signal terminal SZA, and the reverse scan control submodule 208 includes a transistor M37, the gate of which is electrically connected to the first reverse scan signal terminal SFA. The optional transistors M36 and M37 can both be NMOS.

[0126] like Fig. 9As shown, when the scanning order of the display panel is forward scanning, the signal of the optional first level signal terminal VG1 is the same as the signal of the second reverse scanning signal terminal SFB, both of which are low level; the signal of the second level signal terminal VG2 is the same as the signal of the second forward scanning signal terminal SZB, both of which are high level. Of course, when the scanning order of the display panel changes, such as switching to reverse scanning, the signal of the optional second level signal terminal VG2 is the same as the signal of the second reverse scanning signal terminal SFB, both of which are high level; the signal of the first level signal terminal VG1 is the same as the signal of the second forward scanning signal terminal SZB, both of which are low level.

[0127] Fig.10 is a schematic diagram of another display panel provided by an embodiment of the present invention, which can be optionally Fig.10 The structure of the shift register unit 105 is as follows: Fig. 9 As shown. The first forward scan signal terminal SZA of the Mth shift register unit 105 can be electrically connected to the first shift output terminal Gout of the (M-1)th shift register unit 105; the first reverse scan signal terminal SFA of the Mth shift register unit 105 can be electrically connected to the Nth shift output terminal Gout of the (M+1)th shift register unit 105. N=2 is optional.

[0128] like Fig.10 As shown, N=2 is optional; the second area 102 includes the first clock signal line CKL1 to the sixth clock signal line CKL6; the first driving circuit 104 includes a multi-stage shift register circuit 210, the shift register circuit 210 includes a 3-stage shift register unit 105, and the shift register circuit 210 satisfies the following conditions:

[0129] The first input clock terminal CKA of the first stage shift register unit (e.g., VSR1) is electrically connected to the fourth clock signal line CKL4, the second input clock terminal CKB is electrically connected to the fifth clock signal line CKL5, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the first clock signal line CKL1, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the second clock signal line CKL2;

[0130] The first input clock terminal CKA of the second-stage shift register unit (e.g., VSR2) is electrically connected to the sixth clock signal line CKL6, the second input clock terminal CKB is electrically connected to the first clock signal line CKL1, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the third clock signal line CKL3, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the fourth clock signal line CKL4;

[0131] The first input clock terminal CKA of the third-stage shift register unit (e.g., VSR3) is electrically connected to the second clock signal line CKL2, the second input clock terminal CKB is electrically connected to the third clock signal line CKL3, the control clock terminal CKO(1) of the first shift output module 152(1) is electrically connected to the fifth clock signal line CKL5, and the control clock terminal CKO(2) of the second shift output module 152(2) is electrically connected to the sixth clock signal line CKL6.

[0132] Fig.11 yes Fig.10 The timing diagram of the display panel in the first working mode is shown. Here, the first driving circuit can be selected to be forward scanning. The shift register circuit 210 composed of the first-stage shift register unit VSR1, the second-stage shift register unit VSR2 and the third-stage shift register unit VSR3 is taken as an example to describe the working process of the forward scanning. The working process of the shift register circuit 210 is as follows:

[0133] 1) For the first-stage shift register unit VSR1:

[0134] In the stage t31, the start control signal provided by the first start control line STV is at a high level, and the clock signal provided by the first clock signal line CKL1 is at a high level; the transistor M36 is turned on, the second node Q2 is at a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a low level;

[0135] In the stage t32, the clock signal provided by the second clock signal line CKL2 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a high level;

[0136] After stage t32, in the first-stage shift register unit VSR1, the gate driving signal Gout(1) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(2) outputted from the shift output terminal Gout2 is at a low level.

[0137] 2) For the second-stage shift register unit VSR2:

[0138] In the stage t31, the gate drive signal Gout(1) is at a high level, and the clock signal provided by the first clock signal line CKL1 is at a high level; the transistor M36 is turned on, the second node Q2 is at a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a low level;

[0139] In the stage t32, the clock signal provided by the second clock signal line CKL2 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a low level;

[0140] In the stage t33, the clock signal provided by the third clock signal line CKL3 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a low level;

[0141] In the stage t34, the clock signal provided by the fourth clock signal line CKL4 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a high level;

[0142] After stage t34, in the second-stage shift register unit VSR2, the gate driving signal Gout(3) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(4) outputted from the shift output terminal Gout2 is at a low level.

[0143] 3) For the third-level shift register unit VSR3:

[0144] In the stage t33, the gate drive signal Gout(3) is at a high level, and the clock signal provided by the third clock signal line CKL3 is at a high level; the transistor M36 is turned on, the second node Q2 is at a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level;

[0145] In the stage t34, the clock signal provided by the fourth clock signal line CKL4 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level;

[0146] In the stage t35, the clock signal provided by the fifth clock signal line CKL5 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level;

[0147] In the stage t36, the clock signal provided by the sixth clock signal line CKL6 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level;

[0148] After stage t36, in the third-stage shift register unit VSR3, the gate driving signal Gout(5) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(6) outputted from the shift output terminal Gout2 is at a low level.

[0149] Fig.12 yes Fig.10 The timing diagram of the display panel in the second working mode is shown. Here, the first driving circuit can be selected to be forward scanning. The shift register circuit 210 composed of the first-stage shift register unit VSR1, the second-stage shift register unit VSR2 and the third-stage shift register unit VSR3 is taken as an example to describe the working process of the forward scanning. The working process of the shift register circuit 210 is as follows:

[0150] 1) For the first-stage shift register unit VSR1:

[0151] In the stage from t41 to t42, the start control signal provided by the first start control line STV is at a high level, the clock signal provided by the first clock signal line CKL1 is at a high level, and the clock signal provided by the second clock signal line CKL2 is at a high level; then the transistor M36 is turned on, the second node Q2 is at a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a high level;

[0152] From t43 to t44, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; then the transistor M36 is turned off, the transistor M33 is turned on, and the transistor M34 is turned off; the third node Q3 is at a high level to turn on the transistor M35; the first node Q1 is at a high level to turn on the transistors M32, M14, and M17; the second node Q2 is at a low level to turn off the transistors M31, M15, and M18; the gate drive signal Gout(1) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(2) output by the shift output terminal Gout2 is at a low level;

[0153] After stage t44, in the first-stage shift register unit VSR1, the gate driving signal Gout(1) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(2) outputted from the shift output terminal Gout2 is at a low level.

[0154] 2) For the second-stage shift register unit VSR2:

[0155] In the stage from t41 to t42, the gate drive signal Gout(1) is at a high level, the clock signal provided by the first clock signal line CKL1 is at a high level, and the clock signal provided by the second clock signal line CKL2 is at a high level; then the transistor M36 is turned on, the second node Q2 is at a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a low level;

[0156] From t43 to t44, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; then the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(3) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(4) output by the shift output terminal Gout2 is at a high level;

[0157] After stage t44, in the second-stage shift register unit VSR2, the gate driving signal Gout(3) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(4) outputted from the shift output terminal Gout2 is at a low level.

[0158] 3) For the third-level shift register unit VSR3:

[0159] From t43 to t44, the gate drive signal Gout(3) is at a high level, the clock signal provided by the third clock signal line CKL3 is at a high level, and the clock signal provided by the fourth clock signal line CKL4 is at a high level; the transistor M36 is turned on, the second node Q2 is at a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a low level, and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a low level;

[0160] From t45 to t46, the clock signal provided by the fifth clock signal line CKL5 is at a high level, and the clock signal provided by the sixth clock signal line CKL6 is at a high level; the transistor M36 is turned off, the second node Q2 maintains a high level to turn on the transistors M31, M15 and M18, the first node Q1 is at a low level to turn off the transistors M32, M14 and M17, the transistor M33 is turned on and the transistor M34 is turned off, the third node Q3 is at a low level to turn off the transistor M35, the gate drive signal Gout(5) output by the shift output terminal Gout1 is at a high level, and the gate drive signal Gout(6) output by the shift output terminal Gout2 is at a high level;

[0161] After stage t46, in the third-stage shift register unit VSR3, the gate driving signal Gout(5) outputted from the shift output terminal Gout1 is at a low level and the gate driving signal Gout(6) outputted from the shift output terminal Gout2 is at a low level.

[0162] In this embodiment, in the first working mode, multiple clock signal lines provide different clock signals, so that the N shift output terminals of the shift register unit output gate drive signals in time division, and the pixel circuits of each row in the first area are scanned row by row; in the second working mode, there are two clock terminals in the shift register unit that receive the same clock signal provided by two clock signal lines, so that the N shift output terminals of the shift register unit simultaneously output gate drive signals, and the N rows of pixel circuits electrically connected to the shift register unit are scanned simultaneously. Based on this, the display panel adopts the second working mode, which can increase the charging time of each row of pixel circuits, which is beneficial to improve the pixel charging rate and reduce the power consumption of the display panel; or, adopting the second working mode is beneficial to improve the refresh rate of the display panel, so that the display panel can be compatible with a higher refresh rate.

[0163] It is understandable that the structure of the shift register unit and the timing of the display panel provided in the above embodiments are only some examples of the present invention. Relevant practitioners can reasonably design the structure of the shift register unit and the timing of the display panel while ensuring the normal operation of the display panel, and are not limited thereto.

[0164] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel as described in any of the above embodiments. Fig.13 is a schematic diagram of a display device provided by an embodiment of the present invention, such as Fig.13 As shown, the display device 300 provided in the embodiment of the present invention has the corresponding functional modules and beneficial effects of the display panel described in any of the above embodiments. The display device 300 can be a terminal device such as a smart phone, a car display, a tablet computer, a laptop computer, a super mobile personal computer, a netbook, a smart wearable device, an augmented reality (AR) / virtual reality (VR) device, etc. The display panel can be a display panel of any display type, such as a micro light emitting diode display panel or an organic light emitting display panel, but is not limited thereto.

[0165] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0166] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Districts 1 and 2; The first region includes a plurality of rows of pixel circuits; The second area includes a first start control line, a first drive circuit and a plurality of clock signal lines, the first start control line is electrically connected to the first drive circuit, the first drive circuit includes a multi-stage shift register unit; the shift register unit includes a plurality of clock terminals and N shift output terminals, the plurality of clock terminals are electrically connected to the plurality of clock signal lines respectively, the N shift output terminals are electrically connected to adjacent N rows of pixel circuits respectively, N≥2; The display panel includes a first operating mode and a second operating mode; In the first working mode, the multiple clock terminals in the shift register unit receive different clock signals provided by the multiple clock signal lines, so that the N shift output terminals of the shift register unit output gate driving signals in time division; In the second working mode, there are two clock terminals in the shift register unit to receive the same clock signal provided by the two clock signal lines, so that the N shift output terminals of the shift register unit output gate driving signals simultaneously.

2. The display panel according to claim 1, characterized in that: In the first working mode, the effective pulse width of the gate driving signal is H, and H is equal to the scanning time length of a row of the pixel circuits in the display panel.

3. The display panel according to claim 1, characterized in that: In the second working mode, the effective pulse width of the gate driving signal is N*H, where H is equal to the scanning time length of a row of the pixel circuits in the display panel.

4. The display panel according to claim 1, characterized in that: The shift register unit comprises: A node control module, electrically connected to the input terminal, the first input clock terminal, the second input clock terminal, the first node and the second node, and used to control signals of the first node and the second node; N shift output modules, the i-th shift output module is electrically connected to the first node, the second node, the i-th control clock terminal, the first level signal terminal and the i-th shift output terminal, and is used to control the signal of the i-th shift output terminal, 1≤i≤N.

5. The display panel according to claim 4, characterized in that: In the second working mode, in the shift register unit, the first input clock terminal and the second input clock terminal receive the same input clock signal, and the N control clock terminals receive the same control clock signal; The input clock signal is different from the control clock signal.

6. The display panel according to claim 4, characterized in that: In the first working mode, in the shift register unit, the first input clock terminal, the second input clock terminal, and the N control clock terminals receive different clock signals.

7. The display panel according to claim 1, characterized in that: The second area includes Ya clock signal lines, Ya ≥ 4; Among the Ya clock signal lines, any two clock signal lines may provide clock signals having the same frequency.

8. The display panel according to claim 1, characterized in that: The second area includes the 1st clock signal line to the Yath clock signal line, Ya≥4; In the first working mode, the phase of the clock signal provided by the jth clock signal line is earlier than the phase of the clock signal provided by the (j+1)th clock signal line, and the phase difference between the two is a*H, 1≤j≤Ya; In the second working mode, the clock signal provided by the (2j-1)th clock signal line is the same as the clock signal provided by the (2j)th clock signal line, and the phase difference between the clock signal provided by the (2j-2)th clock signal line and the clock signal provided by the (2j)th clock signal line is b*H, 1≤2j≤Ya; a and b are both positive integers, and H is equal to the scanning time length of a row of pixel circuits in the display panel.

9. The display panel according to claim 4, characterized in that: N＝2； The second region includes the first clock signal line to the fourth clock signal line; The first driving circuit includes a multi-stage shift register circuit, the shift register circuit includes two stages of shift register units, and the shift register circuit satisfies the following conditions: The first input clock terminal of the first-stage shift register unit is electrically connected to the second clock signal line, the second input clock terminal is electrically connected to the first clock signal line, the control clock terminal of the first shift output module is electrically connected to the third clock signal line, and the control clock terminal of the second shift output module is electrically connected to the fourth clock signal line; The first input clock terminal of the second-level shift register unit is electrically connected to the fourth clock signal line, the second input clock terminal is electrically connected to the third clock signal line, the control clock terminal of the first shift output module is electrically connected to the first clock signal line, and the control clock terminal of the second shift output module is electrically connected to the second clock signal line.

10. The display panel according to claim 4, characterized in that: N＝2； The second area includes the first clock signal line to the sixth clock signal line; The first driving circuit includes a multi-stage shift register circuit, the shift register circuit includes three stages of shift register units, and the shift register circuit satisfies the following conditions: The first input clock terminal of the first-stage shift register unit is electrically connected to the fourth clock signal line, the second input clock terminal is electrically connected to the fifth clock signal line, the control clock terminal of the first shift output module is electrically connected to the first clock signal line, and the control clock terminal of the second shift output module is electrically connected to the second clock signal line; The first input clock terminal of the second-stage shift register unit is electrically connected to the sixth clock signal line, the second input clock terminal is electrically connected to the first clock signal line, the control clock terminal of the first shift output module is electrically connected to the third clock signal line, and the control clock terminal of the second shift output module is electrically connected to the fourth clock signal line; The first input clock terminal of the shift register unit at the third level is electrically connected to the second clock signal line, the second input clock terminal is electrically connected to the third clock signal line, the control clock terminal of the first shift output module is electrically connected to the fifth clock signal line, and the control clock terminal of the second shift output module is electrically connected to the sixth clock signal line.

11. The display panel according to claim 4, characterized in that: The node control module includes: A first node submodule, electrically connected to the second node, the first input clock terminal and the first node, and used to control a signal of the first node; A second node submodule, electrically connected to the second input clock terminal, the input terminal and the second node, and used to control a signal of the second node; The third node submodule is electrically connected to the first input clock terminal, the second level signal terminal and the first node, and is used to control the signal of the first node.

12. The display panel according to claim 4, characterized in that: The node control module includes: A first node submodule, electrically connected to the second node, the first level signal terminal and the first node, and used to control a signal of the first node; A second node submodule, electrically connected to the first node, the first level signal terminal and the second node, and used to control a signal of the second node; A third node submodule, electrically connected to the first input clock terminal, the second input clock terminal, the second level signal terminal and the first node, and used to control the signal of the first node; The input terminal is the second node.

13. The display panel according to claim 12, characterized in that: The third node submodule includes: A first control subunit, electrically connected to the first control signal terminal, the first input clock terminal and the third node, and used to control the signal of the third node; A second control subunit, electrically connected to the second control signal terminal, the second input clock terminal and the third node, and used to control the signal of the third node; The third control subunit is electrically connected to the third node, the second level signal terminal and the first node, and is used to control the signal of the first node.

14. The display panel according to claim 13, characterized in that: One of the first level signal terminal and the second level signal terminal has the same signal as the first control signal terminal; The other of the first level signal terminal and the second level signal terminal has the same signal as the second control signal terminal.

15. The display panel according to claim 11 or 12, characterized in that: The node control module includes: at least one of a forward sweep control submodule and a reverse sweep control submodule; The forward scanning control submodule is electrically connected to the first forward scanning signal terminal, the second forward scanning signal terminal and the input terminal, and is used to control the signal of the input terminal; The reverse sweep control submodule is electrically connected to the first reverse sweep signal terminal, the second reverse sweep signal terminal and the input terminal, and is used to control the signal of the input terminal; The forward sweep control submodule and the reverse sweep control submodule are turned on in a time-sharing manner.

16. The display panel according to claim 15, characterized in that: The first positive scan signal terminal of the M-th shift register unit is electrically connected to the first shift output terminal of the (M-1)-th shift register unit; The first reverse scan signal terminal of the M-th stage shift register unit is electrically connected to the N-th shift output terminal of the (M+1)-th stage shift register unit.

17. The display panel according to claim 15, characterized in that: One of the first level signal terminal and the second level signal terminal has the same signal as the second positive scan signal terminal; The other of the first level signal terminal and the second level signal terminal has the same signal as the second reverse sweep signal terminal.

18. The display panel according to claim 4, characterized in that: The shift output module comprises: A first output submodule, electrically connected to the first node, the first level signal terminal and the shift output terminal, and used to control the signal of the shift output terminal; The second output submodule is electrically connected to the second node, the control clock terminal and the shift output terminal, and is used to control the signal of the shift output terminal.

19. The display panel according to claim 18, characterized in that: The shift output module comprises: a potential maintaining submodule, wherein the second output submodule is electrically connected to the second node via the potential maintaining submodule; The potential maintaining submodule is also electrically connected to the second level signal terminal, and is used to control the signal of the second node to be transmitted to the second output submodule.

20. The display panel according to claim 19, characterized in that: The shift register unit further includes: a first coupling submodule, electrically connected between the first node and the first level signal terminal; The shift output module includes: a second coupling submodule electrically connected between the output end of the potential holding submodule and the shift output end.

21. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 20.

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