A test meter configured to perform a test of insulation resistance of a device

Abstract

A unipolar or DC insulation resistance measurement meter 1 for measuring the insulation of a device under test 2 comprises: terminals 3, 4 for connection to the device on test; a high voltage generati

Description

Technical Field The present invention relates generally to an improved test meter for measuring insulation resistance, and in particular, but not exclusively, to a test meter configured to discharge a voltage held by the capacitance of a device under test using a solid-state discharge switch. Background Measurements of electrical resistance of an insulation resistance of a device, for example the electrical resistance of insulation of windings of an electric motor or electrical cables, are typically performed periodically, to check the condition of the insulator, which may degrade with time. The measurement may be performed by applying a unipolar high voltage, which may be 15 kV or higher, and measuring the resulting current through the insulation of the device. The device may have a significant capacitance, which will tend to hold the high voltage after the test. For reasons of electrical safety, at the termination of the test this capacitance may be required to be discharged so that no unsafe combination of charge and voltage remains in the device after the test is finished. This can be accomplished by using a manual discharge connection, for example according to IEEE standard 95-2002, according to which a discharge resistor is manually positioned across the device under test using a discharge stick having an insulated handle. In modem test equipment, discharge of the device after the test is typically automated by means of an electro-mechanical discharge switch. In portable insulation testers, the discharge switch is typically implemented as a high-voltage reed relay. A reed relay typically has two contacts enclosed in a glass capsule which move apart when a magnetic field is applied. The magnetic field is typically generated by a coil surrounding the relay. The reed relay may be manufactured so that it operates in a “normally closed” fashion, so that the contacts are in a closed, that is conducting, state when no magnetic field is applied. This provides an inherent safety feature for insulation testers, because even in the case of a sudden loss of power, for example failure of electronics or a battery, the relay will automatically close and thus discharge the insulation under test, without any intervention required from the operator. Summary In accordance with a first aspect, there is provided a test meter configured to perform a unipolar test of insulation resistance of a device, the test meter comprising: a first test terminal and a second test terminal for connection to the device; a voltage generation circuit configured to cause a unipolar voltage to be applied between the first test terminal and the second test terminal during the unipolar test of insulation resistance of the device ;_a discharge switch controllable to discharge the unipolar voltage, the discharge switch having an impedance in a path between the first test terminal and the second test terminal that is controllable by a switch control signal, and a switch control circuit configured to generate the switch control signal, the switch control circuit being configured to be powered by a power source, wherein the discharge switch comprises a series arrangement of transistors in the path between the first test terminal and the second test terminal, and the series arrangement of transistors is configured to default to a state to discharge a voltage between the first test terminal and the second test terminal in an event that the power source does not supply power to the switch control circuit. The series arrangement of transistors, which are solid state semiconductor devices, provides greater reliability than an electromechanical switch. The series arrangement of transistors allows the switch to withstand high voltages, which may be greater than a single transistor could tolerate without damage. By configuring the series arrangement of transistors to default to a state to discharge a voltage between the first test terminal and the second test terminal in an event that the power source fails to supply power to the switch control circuit, a “normally closed” switch is provided. This provides a fail-safe arrangement, which will discharge a voltage on a device under test in the event that the test meter or the switch control circuit should fail. Also, the switch will discharge a voltage on a device connected to the meter if the meter is left unpowered, for example before it is switched on. Conventionally, a semiconductor switch for switching a high voltage is configured as a normally open switch, which is made to conduct by application of a voltage and / or current to the switch, in particular to a controlling connection of a transistor such as a gate or base, because such switches may typically have much lower impedance than normally closed semiconductor switches. The lower impedance of a normally open switch in the “closed” (conducting) state may be advantageous in providing a fast and reliable discharge path. However, a normally open semiconductor switch would not default to a state to discharge a voltage if the test meter suffers a power failure, and so a conventional high voltage semiconductor switch may not be considered suitable for this application for safety reasons. However, according to this disclosure, it has been found that it is possible to achieve sufficiently low impedance to safely discharge the capacitance of a typical device that would be tested by an insulation resistance test meter, such as an electric motor, using a normally closed semiconductor switch. In the normally closed semiconductor switch, the series arrangement of transistors is configured to default to a state to discharge a voltage between the first test terminal and the second test terminal in an event that the power source fails to supply power to the switch control circuit. In an example, the series arrangement of transistors comprises a series arrangement of depletion mode field effect transistors. Depletion mode field effect transistors have a low impedance between source and drain when no voltage is applied to the gate. Therefore, if the switch control circuit fails, the series arrangement of depletion mode field effect transistors will default to a state that discharges the voltage across the device under test. Depletion mode field effect transistors have a relatively higher impedance when in the conducting state than do enhancement mode field effect transistors, and so would not normally be selected for use in a discharge switch, especially as a series arrangement in which the impedances of successive transistors in the series add. However, it has been found that a series arrangement of depletion mode field effect transistors has sufficiently low resistance with no applied voltage to the gate that a safe discharge switch can be provided for an insulation resistance test meter. In an example, the series arrangement of depletion mode field effect transistors comprises a series arrangement of depletion mode MOSFET metal oxide semiconductor field effect transistors, and in another example the series arrangement of depletion mode field effect transistors comprises a series arrangement of JFET junction-gate field effect transistors. In an example, the switch control signal is provided through a relatively low value of resistance to the gate of a first depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors that is at a first end of the series arrangement that is closest to an internal ground connection in the test meter and the switch control signal is provided to the gate of at least one other depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors through a relatively high value of resistance. This arrangement provides a simple and reliable method of automatically applying the correct switch control voltage to the gates of each field effect transistor in the series arrangement and that allows balancing of the gate voltages for a wide range of voltages across the switch, allowing selection of a range of voltages to be generated by the voltage generation circuit without changing the design. This is achieved by applying the switch control signal to the first field effect transistor through a low impedance and propagating the signal to the other field effect transistors from the first field effect transistor. In an example, the gate of each depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors is connected to the gate of an adjacent field effect transistor by a resistance in parallel with a capacitance. This arrangement allows the switch control signal to propagate to the gates of each of the field effect transistors in the series arrangement in a manner that is tolerant to a range of voltages to be discharged. In an example, each resistance is substantially equal and each capacitance is substantially equal. This provides for effective propagation of the switch control signal between the gates, automatically providing signals at the correct potential for the position of the gate of each transistor in the series. The capacitance allows for dynamic balancing by transmitting a triggering pulse to the gates of the transistors in the series arrangement. The resistance provides static balancing, providing for example equal voltage distribution between the gates of the transistors in the series once switching transients have settled. In an example, the gate of a last depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors that is at a second end of the series arrangement that is furthest from to an internal ground connection in the test meter is connected to the second end of the series arrangement by a resistor in parallel with a capacitor, the resistor and capacitor having substantially the same value as the resistance and capacitance connected between the gates of adjacent depletion mode field effect transistors. This provides a connection of the propagation path through the parallel resistances and capacitances between each gate to a terminating impedance at the second end of the series arrangement, to provide for effective static and dynamic balancing of the gate voltages of the transistors in the series. In an example, each depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors has a capacitor connected between the source and drain of the depletion mode field effect transistor, each capacitor having substantially the same value. The capacitor provides further dynamic balancing of voltages across the transistors in the series arrangement during switching. In an example, each depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors except the first depletion mode field effect transistor has a diode connected between the gate and source of the depletion mode field effect transistor. The diode provides protection from voltages exceeding the maximum rating of the transistors during switching transients. In an example, the series arrangement of depletion mode field effect transistors comprises a series arrangement of depletion mode field effect transistors of the same type. This provides for effective balancing of voltages between stages of the series arrangement of transistors in dynamic and static cases. In an example, the voltage generation circuit is configured to generate a controllable range of unipolar voltage. The controllable range of voltage allows a variety of insulation tests to be performed with a difference high voltage applied, or with a high voltage that increases in steps throughout the test, for example. This is enabled by the switch being tolerant of a range of voltages across the series arrangement of transistors. In an example, a sensing resistor is connected between a first end of the series arrangement of depletion mode field effect transistors that is closest to an internal ground connection in the test meter and the internal ground connection and a discharge current sensing circuit is connected to the first end of the series arrangement of depletion mode field effect transistors. The sensing resistor allows a discharge current through the switch to be measured by sensing the voltage across the sensing resistor. In an example, the test meter comprises a field effect transistor having a source-drain path in parallel with the sensing circuit, configured to reduce a voltage across the sensing resistor in the event of a failure of a power supply of the meter, providing protection of the series arrangement of transistors from damage in the event of a failure of the switch control circuit power supply, for example during an uncontrolled power loss in the instrument. In an example, the switch control signal is a voltage, which may be coupled to the switch magnetically, for example via a pulse transformer. In an example, the swich control signal may be optically coupled to the switch, for example to control the impedance of a semiconductor device that has an impedance that depends on light intensity applied to the device. Further features and advantages will be apparent from the following description of exemplary embodiments, which are given by way of example only. Brief Description of the Drawings Figure 1 is a schematic diagram illustrating a test meter for performing a measurement of insulation resistance of an electrical insulator; Figure 2 is a schematic diagram illustrating functional blocks within a test meter in an example; Figure 3 shows a circuit diagram of a discharge switch circuit according to the disclosure in an example; Figure 4 shows a circuit diagram of a switch control circuit according to the disclosure in an example; and Figure 5 shows a circuit diagram of a switch protection circuit according to the disclosure in an example, showing a depletion mode FET configured to protect the discharge switch in the event of power loss in the test meter. Detailed Description By way of example, embodiments will now be described in the context of a portable test meter capable of performing a measurement of insulation resistance of an electrical insulator by applying a voltage to the electrical insulator and measuring the resulting current through the electrical insulator, where the test apparatus is in the form of a dedicated test set designed for the purpose, but it will be understood that the measurement apparatus may take other forms, such a multifunction meter or other test equipment. Figure 1 shows an example of a test meter 1 configured to perform a unipolar test of insulation resistance of a device under test 2, which may be, for example, an electric motor, electrical cables, or other device requiring insulation testing. The test meter has a first test terminal 3 and a second test terminal 4 for connection to the device. The test terminals may be, for example, external sockets, or other connection points to allow a connection to be made to the device under test. Connection to the device under test may be by conductive test leads. A voltage generation circuit 5 is configured to cause a unipolar voltage to be applied between the first test terminal 3 and the second test terminal 4 during the unipolar test of insulation resistance of the device. The unipolar voltage is typically a high voltage, which may be, for example, 1 kV, 15kV, 30 kV or higher or lower voltages. In a unipolar test, the polarity of the voltage of the test does not change during the test, that is to say the test is a DC (direct current) test as opposed to an AC (alternating current) test. The voltage may be constant during the test, or may be varied, for example in a series of steps or in a ramp. The device under test is intended to be an insulator, that is to say it presents a high resistance to the test meter, and the current through the device under test is small. The resistance of the insulator may be found to be lower if the insulator is in a poor condition and this may indicate a likelihood of failure of the insulator. The voltage applied to the device under test is measured by a voltage measurement circuit 8 and the current through the device under test is measured by a current measurement circuit 9. The resistance of the device under test may be calculated from the measured voltage and current. A discharge switch 6 is provided that is controllable to discharge the unipolar voltage generated by the voltage generation circuit. The unipolar voltage that is discharged is typically the unipolar voltage that is generated by the voltage generation circuit and held as a residual voltage by the capacitance of the device under test when a test is completed, typically when the voltage generation circuit is not active. The discharge switch has an impedance in a path between the first test terminal 3 and the second test terminal 4 that is controllable by a switch control circuit 7. A high voltage across the device under test may remain at the end of a test due to the capacitance of the device and may be discharged under control of one or more control processors 10 in the meter at the end of a test to protect the safety of operators. The control processors 10 may be configured to perform instructions encoded as software and / or firmware on a computer-readable medium, such as semi-conductor memory, to allow automatic control of insulation tests carried out by the meter. A switch control circuit 7 is configured to generate the switch control signal, the switch control circuit 7 being powered by a power source, which may be the power source of the meter, for example a battery and one or more voltage regulator circuits. The discharge switch 6 comprises a series arrangement of transistors in a path between the first test terminal 3 and the second test terminal 4. The transistors may be depletion mode field effect transistors, for example metal oxide semiconductor field effect transistors (MOSFETs) or junction-gate field effect transistors (JFETs). The series arrangement of transistors is configured to default to a state to discharge a voltage between the first test terminal 3 and the second test terminal 4 in an event that the power source fails to supply power to the switch control circuit, that is to say it is configured as a “normally closed” switch. Depletion mode field effect transistors have an impedance between source and drain which is lower when no voltage or a positive voltage is applied to the gate than when a negative voltage is applied to the gate. Therefore, if the switch control circuit or the power to the switch control circuit fails, the series arrangement of depletion mode field effect transistors will default to a state that discharges the voltage across the device under test. Depletion mode field effect transistors have a relatively higher impedance when in the conducting state than do enhancement mode field effect transistors, and so would not normally be selected for use in a discharge switch, especially as a series arrangement in which the impedances of successive transistors in the series add. However, it has been found that a series arrangement of depletion mode field effect transistors has sufficiently low resistance with no applied voltage to the gate that a safe discharge switch can be provided for the requirements an insulation resistance test meter, in which the charge to be discharged is simply held by the capacitance of the device under test and is accordingly in a known expected range. In an example, the series arrangement of depletion mode field effect transistors comprises a series arrangement of depletion mode MOSFET metal oxide semiconductor field effect transistors, and in another example the series arrangement of depletion mode field effect transistors comprises a series arrangement of JFET junction-gate field effect transistors. It has been found that a conventional reed switch, although very well suited for use as a discharge switch because it is simple, has low impedance and defaults to a closed condition, may be unreliable and subject to wear. It has been found by the inventors that a semiconductor swich comprising a series arrangement of transistors may be used to provide a discharge switch having higher reliability, and that the relatively high impedance of a depletion mode field effect transistor when in a conducting state nevertheless allows sufficient discharge current to enable a safe discharge of a high voltage on the insulator under test. Figure 2 is a schematic diagram illustrating circuits within a test meter in an example. A voltage generation circuit 5 generates a high voltage HV which is conducted to the test terminals 3, 4 via an ammeter 9, and a diode 13 and series resistor 14 as shown. A power source 30 provides power to a switch control circuit 7, which provides a switch control signal 18 to the discharge switch 6. The power source may be a battery and may include voltage regulation circuits to provide power supply rails to the circuitry of the meter, including the switch control circuit 7. The discharge switch 6 is connected in a path from the first test terminal 3 to the second test terminal 4 via the ammeter 9 via a series resistor 15, in this example. The unipolar voltage is measured by the voltmeter 8. The device under test has an insulation resistance R0 19 and a capacitance CO 20. The capacitance may be determined by measuring the current through the discharge switch 6 when the discharge switch is made to conduct at the end of a test, when the voltage generation circuit 5 is in a state of deactivation and ceases to generate voltage. For this purpose, a resistance Ri 17 may be provided between the discharge switch 6 and the internal ground connection of the meter 12. A capacitance measurement circuit 11 is shown, configured to measure a voltage across the resistance Ri 17 in series with the connections 26, 27 to the discharge switch 6. A switch protection circuit 16 is provided in this example, which is configured to connect a low impedance across the resistance Ri 17 in the event of a power failure, such as a power failure of the power source. This may be achieved by use of a depletion mode field effect transistor connected so that the source-drain path short circuits the resistance Ri 17 in the event that power to the switch protection circuit fails. This is to prevent damage to the discharge switch 6 which may occur in the event of a power failure due to generation of transient voltages by a discharge current through resistor Ri 17. Figure 3 shows a circuit diagram of a discharge switch circuit 6 according to the disclosure in an example. In this example, a series arrangement of MOSFETs 2 la-2 le is shown between a first end 27 of the series arrangement that is nearest to an internal ground connection 12 and a second end 26 of the series arrangement that is furthest from to an internal ground connection 12. In the illustration, 5 MOSFETs are shown in series, but other numbers may be provided in examples. The voltage rating of each MOSFET may be lower than the unipolar voltage that is to be discharged. However, to ensure that the voltage ratings are not exceeded, it is necessary to carefully control the switching process, so that transient conditions are avoided that would exceed the switch ratings, for example if all the MOSFETs except one were conducting, so that the voltage would appear across a single transistor. To provide controlled switching, in particular to provide dynamic balance between the transistors during switching, the circuit of Figure 3 provides for a switch control signal 18 to be provided to a first MOSFET 21a through a relatively low value of resistance 28. The switch control signal 18 is then propagated to the gates of the other MOSFETs 21b - 21e, through parallel combinations of resistors 22a-22e and capacitors 23a-23e between the gates. In addition, balancing capacitor 24a-24e are provided to balance the source-drain voltages of the FETs in the series arrangement during switching. Figure 4 shows a circuit diagram of a switch control circuit according to the disclosure in an example. In this example, +15V and -8V power supply voltages are provided, so that in normal operation, when there is no power failure, a positive voltage or negative voltage may be provided to the gate drive 18 of the discharge switch 6 in response to an on / off control from the control processor 10. In the event of failure of the power supply voltages, the gate drive 18 would float to the internal ground voltage, which would cause the discharge switch 6 to conduct. Figure 5 shows a circuit diagram of a switch protection circuit 16 according to the disclosure in an example, showing a depletion mode field effect transistor (FET) 29 configured to protect the discharge switch in the event of power loss in the test meter. The FET 29 is normally set to a high impedance when the power supply rails, in this example +15V and -8V, are energised. However, in the event of a failure of the power supply rails, the depletion mode FET has a low impedance, and short circuits the resistor Ri 17 in series with the first end 27 of the discharge switch 6, connecting it to the internal ground 12. This may prevent damage to the discharge switch 6 caused by a voltage across the resistor Ri 17 caused by the discharge current through the discharge switch 6 in the event of a power failure. Operation of a specific example of the test meter will now be described in more detail, for a test implemented by the test meter 1 for diagnosing high-voltage characteristics of the insulation of a device under test 2, in which a unipolar voltage is applied to the device and the resulting current, and therefore resistance, is measured of that insulation. The polarity can be positive to ground of the tested object or negative to ground, but during a single test it remains unipolar. The voltage can be applied as a constant value, that is to say substantially DC, or as a series of increasing steps in a step voltage test, or as a continuous ramp in a ramp voltage test. The object under test is the insulation system, but the voltage is applied typically between two metallic contacts, and the whole structure in effect forms a capacitor 20 denoted as CO in Figure 2, the capacitor 20 comprising two electrodes separated by insulation. The insulation resistance of interest 19 is designated as R0. In addition, surface leakage current, for example due to surface contamination, may also be present and may be denoted as Rs, but as will be explained, it is conventional to eliminate surface leakage current by attaching a guard terminal of the instrument to the surface of the insulator. Therefore, Rs is not shown in Figure 2. The insulating material may undergo electrostatic polarisation processes which behave as an RC (resistance-capacitance) circuit (RCpol), also not shown in Figure 2, whose response to charging / discharging is much slower than the main capacitance CO. Because the insulation can comprise several layers or different materials there can be multiple RCpol branches, each with its own time constant. In measuring the insulation resistance RO, which may be referred to as the main resistance, the effects of the capacitance CO may be observed in addition to the time constants of polarisation effects RCpol. Towards the end of the HV test the main capacitance CO will have become charged to the voltage during that part of the test. For safety reasons at the termination of the test this capacitance is discharged so that no unsafe charge / voltage remains in the structure after the test was finished. The HV insulation tests can be run at any voltage from 40 V to 15 kV or even up to 30 kV or higher, depending on the rating of the given insulation system. The output voltage is controlled precisely to a DC value, but it may be changed to any value from within that range. During the test, the insulation under test (R0+C0) is typically charged through some charging resistance Rc 14 in Figure 2, which is a built-in resistor in the test meter. At the end of the test the supply voltage HV, that is to say the voltage generation circuit 5, is de-energised. Typically diode D 13 blocks selfdischarge through the supply, and then the discharge switch 6 is closed to provide a discharge path through the discharge resistor Rd 15. The charging and discharging may utilise the same path, through the same resistors. There can be more than one discharge switch diverting the charge / discharge path. In the same path as the discharge switch 6 there can be an additional resistor Ri 17, which typically has a smaller value than Rd 15, which is used for sensing the current signal during the discharge. This signal can be passed to the capacitance measurement circuit (CapM) for further processing. Knowing the test voltage, as measured by voltmeter V 8, just before the discharge is commenced, and knowing the value of combined resistance in the discharge path (Rd+Ri) it is possible to derive the value of the main capacitance CO of the device under test 2. Such capacitance can be measured, for example, by employing an analogue or digital integrator whose output is proportional to the amount of energy stored in the capacitor, which can be scaled by the voltage and thus measuring the unknown capacitance in the circuit. As shown in Figure 3, the discharge switch 6 comprises a series arrangement of depletion mode FETs, to provide a “normally closed” switch. This is in contrast to most ordinary transistors / thyristors, which are made such that they remain in their open (OFF) state when their gate connection is not activated, so they can be classified as “Normally Open” (N / O). Only upon activation of the gate with an appropriate signal the transistor / thyristor switches on, providing a low-impedance path. However, the depletion mode FETs, for example JFET or MOSFET as already mentioned, are designed and manufactured in a way that makes them remain in their closed (ON) state when the gate connection is not activated, and the gate has to be activated (e.g. by application of some negative voltage) to switch them OFF (open). The circuit shown in Figure 3 may be referred to as the HV stack circuit, and comprises a number of stages connected in series, with the number dictated predominantly by the voltage rating of each transistor and the total voltage to be switched. For example, for a design with depletion mode N-type MOSFETs rated at 1 kV each, for 11 kV total voltage there might be n=14 stages, for 15 kV it could be n=21 stages, and so on. If transistors with higher voltage rating were used, then fewer stages would be needed, and vice versa. The HV stack has one active transistor 21a (bottom-most) whose gate is driven directly by the gate drive circuit, for example the circuit of Figure 4, via the relatively small impedance of Rg 28. The other stages in the HV chain 21b-21e are “passive” so that they are switched by the combined action of the cascading effect and the trigger pulse being propagated through the first set of dynamic balancing capacitances Cgl-Cgn 23a-23e, which all can have similar values for each stage (they can be substantially the same within some tolerance). Also, the second set of dynamic balancing capacitors Cl-Cn 24a-24e can have the same values for each stage (but in general different from Cgl-Cgn 23a-23e). Preferably, the values of balancing capacitors are greater than the corresponding parasitic capacitances of the FET (e.g. capacitance from gate to source, source to drain, or gate to drain, as applicable). The static balancing resistors Rgl-Rgn 22a-22e have large values so that in an example, their combined resistance exceeds 1 MQ and may be 20 MQ or higher, but also they have the same values for each stage (within tolerance). This gives equal voltage distribution between the stages for static balancing. It should be noted that Rgl-Rgn 22a-22e have high impedance and generally do not take part during the transients of switching the switch into closed or into open configuration. There are also diodes DgO-Dgn 25b-25e, which may be Zener diodes or TVS diodes, varistors, or similar, between the gate (trigger pin of the transistor) and source (bottom pin of the transistor) of each MOSFET, and they serve the purpose of protecting the gates from exceeding the maximum VGS rating (voltage between gate and source) of the MOSFET from transients during switching the solid state relay from the open to closed condition and from the closed to open condition. The operation of the discharge switch may be described as follows. As shown in Figure 3, several FETs are combined together in series, so that their combination can withstand much higher total voltage than the rating of each single device. A difficulty with using such in-series stack of electronic switches is that during their OFF state each of them has to float at a potential / voltage which is proportional to their position in the whole stack. Therefore, in order to trigger the switch the signals driving the gates should also float or be adjusted to the same potentials. All the stacked FETs may be switched by providing the gate signal only to the bottom-most (or top-most) transistor in the series. As soon as this transistor is switched on, then the voltage across it collapses, and appropriately biases the gate of the next transistor in series so that it switches too. This results in a “cascade” effect. This allows a single low-voltage signal to switch the whole structure open (OFF) or close (ON). However, for such multi-stage switch to work reliably each stage in the chain has to be “balanced” so that the same voltage is present across it in the open state (static balancing), as well as the same switching speed occurs during the transition from off / on or on / off (dynamic balancing). Otherwise, the last section to switch ON would have all the voltage present across it, and it would fail because its voltage rating would be exceeded. In practice the balancing can be achieved so that the turn on / off action is selfsynchronised to better than a micro-second level, and even to nanoseconds. For such short times the voltages can be equalised either by the balancing capacitors or the parasitic capacitances which are always present to some extent. In the ON state the balancing is irrelevant because only low voltage drop is present on each stage (all within ratings of each device). However, in the OFF state the static balancing is achieved typically by a series of resistors which are connected across each FET. The addition of such hard-wired resistors across the open switch causes a proportional leakage of current (due to the effective resistance at the level of MQ). so the stacked switch is inferior in that aspect as compared to a reed relay which is truly open in its off state (its insulation resistance can exceed TQ). Figure 4 shows a gate drive circuit for providing the switch control signal to the discharge switch 6. The circuit comprises two transistors of any type (bipolar junction transistors are shown in Figure 4). The configuration is such that if the on / off signal is kept low (0 V) then gate drive is pulled down to -8V, and if on / off is high (e.g. 5 V) then gate drive = +15 V. Therefore, the circuit of Figure 4 acts effectively as a “level shifter” because the input signal at some voltages is translated to an output signal at different levels of voltage. The signal gate drive is connected directly to that of Figure 3. The gate drive signal is pulled to negative voltage (-8 V) which ensures that he HV switch is kept open (high impedance) during normally intended operation of insulation resistance testing. The actual implementation of this sub-circuit can be achieved in a number of suitable ways, including off-the-shelf level shifter integrated circuits. Figure 5 shows a switch protection circuit including a discharge current sensing circuit. This circuit performs two distinct tasks. The “HV-“ connection 27 is made to the corresponding one in Figure 3. This presents the discharge current sensing resistor Ri 17 in the path of the discharge switch 6, so that during normal operation all of the discharge current flows through Ri 17, therefore producing an instantaneous voltage which is proportional to the instantaneous discharge current. This signal can be then processed by further circuitry connected to the point CapM in Figure 5. The circuit of Figure 5 provides increased safety against a sudden loss of power within the test instrument. Upon such event the main gate drive signal becomes 0 V (because the supply +15 V in Figure 5 collapses), but due to continuing discharge there can be a substantial voltage drop across Ri. This pushes all the MOSFETs towards higher potential and begins to turn them off, so that they will end up with the “constant current” discharge because their impedance will be automatically controlled to some self-balancing voltage drop across them. This is to be avoided because it is likely to damage the main HV transistors Ql-Qn 21a-21e. So in order to avoid the damage, under normal conditions Qa and Qb in Figure 5 are biased such that Q0 is kept open (high impedance), so that all the discharge current flows through Ri. But in the case of power failure the +15V supply (in Figure 5 also becomes 0V and as a consequence the Q0 becomes closed (low impedance) because it operates in a similar way as the main HV transistors (normally closed with 0 V on its gate). This will short circuit across Ri collapsing its voltage and thus protecting Ql-Qn from damage. Q0 can be of similar or different type to Ql-Qn. There might be an additional Zener diode DO which provides passive protection against the voltage across Ri in case it raises too much during normal or fault conditions. In Figure 3, the bottom of the stack (marked as “HV-“) 27 may in some examples be connected directly to ground 12, to the current sensing resistor Ri 17, or to any other further circuitry. In some examples “HV-“ may be connected through Ri to a further overcurrent sensing circuit, which controls the HV generation. The advantage for using Ri 17 and an integrator circuit in a capacitance measuring circuit 11 is that the capacitance can be measured in a very noisy environment where other simpler methods would fail. For example, due to excessive noise there could be a lot of 50 Hz ripple during the discharge phase and therefore measuring the simple exponential time-to-discharge could produce multiple crossings through the given threshold and thus falsify the reading. In an example, the circuit of Figure 3 comprises depletion mode N-channel MOSFETs which offer relatively high voltage rating (1000 V) and conveniently low resistance when switched on (closed) of about 21 Q. So, in the example of a 10 kV discharge switch, a chain of 14 transistors results with a combined resistance of around 300 Q which is insignificant when compared with the total discharge resistance Rd >1 kQ. The additional high-power resistors Rd are placed between the capacitance under test and the discharge switch. In an example, the value of Rd may be greater than 40 kQ. for example 80 kQ. This decreases the peak discharge current so that the voltage drop across Ri remains within a range that was safe for the operation of the FETs of the discharge switch. Another type of transistor which could be used for the same purpose is JFET, which operates similarly if made in the depletion mode (normally closed). But the JFET transistors typically have inferior parameters, either lower voltage rating, higher resistance when switched on (closed), or both. In an example, the discharge switch is designed to discharge voltages of 1 kV or higher. In an example, an isolating pulse transformer may be used to trigger the first active transistor in the chain, i.e QI 21a. In this example, the switch control signal would drive the primary winding of the transformer. The secondary winding would then drive the gate of the active MOSFET 21a. This has the additional advantage of being able to increase the value of Ri to improve the discharge current sensing capabilities, and fully isolated solution would be obtained with just one transformer. The circuits presented herein were shown for switching positive HV voltage to ground. It would be also possible to design a similar circuit which would switch negative HV voltage to ground. In that case the upper-most FET would be actively switched, “HV+” would be close to the local ground potential, and “HV-“ would be at the high negative potential. Ri would be placed above “HV+”, and so on. In an example, a second static balancing circuit could be added across the transistors, between source-drain (rather than across their gates as shown in Figure 3). In an example, where spacing between the pins of the FETs is too small to withstand the rated voltage, they may be encapsulated with additional insulating material. This may be achieved by applying the so-called “conformal coating”, which can be sprayed onto the fully populated PCB. It is also possible to apply the coating by dipping in varnish. Alternatively, the components or the whole discharge switch board may be encapsulated in resin (such as epoxy resin). This could be made by creating a small box (slightly larger than the discharging switch) and pouring liquid resin into the box. The resin would submerge all the components and thus provide solid insulation after curing. It is also possible to submerge all of the components in liquid insulation such as transformer oil. In examples, additional circuitry is provided for providing further functionality apart from measuring insulation resistance. As shown in Figure 5 there can be a capacitance measurement circuit which relies on the signal provided by the shunt resistor Ri which is conveniently placed below the discharge switch 6, so that relatively low voltage is generated across it, suitable for processing by the electronic circuit downstream. During the discharge phase there will be an additional voltage drop across Ri which will raise the potential of the bottom connection of the discharge switch 6. There is a risk that this additional potential (even though relatively low) would start opening the discharge switch, because its gate would be kept at a fixed value which might become lower than the increased potential. This would be equivalent to pulling the potential of the gate of the FET down, and thus opening it. As a result, the FETs would run in a “constant-current” mode dissipating significant amount of heat, which might lead to their destruction. For this reason, the value of Ri resistor may be limited to a small value so that the rising potential during discharge is kept within safe limits. In an example, the value of Ri may be less than 1 kOhm, for example 167 Q to avoid problems with unreliable switching and hence damage of the HV MOSFETs. Providing this low value is counterintuitive since it will lower the signal voltage delivered to the capacitance measurement circuit which may result in somewhat reduced accuracy. The above embodiments are to be understood as illustrative examples of the invention. It is to be understood that any feature described in relation to any 5 one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in 10 the accompanying claims.

Claims

1. A test meter configured to perform a unipolar test of insulation resistance of a device, the test meter comprising:a first test terminal and a second test terminal for connection to the device;a voltage generation circuit configured to cause a unipolar voltage to be applied between the first test terminal and the second test terminal during the unipolar test of insulation resistance of the device;a discharge switch controllable to discharge the unipolar voltage, the discharge switch having an impedance in a path between the first test terminal and the second test terminal that is controllable by a switch control signal, anda switch control circuit configured to generate the switch control signal, the switch control circuit being configured to be powered by a power source,wherein the discharge switch comprises a series arrangement of transistors in the path between the first test terminal and the second test terminal,and the series arrangement of transistors is configured to default to a state to discharge a voltage between the first test terminal and the second test terminal in an event that the power source does not supply power to the switch control circuit.

2. A test meter according to claim 1, wherein the series arrangement of transistors comprises a series arrangement of depletion mode field effect transistors.

3. A test meter according to claim 2, wherein the series arrangement of depletion mode field effect transistors comprises a series arrangement of depletion mode MOSFET metal oxide semiconductor field effect transistors.

4. A test meter according to claim 2, wherein the series arrangement of depletion mode field effect transistors comprises a series arrangement of JFET junction-gate field effect transistors.

5. A test meter according to any one of claims 2 to 4, wherein:the switch control signal is provided through a relatively low value of resistance to the gate of a first depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors that is at a first end of the series arrangement that is closest to an internal ground connection in the test meter; andthe switch control signal is provided to the gate of at least one other depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors through a relatively high value of resistance.

6. A test meter according to claim 5, wherein:the gate of each depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors is connected to the gate of an adjacent field effect transistor by a resistance in parallel with a capacitance.

7. A test meter according to claim 6, wherein each resistance is substantially equal and each capacitance is substantially equal.

8. A test meter according to claim 7, wherein the gate of a last depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors that is at a second end of the series arrangement that is furthest from to an internal ground connection in the test meter is connected to the second end of the series arrangement by a resistor in parallel with a capacitor, the resistor and capacitor having substantially the same value as the resistance and capacitance connected between the gates of adjacent depletion mode field effect transistors.

9. A test meter according to claim 8, wherein each depletion mode fieldeffect transistor of the series arrangement of depletion mode field effect transistors has a capacitor connected between the source and drain of the depletion mode field effect transistor, each capacitor having substantially the same value.

10. A test meter according to claim 9, wherein each depletion mode field effect transistor of the series arrangement of depletion mode field effect transistors except the first depletion mode field effect transistor has a diode connected between the gate and source of the depletion mode field effect transistor.

11. A test meter according to any preceding claim, wherein the seriesarrangement of depletion mode field effect transistors comprises a series arrangement of depletion mode field effect transistors of the same type.

12. A test meter according to any preceding claims, wherein the voltage generation circuit is configured to generate a controllable range of unipolar voltage.

13. A test meter according to any preceding claim, wherein a sensing resistor is connected between a first end of the series arrangement of depletion mode field effect transistors that is closest to an internal ground connection in the test meter and the internal ground connection and wherein a discharge current sensing circuit is connected to the first end of the series arrangement of depletion mode field effect transistors.

14. A test meter according to claim 13, comprising a field effect transistor having a source-drain path in parallel with the sensing circuit, configured to reduce a voltage across the sensing resistor in the event of a failure of a power supply of the meter.

15. A test meter according to any preceding claim, wherein the switchcontrol signal is a voltage.

16. A test meter according to claim 15, wherein the switch control voltage is magnetically coupled to the switch.

17. A test meter according to any one of claims 1 to 14, wherein the swich control signal is optically coupled to the switch.

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