Display device and driving method thereof

Abstract

A display panel comprises a pixel capable of being driven in two different frequency modes. The pixel comprises a light emitting device ED such as an LED or OLED. The panel comprises a gate driver cir

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application claims the benefit and priority from Korean Patent Application No. 10-2020-0157158, filed in the Republic of Korea on November 20, 2020, the entire contents of which are hereby incorporated by reference for all purposes as if fully set forth into the present application. BACKGROUND Technical Field [1] The present disclosure relates to a display device and a driving method thereof. Description of the Related Art [2] As the information society develops, demands for display devices for displaying images are increasing in various forms. As a display device, various types of display devices such as a liquid crystal display device (LCD) and an Electroluminescence display device (ELD) are used. [3] The electroluminescent display device (ELD) may include a quantum-dot light emitting display device including a quantum-dot, an inorganic light emitting display device, and an organic light emitting display device. [4] Among the above display devices, an electroluminescent display device (ELD) has an advantage that a response speed, a viewing angle, color reproducibility, and the like can be very excellently implemented, and also can be implemented to have a thin thickness. [5] The above display devices can display a still image. When a still image is displayed on the display device, power consumption can be reduced by driving at a low frequency. [6] When the display device is driven at a low frequency, the time of a frame increases as long as the data signal written to the pixel is maintained. In addition, when a still image is displayed on the display device, the same data signal may be written to the pixel during a plurality of frames. SUMMARY [7] Even if the same data signal is written to the pixel during a plurality of frames, the luminance may decrease between one frame and the next frame. When driving at a high frequency, the user does not recognize that the luminance decreases, but when driving at a low frequency, the user may recognize that the luminance decreases. Accordingly, there is disclosed a display device and a driving method thereof that prevent a user from recognizing that the luminance decreases while driving at a low frequency. [8] The problems to be solved according to an embodiment of the present specification are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description. [9] Exemplary embodiments of the present disclosure provide a display device comprising: a display panel including a pixel including a light emitting device, wherein the pixel receives a data signal corresponding to a gate signal, the light emitting device emits light by receiving a driving current flowing from a first power voltage to a second power voltage in response to the data signal, and the pixel receives a reset voltage at least once after receiving one data signal and before receiving the next data signal; a data driver circuit configured to supply the data signal to the pixel through a data line; a gate driver circuit configured to supply the gate signal to the pixel through a gate line and output a light emission control signal for controlling supply of one of the reset voltage and the first power voltage to the light emitting device; and a timing controller configured to control the data driver circuit and the gate driver circuit.

[10] When a first time period elapses after the reset voltage is transmitted to the light emitting device, the first power voltage may be transferred to the light emitting device, and the first time period may be determined by the light emission control signal.

[11] In addition, exemplary embodiments of the present disclosure provide a display device comprising: a display panel driven in one of a first frequency mode in which a data signal is supplied in response to a first frequency and a second frequency mode in which the data signal is supplied in response to a second frequency lower than the first frequency; a gate driver circuit configured to supply a gate signal and a light emission control signal to the display panel; a data driver circuit configured to supply the data signal to the display panel; and a timing controller configured to control the data driver circuit and the gate driver circuit, wherein each of the first frequency mode and the second frequency mode includes at least one light emission period and at least one non-light emission period, and wherein in the first frequency mode and the second frequency mode, the number of times the light emission period and the non-light emission period are generated are the same.

[12] In addition, exemplary embodiments of the present disclosure provide a driving method of a display device including a pixel including a light emitting device, the pixel receives a data signal corresponding to a gate signal, the light emitting device emits light by receiving a driving current flowing from a first power voltage to a second power voltage in response to the data signal, the driving method comprising: supplying the data signal and the first power voltage to the pixel, and supplying a driving current generated in response to the data signal to the light emitting device in the pixel; cutting off the first power voltage supplied to the pixel and supplying a reset voltage to the pixel while the pixel holds the data signal; supplying the first power voltage to the pixel; and supplying the data signal to the pixel.

[13] According to the exemplary embodiments of the present specification, by selectively selecting one of a high frequency and a low frequency to be driven, there is an effect of reducing power consumption consumed in the display device.

[14] In addition, according to the exemplary embodiments of the present specification, when the display device is driven at a low frequency, a change in luminance occurring in the display device can be minimized, thereby preventing deterioration of image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[15] The above and other aspects, features and advantages of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view illustrating a display device according to example embodiments of the present specification. FIGS. 2A and 2B are timing diagrams illustrating a change in luminance in a display device according to example embodiments of the present specification. FIG. 3 is a conceptual diagram illustrating a pixel illustrated in FIG. 1. FIG. 4 is a timing diagram illustrating that luminance is changed by a reset voltage in the pixel shown in FIG. 3. FIGS. 5A and 5B are timing diagrams illustrating an operation of a display device according to exemplary embodiments of the present specification. FIG. 6A is a timing diagram showing that the rate at which the voltage of the anode electrode increases in the refresh period is greater than the rate at which the voltage of the anode electrode increases in the reset period. FIG. 6B is a timing diagram showing that the rate at which the voltage of the anode electrode increases in the refresh period is lower than the rate at which the voltage of the anode electrode increases in the reset period. FIG. 7A is a timing diagram showing that the start point of the refresh period is adjusted. FIG. 7B is a timing diagram showing that the start point of the reset period is adjusted. FIG. 7C is a timing diagram showing that the end point of the refresh period is adjusted. FIG. 7D is a timing diagram showing that the end point of the reset period is adjusted. FIG. 8 is a circuit diagram illustrating an embodiment of the pixel illustrated in FIG. 1. FIG. 9 is a timing diagram illustrating an operation in a refresh period of the pixel shown in FIG. 8. FIG. 10 is a timing diagram illustrating an operation in a reset period of the pixel shown in FIG. 8. FIG. 11 is a structural diagram illustrating the timing controller shown in FIG. 1. FIG. 12 is a flowchart illustrating a method of driving a display device according to exemplary embodiments of the present specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[16] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which it is shown by way of illustration specific examples or embodiments that can be implemented, and in which the same reference numerals and signs can be used to designate the same or like components even when they are shown in different accompanying drawings from one another. Further, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure rather unclear. The terms such as “including”, “having”, “containing”, “constituting” “make up of”, and “formed of” used herein are generally intended to allow other components to be added unless the terms are used with the term “only”. As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[17] Terms, such as “first”, “second”, “A”, “B”, “(A)”, or “(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define essence, order, sequence, or number of elements etc., but is used merely to distinguish the corresponding element from other elements.

[18] When it is mentioned that a first element "is connected or coupled to", “contacts or overlaps” etc. a second element, it should be interpreted that, not only can the first element “be directly connected or coupled to” or “directly contact or overlap” the second element, but a third element can also be "interposed" between the first and second elements, or the first and second elements can "be connected or coupled to", “contact or overlap”, etc. each other via a fourth element. Here, the second element may be included in at least one of two or more elements that "are connected or coupled to", “contact or overlap”, etc. each other.

[19] When time relative terms, such as "after," "subsequent to," "next," "before," and the like, are used to describe processes or operations of elements or configurations, or flows or steps in operating, processing, manufacturing methods, these terms may be used to describe non-consecutive or non-sequential processes or operations unless the term "directly" or "immediately" is used together.

[20] In addition, when any dimensions, relative sizes etc. are mentioned, it should be considered that numerical values for an elements or features, or corresponding information (e.g., level, range, etc.) include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impact, noise, etc.) even when a relevant description is not specified. Further, the term “may” fully encompasses all the meanings of the term “can”.

[21] FIG. 1 is a plan view illustrating a display device 100 according to example embodiments of the present specification.

[22] Referring to FIG. 1, the display device 100 may include a display panel 110, a data driver circuit 120, a gate driver circuit 130, and a timing controller 140.

[23] The display panel 110 may include a plurality of pixels 101. The plurality of pixels 101 may be arranged in a matrix form within the display panel 110, but the present invention is not limited thereto. Each of the plurality of pixels 101 may emit light of various colors such as red, green, or blue. However, the color of light emitted from each pixel is not limited thereto. Also, for example, the display panel 110 may have a rectangular shape.

[24] A plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm may be disposed on the display panel 110. The plurality of pixels 101 may be connected to the gate lines GL1 to GLn and the data lines DL1 to DLm. Each pixel 101 may receive a data signal transmitted through the corresponding data line among the data lines DL1 to DLm in response to a gate signal transmitted through the corresponding gate line among the gate lines GL1 to GLn. In addition, a plurality of light emission control lines EML1 to EMLn may be disposed on the display panel 110. The light emission control lines EML1 to EMLn transmit light emission control signals to the plurality of pixels 101, so that the time for the plurality of pixels 101 to emit light may be controlled.

[25] The data driver circuit 120 may be electrically connected to the plurality of data lines DL1 to DLm to transmit the data signal to the pixel 101 through the data lines DL1 to DLm. Here, although one data driver circuit 120 is shown, it is not limited thereto. In addition, the data driver circuit 120 may supply a reset voltage to the plurality of data lines DL1 to DLm. However, the present invention is not limited thereto, and the reset voltage may be transmitted through separate lines different from the plurality of data lines DL1 to DLm. The data driver circuit 120 may be an integrated circuit.

[26] The gate driver circuit 130 may be electrically connected to the plurality of gate lines GL1 to GLn and may supply gate signals to the plurality of pixels 101 through the plurality of gate lines GL1 to GLn.

[27] The gate driver circuit 130 may be electrically connected to the plurality of light emission control lines EML1 to EMLn and may supply light emission control signals to the plurality of pixels 101 through the plurality of light emission control lines EML1 to EMLn.

[28] Here, the gate driver circuit 130 is shown to be disposed on one side of the display panel 110, but is not limited thereto, and may be disposed on both sides of the display panel 110. Further, the display device 100 may not include a separate gate driver circuit separated from the display panel 110, but may include a gate driver circuit 130 disposed in the display panel 110 in a gate generating circuit type (referred to as the GIP (Gate In Panel) type). When the gate driver circuit 130 is included in the display device 100 in the gate generating circuit type (GIP type), the gate driver circuit 130 may be formed on the display panel 110 while the plurality of pixels 101 are formed on the display panel 110.

[29] The timing controller 140 may control the data driver circuit 120 and the gate driver circuit 130. The timing controller 140 may supply the image signal RGB and the data control signal DCS to the data driver circuit 120 and may supply the gate control signal GCS to the gate driver circuit 130.

[30] In addition, the display device 100 may operate in a first frequency mode that emits light in response to a first frequency and a second frequency mode that emits light in response to a second frequency lower than the first frequency. An image displayed on the display device 100 has a plurality of frames. If the image is driven in the second frequency mode, the time for which one frame is maintained becomes longer. When the time for which one frame is held increases, the number of signals generated and processed by the data driver circuit 120, the gate driver circuit 130, and the timing controller 140 may decrease. Accordingly, power consumption in the display device 100 may be lowered. Accordingly, when the display device 100 operates in the second frequency mode, power consumption of the display device 100 may be lowered.

[31] In addition, while the display device 100 is operating in the second frequency mode, the pixel 101 may receive the reset voltage.

[32] And, the timing controller 140 may select that the display device 100 operates in a first frequency mode or a second frequency mode, and may control the data driver circuit 120 and the gate driver circuit 130 according to the selected first frequency mode or the second frequency mode.

[33] FIGS. 2A and 2B are timing diagrams illustrating a change in luminance in the display device 100 according to example embodiments of the present specification. FIG. 2A shows a case of operating in a first frequency mode, and FIG. 2B shows a case of operating in a second frequency mode.

[34] Referring to FIGS. 2A and 2B, the display device 100 may operate in the first frequency mode operating in response to the first frequency and a second frequency mode operating in response to a second frequency lower than the first frequency. For example, the first frequency may be 60 Hz and the second frequency may be 1 Hz. However, values of the first frequency and the second frequency are not limited thereto.

[35] As illustrated in FIG. 2A, when the display device 100 is driven at 60 Hz, the data signal 60 times may be written to the pixel 101 in one second (1 s). On the other hand, as illustrated in FIG. 2B, when the display device 100 is driven at 1 Hz, a data signal may be written to the pixel 101 once every second (1 s). A period in which a data signal is newly written in the pixel 101 and an image is displayed corresponding to the written data signal may be referred to as a "refresh period".

[36] The pixel 101 includes a plurality of transistors. When a data signal is written to the pixel 101, a kickback phenomenon may occur due to the operation of transistors included in the pixel 101. The luminance of light emitted from the pixel 101 may be lowered due to the kickback phenomenon that occurs when the data signal is written to the pixel 101.

[37] Accordingly, as shown in FIG. 2A, when the display device 100 is driven at 60 Hz, the image displayed on the display device 100 has a luminance decrease of 60 times per second (1 s). As shown in FIG. 2B, when the display device 100 is driven at 1 Hz, an image displayed on the display device 100 may have a luminance decrease once every 1 second (1 s).

[38] If the luminance decrease occurs 60 times in 1 second (1s), the user may not be able to recognize that the luminance decreases in the image displayed on the display device 100. However, when the luminance decrease occurs once every second (1s) in the displayed image, the user may recognize that the luminance of the image displayed on the display device 100 decreases.

[39] Therefore, when the display device 100 is driven in a second frequency mode that operates in response to the second frequency in order to reduce power consumption, the user may recognize that the image displayed on the display device 100 is flickering. When a still image is displayed on the display device 100, the user may feel a flickering of the image displayed on the display device 100 to a greater extent.

[40] FIG. 3 is a conceptual diagram illustrating the pixel 101 illustrated in FIG. 1. FIG. 4 is a timing diagram illustrating that luminance is changed by a reset voltage Vreset in the pixel 101 shown in FIG. 3.

[41] Referring to Figures 3 and 4, the pixel 101 may include a light emitting device ED that emits light by receiving a driving current Id, and a pixel circuit 101 p supplying a driving current Id to the light emitting device ED.

[42] The light emitting device ED may include an anode electrode 101a, a cathode electrode 101c, and a light emitting layer 101b disposed between the anode electrode 101a and the cathode electrode 101c. For example, the light emitting device ED may be a light emitting diode. In particular, the light emitting device ED may be an organic light emitting diode (OLED).

[43] The pixel circuit 101 p may receive the first power voltage EVDD from the first node N1. The pixel circuit 101 p may receive the data signal Vdata or the reset voltage Vreset from the data line DL. Further, by the operation of the pixel circuit 101p, the second node N2 is electrically connected to the point (first node N1) where the first power voltage EVDD is applied through the pixel circuit 101p, or the second node N2 may be applied with the reset voltage Vreset through the pixel circuit 101p. Since the second node N2 is electrically connected to the anode electrode 101a of the light emitting device ED, the anode electrode 101a of the light emitting device ED may be electrically connected to the first power voltage EVDD or applied with the reset voltage Vreset. The voltage level of the first power voltage EVDD may be higher than the voltage level of the second power voltage EVSS. Also, the voltage level of the reset voltage Vreset may be a voltage level lower than the threshold voltage of the light emitting device ED.

[44] By the operation of the pixel circuit 101 p, the first power voltage EVDD is applied to the anode electrode 101a of the light emitting device ED and the second power voltage EVSS is applied to the cathode electrode 101c. Then, the voltage level of the anode electrode 101a becomes higher than the voltage level of the cathode electrode 101c. Accordingly, the driving current Id may flow from the anode electrode 101a to the cathode electrode 101c. Since the light-emitting layer 101b emits light when the driving current Id flows, the light-emitting layer 101b can emit light in response to the data signal Vdata.

[45] On the other hand, when the reset voltage Vreset is applied to the anode electrode 101a and the first power voltage EVDD is not transmitted, the voltage level of the anode electrode 101a may be lowered by the reset voltage Vreset. Accordingly, even if the data signal Vdata is supplied to the pixel circuit 101p, the driving current Id may not flow from the anode electrode 101a to the cathode electrode 101c. Accordingly, when the reset voltage Vreset is applied to the anode electrode 101a, the light emitting device ED may not emit light. Here, the reset voltage Vreset is illustrated as being transmitted through the data line DL, but is not limited thereto. And, when the first power voltage EVDD is again supplied to the anode electrode 101a, the voltage level of the anode electrode 101a increases, so that a driving current flows through the light emitting device ED, and the light emitting device ED emits light. When the first power voltage EVDD is again supplied to the anode electrode 101a, the reset voltage Vreset may not be transmitted to the anode electrode 101a.

[46] Accordingly, since the light emitting device ED does not emit light when the reset voltage Vreset is applied, the luminance may be temporarily lowered in the image displayed on the display device 100. In addition, when the reset voltage Vreset is periodically applied to the anode electrode 101a, as shown in FIG. 4, the luminance decreases repeatedly, resulting in a luminance change such as driving at 60 Hz.

[47] For the above reasons, even if the display device 100 is driven in the second frequency mode, the user may not be able to recognize that the luminance of the image displayed on the display device 100 is deteriorated. And, in a state in which the voltage of the data signal Vdata is constant, the voltage level of the anode electrode 101a may be lowered by the transmission of the reset voltage Vreset, and may be raised again by the voltage level of the data signal Vdata. This period may be referred to as a "reset period".

[48] FIGS. 5A and 5B are timing diagrams illustrating an operation of the display device 100 according to exemplary embodiments of the present specification.

[49] Referring to FIG. 5A, when the display device 100 is driven in the first frequency mode, since data signals are periodically written to the pixel 101, the refresh period Trefresh in which the data signal is written to the pixel 101 may be periodically repeated. For example, when the display device 100 is driven in a first frequency mode driven at a driving frequency of 60 Hz, the refresh period Trefresh may be repeated 60 times per second.

[50] On the other hand, referring to FIG. 5B, when the display device 100 is driven in the second frequency mode, since the data signal Vdata may be written once for a certain time, a refresh period Trefresh may appear once for a certain period of time, and a reset period Treset in which the reset voltage Vreset is applied to the anode electrode 101a may repeatedly appear. Accordingly, it is possible to prevent a decrease in luminance from being recognized in the second frequency mode. For example, when the display device 100 is driven in a second frequency mode driven at 1 Hz, after the refresh period Trefresh in which the data signal is written to the pixel 101 appears once for 1 second (1s), the reset period Treset may appear 59 times in succession.

[51] The rate (speed) at which the voltage level of the anode electrode 101a increases during the refresh period Trefresh and the rate (speed) at which the voltage level of the anode electrode 101a increases during the reset period Treset may be different. Due to the difference in speed at which the voltage level of the anode electrode 101a increases, the time to emit light from the light emitting device ED may be different. Accordingly, due to a difference in speed at which the voltage level of the anode electrode 101a increases, the luminance of the display device 100 may be different. More specifically, due to the difference in the speed at which the voltage level of the anode electrode 101a increases, the light emitting time (amount of light emission) of the light emitting device ED in the refresh period Trefresh and the light emitting time (amount of light emission) of the light emitting device ED in the reset period Treset may be different from each other. Accordingly, the luminance of the display device 100 may be different from each other in the refresh period (Trefresh) and the reset period (Treset).

[52] FIG. 6A is a timing diagram showing that the rate (speed) at which the voltage of the anode electrode 101a increases in the refresh period is greater than the rate (speed) at which the voltage of the anode electrode 101a increases in the reset period. FIG. 6B is a timing diagram showing that the rate at which the voltage of the anode electrode 101a increases in the refresh period is lower than the rate at which the voltage of the anode electrode 101a increases in the reset period.

[53] As shown in Figure 6A, when the rate at which the voltage Va at the anode electrode 101a of the light emitting device ED increases during the refresh period Trefresh is faster than the rate at which the voltage Va increases during the reset period Treset, the timing of emitting light from the light emitting device ED during the refresh period Trefresh may be earlier than the timing of emitting light from the light emitting device ED during the reset period Treset. Accordingly, the amount of light emitted by the display device 100 during the refresh period Trefresh is greater than the amount of light emitted by the display device 100 during the reset period Treset. Accordingly, the luminance of the display device 100 during the refresh period Trefresh may be higher than that of the display device during the reset period Treset.

[54] And, as shown in Figure 6B, when the rate at which the voltage Va increases at the anode electrode 101a of the light emitting device ED during the refresh period Trefresh is slower than the rate at which the voltage Va increases at the anode electrode 101a during the reset period Treset, the timing of emitting light from the light emitting device ED during the refresh period Trefresh may be later than the timing of emitting light from the light emitting device ED during the reset period Treset. Accordingly, the amount of light emitted by the display device 100 during the refresh period Trefresh may be smaller than the amount of light emitted by the display device 100 during the reset period Treset. Accordingly, in the refresh period Trefresh, the luminance of the display device 100 may be lower than that of the display device 100 in the reset period Treset.

[55] Accordingly, when the display device 100 operates in the second frequency mode, the amount of light emitted by the light emitting device ED may be different in the refresh period Trefresh and the reset period Treset. Thus, a difference may occur between the luminance of the display device 100 in the refresh period Trefresh and the luminance of the display device 100 in the reset period Treset. That is, the luminance of the display device 100 during the refresh period Trefresh becomes higher or lower than the luminance of the display device 100 during the reset period Treset, and the user can recognize that the image displayed on the display device 100 is flickering.

[56] By controlling the amount of light emitted by the light emitting device ED during the refresh period Trefresh and the amount of light emitted from the light emitting device ED during the reset period Treset to be the same, the problem of recognizing a flickering image can be solved. In addition, in order to equalize the amount of light emitted from the light emitting device ED during the refresh period Trefresh and the amount of light emitted from the light emitting device ED during the reset period Treset, the point in time when the driving current Id flows to the light emitting device ED may be adjusted.

[57] FIG. 7A is a timing diagram showing that the start point of the refresh period is adjusted, FIG. 7B is a timing diagram showing that the start point of the reset period is adjusted, FIG. 7C is a timing diagram showing that the end point of the refresh period is adjusted, and FIG. 7D is a timing diagram showing that the end point of the reset period is adjusted.

[58] Adjusting the start point and end point of the refresh period Trefresh and the start point and end point of the reset period Treset can be achieved by controlling the point in time when the driving current Id is supplied to the light emitting device ED.

[59] As shown in Fig. 7A, by controlling the start point at which the voltage level Va of the anode electrode 101a increases during the refresh period Trefresh differently as in cases i, ii, and Hi, the timing at which the driving current Id is supplied to the light emitting device ED can be controlled differently.

[60] Referring to FIG. 7A, the time point when the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh may be the fastest in case i and the slowest in case iii. Based on case ii, when the luminance of the reset period Treset is lower than the luminance of the refresh period Trefresh, the start point (start timing) at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh may be controlled to be slower so that the start point (start timing) at which the voltage level Va of the anode electrode 101a increases during the refresh period Trefresh becomes the start point in case iii.

[61] In addition, based on case ii, when the luminance of the reset period Treset is higher than the luminance of the refresh period Trefresh, the start point (start timing) at which the voltage level Va of the anode electrode 101a rises during the refresh period Trefresh may be controlled to be faster so that the start point (start timing) at which the voltage level Va of the anode electrode 101a increases during the refresh period Trefresh becomes the start point in case i.

[62] Referring to FIG. 7B, the time point when the voltage level Va of the anode electrode 101a increases during the reset period Treset may be the fastest in case i, and the slowest in case iii. Based on case ii, when the luminance during the reset period Treset is lower than the luminance during the refresh period Trefresh, the start point (start timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset may be controlled to be faster so that the start point (start timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset becomes the starting point in case i.

[63] Also, based on case ii, when the luminance during the reset period Treset is higher than the luminance during the refresh period Trefresh, the start point (start timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset may be controlled to be slower so that the start point (start timing) at which the voltage level Va of the anode electrode 101a increases during the reset period Treset becomes the starting point in case Hi.

[64] Further, as shown in Fig. 7C, the time point at which the driving current Id supplied to the light emitting device ED is cut off during the refresh period Trefresh may be controlled differently as in cases i, ii, and ill, so that the timing at which the supply of the driving current Id to the light emitting device ED is terminated may be controlled differently.

[65] Referring to FIG. 7C, the time point when the driving current Id supplied to the light emitting device ED is cut off during the refresh period Trefresh may be the fastest in case i, and the slowest in case ill. Based on case ii, when the luminance during the reset period Treset is higher than the luminance during the refresh period Trefresh, the blocking point (blocking timing) at which the driving current Id supplied to the light emitting device ED is cut off during the refresh period Trefresh may be controlled to be slower so that the blocking point (blocking timing) at which the driving current Id supplied to the light emitting device ED is cut off during the refresh period Trefresh becomes the blocking point in case iii.

[66] Further, as shown in Fig. 7D, the time point at which the driving current Id supplied to the light emitting device ED is cut off during the reset period Treset may be controlled differently as in cases i, ii, and iii, so that the timing at which the supply of the driving current Id to the light emitting device ED is terminated may be controlled differently.

[67] Referring to FIG. 7D, the time point when the driving current Id supplied to the light emitting device ED is cut off during the reset period Treset may be the fastest in case i, and the slowest in case iii. Based on case ii, when the luminance during the reset period Treset is lower than the luminance during the refresh period Trefresh, the blocking point (blocking timing) at which the driving current Id supplied to the light emitting device ED is cut off during the reset period Treset may be controlled to be slower so that the blocking point (blocking timing) at which the driving current Id supplied to the light emitting device ED is cut off during the reset period Treset becomes the blocking point in case iii.

[68] FIG. 8 is a circuit diagram illustrating an embodiment of the pixel 101 illustrated in FIG. 1.

[69] Referring to FIG. 8, the pixel 101 may include the pixel circuit 101p and the light emitting device ED. The pixel circuit 101 p may include first to fourth nodes N1 to N4 as electrical nodes. A plurality of signal lines for driving the pixel circuit 101p may include a data line DL, first and second gate lines GL1 and GL2, and first and second light emission control lines EML1 and EML2.

[70] The pixel circuit 101p may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a capacitor Cst. The first transistor M1 may supply a driving current to the light emitting device ED in response to a data signal Vdata. The second transistor M2 may supply the data signal Vdata from the data line DL to the first transistor M1 in response to a first gate signal GATE1. The third transistor M3 may supply the first power voltage EVDD to the first transistor M1 in response to a first light emission control signal EMS1. The fourth transistor M4 may supply the first power voltage EVDD or the reset voltage Vreset to the light emitting device ED in response to a second light emission control signal EMS2. The fifth transistor M5 may cause the first transistor M1 to be a diode connection in response to a second gate signal GATE2. The capacitor Cst may hold the data signal Vdata supplied to the first transistor M1. The sixth transistor M6 may deliver an initialization voltage Vini for initializing the capacitor Cst and the anode electrode 101a (corresponding to the node N4) of the light emitting device ED to the capacitor Cst in response to the second gate signal GATE2.

[71] The first transistor M1 may include the first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3. The first transistor M1 may supply the driving current from the first node N1 to the second node N2 in response to the data signal Vdata transmitted to the third node N3.

[72] The second transistor M2 may include a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate electrode connected to the first gate line GL1. The second transistor M2 may supply the data signal Vdata flowing through the data line DL to the third node N3 in response to the first gate signal GATE1 transmitted to the first gate line GL1.

[73] The third transistor M3 may have a first electrode connected to the first power voltage EVDD, a second electrode connected to the first node N1, and a gate electrode connected to the first light emission control line EML1. The first power voltage EVDD may be supplied to the first electrode of the third transistor M3 through the first power line VL1. The third transistor M3 may supply the first power voltage EVDD to the first node N1 in response to the first light emission control signal EMS1 transmitted through the first light emission control line EML1. When the third transistor M3 is turned on and the first power voltage EVDD is supplied to the first node N1, the first transistor M1 receives the first power voltage EVDD. Accordingly, when the first transistor M1 is turned on, a driving current corresponding to the data signal DL may flow from the first node N1 to the second node N2.

[74] The fourth transistor M4 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4, and a gate electrode connected to the second light emission control line EML2. The fourth transistor M4 may electrically connect the second node N2 and the light emitting device ED in response to the second light emission control signal EMS2 transmitted through the second light emission control line EML2. When the fourth transistor M4 is turned on and the light emitting device ED is electrically connected to the second node N2, the driving current flowing from the first node N1 to the second node N2 can be transferred to the light emitting device ED. Accordingly, the light emitting device ED can emit light.

[75] The fifth transistor M5 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode connected to the second gate line GL2. The fifth transistor M5 may electrically connect the first node N1 and the third node N3 in response to the second gate signal GL2 transmitted to the second gate line GL2. When the first node N1 and the third node N3 are electrically connected, the first transistor M1 may be in a diode-connected state. Accordingly, the first transistor M1 may operate like a diode.

[76] The capacitor Cst may include a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4. The capacitor Cst may maintain a voltage applied to the third node N3.

[77] The sixth transistor M6 may include a first electrode connected to the initialization voltage line VL2 transmitting the initialization voltage Vini, a second electrode connected to the fourth node N4, and a gate electrode connected to the second gate line GL2. The sixth transistor M6 may be turned on in response to the second gate signal GATE2 to transmit the initialization voltage Vini transmitted through the initialization voltage line VL2 to the fourth node N4. The fourth node N4 may be connected to the second electrode of the capacitor Cst and the anode electrode 101a of the light emitting device ED. When the sixth transistor M6 is turned on, the second electrode of the capacitor Cst and the anode electrode 101a of the light emitting device ED may be initialized by the initialization voltage Vini.

[78] In the light emitting device ED, the anode electrode 101a may be electrically connected to the fourth node N4 and the cathode electrode 101c may be electrically connected to the second power voltage EVSS. The light emitting device ED may emit light by the amount of current flowing from the anode electrode 101a to the cathode electrode 101c. The light emitting device ED may emit light when the fifth transistor M5 is turned on and a driving current is supplied from the first transistor M1.

[79] Here, as shown in FIG. 8, the reset voltage Vreset is supplied to the data line DL, and the reset voltage Vreset supplied to the data line DL may be transmitted to the anode electrode 101a of the light emitting device ED through the second transistor M2 and the fourth transistor M4. In FIG. 8, the reset voltage Vreset is shown to be transmitted to the anode electrode 101a of the light emitting device ED through the data line DL, but is not limited thereto. The reset voltage Vreset may be transmitted to the anode electrode 101a of the light emitting device through a separate line different from the data line DL. In addition, the circuit diagram of the pixel is shown in Fig. 8 for illustrative purpose only, and embodiments of the present disclosure are not limited thereto. For example, the pixel in the display device of the present disclosure may have various circuit structures in addition to the circuit structure shown in Fig. 8.

[80] FIG. 9 is a timing diagram illustrating an operation in a refresh period of the pixel shown in FIG. 8.

[81] Referring to FIG. 9, the refresh period Trefresh is a period in which light is emitted in response to the data signal Vdata written in the pixel 101 after the data signal Vdata is written in the pixel 101. The refresh period Trefresh may include the first to third periods Tf 1 to Tf3.

[82] In the first period Tf1, the first gate signal GATE1 may be transmitted in a low state (also referred to as an off state or a turn-off level voltage state)and the second gate signal GATE2 may be transmitted in a high state (also referred to as an on state or turn-on level voltage state). In addition, in the first period Tf1, the first light emission control signal EMS1 may be transmitted in the high state and the second light emission control signal EMS2 may be transmitted in the low state. Here, each of the gate signals GATE1 and GATE2 and the light emission control signals EMS1 and EMS2 may have the low state or the high state. For example, in the embodiments of the present disclosure, it is assumed that the first to sixth transistors M1 to M6 are applied as n-type. In this case, the low state (low level voltage state) of signals (GATE1, GATE2, EMS1, and EMS2) may be a turn-off level voltage state, and the high state (high level voltage state) of signals (GATE1, GATE2, EMS1, and EMS2) may be a turn-on level voltage state. For another example, all or part of the first to sixth transistors M1 to M6 may be applied as p-type. In this case, in the signal applied to the p-type transistor, the low state may be a turn-on level voltage state, and the high state may be a turn-off level voltage state.

[83] Accordingly, the second transistor M2 and the fourth transistor M4 may be turned off, and the third transistor M3, the fifth transistor M5, and the sixth transistor M6 may be turned on. When the sixth transistor M6 is turned on, the initialization voltage Vini transmitted through the initialization voltage line VL2 may be supplied to the fourth node N4 through the sixth transistor M6. At this time, since the second transistor M2 and the fourth transistor M4 are in the off state and the third transistor M3 and the fifth transistor M5 are in the on state, the capacitor Cst and the anode electrode 101a of the light emitting device ED may be initialized by the initialization voltage Vini.

[84] In addition, in the second period Tf2, the first gate signal GATE1 may be in the high state, and the second gate signal GATE2 may be in the low state for a certain period of the second period Tf2 and then may be changed to the high state for the remainder of the second period Tf2. In addition, in the second period Tf2, the first light emission control signal EMS1 and the second light emission control signal EMS2 may be in the low state.

[85] When the first gate signal GATE1 is in the high state, the second transistor M2 is turned on. Accordingly, the data signal Vdata supplied to the data line DL may be transmitted to the second node N2. In addition, when the second gate signal GATE2 is in the low state, the fifth transistor M5 and the sixth transistor M6 are in the off state. Accordingly, the initialization voltage Vini may not be transmitted to the capacitor Cst and the anode electrode 101a of the light emitting device ED.

[86] In addition, when the second gate signal GATE2 changes to the high state, the fifth transistor M5 is turned on. Accordingly, the first transistor M1 may be in a diode connection state. When the first transistor M1 is in a diode connection state, the data signal Vdata transmitted to the second node N2 may be supplied to the third node N3 through the first node N1. In this case, when the data signal Vdata is supplied to the third node N3, the threshold voltage of the first transistor M1 may be compensated. Accordingly, the data signal Vdata stored in the third node N3 may have a voltage value in which the threshold voltage of the first transistor M1 is compensated.

[87] In addition, in the third period Tf3, the first gate signal GATE1 and the second gate signal GATE2 may be in the low state, and the second light emission control signal EMS2 and the first light emission control signal EMS1 may be sequentially changed from the low state to the high state. In the third period Tf3, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 may be turned off by the first gate signal GATE1 and the second gate signal GATE2. In the third period Tf3, the third transistor M3 and the fourth transistor M4 may be sequentially turned on by the second light emission control signal EMS2 and the first light emission control signal EMS1.

[88] When the third transistor M3 and the fourth transistor M4 are sequentially turned on, a driving current may flow from the first node N1 to the second node N2 by the first transistor M1. Accordingly, the driving current may be supplied to the light emitting device ED, and the light emitting device ED may emit light in response to the supplied driving current.

[89] In this case, the third transistor M3 and the fourth transistor M4 may be turned on with a difference between the first time period t1. That is, the fourth transistor M4 may be turned on first, and the third transistor M3 may be turned on later. After the first time period t1 elapses from the point when the fourth transistor M4 is turned on, the third transistor M3 may be turned on. The first time period t1 may be adjusted according to the rate at which the voltage of the anode electrode of the light emitting device ED increases during the refresh period Trefresh or the reset period Treset.

[90] When the rate at which the voltage of the anode electrode increases during the refresh period is faster than the rate at which the voltage of the anode electrode increases during the reset period, the first time period t1 may be set to be short. In addition, when the rate at which the voltage of the anode electrode increases during the refresh period is slower than the rate at which the voltage of the anode electrode increases during the reset period, the first time period t1 may be set longer. When the third transistor M3 is turned on, the first power voltage EVDD is applied to the first transistor M1 of the pixel 101 so that the driving current can flow from the first transistor M1. Accordingly, in order to shorten the first time period t1, the turn-on timing of the third transistor M3, which is turned on after the fourth transistor M4 is turned on, may be accelerated (faster). In order to set the first time period t1 to be long, the turn-on timing of the third transistor M3 that is turned on after the fourth transistor M4 is turned on may be delayed (slower).

[91] FIG. 10 is a timing diagram illustrating an operation in a reset period of the pixel shown in FIG. 8.

[92] Referring to FIG. 10, the reset period Treset may be a period in which the luminance of an image displayed on the display device 100 decreases by supplying a reset voltage Vreset to the anode electrode 101a of the light emitting device ED to prevent the driving current from being supplied to the light emitting device ED. During a period in which one data signal Vdata is written to the capacitor Cst and the data signal Vdata is maintained in the capacitor Ost, the reset period Treset may be repeated, thereby preventing the user from recognizing the decrease in luminance of the image.

[93] The reset period Treset may include a first to third periods Tr1 to Tr3. In the reset period Treset, in order to prevent the data signal Vdata from being transmitted to the pixel 101, the second gate signal GATE2 may be maintained in a low state. Accordingly, the fifth transistor M5 and the sixth transistor M6 may be maintained in the off state during the reset period Treset. In addition, during the reset period Treset, the data signal Vdata transmitted in the refresh period Trefresh may be maintained at the capacitor Cst.

[94] In the first period Tr1, the reset voltage Vreset may be transmitted to the data line DL. However, the present disclosure is not limited thereto, and the reset voltage Vreset in the first period Tr1 may be transmitted through a separate line different from the data line DL. In addition, in the first period Tr1, the first gate signal GATE1 may change from the low state to the high state, and the first light emission control signal EMS1 may change from the high state to the low state. In addition, the second light emission control signal EMS2 may maintain the low state. Accordingly, in the first period Tr1, the second transistor M2 may be turned on and the third transistor M3 and the fourth transistor M4 may be turned off. When the second transistor M2 is turned on, the reset voltage Vreset supplied to the data line DL may be transmitted to the second node N2 through the second transistor M2.

[95] Then, in the second period Tr2, the first light emission control signal EMS1 may maintain the low state, the first gate signal GATE1 may change from a high state to a low state, and the second light emission control signal EMS2 may change from the low state to the high state. In the second period Tr2, a period in which the first gate signal GATE1 maintains the high state and a period in which the second light emission control signal EMS2 maintains the high state may overlap. That is, a period in which the fourth transistor M4 is turned on may overlap a period in which the second transistor M2 is turned on. While in the refresh period Trefresh, the period in which the fourth transistor M4 is turned on may not overlap the period in which the second transistor M2 is turned on, as shown in Fig. 9.

[96] When the first light emission control signal EMS1 is maintained in a low state, the third transistor M3 is maintained in an off state, so that the first power voltage EVDD is not supplied to the pixel 101. In addition, during a period in which both the first gate signal GATE1 and the second light emission control signal EMS2 are in the high state, the second transistor M2 and the fourth transistor M4 may be turned on. Accordingly, the reset voltage Vreset supplied to the data line DL may be transmitted to the fourth node N4 through the second node N2. Accordingly, the anode electrode 101a of the light emitting device ED may be initialized by the reset voltage Vreset.

[97] When the anode electrode 101a of the light emitting device ED is initialized by the reset voltage Vreset, the voltage of the anode electrode 101a of the light emitting device ED may be lowered, and the driving current may be not supplied to the light emitting device ED. Accordingly, when the anode electrode 101a of the light emitting device ED is initialized by the reset voltage Vreset, the light emitting device ED does not emit light, so that the luminance of the image displayed on the display device 100 decreases.

[98] In addition, in the third period Tr3, the first gate signal GATE1 may maintain the low state, and the second light emission control signal EMS2 may maintain the high state. During the third period Tr3, the first light emission control signal EMS1 may change from the low state to the high state. The timing at which the first light emission control signal EMS1 changes from the low state to the high state may be after the first time period t1 has elapsed from the time when the second light emission control signal EMS2 changes from the low state to the high state. In this case, the first time period t1 may be adjusted according to the rate at which the voltage of the anode electrode 101a increases during the refresh period Trefresh or the reset period Treset.

[99] In the refresh period Trefresh or the reset period Treset, when the rate at which the voltage of the anode electrode 101a increases is fast, the first time period t1 may be set to be short. In the refresh period Trefresh or the reset period Treset, when the rate at which the voltage of the anode electrode 101a increases is slow, the first time period t1 may be set to be long. In order to shorten the first time period t1, the timing at which the third transistor M3 is turned on after the fourth transistor M4 is turned on may be controlled to be relatively advanced. In order to set the first time period t1 to be long, a time point at which the third transistor M3 is turned on after the fourth transistor M4 is turned on may be controlled to be relatively delayed.

[100] FIG. 11 is a structural diagram illustrating the timing controller 140 shown in FIG. 1.

[101] Referring to FIG. 11, the timing controller 140 may include a first frequency driving mode circuit 141 performing a first frequency mode and a second frequency driving mode circuit 142 performing a second frequency mode. In addition, the timing controller 140 may select the first frequency driving mode circuit 141 or the second frequency driving mode circuit 142 in response to the selection signal.

[102] When the first frequency driving mode circuit 141 is selected by the selection signal, the timing controller 140 may output a data control signal DCS and a gate control signal GCS in response to the first frequency. Here, the data control signal DCS may include a clock, a start pulse, a synchronization signal, and the like. The timing controller 140 may supply the image signal RGB to the data driver circuit 120 based on a synchronization signal and a clock signal output in response to the first frequency. The timing controller 140 may cause the data driver circuit 120 to supply the data signal Vdata to the pixel 101 through the data line DL in response to the first frequency.

[103] In addition, when the second frequency driving mode circuit 142 is selected by the selection signal, the timing controller 140 may output the data control signal DCS and the gate control signal GCS in response to the second frequency. Here, the data control signal DCS may include a clock, a start pulse, a synchronization signal, and the like. In addition, the timing controller 140 may supply the image signal RGB to the data driver circuit 120 based on a synchronization signal and a clock signal output in response to the second frequency. In addition, the timing controller 140 may cause the data driver circuit 120 to supply the data signal Vdata or the reset voltage Vreset to the pixel 101 through the data line DL in response to the second frequency.

[104] The timing controller 140 may store information on the first time period t1 in FIG. 9 or 10. The timing controller 140 may adjust the timing at which the first light emission control signal EMS1 and the second light emission control signal EMS2 are output based on the stored first time period t1.

[105] After the fourth transistor M4 is turned on by the second light emission control signal EMS2, the first time period t1 that elapse until the third transistor M3 is turned on by the first light emission control signal EMS1 may be adjusted. Accordingly, a time point at which the refresh period Trefresh or the reset period Treset starts may be adjusted. Accordingly, a difference in luminance of images displayed on the display device 100 during the refresh period Trefresh and the reset period Treset may be suppressed to prevent the user from recognizing that the image flickers in the second frequency mode.

[106] In addition, the timing controller 140 may further include a selection circuit 143 that receives the selection signal and selects the first frequency driving mode circuit 141 or the second frequency driving mode circuit 142 based on the selection signal.

[107] FIG. 12 is a flowchart illustrating a method of driving the display device 100 according to exemplary embodiments of the present specification.

[108] Referring to FIG. 12, a pixel 101 in the display device 100 may receive a first power voltage EVDD (S1200). Also, the pixel 101 may receive a second power voltage EVSS having a lower voltage level than the first power voltage EVDD.

[109] The pixel 101 may receive the data signal Vdata (S1210). The data signal Vdata may be transmitted to the pixel 101 through the data line DL. The pixel 101 may include a light emitting device ED that emits light by a driving current flowing from the first power voltage EVDD to the second power voltage EVSS. The pixel 101 may receive the data signal Vdata in response to the gate signal. The gate signal may include a first gate signal GATE1 and a second gate signal GATE2. Also, when the pixel 101 may receive the data signal Vdata while receiving the first power voltage EVDD, the pixel 101 may generate a driving current corresponding to the data signal Vdata. The driving current may be supplied to the light emitting device ED.

[110] A reset voltage Vreset may be supplied to the pixel 101 (S1220). The reset voltage Vreset may be supplied to the pixel 101 through the data line DL. However, the present invention is not limited thereto, and the pixel 101 may receive the reset voltage Vreset through a line different from the data line DL. Theresetvoltage Vreset supplied to the pixel 101 maybe supplied to the anode electrode 101a of the light emitting device ED. When the reset voltage Vreset is supplied to the anode electrode 101a of the light emitting device ED, the power voltage EVDD may not be supplied to the pixel 101.

[111] Since the first power voltage EVDD is not supplied to the pixel 101, the voltage level of the anode electrode 101a receiving the reset voltage Vreset is lowered. Accordingly, the driving current does not flow through the light emitting device ED. When the driving current does not flow through the light emitting device ED, the light emitting device ED does not emit light, so that the luminance of an image displayed on the display device 100 may be lowered. Also, the voltage level of the reset voltage Vreset may be a voltage level lower than the threshold voltage of the light emitting device ED included in the pixel 101.

[112] When the first time period t1 elapses after the reset voltage Vreset is transmitted to the light emitting device, the first power voltage EVDD may be supplied to the pixel 101 again (S1230). When the first power voltage EVDD is supplied to the pixel 101, the voltage level of the anode electrode of the light emitting device ED may increase again. Accordingly, a driving current flows through the light emitting device ED, and the light emitting device ED emits light again. In addition, after the reset voltage Vreset is supplied again and the reset voltage Vreset is transmitted to the light emitting device again, when the first time period t1 elapses, the first power voltage EVDD may be supplied to the pixel 101. While the data signal Vdata is maintained, the reset voltage Vreset and the first power voltage EVDD may be repeatedly supplied.

[113] In addition, the length of the first time period t1 may be adjusted by adjusting the timing at which the first power voltage EVDD is supplied to the pixel 101. There may be a difference between a first luminance of the image after the data signal Vdata is supplied and before the reset voltage Vreset is supplied and a second luminance of the image after one reset voltage Vreset is supplied and before the next reset voltage Vreset is supplied. In this case, the first time period t1 after which the first power voltage EVDD is supplied may be adjusted. Here, it has been described that the first power voltage EVDD may be supplied after the reset voltage Vreset is cut off, but is not limited thereto, and the reset voltage Vreset may be cut off after the first power voltage EVDD is first supplied.

[114] In addition, a data signal Vdata may be supplied to the pixel 101 again (S1240). The data signal Vdata may be newly stored in the capacitor Cst in the pixel 101 by the data signal Vdata supplied to the pixel 101. In addition, after the capacitor Cst is initialized, the data signal Vdata may be stored in the capacitor Cst.

[115] In addition, the display device 100 may be driven in one of a first frequency mode driven with a first frequency and a second frequency mode driven with a second frequency lower than the first frequency. The display device 100 may supply the reset voltage Vreset while the data signal Vdata is maintained to the pixel 101 in the second frequency mode. The first frequency mode and the second frequency mode may be selected by the timing controller 140.

[116] Each of the first frequency mode and the second frequency mode may include a light-emitting period that emits light from the display device 100 and a non-emission period that does not emit light from the display device 100. The number of times the emission period and the non-emission period occur in the display device 100 may be the same in the first frequency mode and the second frequency mode.

[117] Clause 1. A display device comprising: a display panel including a pixel including a light emitting device, wherein the pixel receives a data signal corresponding to a gate signal, the light emitting device emits light by a driving current flowing from a first power voltage to a second power voltage in response to the data signal, and the pixel receives a reset voltage at least once after receiving one data signal and before receiving the next data signal; a data driver circuit configured to supply the data signal to the pixel through a data line; a gate driver circuit configured to supply the gate signal to the pixel through a gate line and output a light emission control signal for controlling supply of one of the reset voltage and the first power voltage to the light emitting device; and a timing controller configured to control the data driver circuit and the gate driver circuit.

[118] Clause 2. The display device according to clause 1, wherein when a first time period elapses after the reset voltage is transmitted to the light emitting device, the first power voltage is transferred to the light emitting device, and the first time period is determined by the light emission control signal.

[119] Clause 3. The display device according to clause 2, wherein the first time period is adjusted such that a flickering of an image displayed on the display device is removed.

[120] Clause 4. The display device according to clause 2 or 3, wherein the light emitting device includes an anode electrode, a cathode electrode, and a light emitting layer disposed between the anode electrode and the cathode electrode, and wherein the first power voltage or the reset voltage is transmitted to the anode electrode, and the second power voltage is transmitted to the cathode electrode.

[121] Clause 5. The display device according to clause 4, wherein the gate signal includes a first gate signal and a second gate signal, the light emission control signal includes a first light emission control signal and a second light emission control signal, and wherein the pixel comprises: a first transistor for supplying the driving current to the light emitting device in response to the data signal; a second transistor supplying the data signal from the data line to the first transistor in response to the first gate signal; a third transistor for supplying the first power voltage to the first transistor in response to the first light emission control signal; a fourth transistor for supplying the first power voltage or the reset voltage to the light emitting device in response to the second light emission control signal; a fifth transistor for causing the first transistor to be in a diode connection in response to the second gate signal; a capacitor for holding the data signal supplied to the first transistor; and a sixth transistor for transmitting an initialization voltage for initializing the capacitor and the anode electrode to the capacitor in response to the second gate signal.

[122] Clause 6. The display device according to clause 5, wherein the first time period is a time difference between the second light emission control signal and the first light emission control signal.

[123] Clause 7. The display device according to clause 5 or 6, wherein a period in which the fourth transistor is turned on overlap a period in which the second transistor is turned on.

[124] Clause 8. The display device according to any of clause 2 to 4, wherein the pixel comprises: a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor having a first electrode connected to the data line, a second electrode connected to the second node, and a gate electrode connected to a first gate line; a third transistor having a first electrode applied with the first power voltage, a second electrode connected to the first node, and a gate electrode connected to a first light emission control line; a fourth transistor having a first electrode connected to the second node, a second electrode connected to a fourth node, and a gate electrode connected to a second light emission control line; a fifth transistor having a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to a second gate line; a capacitor having a first electrode connected to the third node and a second electrode connected to the fourth node; and a sixth transistor having a first electrode connected to an initialization voltage line transmitting an initialization voltage, a second electrode connected to the fourth node, and a gate electrode connected to the second gate line,

[125] Clause 9. The display device according to any preceding clause, wherein the display panel operates in one of a first frequency mode operating in response to a first frequency and a second frequency mode operating in response to a second frequency lower than the first frequency, and wherein the reset voltage is transmitted through the data line in the second frequency mode.

[126] Clause 10. The display device according to any of clauses 2 to 9, wherein the timing controller stores information about a time when the reset voltage is supplied and the first time period.

[127] Clause 11. The display device according to any of clauses 1 to 8 or clause 9, wherein the reset voltage is transmitted through the data line.

[128] Clause 12. A display device comprising: a display panel driven in one of a first frequency mode in which a data signal is supplied in response to a first frequency and a second frequency mode in which the data signal is supplied in response to a second frequency lower than the first frequency; a gate driver circuit configured to supply a gate signal and a light emission control signal to the display panel; a data driver circuit configured to supply the data signal to the display panel; and a timing controller configured to control the data driver circuit and the gate driver circuit, wherein each of the first frequency mode and the second frequency mode includes at least one light emission period and at least one non-light emission period, and wherein in the first frequency mode and the second frequency mode, the number of times the light emission period and the non-light emission period are generated are the same.

[129] Clause 13. The display device according to clause 12, wherein the display panel includes a pixel in which the data signal is written in response to the gate signal, and the light emission period and the non-light emission period are determined in response to the light emission control signal, wherein the pixel includes a light emitting device having an anode electrode, a cathode electrode, and a light emitting layer disposed between the anode electrode and the cathode electrode, and wherein one of a first power voltage for supplying a driving current generated in response to the data signal and a reset voltage for resetting the voltage of the anode electrode is applied to the anode electrode.

[130] Clause 14. The display device according to clause 13, wherein when a first time period elapses after the reset voltage is transmitted to the light emitting device, the first power voltage is transferred to the light emitting device, and the first time period is determined by the light emission control signal.

[131] Clause 15. The display device according to clause 14, wherein the first time period is adjusted such that a flickering of an image displayed on the display device is removed.

[132] Clause 16. The display device according to clause 14 or 15, wherein the gate signal includes a first gate signal and a second gate signal, the light emission control signal includes a first light emission control signal and a second light emission control signal, and wherein the pixel comprises: a first transistor for supplying the driving current to the light emitting device in response to the data signal; a second transistor supplying the data signal from a data line to the first transistor in response to the first gate signal; a third transistor for supplying the first power voltage to the first transistor in response to the first light emission control signal; a fourth transistor for supplying the first power voltage or the reset voltage to the light emitting device in response to the second light emission control signal; a fifth transistor for causing the first transistor to be in a diode connection in response to the second gate signal; a capacitor for holding the data signal supplied to the first transistor; and a sixth transistor for transmitting an initialization voltage for initializing the capacitor and the anode electrode to the capacitor in response to the second gate signal.

[133] Clause 17. The display device according to clause 16, wherein the first light emission control signal and the second light emission control signal are generated with a time difference by the first time period.

[134] Clause 18. The display device according to clause 16 or 17, wherein in the second frequency mode, a period in which the fourth transistor is turned on overlap a period in which the second transistor is turned on.

[135] Clause 19. The display device according to clause 18, wherein in the first frequency mode, the period in which the fourth transistor is turned on does not overlap the period in which the second transistor is turned on.

[136] Clause 20. A driving method of a display device including a pixel including a light emitting device, the pixel receives a data signal corresponding to a gate signal, the light emitting device emits light by a driving current flowing from a first power voltage to a second power voltage in response to the data signal, the driving method comprising: supplying the data signal and the first power voltage to the pixel, and supplying a driving current generated in response to the data signal to the light emitting device in the pixel; cutting off the first power voltage supplied to the pixel and supplying a reset voltage to the pixel while the pixel holds the data signal; supplying the first power voltage to the pixel again; and supplying the data signal to the pixel again.

[137] Clause 21. The driving method according to clause 20, wherein the light emitting device emits light by receiving a first light emission control signal and a second light emission control signal, and the first light emission control signal and the second light emission control signal are generated at intervals of a first time period.

[138] Clause 22. The driving method according to clause 21, wherein the first light emission control signal is used to control the supplying of the first power voltage to the pixel, and the second light emission control signal is used to control the supplying of the first power voltage or the reset voltage to the light emitting device.

[139] Clause 23. The driving method according to clause 21 or 22, wherein the first time period is adjusted such that a flickering of an image displayed on the display device is removed.

[140] Clause 24. The driving method according to any of clauses 20 to 23, wherein the supplying of the reset voltage to the pixel is cut off before supplying the first power voltage to the pixel again.

[141] Clause 25. The driving method according to any of clauses 20 to 24, wherein the pixel operates in one of a first frequency mode operating in response to a first frequency and a second frequency mode operating in response to a second frequency lower than the first frequency, and wherein the reset voltage is transmitted to the pixel through a data line in the second frequency mode.

[142] Clause 26. The driving method according to clause 25 wherein in the second frequency mode, before supplying the data signal to the pixel again, the cutting off of the first power voltage supplied to the pixel and the supplying of the reset voltage to the pixel while the pixel holds the data signal as well as the supplying of the first power voltage to the pixel again can be repeated one or more times.

[143] Clause 27. The driving method according to clause 25 or 26 wherein each of the first frequency mode and the second frequency mode include at least one light emission period and at least one non-light emission period, and wherein in the first frequency mode and the second frequency mode, the number of times the light emission period and the non-light emission period are generated are the same.

[144] The above description has been presented to enable any person skilled in the art to make and use the technical idea of the present disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and the accompanying drawings provide an example of the technical idea of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure. Thus, the scope of the present disclosure is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims. The scope of protection of the present disclosure should be construed based on the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included within the scope of the present disclosure. Below follow a list of numbered items. These items may be combined with any other features described herein in any combination beyond those expressly stated below: 1. A display device, comprising: a display panel comprising a pixel, the pixel comprising a light-emitting device, the light-emitting device being configured to emit light by a driving current flowing from a flrat power voltage to a second power voltage in response to a data signal, the first power voltage and the second power voltage being applied to different portions of the light-emitting device, and the pixel being configured to receive a reset voltage at least once after receiving one data signal and before receiving a next data signal; a data driver circuit configured to supply the data signal to the pixel through a data line; a gate driver circuit configured to supply a gate signal and a light emission control signal; and a timing controller comprising a first frequency driving mode circuit configured to perform a first frequency mode, and a second frequency driving mode circuit configured to perform a second frequency mode, wherein the timing controller configured to store information on a first time period, adjust a timing at which a first light emission control signal is output based on the stored information on the first time period. 2. The display device of item 1, wherein the light-emitting device comprises: an anode electrode; a cathode electrode; and a light-emitting layer between the anode electrode and the cathode electrode, wherein the first power voltage or the reset voltage is transmitted to the anode electrode, and the second power voltage is transmitted to the cathode electrode. 3. The display device of item 1, wherein the light emission control signal comprises the first light emission control signal and a second light emission control signal different from the first light emission control signal, and wherein the first time period is a time difference between the second light emission control signal and the first light emission control signal. 4. The display device of item 1, wherein, when the first time period elapses after the reset voltage is transmitted to the light-emitting device, the first power voltage is transferred to the light-emitting device. 5. The display device of item 1, wherein each of the first frequency mode and the second frequency mode comprises: at least one light emission period, and at least one non-light emission period, and wherein, in the first frequency mode and the second frequency mode, respective numbers of times that the light emission period and the non-light emission period are generated are the same. 6. The display device of item 1, wherein the pixel further comprises: a first transistor configured to supply the driving current to the light-emitting device, in response to the data signal; and a second transistor electrically connected between the first transistor and the light-emitting device. 7. The display device of item 6, wherein the second transistor is controlled by the light emission control signal. 8. The display device of item 7, wherein the pixel further comprises: a third transistor configured to supply the data signal to the first transistor, in response to a first gate signal; a fourth transistor configured to supply the first power voltage to the first transistor, in response to a first light emission control signal; a fifth transistor configured to cause the first transistor to be in a diode connection, in response to a second gate signal; a capacitor configured to hold the data signal supplied to the first transistor; and a sixth transistor configured to transmit an Initialization voltage for Initializing the capacitor and the anode electrode to the capacitor, in response to a second gate signal. 9. The display device according to item 8, wherein a period in which the second transistor is turned on overlaps a period in which the third transistor is turned on. 10. The display device according to item 8, wherein after the first time period elapses after the second transistor is turned on, the fourth transistor is turned on, and the first time period is adjusted according to a rate at which a voltage of the anode electrode of the light-emitting device increases during a refresh period or reset period. 11. The display device according to item 4, wherein the reset voltage is transmitted through the data line. 12. The display device according to item 4, wherein the first time period is adjusted based on a rate at which voltage of the anode electrode of the light-emitting device increases during a refresh period or reset period. 13. The display device according to item12, wherein the rate at which the voltage of the anode electrode increases during the refresh period is greater than the rate at which the voltage of the anode electrode increases during the reset period. 14. The display device according to item 12, wherein when the rate at which the voltage of the anode electrode increases during the refresh period is less than the rate at which the voltage of the anode electrode increases during the reset period, the first time period is set longer. 15. The display device according to item 12, wherein the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is faster than the rate at which the voltage of the anode electrode increases during the reset period is shorter than the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is slower than the rate at which the voltage of the anode electrode increases during the reset period. Below follow a list of numbered aspects. These aspects may be combined with any other features described herein in any combination beyond those expressly stated below: 1. A display device, comprising: a display panel comprising a pixel comprising a light-emitting device, the pixel being driven in a first frequency mode or a second frequency mode; a data driver circuit configured to supply a data signal to the pixel through a data line; and a gate driver circuit configured to supply at least one gate signal and at least one light emission control signal including a first light emission control signal, wherein the light-emitting device is configured to emit light by a driving current flowing from a first power voltage to a second power voltage in response to the data signal, the first power voltage and the second power voltage being applied to different portions of the light-emitting device, wherein the pixel is configured to receive a reset signal at least once between data signals received by the pixel at different times, and wherein the first light emission control signal is supplied based on a first time period. 2. The display device of aspect 1,further comprising: a timing controller comprising a first frequency driving mode circuit configured to perform the first frequency mode, and a second frequency driving mode circuit configured to perform the second frequency mode. 3. The display device of aspect 2, wherein the timing controller is configured to store information on the first time period, and adjust a timing at which the first light emission control signal is output based on the stored information on the first time period. 4. The display device of any of aspects 1 to 3, wherein the at least one light emission control signal further comprises a second light emission control signal different from the first light emission control signal, and wherein the first time period is a time difference between the first light emission control signal and the second light emission control signal. 5. The display device of any of aspects 1 to 4, wherein the pixel further comprises: a first transistor configured to supply the driving current to the light-emitting device, in response to the data signal; and a second transistor electrically connected between the first transistor and the light-emitting device. 6. The display device of aspect 5, wherein the second transistor is controlled by the second light emission control signal. 7. The display device of aspect 5 or aspect 6, wherein the pixel further comprises: a third transistor configured to supply the data signal to the first transistor, in response to a first gate signal; a fourth transistor configured to supply the first power voltage to the first transistor, in response to a first light emission control signal; a fifth transistor configured to cause the first transistor to be in a diode connection, in response to a second gate signal; a capacitor configured to hold the data signal supplied to the first transistor; and a sixth transistor configured to transmit an initialization voltage for initializing the capacitor and the anode electrode to the capacitor, in response to a second gate signal. 8. The display device of aspect 7. wherein a period in which the second transistor is turned on overlaps a period in which the third transistor is turned on. 9. The display device of aspect 7 or aspect 8, wherein after the first time period elapses after the second transistor is turned on, the fourth transistor is turned on, and the first time period is adjusted according to a rate at which a voltage of the anode electrode of the light-emitting device increases during a refresh period or reset period. 10. The display device of any of aspects 7 to 9, wherein the reset signal is supplied to the light-emitting device through the data line, the third transistor, and the second transistor. 11. The display device of any of aspects 7 to 10, wherein an initialization voltage for initializing at least one of the capacitor and an anode electrode of the light-emitting device is supplied to the at least one the capacitor and the anode electrode through the sixth transistor. 12. The display device of any of aspects 7 to 11, wherein the fifth transistor and the sixth transistor are turned off during a refresh period. 13. The display device of any of aspects 1 to 12, wherein the light-emitting device comprises: an anode electrode; a cathode electrode; and a light-emitting layer between the anode electrode and the cathode electrode, wherein the first power voltage or the reset signal is transmitted to the anode electrode, and the second power voltage is transmitted to the cathode electrode. 14. The display device of any of aspects 1 to 13, wherein while the data signal is maintained, the reset signal and the first power voltage are repeatedly supplied to the lightemitting device at least two or more times. 15. The display device of any of aspects 1 to 14, wherein each of the first frequency mode and the second frequency mode comprises: at least one light emission period, and at least one non-light emission period, and wherein, in the first frequency mode and the second frequency mode, respective numbers of times that the light emission period and the non-light emission period are generated are the same. 16. The display device of any of aspects 1 to 15, wherein, when the first time period elapses after the reset signal is transmitted to the light-emitting device, the first power voltage is transferred to the light-emitting device. 17. The display device of aspect 16, wherein the first time period is adjusted based on a rate at which voltage of the anode electrode of the light-emitting device increases during a refresh period or reset period. 18. The display device of aspect 17, wherein the rate at which the voltage of the anode electrode increases during the refresh period is greater than the rate at which the voltage of the anode electrode increases during the reset period. 19. The display device of aspect 17, wherein when the rate at which the voltage of the anode electrode increases during the refresh period is less than the rate at which the voltage of the anode electrode increases during the reset period, the first time period is set longer. 20. The display device of aspect 17, wherein the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is faster than the rate at which the voltage of the anode electrode increases during the reset period is shorter than the first time period set when the rate at which the voltage of the anode electrode increases during the refresh period is slower than the rate at which the voltage of the anode electrode increases during the reset period.

Claims

04 07 251. A display device, comprising:a display panel comprising a pixel comprising a light-emitting device, the pixel being driven in a first frequency mode or a second frequency mode;a gate driver circuit configured to supply at least one gate signal and at least one light emission control signal,wherein the light-emitting device is configured to emit light by a driving current flowing from a first power voltage to a second power voltage in response to a data signal, the first power voltage being higher than the second power voltage,wherein the pixel is configured to receive a reset signal having a voltage level less than a threshold voltage of the light-emitting device after the data signal is received while the display device is driven in the second frequency mode,wherein the at least one light emission control signal has a low voltage level at a portion of a period during which the at least one gate signal has a high voltage level,wherein the at least one light emission control signal comprises first and second light emission control signals different from each other, and while the display device is driven in the second frequency mode, the second light emission control signal is changed from the low voltage level to a high voltage level while the at least one gate signal has the high voltage level.

2. The display device of claim 1, wherein the reset signal is applied to an anode of the light-emitting device to initialize the anode of the light-emitting device.

3. The display device of claim 1 or claim 2, wherein the at least one gate signal is changed from the high voltage level to a low voltage level, and the first light emission control signal is changed from a low voltage level to a high voltage level after a first time from a time at which the second light emission control signal is changed to the high voltage level.

4. The display device of claim 3, wherein a period of the first time is adjusted according to a rate at which a voltage of the anode of the light-emitting device increases during a refresh period or a reset period.04 07 255. The display device of claim 3 or claim 4, wherein when the rate at which the voltage of the anode of the light-emitting device increases is greater than a predetermined rate during the refresh period or the reset period, the period of the first time is adjusted to be less than a predetermined time.

6. The display device of claim 4 or claim 5, wherein when the rate at which the voltage of the anode of the light-emitting device increases is less than a predetermined rate during the refresh period or the reset period, the period of the first time is adjusted to be greater than a predetermined time.

7. The display device of any of claims 4 to 6, wherein when the rate at which the voltage of the anode of the light-emitting device increases during the refresh period is less than the rate at which the voltage of the anode of the light-emitting device increases during the reset period, the first time period is set longer.

8. The display device of claim 1, wherein the pixel further comprises:a first transistor configured to supply the driving current to the light-emitting device, in response to the data signal; anda second transistor electrically connected between the first transistor and the lightemitting device.

9. The display device of claim 8, wherein the second transistor is controlled by the second light emission control signal.

10. The display device of claim 8 or claim 9, wherein the pixel further comprises:a third transistor configured to supply the data signal to the first transistor, in response to a first gate signal;a fourth transistor configured to supply the first power voltage to the first transistor, in response to the first light emission control signal;04 07 25a fifth transistor configured to cause the first transistor to be in a diode connection, in response to a second gate signal;a capacitor configured to hold the data signal supplied to the first transistor; anda sixth transistor configured to transmit an initialization voltage for initializing the capacitor and an anode of the light-emitting device to the capacitor, in response to the second gate signal.

11. The display device of claim 10, wherein a period in which the second transistor is turned on overlaps with a period in which the third transistor is turned on.

12. The display device of claim 10 or claim 11, wherein after a first time from a time at which the second transistor is turned on, the fourth transistor is turned on, and a period of the first time is adjusted according to a rate at which a voltage of the anode of the light-emitting device increases during a refresh period or a reset period.

13. The display device of any of claims 10 to 12, wherein the reset signal is supplied to the anode of the light-emitting device through the data line, the third transistor, and the second transistor.

14. The display device of any of claims 10 to 13, wherein an initialization voltage for initializing at least one of the capacitor and the anode of the light-emitting device is supplied to the at least one of the capacitor and the anode through the sixth transistor.

15. The display device of claim 10 or claim 11, wherein the fifth transistor and the sixth transistor are turned off during a refresh period.

16. The display device of claim 1, wherein the light-emitting device comprises:an anode;a cathode; anda light-emitting layer between the anode and the cathode,04 07 25wherein the first power voltage or the reset signal is transmitted to the anode, and the second power voltage is transmitted to the cathode.

17. The display device of any of claims 1 to 16, wherein while the data signal is maintained, the reset signal and the first power voltage are repeatedly supplied to the lightemitting device at least two or more times.

18. The display device of any of claims 1 to 17, wherein each of the first frequency mode and the second frequency mode comprises:at least one light emission period, andat least one non-light emission period, andwherein, in the first frequency mode and the second frequency mode, respective numbers of times that the light emission period and the non-light emission period are generated are the same.

19. The display device of any of claims 1 to 18, wherein after a first time from a time at which the reset signal is transmitted to the light-emitting device, the first power voltage is transferred to the light-emitting device.

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