Attribute information

Abstract

Disclosed is address translation circuitry to translate a target virtual address to a target physical address. The physical address space selection circuitry selects a physical address space from amon

Description

The present technique relates to the field of data processing. A data processing system may have address translation circuitry to translate a virtual address of memory access request to a physical address corresponding to a location to be accessed in a memory system. At least some examples provide an apparatus comprising: address translation circuitry to translate a target virtual address of a memory access request to a target physical address; physical address space selection circuitry to select a selected physical address space for the memory access request from among a plurality of physical address spaces; physical address space checking circuitry to determine whether to reject the memory access request based on protection information corresponding to the target physical address, the protection information specifying which of the plurality of physical address spaces is allowed to provide access to the target physical address; tag checking circuitry configured to perform, according to a tag checking architecture supporting definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of physical addresses, a tag check comprising: comparing an address tag, derived from a portion of an address operand from which the target virtual address was derived, with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target physical address; generating an indication of whether a match is detected between the guard tag and the address tag; and selectively performing an error handling response in dependence on the indication of whether a match is detected; and table lookup circuitry configured to perform a lookup in a physically addressed table structure to identify a corresponding entry corresponding to the target physical address, and based on that lookup obtain target physical address attribute information comprising both the protection information and at least one of said memory tagging attributes associated with a target region of physical addresses including the target physical address. At least some examples provide a method comprising: translating a target virtual address of a memory access request to a target physical address; selecting a selected physical address space for the memory access request from among a plurality of physical address spaces; determining whether to reject the memory access request based on protection information corresponding to the target physical address, the protection information specifying which of the plurality of physical address spaces is allowed to provide access to the target physical address; performing, according to a tag checking architecture supporting definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of physical addresses, a tag check comprising: comparing an address tag, derived from a portion of an address operand from which the target virtual address was derived, with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target physical address; generating an indication of whether a match is detected between the guard tag and the address tag; and selectively performing an error handling response in dependence on the indication of whether a match is detected; and performing a lookup in a physically addressed table structure to identify a corresponding entry corresponding to the target physical address, and based on that lookup obtaining target physical address attribute information comprising both the protection information and at least one of said memory tagging attributes associated with a target region of physical addresses including the target physical address. At least some examples provide a computer-readable medium to store computer-readable code for fabrication of the apparatus as described above. At least some examples provide a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising: address translation program logic to translate a target virtual address of a memory access request to a target simulated physical address; physical address space selection program logic to select a selected physical address space for the memory access request from among a plurality of physical address spaces; physical address space checking program logic to determine whether to reject the memory access request based on protection information corresponding to the target simulated physical address, the protection information specifying which of the plurality of physical address spaces is allowed to provide access to the target simulated physical address; tag checking program logic configured to perform, according to a tag checking architecture supporting definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of simulated physical addresses, a tag check comprising: comparing an address tag, derived from a portion of an address operand from which the target virtual address was derived, with a guard tag stored in simulated memory in association with a block of one or more simulated memory locations comprising an addressed location identified by the target simulated physical address; generating an indication of whether a match is detected between the guard tag and the address tag; and selectively performing an error handling response in dependence on the indication of whether a match is detected; and table lookup program logic configured to perform a lookup in a physically addressed table structure to identify a corresponding entry corresponding to the target simulated physical address, and based on that lookup obtain target physical address attribute information comprising both the protection information and at least one of said memory tagging attributes associated with a target region of simulated physical addresses including the simulated target physical address. A storage medium may store the computer program mentioned above. The storage medium may be a non-transitory storage medium. Further aspects, features and advantages of the present technique will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings, in which: Figure 1 illustrates an example of a data processing apparatus; Figure 2 illustrates a number of domains in which processing circuitry of the apparatus can operate; Figure 3 illustrates an example of a processing system supporting granule protection lookups; Figure 4 schematically illustrates aliasing of a number of physical address spaces onto a system physical address space identifying locations in the memory system; Figure 5 illustrates an example of partitioning the effective hardware physical address space so that different architectural physical address spaces have access to respective portions of the system physical address space; Figure 6 is a flow diagram illustrating a method of determining the current domain of operation of the processing circuitry; Figure 7 shows examples of page table entry formats for page table entries used for translating virtual addresses to physical addresses; Figure 8 is a flow diagram showing a method of selecting a physical address space to be accessed by a given memory access request; Figure 9 illustrates a number of stages of address translation and granule protection information filtering; Figure 10 illustrates a method of performing a granule protection check based on granule protection information; Figure 11 shows an example of a tag check comprising checking whether an address tag matches a guard tag; Figure 12 illustrates a number of stages of address translation tables and a physically addressed table structure; Figure 13 illustrates use of a set of attribute storage locations to determine attribute information associated with a target physical address; Figure 14 is a flow diagram illustrating a method of handling a memory access request; Figures 15 and 16 illustrate examples of use of a memory tagging attribute to control memory tagging behaviour for a memory access to a region of physical addresses associated with the memory tagging attribute; Figure 17 illustrates an example of a data processing apparatus; and Figure 18 illustrates a simulator example. Data processing systems may support use of virtual memory, where address translation circuitry is provided to translate a virtual address specified by a memory access request into a target physical address associated with a location in a memory system to be accessed. The address translation circuitry may, for example, comprise one of a memory management unit associated with a processor; and a system memory management unit associated with at least one device, the at least one device comprising at least one hardware accelerator and / or at least one input / output device. The mappings between virtual addresses and physical addresses may be defined in one or more page table structures. The page table entries within the page table structures could also define some access permission information which may control whether a given software process executing on the processing circuitry is allowed to access a particular virtual address. In some processing systems, virtual addresses may be mapped by the address translation circuitry onto a single physical address space which is used by the memory system to identify locations in memory to be accessed. In such a system, control over whether a particular software process can access a particular address may be provided solely based on the page table structures used to provide the virtual-to-physical address translation mappings. However, such page table structures may typically be defined by an operating system and / or a hypervisor. If the operating system or the hypervisor is compromised then this may cause a security leak where sensitive information may become accessible to an attacker. Therefore, for some systems where there is a need for certain processes to execute securely in isolation from other processes, the system may support a number of distinct physical address spaces (PASs). The system may prohibit certain physical address spaces from being selected for certain memory access requests, for example taking into account a domain of processing from which the memory access request was issued. By isolating accesses into distinct physical address spaces and restricting which physical address space can be selected for certain memory access requests, this can provide a stronger security guarantee which does not rely on the page table permission information set by an operating system or hypervisor. In a system in which a virtual address of a memory access request can be mapped to a physical address in one of two or more distinct physical address spaces, protection information can be used to limit which physical addresses are accessible within a particular physical address space. This can be useful for ensuring that certain physical memory locations implemented in hardware either on-chip or off-chip can be restricted for access within a particular physical address space or a particular subset of physical address spaces if desired, which can therefore limit access to those physical memory locations so they can only be accessed by certain memory access requests for which the corresponding physical address space is permitted to be selected by the physical address space selection circuitry. For example, this can limit access to certain memory locations so they can only be accessed by domains of processing which are permitted to issue a memory access request in the corresponding physical address space. Hence, an apparatus comprises address translation circuitry, physical address space (PAS) selection circuitry, and physical address space checking circuitry. The address translation circuitry translates a target virtual address (VA) of a memory access request to a target physical address (PA). The PAS selection circuitry selects a selected PAS for the memory access request from among two or more PASs based on properties of the memory access request, such as a domain of processing from which it was issued. The checking circuitry determines whether to reject the memory access request based on protection information corresponding to the target PA. The protection information specifies which of the PASs is allowed to provide access to the target physical address. The protection information corresponding to the target physical address is determined based on a lookup in a physically addressed table structure (which in some examples is referred to as a granule protection table) which associates protection information with physical addresses. For example, the physically addressed table structure may comprise a number of entries each corresponding to a granule (or region) of physical addresses (where a granule is a contiguous portion of the physical address space) of a certain size, and a corresponding entry of the physically addressed table structure is the entry corresponding to a granule of physical addresses comprising the target physical address. The protection information may be directly specified in the corresponding entry of the physically addressed table, although in some examples discussed below the corresponding entry may specify an index and the protection information may be retrieved from an attribute storage location identified by the index specified by the corresponding entry of the physically addressed table. In either case, the protection information is obtained based on the lookup in the physically addressed table structure. By obtaining the protection information using a physically addressed table structure (a table looked up based on physical address, and hence independent of the translation table structures used to provide the mapping from virtual address to physical address), an added layer of security can be provided beyond that controlled by the operating system or hypervisor, to reduce risk that an attacker can cause inappropriate access to certain physical addresses used by sensitive processing workloads. Whilst the separation of memory access requests into different physical address spaces can provide a security guarantee protecting regions of memory from malicious access by agents unable to access certain physical address spaces, this does not necessarily protect the system against memory related errors within a physical address space. Software to be executed by a data processing apparatus may typically be written in a high-level programing language and then compiled into code according to the instruction set architecture supported by the apparatus on which the software is to be executed. For example, the software may originally be written in a higher level language such as Java, C or C++, and then compiled into a natively supported instruction set architecture such as x86 or Arm®. Some higher level programing languages, such as Java, are considered memory-safe languages because they include run time error detection checks for checking for certain errors relating to memory accesses. In contrast, memory-unsafe languages, such as C and C++, do not include such run time error checks. The enduring prevalence of use of memory-unsafe languages means that in compiled code according to a given instruction set architecture, there may be a large number of memory related errors which may be vulnerable to exploitation by an attacker or other malicious party. Such errors may include: • Bounds violations, in which an array index supplied by the code is outside the legitimate bounds of the array; • Use-after-free errors, in which an access to a memory location is made after that memory location has already be deallocated or freed; • Use-after-return, in which a memory access to an address associated with a variable used within a function (such as a value on a stack) is made after already returning from the function; • Use-out-of-scope errors, in which variables are accessed outside of the scope in which they are declared; and • Use-before-initialisation errors, in which a memory address associated with a variable is accessed before the variable has been initialised. These are just some examples of memory-related errors which can result in unpredictable behaviour and potentially provide avenues for attackers to exploit. One approach for protecting against certain memory usage errors of the type discussed above may be to implement tag checks according to a tag checking architecture. In such a tag checking architecture, guard tags are stored in a memory system in association with blocks of one or more memory locations. When a memory access operation requiring tag checking is requested based on a target physical address identifying a particular addressed location in the memory system, tag checking circuitry compares an address tag that is associated with the target address with a guard tag that is stored in the memory system in association with a block of one or more memory locations which includes the addressed location identified by the target physical address. The tag checking circuitry may generate an indication of whether a match is detected between the guard tag and the address tag, and based on the indication selectively perform an error handling response depending on whether a match is detected or not. The error handling response can include controlling whether the memory access is allowed to succeed or whether subsequent operations can succeed, or could merely be reported while allowing memory accesses to continue as normal. A “match” between an address tag and a guard tag does not necessarily require the two tags to have an identical numerical value. In some examples, a “match all” tag may be provided having an encoding which matches against any other tag, even if the two tags have different values. This can be useful to support selective disabling of the tag check for certain regions of memory. In addition, one or both of the address tag or guard tag may be remapped before the comparison, so that “matching” values of the address and guard tags do not need to be equal to each other in order to match. The address tag is associated with a target address by being derived from a portion of an address operand from which the target virtual address was derived. For example, the target virtual address may be determined based on a value stored in a register, and the address tag may be specified in the register from which the target virtual address is determined. For example, a system may support 64 bit addresses, and hence provide 64 bit registers for specifying addresses. However, with current trends in device usage there is not yet (and will not be for many years) a need to provide 264 individual addressable locations. Therefore, often some bits of the memory addresses may effectively be unused and may either always have the same value, or be set as a sign extension of the most significant “real” address bit (so that the unused portion is set to all Os or all 1s). This unused portion can therefore be reused to represent the address tag or a value for deriving the address tag. The address tag can be used to police whether a certain operand is being used in the manner expected to access a location in memory having corresponding guard tags. This can be useful as, for example, a compiler compiling code based on a memory-unsafe language such as C or C++ can, when initialising regions of memory, set the guard tags of blocks of memory which the code is expected to access to particular values, and may associate the corresponding address tag values with the operands (e.g. address pointers) pointing to those blocks. If a memory usage error occurs, and for example the address pointer is used out of scope or extends out of the bounds of the valid range which was initialised, then it may be likely that the guard tag associated with the addressed location may not match the address tag associated with the target address, and then the indication of whether a match is detected can be used to trigger some error handling response. The particular response taken can depend on the particular needs of the software being executed or on the particular micro-architectural implementation of the architecture. Hence, even if the high level language does not have means for performing run time error checks in order to guard against memory access errors, the ISA used for the compiled code may include architectural features for performing such checks. Tag checks can be useful to identify errors which cause an address to be calculated incorrectly, because the incorrect address will point to a location in memory which is unlikely to have a guard tag matching the address tag associated with the request. In some examples, the blocks of memory locations which have corresponding guard tags may each comprise a single memory location. In this case, each individual memory location may have a different guard tag, which can provide fine granularity of setting the guard tags so that a greater range of memory errors can be detected. However, in practise the overhead of setting individual guard tags for each addressed location may be too high, and it can be more efficient to associate each guard tag with a block of multiple memory locations. In this case several adjacent memory locations may share the same guard tag, which can be enough for detecting common forms of memory-related error. The guard tag which is associated with a given block of memory locations can be stored at any other memory location within the memory system. The particular way in which the location of the guard tags in the memory system is selected may vary significantly from implementation to implementation or at run time. In some examples, the location storing the guard tags could be architecturally accessible by the processing circuitry, i.e. the guard tag storage location may be a location mapped to part of the same address space as the addressed location. In this case, the mapping between the addressed location itself and the address of the corresponding tag storage location could be fixed or hardwired, or could be variable, e.g. tracked in a tracking table maintained by the memory access circuitry or in a translation lookaside buffer. Alternatively, other implementations may store the guard tag associated with a given addressed location in a further storage location which is not architecturally accessible to the processing circuitry, e.g. in additional storage provided in the micro-architecture which is not mapped to the address space which can be addressed by instructions executed by the processing circuitry. In this case, the memory access circuitry may determine, based on the address of the addressed location, the particular internal address used to refer to the corresponding tag storage location, and trigger any additional memory access needed to read the tag data from the tag storage location. Regardless of whether or not the tag storage location is architecturally accessible to the processing circuitry, tag values could also be cached within a cache for faster access, either within the same cache used for data values, or in a dedicated tag cache. Hence, in addition to supporting physical address space checks using the physical address space checking circuitry, a system can also comprise tag checking circuitry configured to perform a tag check. The tag checking architecture supports definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of physical addresses. Such attributes can express a wide variety of behaviour types associated with the tag checking architecture, for example behaviours governing whether to (or how to) perform the tag check and / or behaviours for maintaining guard tag values. Various examples of behaviours that can be controlled based on per-region memory tagging attributes are set out further below. The checks performed by the physical address space checking circuitry and the tag checking circuitry are orthogonal. As discussed above, the physical address space checks are generally for preventing malicious access caused by circumvention of page table permissions by a compromised hypervisor or operating system, whereas the memory tagging checks are for preventing or detecting memory related software coding errors which may be present even within a physical address space. Hence, physical address space checking circuitry and the tag checking circuitry would appear to be separate and largely unrelated. However, the inventors of the present technique have realised that despite being orthogonal checks, both the physical address space based checks and the memory tagging checks may have a dependence on (or be related to) attributes defined for respective regions of the physical address space. In particular, both the protection information and at least one memory tagging attribute may be defined for a target region comprising the target physical address. Hence, the inventors have realised that there may be efficiency improvements associated with providing a combined mechanism for determining, for the target physical address of a memory access request, both attributes associated with physical address space checking and attributes associated with the tag checking architecture. Hence, the present technique provides table lookup circuitry configured to perform a lookup in a physically addressed table structure to identify a corresponding entry corresponding to the target physical address, and based on that lookup obtain target physical address attribute information comprising both the protection information and at least one of the memory tagging attributes defined according to the tag checking architecture for a target region of physical addresses including the target physical address. Use of the physically addressed table structure provided for defining the protection information to also represent the memory tagging attributes can be particularly useful compared to other ways of representing the same information. For example, an alternative technique could indicate whether regions of memory are protected by memory tag checks using set of registers defining ranges (with start and end addresses), and in response to a memory access request a lookup can be performed to identify which range the target physical address falls within to determine memory tagging attributes associated with that range. Using the physically addressed table structure shared with the protection information used in PAS checks for determining a memory tagging attribute however avoids the need to perform such additional range register lookups, because a single lookup of the physically addressed table structure (which may be performed anyway for the PAS checks) can also be used to obtain the memory tagging attributes. In addition, use of the physically addressed table for determining the memory tagging attributes allows fine grained specification of memory tagging attributes, which allows distinct non-contiguous regions of memory to be defined throughout the address space with different combinations of memory tagging attributes. As noted above, a wide variety of memory tagging behaviours could be expressed using the at least one memory tagging attribute obtained from the physically addressed table for the region of physical addresses including the target physical address. In general, the tag checking circuitry and / or memory access circuitry for controlling handling of memory accesses may use the at least one memory tagging attribute obtained from the physically addressed table to control handling of at least one type of memory access request. In some examples, guard tags may be configured for the whole of the physical address space. However, in many cases software may not require guard tags to be configured for certain blocks of memory, and therefore untagged regions of memory can be provided which do not have a corresponding guard tag storage location. Defining untagged regions of memory can reduce the overhead of implementing mechanisms for associating regions of memory with guard tags as this overhead can be avoided where not necessary (e.g. for regions storing less sensitive data). When accessing an untagged region of memory, it may be unnecessary to perform a tag check, and the memory access request may be handled independently of any tag checks. Hence, it can be useful when handling a memory access request to be able to determine whether the target physical address lies in an untagged region of physical addresses, as this can enable the tag check steps to be avoided. Hence, in some examples, said at least one of said memory tagging attributes indicates whether memory access requests to the target region of physical addresses are to be subject to the tag check. Depending on the memory tagging attribute obtained from the physically addressed table for the target physical address, the tag checking circuitry can determine whether to perform the tag check. In some examples, the memory tagging attribute obtained from the physically addressed table could comprise an indication of a location in memory storing the guard tag corresponding to the target physical address. For example, whilst in some examples the mapping between physical addresses and their corresponding guard tags may be fixed, in other examples the mapping may be variable to provide an increased level of flexibility (and allow several memory locations to specify the same guard tag, if desired). Hence, in some examples it may be desirable to provide an indication, for tagged physical addresses, of a location in memory storing the guard tag corresponding to the target physical address. For example, the target physical address attribute information may comprise a pointer indicating the address of the corresponding guard tag storage location (which could be the full address of the guard tag storage location, but to reduce storage requirements in some examples may be an offset to be combined with a base address that could be obtained from another location other than the physically addressed table). Providing in the physically addressed table entry corresponding to the target address an indication of the location in memory storing the guard tag associated with the target address can provide a particularly efficient mechanism for controlling access to memory, because a single lookup in the physically addressed table can provide (in addition to information regarding allowed physical address spaces and any indication of whether the target physical address requires a tag check) information for identifying the location of the guard tag required for the tag check. In some examples, said at least one of said memory tagging attributes (obtained based on the physically addressed table also used for PAS checking protection information) indicates whether the target region of physical addresses is for storing guard tags. As discussed above, guard tags may be stored in architecturally accessible regions of memory. Because the guard tags themselves may be directly accessible by memory access requests, it can be desirable to handle memory access requests in a way which enables control over access to guard tags and prevents incorrect modification of guard tags, to preserve integrity of the tag checks. Therefore, it can be beneficial to provide at least one memory tagging attribute which can be used by circuitry when handling a memory access request to determine whether the target physical address is within a region of physical addresses for storing guard tags. Such a memory tagging attribute can be expressed in the same physically addressed table as the one used to obtain protection information for PAS checking, to allow a single lookup process to be used to identify both types of attributes. In some examples, whether a region of memory is for storing tags may be independent from whether the region of memory is protected by memory tagging (with separate attributes specifying both properties). However, in some examples regions of memory storing guard tags may by definition not themselves subject to tag checking. Hence, in some examples, the tag checking circuitry may be configured to permit the memory access request to proceed without being subject to the tag check in response to determining that the target physical address lies in a region of physical addresses for storing guard tags. This can reduce the amount of encoding space needed to express the combination of whether the region is for storing tags and whether the region is protected by memory tagging, as there is no need to provide encodings corresponding to “region stores tags and requires protection by memory tagging”. As discussed above, it can be desirable to handle memory access requests in a way which prevents incorrect modification of guard tags. This prevents software from (maliciously or accidentally) setting guard tags for a sensitive region of memory to “match all” tags, for example, or modifying such guard tags to cause errors in the system. Hence, in some examples memory access checking circuitry is provided which is responsive to a determination that the target physical address lies in a region of physical addresses for storing guard tags to apply a restriction on accesses to the target physical address to prevent incorrect modification of the guard tags. The restriction could take various forms. For example, the memory access checking circuitry may restrict modification of the guard tags such that only memory access requests issued from certain privilege levels or domains may modify the guard tags. In one example which provides a stronger guarantee of security over the guard tags, the restriction comprises controlling access to the target physical address in dependence on whether the memory access request is a predetermined type of tag modifying memory access request. For example, the predetermined type of tag modifying memory access request may be generated by processing circuitry in response to a dedicated class of tag modifying instruction (separate from more general purpose store instructions which may trigger generation of other types of write memory access request). By restricting modification of guard tags to certain types of access request, then incorrect modification of the guard tags can be made more difficult, as it means that erroneous setting of operands for general purpose store instructions (say) cannot accidentally modify guard tags when not intended to do so. In some examples, such a tag modifying memory access request may be triggered by an instruction specifying a different address to the target physical address identifying the guard tag storage location whose tags are to be updated (e.g. the tag modifying instruction could specify operands defining the address of the location whose tag checks would depend on the guard tag at the guard tag storage location, rather than the address of the guard tag storage location itself). Hence, a variety of different behaviours may be expressed by the at least one of the memory tagging attributes obtained based on the physically addressed table. It will be appreciated that although such attributes may initially be derived from the physically addressed table, the attributes (or information derived from the attributes) may be cached in a cache structure and so it is not necessary for the physically addressed table itself to be looked up on every memory access to the target physical address (e.g. a lookup of the physically addressed table may occur in response to detecting a miss in the cache structure). In some examples, the at least one memory tagging attribute obtained from the physically addressed table may express at least one of: whether memory access requests to the target region of physical addresses are to be subject to the tag check; and / or whether the target region of physical addresses is for storing guard tags. One or both of these behaviours could be expressed using the at least one memory tagging attribute. In some examples, the indication of whether a match is detected between the guard tag and address tag may be a signal representing a fault condition. For example, the memory access circuitry may signal a similar memory fault to faults generated if access permissions are violated or unmapped addresses are accessed, or a different kind of fault condition could be indicated. The fault signal could trigger the processing circuitry to execute an exception handling routine for responding to the detected fault. In some examples, the error handling response may be performed in response to a mismatch between the guard tag and address tag. The error handling response may comprise preventing a memory access request from accessing the target physical address when a mismatch is detected between the guard tag and the address tag. This provides stronger security, because preventing memory accesses from being allowed to access incorrectly calculated addresses may prevent the use of memory errors as a method for extracting secret information from a system. However, in other examples, the tag checking circuitry may permit a memory access to the addressed location irrespective of the outcome of the tag check, and the error handling response may comprise generating a report that the guard tag and the address tag did not match. For example, whether the address tag and guard tag matched or mismatched can be recorded in an error log associated with an executed piece of code, which tracks any guard tag errors detected throughout the piece of code. In this case, rather than performing any specific action to impede the operation of the code, the errors could simply be recorded in the error log. The error log could then be made available to a software provider of the code to assist the provider with eliminating errors in subsequent versions of the software. This recognises that often memory errors are not malicious attempts to access secret information but errors in the way code has been written, and so actually preventing memory access when a tag mismatch is detected may be too invasive and protect useful functioning of the code being executed. The memory usage error may be a potential vulnerability which could be recommended to be fixed later to reduce risk of attack, rather than an indication that there is an attack occurring now, and so mere error logging can be considered a more proportionate response than preventing access to the target physical address itself. In some examples errors can be logged even if access to the target physical address is prevented following a tag mismatch. It will also be appreciated that in some cases both types of error handling responses discussed above may be supported, and the system may select between the alternative types of error handling responses. For example, a setting in a control register may determine which error handling response is used at a particular time, or different error handling responses may be used for different types of memory access request, for example. Whilst the address tag is derived from a portion of an address operand from which the target virtual address was derived, note that this address tag is different to a tag portion of the target address which may be used by caches to determine whether the information associated with the addressed location identified by the target address is stored within the cache. Many caching schemes may store a tag portion of the address associated with a cached piece of information alongside that information within the cache, so that on searching the cache for information associated with a given address, part of the address can be compared with the tags stored alongside the cached information in order to determine whether the cached data actually corresponds to the required address. However, in this case the tag portion of the address, which is compared with the tag in the cache would be part of the portion of the address which actually identifies the particular addressed location for which the information is required, i.e., changing the cache tag portion of an address would by definition result in the address pointing to a different addressed location within the memory system. In contrast, with the address tag used for the tag check, the memory access circuitry may select the addressed location for which information is required independent of the address tag. That is, even if the address tag has different values, the addressed location referenced by the target address may still be the same since the selection of the addressed location depends only on other portions of the target address. This gives the freedom for compilers to set the address tags associated with particular addresses to any value to match the corresponding guard tag values which have been allocated to the relevant blocks of data in the memory system. Whilst in some examples the target physical address attribute information may be directly specified in the corresponding entry of the physically addressed table structure, this is not necessarily always the case. The inventors have realised that given the potentially large number of distinct pieces of information which may be represented by the target physical address attribute information, if the physically addressed table structure were to directly specify the attribute information in each entry then the size of the physically addressed table structure could become undesirably large and storage and use of the table may be associated with a large overhead. Additionally, the inventors realised that in cases where attribute information may be updated, then updating the attribute information separately for each entry may incur a large overhead. The inventors have also recognised that despite the potentially large number of options for encodings of the target physical address attribute information, in practice some encodings are used much more frequently than others. In practice, only a subset of the different potential encodings of the attribute information may be desired to be associated with granules of physical addresses at a given time. Therefore, rather than directly specifying the attribute information in each entry of the physically addressed table structure, the inventors have recognised that in some examples a set of encodings of attribute information which are most likely to be used may be stored in a set of attribute storage locations, and entries of the physically addressed table structure may specify an index identifying one of the attribute storage locations to identify a particular encoding of the attribute information. Hence, entries of the physically addressed table structure may incur the much smaller storage cost of indicating an index identifying a corresponding portion of attribute information, rather than directly specifying said portion of attribute information itself. The larger storage cost associated with storing the portion of attribute information can therefore be incurred a reduced number of times, because rather than incurring the cost of storing the same portion of attribute information in several entries of the physically addressed table structure, each of those entries can use a smaller index to refer to the attribute information stored once in the attribute storage location. Further, when it is desired to update the portion of attribute information, then the small number of attribute storage locations may be updated and the indices stored in each entry of the physically addressed table structure may remain the same, meaning that much fewer update operations may need to be performed. Providing at least a portion of the attribute information in a set of attribute storage locations rather than directly in the physically addressed table structure would appear to be unusual, since it leads to an increase in the number of accesses which are required to determine the attribute information. Rather than directly accessing the attribute information in the physically addressed table structure, a further access is carried out (at least on the first time the attribute information is determined from the set of attribute storage locations) to the attribute storage location based on the access to the physically addressed table structure. However, the inventors have realised that surprisingly this increased number of accesses is worth incurring due to the increase in the number of attributes which may be represented by the attribute information for a given size of physically addressed table entry, and the reduced overhead which may be incurred if the attribute information is updated. It is especially surprising that the indirection is worthwhile in a physically addressed table structure, since it is typically the virtually addressed page tables which are relied on to provide a large number of permissions, and physically addressed table structures may be expected to provide a much more limited number of attributes such that storage requirements for the table may be minimal in any case meaning that indirection is not worthwhile. However, the inventors have recognised that representing both the physical address space attributes and the memory tagging attributes in the physically addressed table may increase the size of the physically addressed table structure to such an extent that may justify incurring the extra overhead of indirection even in the case of a physically addressed table structure. The entries of the physically addressed table structure may correspond to a granule of physical addresses, where a given granule is a contiguous block of addresses of some defined size. The particular size of a granule can vary depending on the particular implementation. However, in one example the physically addressed table structure has an encoding capable of assigning independent indices to each 4 KB granule of physical addresses within a physical address space managed using the physically addressed table structure. Use of 4 KB granules is particularly useful as 4 KB is a typical page size for defining translation table attributes in the translation table structures, so this approach allows the physically addressed table structure to define attribute information at a corresponding granularity to the granularity with which an operating system or hypervisor would control access to memory. Although the physically addressed table structure may have an encoding which supports 4 KB granule sizes, it may also support the option of indicating indices for multiple granules in a single entry (e.g. by encoding an index at a higher-level of a multi-level table structure indicating that the indices are the same for a corresponding block of memory of size larger than the minimum granule size, so that it is not necessary to access a further level of the table structure which would have been accessed had separately defined attributes been desired for smaller granules within that block -see below). Hence, while the encoding of the physically addressed table structure may support 4 KB granules, it is not necessary for all encodings of the table to actually define 4 KB granules, and some encodings could define a coarser granularity for setting the indices. Some examples may support granules having a size other than 4 KB. For example, 16 KB and 64 KB granules may be supported. Larger granules may correspond to a page size or may be a multiple of a page size, for example, and the use of larger granules can reduce the number of entries which may be provided in the granule protection table and therefore reduce the storage overhead of the granule protection table. The physically addressed table structure may be provided in memory, although information derived from portions of the physically addressed table structure may be cached locally at the attribute determination circuitry. Although some examples may implement a linear structure for the physically addressed table structure (represented using a contiguous block of address space indexed with a single lookup relative to a base address), this may limit the granularity with which distinct entries can be defined for respective granules of address space, as it may be difficult for a sufficiently large contiguous block of address space to be allocated for a single level of granule protection table covering a large address space. Therefore, in some examples, the physically addressed table structure comprises a multi-level table structure comprising a plurality of levels of physically addressed table structure, the entry corresponding to the target physical address being stored at a memory system location associated with a physical address derived from a portion of the target physical address and a table pointer obtained from a higher-level entry corresponding to the target physical address in a higher-level physically addressed table structure. This enables fine-grained control of distinct attributes for smaller granules of physical addresses, without imposing the limitation that the whole table has to be located in a contiguous block of memory of size corresponding to the size of the whole physical address space to be protected using the table as would be the case for a single linear structure. Some systems supporting a plurality of physical address spaces may support operation in a number of domains. Domains provide one mechanism by which access to certain physical address spaces may be controlled. For example, the physical address space selection circuitry may select a physical address space for the memory access request depending on the domain from which the memory access request was issued. In some examples, the domains may include at least a less secure domain and a more secure domain (corresponding to a less secure physical address space and more secure physical address space respectively), and the more secure physical address space may be prohibited from being selected for memory access requests associated with the less secure domain. By prohibiting the less secure domain from selecting the more secure physical address space for memory access requests, then the less secure domain can be prevented from accessing data stored in locations indicated by the attribute information as accessible only from the secure physical address space. Hence, the secure domain can have access to regions of memory which are entirely isolated from the less secure domain, which can be useful for improving security. The more secure domain may be permitted to issue memory access requests in either the more secure or less secure physical address spaces, thereby having access to a greater range of physical addresses than the less secure domain. In some examples, further domains of processing may also be supported. For example, an additional more secure domain associated with an additional more secure PAS may be supported. The additional more secure PAS may be prohibited from being selected for memory access requests associated with the less secure domain. The additional more secure PAS may also be prohibited from being selected for memory access requests associated with the more secure domain, and the more secure PAS may be prohibited from being selected for memory access requests associated with the additional more secure domain. By providing two more secure domains each with a corresponding more secure PAS which cannot be accessed from the other more secure domain (while memory access requests associated with the less secure domain cannot access any of those more secure PASs), this allows software provided by two mutually untrusted software developers to coexist on the same hardware without having to trust each other, even when both providers require guarantees of isolation from less secure software components. For example, the more secure domain and additional more secure domain may corresponding to the Secure and Realm domains mentioned below (or vice versa). In some examples, there may be a most secure domain which is allowed to access any physical address space, and which has access to a physical address space which cannot be accessed by any other domain. For example, the domains may include a root domain for managing switching between other domains of the plurality of domains. The root domain is associated with a root PAS which is prohibited from being selected for memory access requests associated with a domain other than the root domain. The apparatus may have a point of physical aliasing (PoPA) memory system component configured to de-alias a plurality of aliasing physical addresses from different PASs which correspond to a same memory system location, to map any of the plurality of aliasing physical addresses to a de-aliased physical address to be provided to at least one downstream memory system component; and at least one pre-PoPA memory system component provided upstream of the PoPA memory system component, where the at least one pre-PoPA memory system component is configured to treat the aliasing physical addresses from different PASs as if the aliasing physical addresses correspond to different memory system locations. Hence, for at least some components of the memory system, memory access requests whose virtual addresses are translated into physical addresses in different physical address spaces are treated as if they were accessing completely separate addresses in memory, even if the physical addresses in the respective physical address spaces actually correspond to the same location in memory. For example, the at least one pre-PoPA memory system component could include a cache or translation lookaside buffer which may cache data, program code or address translation information for the aliasing physical addresses in separate entries, so that if the same memory system resource is requested to be accessed from different physical address spaces, then the accesses will cause separate cache or TLB entries to be allocated. Also, the pre-PoPA memory system component could include coherency control circuitry, such as a coherent interconnect, snoop filter, or other mechanism for maintaining coherency between cached information at respective master devices. The coherency control circuitry could assign separate coherency states to the respective aliasing physical addresses in different physical address spaces. Hence, the aliasing physical addresses are treated as separate addresses for the purpose of maintaining coherency even if they do actually correspond to the same underlying memory system resource. Although on the face of it, tracking coherency separately for the aliasing physical addresses could appear to cause a problem of loss of coherency, in practice this is not a problem because if processes operating in different domains are really intended to share access to a particular memory system resource then they can use a physical address space accessible to the different domains to provide access to that resource. Another example of a pre-PoPA memory system component may be a memory protection engine which is provided for protecting data saved to off-chip memory against loss of confidentiality and / or tampering. Such a memory protection engine could, for example, separately encrypt data associated with a particular memory system resource with different encryption keys depending on which physical address space the resource is accessed from, effectively treating the aliasing physical addresses as if they were corresponding to different memory system resources (e.g. an encryption scheme which makes the encryption dependent on the address may be used, and the physical address space identifier may be considered to be part of the address for this purpose). Regardless of the form of the pre-PoPA memory system component, it can be useful for such a PoPA memory system component to treat the aliasing physical addresses as if they correspond to different memory system resources, as this provides hardware-enforced isolation between the accesses issued to different physical address spaces so that information associated with one domain cannot be leaked to another domain by features such as cache timing side channels or side channels involving changes of coherency triggered by the coherency control circuitry. It may be possible, in some implementations, for the aliasing physical addresses in the different physical address spaces to be represented using different numeric physical address values for the respective different physical address spaces. This approach may require a mapping table to determine at the PoPA which of the different physical address values correspond to the same memory system resource. However, this overhead of maintaining the mapping table may be considered unnecessary, and so in some implementations it may be simpler if the aliasing physical addresses comprise physical addresses which are represented using the same numeric physical address value in each of the different physical address spaces. If this approach is taken then, at the point of physical aliasing, it can be sufficient simply to discard the physical address space identifier which identifies which physical address space is accessed using a memory access, and then to provide the remaining physical address bits downstream as a de-aliased physical address. Hence, in addition to the pre-PoPA memory system component, the memory system may also include a PoPA memory system component configured to de-alias the plurality of aliasing physical addresses to obtain a de-aliased physical address to be provided to at least one downstream memory system component. The PoPA memory system component could be a device accessing a mapping table to find the dealiased address corresponding to the aliasing address in a particular address space, as described above. However, the PoPA component could also simply be a location within the memory system where the physical address tag associated with a given memory access is discarded so that the physical address provided downstream uniquely identifies a corresponding memory system resource regardless of which physical address space this was provided from. Alternatively, in some cases the PoPA memory system component may still provide the physical address space tag to the at least one downstream memory system component (e.g. for the purpose of enabling completer-side filtering as discussed further below), but the PoPA may mark the point within the memory system beyond which downstream memory system components no longer treat the aliasing physical addresses as different memory system resources, but consider each of the aliasing physical addresses to map the same memory system resource. For example, if a memory controller or a hardware memory storage device downstream of the PoPA receives the physical address tag and a physical address for a given memory access request, then if that physical address corresponds to the same physical address as a previously seen transaction, then any hazard checking or performance improvements performed for respective transactions accessing the same physical address (such as merging accesses to the same address) may be applied even if the respective transactions specified different physical address space tags. In contrast, for a memory system component upstream of the PoPA, such hazard checking or performance improving steps taken for transactions accessing the same physical address may not be invoked if these transactions specify the same physical address in different physical address spaces. Particular examples will now be described with reference to the Figures. Figure 1 schematically illustrates an example of a data processing system 2 having at least one requester device 4 and at least one completer device 6. An interconnect 8 provides communication between the requester devices 4 and completer devices 6. A requester device is capable of issuing memory access requests requesting a memory access to a particular addressable memory system location. A completer device 6 is a device that has responsibility for servicing memory access requests directed to it. Although not shown in Figure 1, some devices may be capable of acting both as a requester device and as a completer device. The requester devices 4 may for example include processing elements such as a central processing unit (CPU) or graphics processing unit (GPU) or other master devices such as bus master devices, network interface controllers, display controllers, DMA controllers, etc. The completer devices may include memory controllers responsible for controlling access to corresponding memory storage units, peripheral controllers for controlling access to a peripheral device, etc. Figure 1 shows an example configuration of one of the requester devices 4 in more detail but it will be appreciated that the other requester devices 4 could have a similar configuration. Alternatively, the other requester devices may have a different configuration to the requester device 4 shown on the left of Figure 1 (e.g., as shown in Figure 12 discussed in more detail below, in some cases another requester device 4 may be a system memory management unit (SMMU) which has address translation circuitry 16 and a PAS filter 20 but does not have the processing circuitry 10 shown in Figure 1). The requester device 4 shown in Figure 1 has processing circuitry 10 for performing data processing in response to instructions, with reference to data stored in registers 12. The registers 12 may include general purpose registers for storing operands and results of processed instructions, as well as control registers for storing control data for configuring how processing is performed by the processing circuitry. For example the control data may include a current domain indication 14 used to select which domain of operation is the current domain, and a current exception level indication 15 indicating which exception level is the current exception level in which the processing circuitry 10 is operating. The processing circuitry 10 may be capable of issuing memory access requests specifying a virtual address (VA) identifying the addressable location to be accessed and a domain identifier (Domain ID or ‘security state’) identifying the current domain. Address translation circuitry 16 (e.g. a memory management unit (MMU)) translates the virtual address into a physical address (PA) through one of more stages of address translation based on page table data defined in page table structures stored in the memory system. A translation lookaside buffer (TLB) 18 acts as a lookup cache for caching some of that page table information for faster access than if the page table information had to be fetched from memory each time an address translation is required. In this example, as well as generating the physical address, the address translation circuitry 16 also selects one of a number of physical address spaces associated with the physical address and outputs a physical address space (PAS) identifier identifying the selected physical address space. Selection of the PAS will be discussed in more detail below. A PAS filter 20 (physical address space checking circuitry) acts as PAS checking circuitry for checking, based on the translated physical address and the PAS identifier, whether that physical address is allowed to be accessed within the specified physical address space identified by the PAS identifier. This lookup is based on granule protection information (which is an example of the protection information discussed above) which is accessed using a granule protection table structure (which is a physically addressed table structure) stored within the memory system. As discussed above, the granule protection information may be directly specified in an entry of the granule protection table corresponding to the target PA, or alternatively the corresponding entry may specify an index, and the granule protection information may be retrieved from an attribute storage location identified by that index (not shown, although this may be a location within the registers 12 or within memory, for example at a completer device 6). The granule protection information, once retrieved using the physically addressed granule protection table, may be cached within a granule protection information cache 22, similar to caching of page table data in the TLB 18. While the granule protection information cache 22 is shown as a separate structure from the TLB 18 in the example of Figure 1, in other examples these types of lookup caches could be combined into a single lookup cache structure so that a single lookup of an entry of the combined structure provides both the page table information and the granule protection information. The granule protection information defines information restricting the physical address spaces from which a given physical address can be accessed, and based on this lookup the PAS filter 20 determines whether to allow the memory access request to proceed to be issued to one or more caches 24 and / or the interconnect 8. If the specified PAS for the memory access request is not allowed to access the specified physical address then the PAS filter 20 blocks the transaction and may signal a fault. While Figure 1 shows an example with a system having multiple requester devices 4, the features shown for the one requester device on the left hand side of Figure 1 could also be included in a system where there is only one requester device, such as a single-core processor. While Figure 1 shows an example where selection of the PAS for a given request is performed by the address translation circuitry 16, in other examples information for determining which PAS to select can be output by the address translation circuitry 16 to the PAS filter 20 along with the PA, and the PAS filter 20 may select the PAS and check whether the PA is allowed to be accessed within the selected PAS. Hence, PAS selection circuitry could be provided by either the address translation circuitry 16, or the PAS filter 20, or both working together. The provision of the PAS filter 20 helps to support a system which can operate in a number of domains of operation each associated with its own isolated physical address space where, for at least part of the memory system (e.g. for some caches or coherency enforcing mechanisms such as a snoop filter), the separate physical address spaces are treated as if they refer to completely separate sets of addresses identifying separate memory system locations, even if addresses within those address spaces actually refer to the same physical location in the memory system. This can be useful for security purposes. The system of Figure 1 also comprises tag checking circuitry 27 and a tag cache 19, the function of which will be described below with reference to Figure 11. Table lookup circuity 21 is provided which carries out a combined lookup to determine the granule protection information for the PAS filter 20 and one or more memory tagging attributes for use by the tag checking circuitry 27 (and / or other parts of the requester device 4, such as the memory access circuitry which handles load / store operations) in implementing memory access control behaviour associated with a tag checking architecture discussed above. The table lookup circuitry 21 is discussed further below. Figure 2 shows an example of different operating states and domains in which the processing circuitry 10 can operate, and an example of types of software which could be executed in the different exception levels and domains (of course, it will be appreciated that the particular software installed on a system is chosen by the parties managing that system and so is not an essential feature of the hardware architecture). The processing circuitry 10 is operable at a number of different exception levels 80, in this example four exception levels labelled EL0, EL1, EL2 and EL3, where in this example EL3 refers to the exception level with the greatest level of privilege while EL0 refers to the exception level with the least privilege. It will be appreciated that other architectures could choose the opposite numbering so that the exception level with the highest number could be considered to have the lowest privilege. In this example the least privileged exception level ELO is for application-level code, the next most privileged exception level EL1 is used for operating system-level code, the next most privileged exception level EL2 is used for hypervisor-level code which manages switching between a number of virtualised operating systems, while the most privileged exception level EL3 is used for monitor code which manages switches between respective domains and allocation of physical addresses to physical address spaces, as described later. When an exception occurs while processing software in a particular exception level, for some types of exceptions, the exception is taken to a higher (more privileged) exception level, with the particular exception level in which the exception is to be taken being selected based on attributes of the particular exception which occurred. However, it may be possible for other types of exceptions to be taken at the same exception level as the exception level associated with the code being processed at the time an exception was taken, in some situations. When an exception is taken, information characterising the state of the processor at the time the exception was taken may be saved, including for example the current exception level at the time the exception was taken, and so once an exception handler has been processed to deal with the exception, processing may then return to the previous processing and the saved information can be used to identify the exception level to which processing should return. In addition to the different exception levels, the processing circuitry also supports a number of domains of operation (also known as “security states”), the domains including a root domain 82, a secure (S) domain 84, a less secure domain 86 and a realm domain 88. For ease of reference, the less secure domain will be described below as the “non-secure” (NS) domain, but it will be appreciated that this is not intended to imply any particular level of (or lack of) security. Instead, “non-secure” merely indicates that the non-secure domain is intended for code which is less secure than code operating in the secure domain. The root domain 82 is selected when the processing circuitry 10 is in the highest exception level EL3. When the processing circuitry is in one of the other exception levels ELO to EL2, the current domain is selected based on the current domain indicator 14, which indicates which of the other domains 84, 86, 88 is active. For each of the other domains 84, 86, 88 the processing circuitry could be in any of the exception levels ELO, EL1 or EL2. At boot time, a number of pieces of boot code (e.g. BL1, BL2, OEM Boot) may be executed, e.g. within the more privileged exception levels EL3 or EL2. The boot code BL1, BL2 may be associated with the root domain for example and the OEM boot code may operate in the Secure domain. However, once the system is booted, at runtime the processing circuitry 10 may be considered to operate in one of the domains 82, 84, 86 and 88 at a time. Each of the domains 82 to 88 is associated with its own associated physical address space (PAS) which enables isolation of data from the different domains within at least part of the memory system. This will be described in more detail below. The non-secure domain 86 can be used for regular application-level processing, and for the operating system and hypervisor activity for managing such applications. Hence, within the non-secure domain 86, there may be application code 30 operating at ELO, operating system (OS) code 32 operating at EL1 and hypervisor code 34 operating at EL2. The secure domain 84 enables certain system-on-chip security, media or system services to be isolated into a separate physical address space from the physical address space used for non-secure processing. The secure and non-secure domains are not equal, in the sense that the non-secure domain code cannot access resources associated with the secure domain 84, while the secure domain can access both secure and non-secure resources (at least for regions of memory for which the predetermined less-secure memory property described further below is not defined). An example of a system supporting such partitioning of secure and non-secure domains 84, 86 is a system based on the TrustZone® architecture provided by Arm® Limited. The secure domain can run trusted applications 36 at ELO, a trusted operating system 38 at EL1, as well as optionally a secure partition manager 40 at EL2 which may, if secure partitioning is supported, use stage 2 page tables to support isolation between different trusted operating systems 38 executing in the secure domain 84 in a similar way to the way that the hypervisor 34 may manage isolation between virtual machines or guest operating systems 32 executing in the non-secure domain 86. Extending the system to support a secure domain 84 has become popular in recent years because it enables a single hardware processor to support isolated secure processing, avoiding the need for the processing to be performed on a separate hardware processor. However, with the increasing popularity of use of the secure domain, many practical systems having such a secure domain now support, within the secure domain, a relatively sophisticated mixed environment of services which are provided by a wide range of different software providers. For example the code operating in the secure domain 84 may include different pieces of software provided by (among others): the silicon provider who manufactured the integrated circuit, an original equipment manufacturer (OEM) who assembles the integrated circuit provided by the silicon provider into an electronic device such as a mobile telephone, an operating system vendor (OSV) who provides the operating system 32 for the device; and / or a cloud platform provider who manages a cloud server supporting services for a number of different clients through the cloud. However, increasingly there is a desire for parties providing user-level code (which might normally be expected to execute as applications 30 within the non-secure domain 86) to be provided with secure computing environments which can be trusted not to leak information to other parties operating code on the same physical platform. It may be desirable for such secure computing environments to be dynamically allocatable at runtime, and to be certified and attestable so that the user is able to verify whether sufficient security guarantee is provided on the physical platform, before trusting the device to process potentially sensitive code or data. A user of such software may not wish to trust the party providing a rich operating system 32 or hypervisor 34 which might normally operate in the non-secure domain 86 (or even if those providers themselves can be trusted, the user may wish to protect themselves against the operating system 32 or hypervisor 34 being compromised by an attacker). Also, while the secure domain 84 could be used for such user-provided applications needing secure processing, in practice this causes problems both for the user providing the code requiring the secure computing environment and for the providers of existing code operating within the secure domain 84. For the providers of existing code operating within the secure domain 84, the addition of arbitrary user-provided code within the secure domain would increase the attack surface for potential attacks against their code, which may be undesirable, and so allowing users to add code into the secure domain 84 may be strongly discouraged. On the other hand, the user providing the code requiring the secure computing environment may not be willing to trust all of the providers of the different pieces of code operating in the secure domain 84 to have access to its data or code, if certification or attestation of the code operating in a particular domain is needed as a prerequisite for the user-provided code to perform its processing, it may be difficult to audit and certify all of the distinct pieces of code operating in the secure domain 84 provided by the different software providers, which may limit the opportunities for third parties to provide more secure services. Therefore, as shown in Figure 2, an additional more secure domain 88, called the realm domain, is provided which can be used by such user-introduced code to provide a secure computing environment orthogonal to any secure computing environment associated with components operating in the secure domain 24. In the realm domain, the software executed can include a number of realms, where each realm can be isolated from other realms by a realm management module (RMM) 46 operating at exception level EL2. The RMM 46 may control isolation between the respective realms 42, 44 executing the realm domain 88, for example by defining access permissions and address mappings in page table structures similar to the way in which hypervisor 34 manages isolation between different components operating in the nonsecure domain 86. In this example, the realms include an application-level realm 42 which executes at ELO and an encapsulated application / operating system realm 44 which executes across exception levels ELO and EL1. It will be appreciated that it is not essential to support both ELO and EL0 / EL1 types of realms, and that multiple realms of the same type could be established by the RMM 46. The realm domain 88 has its own physical address space allocated to it, similar to the secure domain 84, but the realm domain is orthogonal to the secure domain 84 in the sense that while the realm and secure domains 88, 84 can each access the non-secure PAS associated with the non-secure domain 86, the realm and secure domains 88, 84 cannot access each other’s physical address spaces. This means that code executing in the realm domain 88 and secure domains 84 have no dependencies on each other. Code in the realm domain only needs to trust the hardware, the RMM 46 and the code operating in the root domain 82 which manages switching between domains, which means attestation and certification becomes more feasible. Attestation enables a given piece of software to request verification that code installed on the device matches certain anticipated properties. This could be implemented by checking whether a hash of the program code installed on the device matches an expected value that is signed by a trusted party using a cryptographic protocol. The RMM 46 and monitor code 29 could for example be attested by checking whether a hash of this software matches an expected value signed by a trusted party, such as the silicon provider who manufactured the integrated circuit comprising the processing system 2 or an architecture provider who designed the processor architecture which supports the domain-based memory access control. This can allow user-provided code 42, 44 to verify whether the integrity of the domain-based architecture can be trusted prior to executing any secure or sensitive functions. Hence, it can be seen that the code associated with realms 42, 44, which would previously have executed in the non-secure domain 86 as shown by the dotted lines showing the gap in the non-secure domain where these processes would previously have executed, can now be moved to the realm domain where they may have stronger security guarantees because their data and code is not accessible by other code operating in a non-secure domain 86. However, due to the fact that the realm domain 88 and secure domain 84 are orthogonal and so cannot see each other’s physical address spaces, this means that the providers of code in the realm domain do not need to trust the providers of code in the secure domain and vice versa. The code in the realm domain can simply trust the trusted firmware providing the monitor code 29 for the root domain 82 and the RMM 46, which may be provided by the silicon provider or the provider of the instruction set architecture supported by the processor, who may already inherently need to be trusted when the code is executing on their device, so that no further trust relationships with other operating system vendors, OEMs or cloud hosts are needed for the user to be able to be provided with a secure computing environment. This can be useful for a range of applications and use cases, including for example mobile wallet and payment applications, gaming anti-cheating and piracy mechanisms, operating system platform security enhancements, secure virtual machine hosting, confidential computing, networking, or gateway processing for Internet of Things devices. It will be appreciated that users may find many other applications where the realm support is useful. To support the security guarantees provided to a realm, the processing system may support an attestation report function, where at boot time or at run time measurements are made of firmware images and configuration, e.g. monitor code images and configuration or RMM code images and configuration and at runtime realm contents and configuration are measured, so that the realm owner can trace the relevant attestation report back to known implementations and certifications to make a trust decision on whether to operate on that system. As shown in Figure 2, a separate root domain 82 is provided which manages domain switching, and that root domain has its own isolated root physical address space. The creation of the root domain and the isolation of its resources from the secure domain allows for a more robust implementation even for systems which only have the non-secure and secure domains 86, 84 but do not have the realm domain 88, but can also be used for implementations which do support the realm domain 88. The root domain 82 can be implemented using monitor software 29 provided by (or certified by) the silicon provider or the architecture designer, and can be used to provide secure boot functionality, trusted boot measurements, system-on-chip configuration, debug control and management of firmware updates of firmware components provided by other parties such as the OEM. The root domain code can be developed, certified and deployed by the silicon provider or architecture designer without dependencies on the final device. In contrast the secure domain 84 can be managed by the OEM for implementing certain platform and security services. The management of the non-secure domain 86 may be controlled by an operating system 32 to provide operating system services, while the realm domain 88 allows the development of new forms of trusted execution environments which can be dedicated to user or third party applications while being mutually isolated from existing secure software environments in the secure domain 84. Figure 3 schematically illustrates another example of a processing system 2 for supporting these techniques. Elements which are the same as in Figure 3 are illustrated with the same reference numeral. Figure 3 shows more detail in the address translation circuitry 16, which comprises stage 1 and stage 2 memory management units 50, 52. The stage 1 MMU 50 may be responsible for translating virtual addresses to either physical addresses (when the translation is triggered by EL2 or EL3 code) or to intermediate addresses (when the translation is triggered by EL0 or EL1 code in an operating state where a further stage 2 translation by the stage 2 MMU 52 is required). The stage 2 MMU may translate intermediate addresses into physical addresses. The stage 1 MMU may be based on page tables controlled by an operating system for translations initiated from EL0 or EL1, page tables controlled by a hypervisor for translations from EL2, or page tables controlled by monitor code 29 for translations from EL3. On the other hand, the stage 2 MMU 52 may be based on page table structures defined by a hypervisor 34, RMM 46 or secure partition manager 14 depending on which domain is being used. Separating the translations into two stages in this way allows operating systems to manage address translation for themselves and applications under the assumption that they are the only operating system running on the system, while the RMM 46, hypervisor 34 or SPM40 may manage isolation between different operating systems running in the same domain. As shown in Figure 3, the address translation process using the address translation circuitry 16 may return security attributes 54 which, in combination with the current exception level 15 and the current domain 14 (or security state), allow section of a particular physical address space (identified by a PAS identifier or “PAS TAG”) to be accessed in response to a given memory access request. The physical address and PAS identifier may be looked up in a granule protection table 56 which provides an index to identify an attribute storage location providing the granule protection information described earlier. In this example the PAS filter 20 is shown as a granular memory protection unit (GMPU) which verifies whether the selected PAS is allowed to access the requested physical address and if so allows the transaction to be passed to any caches 24 or interconnect 8 which are part of the system fabric of the memory system. The GMPU 20 allows assigning memory to separate address spaces while providing a strong, hardware-based, isolation guarantee and providing spatial and temporal flexibility in the assignment methods of physical memory into these address spaces, as well as efficient sharing schemes. As described earlier, the execution units in the system are logically partitioned to virtual execution states (domains or “Worlds”) where there is one execution state (Root world) located at the highest exception level (EL3), referred to as the “Root World” that manages physical memory assignment to these worlds. A single System physical address space is virtualized into multiple “Logical” or “Architectural” Physical Address Spaces (PAS) where each such PAS is an orthogonal address space with independent coherency attributes. A System Physical Address is mapped to a single “Logical” Physical Address Space by extending it with a PAS tag. A given World is allowed access to a subset of Logical Physical Address Spaces. This is enforced by a hardware filter 20 that can be attached to the output of the Memory Management Unit 16. A World defines the security attributes (the PAS tag) of the access using fields in the Translation Table Descriptor of the virtually addressed page tables used for address translation. The hardware filter 20 has access to a table (Granule Protection Table 56, or GPT) which can be used to obtain granule protection information (GPI) indicating the PAS TAG it is associated with and (optionally) other Granule Protection attributes. The hardware filter 20 checks the World ID and the Security Attributes against the Granule’s GPI and decides if access can be granted or not, thus forming a Granular Memory Protection Unit (GMPU). The GPT 56 can reside in on-chip SRAM or in off-chip DRAM, for example. If stored off-chip, the GPT 56 may be integrity-protected by an on-chip memory protection engine that may use encryption, integrity and freshness mechanisms to maintain security of the GPT 56. Locating the GMPU 20 on the requester-side of the system (e.g. on the MMU output) rather than on the completer-side allows allocating access permissions in page granularity while permitting the interconnect 8 to continue hashing / striping the page across multiple DRAM ports. Transactions remain tagged with the PAS TAG as they propagate throughout the system fabric 24, 8 until reaching a location defined as the Point of Physical Aliasing 60. This allows to locate the filter on the Master-side without diminishing the security guarantees comparing to Slave-side filtering. As the transaction propagates throughout the system, the PAS TAG can be used as an in-depth security mechanism for address isolation: e.g. caches can add the PAS TAG to the address tag in the cache, preventing accesses made to the same PA using the wrong PAS TAG from hitting in the cache and therefore improving side-channel resistance. The PAS TAG can also be used as context selector for a Protection Engine attached to the memory controller that encrypts data before it is written to external DRAM. The Point of Physical Aliasing (PoPA) is a location in the system where the PAS TAG is stripped and the address changes back from a Logical Physical Address to a System Physical Address. The PoPA can be located below the caches, at the completer-side of the system where access to the physical DRAM is made (using encryption context resolved through the PAS TAG). Alternatively, it may be located above the caches to simplify system implementation at the cost of reduced security. At any point in time, a world can request to transition a page from one PAS to another. The request is made to the monitor code 29 at EL3 which inspects the current state of the GPI. EL3 may only allow a specific set of transitions to occur (e.g. from Non-secure PAS to Secure PAS but not from Realm PAS to Secure PAS - another supported transition may be between Non-Secure PAS with the predetermined less secure memory property and Non-Secure PAS with the second less secure memory property). To provide a clean transition, a new instruction is supported by the System - “Data Clean and Invalidate to the Point of Physical Aliasing” which EL3 can submit before transitioning a page to the new PAS - this guarantees that any residual state associated with the previous PAS is flushed from any caches upstream of (closer to the requester-side than) the PoPA 60. Another property that can be achieved by attaching the GMPLI 20 to the master side is efficient sharing of memory between worlds. It may be desirable to grant a subset of N worlds with shared access to a physical granule while preventing other worlds from accessing it. This can be achieved by adding a “restrictive shared” semantic to the Granule Protection Information, while forcing it to use a specific PAS TAG. As an example, the GPI can indicate that a physical Granule is can accessed only by “Realm World” 88 and “Secure World” 84 while being tagged with the PAS TAG of the Secure PAS 84. An example of the above property is making fast changes in the visibility properties of a specific physical granule. Consider a case where each world is assigned with a private PAS that is only accessible to that World. For specific granules, the World can request to make them visible to the Non-Secure world at any point in time by changing their GPI from “exclusive” to “restrictive shared with Non-Secure world”, and without changing the PAS association. This way, the visibility of that granule can be increased without requiring costly cache-maintenance or data copy operations. Figure 4 illustrates the concept of aliasing of the respective physical address spaces onto physical memory provided in hardware. As described earlier, each of the domains 82, 84, 86, 88 has its own respective physical address space 61. At the point when a physical address is generated by address translation circuitry 16, the physical address has a value within a certain numeric range 62 supported by the system, which is the same regardless of which physical address space is selected. However, in addition to the generation of the physical address, the address translation circuitry 16 may also select a particular physical address space (PAS) based on the current domain 14 and / or information in the page table entry used to derive the physical address. Alternatively, instead of the address translation circuitry 16 performing the selection of the PAS, the address translation circuitry (e.g. MMU) could output the physical address and the information derived from the page table entry (PTE) which is used for selection of the PAS, and then this information could be used by the PAS filter or GMPLI 20 to select the PAS. The selection of PAS for a given memory access request may be restricted depending on the current domain in which the processing circuitry 10 is operating when issuing the memory access request, according to rules defined in the following table: Current Domain Non-Secure PAS Secure PAS Realm PAS Root PAS Non-secure Accessible Inaccessible Inaccessible Inaccessible Secure Accessible* Accessible Inaccessible Inaccessible Realm Accessible* Inaccessible Accessible Inaccessible Root Accessible Accessible Accessible Accessible For those domains for which there are multiple physical address spaces available for selection, the information from the accessed page table entry used to provide the physical address is used to select between the available PAS options. For the entries in the table marked * regarding access to the Non-Secure PAS, whether the Secure and Realm domains are able to access the Non-Secure PAS also depends on whether the predetermined less-secure memory property defined earlier has been specified in the granule protection information (GPI) for the PA being accessed (at least in some modes of operation - it is possible to provide a mode where use of this property is disabled for backwards compatibility reasons). Hence, at the point when the PAS filter 20 outputs a memory access request to the system fabric 24, 8 (assuming it passed any filtering checks), the memory access request is associated with a physical address (PA) and a selected physical address space (PAS). From the point of view of memory system components (such as caches, interconnects, snoop filters etc.) which operate before the point of physical aliasing (PoPA) 60, the respective physical address spaces 61 are viewed as entirely separate ranges of addresses which correspond to different system locations within memory. This means that, from the point of view of the pre-PoPA memory system components, the range of addresses identified by the memory access request is actually four times the size of the range 62 which could be output in the address translation, as effectively the PAS identifier is treated as additional address bits alongside the physical address itself, so that depending on which PAS is selected the same physical address PAx can be mapped to a number of aliasing physical addresses 63 in the distinct physical address spaces 61. These aliasing physical addresses 63, all actually correspond to the same memory system location implemented in physical hardware, but the pre-PoPA memory system components treat aliasing addresses 63 as separate addresses. Hence, if there are any pre-PoPA caches or snoop filters allocating entries for such addresses, the aliasing addresses 63 would be mapped into different entries with separate cache hit / miss decisions and separate coherency management. This reduces likelihood or effectiveness of attackers using cache or coherency side channels as a mechanism to probe the operation of other domains. The system may include more than one PoPA 60 (e.g. memory access requests specifying different physical addresses may be routed via different paths through the memory system and may be handled by different PoPAs 60). At each PoPA 60, the aliasing physical addresses are collapsed into a single de-aliased address 65 in the system physical address space 64. The de-aliased address 65 is provided downstream to any post-PoPA components, so that the system physical address space 64 which actually identifies memory system locations is once more of the same size as the range of physical addresses that could be output in the address translation performed on the requester side. For example, at the PoPA 60 the PAS identifier may be stripped out from the addresses, and for the downstream components the addresses may simply be identified using the physical address value, without specifying the PAS. Alternatively, for some cases where some completer-side filtering of memory access request is desired, the PAS identifier could still be provided downstream of the PoPA 60, but may not be interpreted as part of the address so that the same physical addresses appearing in different physical address spaces 60 would be interpreted downstream of the PoPA as referring to the same memory system location, but the supplied PAS identifier can still be used for performing any completer-side security checks. Figure 5 illustrates how the system physical address space 64 can be divided, using the granule protection table 56, into chunks allocated for access within a particular architectural physical address space 61. The attribute information corresponding to each granule of physical addresses defines which portions of the system physical address space 65 are allowed to be accessed from each architectural physical address space 61. For example the GPT 56 may comprise a number of entries each corresponding to a granule of physical addresses of a certain size (e.g. a 4K page). The GPT entry corresponding to a particular target physical address may specify an index for identifying an attribute storage location corresponding to that physical address, the attribute storage location specifying the granule protection information (GPI). The GPI may assign a particular PAS for that granule, or may indicate that more than one PAS can be used to access the granule. The GPI may also impose a further requirement regarding which domain is associated with the memory access request. If a particular granule or set of granules of physical memory address space is defined in the GPT as being accessible from only one PAS, then it can only be accessed within that PAS and cannot be accessed within the PASs of the other domains. However, note that while a granule allocated to the secure PAS (for instance) cannot be accessed from within the root PAS, the root domain 82 is nevertheless able to access that granule of physical addresses by specifying in its page tables the PAS selection information for ensuring that virtual addresses associated with pages which map to that region of physical addressed memory are translated into a physical address in the secure PAS instead of the root PAS. Hence, the sharing of data across domains (to the extent permitted by the accessibility / inaccessibility rules defined in the table described earlier) may be controlled at the point of selecting the PAS for a given memory access request. However, in some implementations, in addition to allowing a granule of physical addresses to be accessed within a single assigned PAS defined by the GPI, the GPI could mark certain regions of the address space as shared with another address space (e.g. an address space associated with a domain of lower or orthogonal privilege which would not normally be allowed to select the assigned PAS for that domain’s access requests). This can facilitate temporary sharing of data without needing to change the assigned PAS for a given granule. For example, in Figure 5 the region 70 of the realm PAS is defined in the GPI identified by the attribute storage location indicated by the GPT as corresponding to that region as being assigned to the realm domain, so normally it would be inaccessible from the non-secure domain 86 because the non-secure domain 86 cannot select the realm PAS for its access requests. As the non-secure domain 26 cannot access the realm PAS, then normally non-secure code could not see the data in region 70. However, if the realm temporarily wishes to share some of its data in its assigned regions of memory with the non-secure domain then it could request that the monitor code 29 operating in the root domain 82 updates the GPI 56 to indicate that region 70 is to be shared with the non-secure domain 86, and this may make region 70 also be accessible from the non-secure PAS as shown on the left hand side of Figure 5, without needing to change which domain is the assigned domain for region 70. If the realm domain has designated a region of its address space as shared with the non-secure domain, then although the memory access requests targeting that region which are issued from the non-secure domain may initially specify the non-secure PAS, the PAS filter 20 may remap the PAS identifier of the request to specify the realm PAS instead, so that downstream memory system components treat the request as if it was issued from the realm domain all along. This sharing can improve performance because the operations for assigning a different domain to a particular memory region may be more performance intensive involving a greater degree of cache / TLB invalidation and / or data zeroing in memory or copying of data between memory regions, which may be unjustified if the sharing is only expected to be temporary. Other implementations may not support such sharing options and so the GPT may restrict each physical address to being accessible through one PAS only. Figure 6 is a flow diagram showing how to determine the current domain of operation, which could be performed by the processing circuitry 10 or by address translation circuitry 16 or the PAS filter 20. At step 100 it is determined whether the current exception level 15 is EL3 and if so then at step 102 the current domain is determined to be the root domain 82. If the current exception level is not EL3, then at step 104 the current domain is determined to be one of the non-secure, secure and realm domains 86, 84, 88 as indicated by at least two domain indicating bits 14 within an EL3 control register of the processor (as the root domain is indicated by the current exception level being EL3, it may not be essential to have an encoding of the domain indicating bits 14 corresponding to the root domain, so at least one encoding of the domain indicating bits could be reserved for other purposes). The EL3 control register is writable when operating at EL3 and cannot be written from other exception levels EL2-EL0. Figure 7 shows an example of page table entry (PTE) formats which can be used for page table entries in the page table structures used by the address translation circuitry 16 for mapping virtual addresses to physical addresses, mapping virtual addresses to intermediate addresses or mapping intermediate addresses to physical addresses (depending on whether translation is being performed in an operating state where a stage 2 translation is required at all, and if stage 2 translation is required, whether the translation is a stage 1 translation or a stage 2 translation). In general, a given page table structure may be defined as a multi-level table structure which is implemented as a tree of page tables where a first level of the page table is identified based on a base address stored in a translation table base address register of the processor, and an index selecting a particular level 1 page table entry within the page table is derived from a subset of bits of the input address for which the translation lookup is being performed (the input address could be a virtual address for stage 1 translations of an intermediate address for stage 2 translations). The level 1 page table entry may be a “table descriptor” 110 which provides a pointer 112 to a next level page table, from which a further page table entry can then be selected based on a further subset of bits of the input address. Eventually, after one or more lookups to successive levels of page tables, a block or page descriptor PTE 114, 116, 118 may be identified which provides an output address 120 corresponding to the input address. The output address could be an intermediate address (for stage 1 translations performed in an operating state where further stage 2 translation is also performed) or a physical address (for stage 2 translations, or stage 1 translations when stage 2 is not needed). To support the distinct physical address spaces described above, the page table entry formats may, in addition to the next level page table pointer 112 or output address 120, and any attributes 122 for controlling access to the corresponding block of memory, also specify some additional state for use in physical address space selection. For a table descriptor 110, the PTEs used by any domain other than the non-secure domain 86 includes a non-secure table indicator 124 which indicates whether the next level page table is to be accessed from the non-secure physical address space or from the current domain’s physical address space. This helps to facilitate more efficient management of page tables. Often the page table structures used by the root, realm or secure domains 24 may only need to define special page table entries for a portion of the virtual address space, and for other portions the same page table entries as used by the non-secure domain 26 could be used, so by providing the non-secure table indicator 124 this can allow higher levels of the page table structure to provide dedicated realm / secure table descriptors, while at a certain point of the page table tree, the root realm or secure domains could switch to using page table entries from the non-secure domain for those portions of the address space where higher security is not needed. Other page table descriptors in other parts of the tree of page tables could still be fetched from the relevant physical address space associated with the root, realm or the secure domain. On the other hand, the block / page descriptors 114, 116, 118 may, depending on which domain they are associated with, include physical address space selection information 126. The non-secure block / page descriptors 118 used in the non-secure domain 86 do not include any PAS selection information because the non-secure domain is only able to access the non-secure PAS. However for the other domains the block / page descriptor 114, 116 includes PAS selection information 126 which is used to select which PAS to translate the input address into. For the root domain 22, EL3 page table entries may have PAS selection information 126 which includes at least 2 bits to indicate the PAS associated with any of the 4 domains 82, 84, 86, 88 as the selected PAS into which the corresponding physical address is to be translated. In contrast, for the realm and secure domains, the corresponding block / page descriptor 116 need only include one bit of PAS selection information 126 which, for the realm domain, selects between the realm and non-secure PASs, and for the secure domain selects between the secure and non-secure PASs. To improve efficiency of circuit implementation and avoid increasing the size of page table entries, for the realm and secure domains the block / page descriptor 116 may encode the PAS selection information 126 at the same positon within the PTE, regardless of whether the current domain is realm or secure, so that the PAS selection bit 126 can be shared. Hence, Figure 8 is a flow diagram showing a method of selecting the PAS based on the current domain and the information 124, 126 from the block / page PTE used in generating the physical address for a given memory access request. The PAS selection could be performed by the address translation circuitry 16, or if the address translation circuitry forwards the PAS selection information 126 to the PAS filter 20, performed by a combination of address translation circuitry 16 and the PAS filter 20. At step 130 in Figure 8, the processing circuitry 10 issues a memory access request specifying a given virtual address (VA) as a target VA. At step 132 the address translation circuitry 16 looks up any page table entries (or cached information derived from such page table entries) in its TLB 18. If any required page table information is not available, address translation circuitry 16 initiates a page table walk to memory to fetch the required PTEs (potentially requiring a series of memory accesses to step through respective levels of the page table structure and / or multiple stages of address translation for obtaining mappings from a VA to an intermediate address (IPA) and then from an I PA to a PA). Note that any memory access requests issued by the address translation circuitry 16 in the page table walk operations may themselves be subject to address translation and PAS filtering, so the request received at step 130 could be a memory access request issued to request a page table entry from memory. Once the relevant page table information has been identified, the virtual address is translated into a physical address (possibly in two stages via an IPA). At step 134 the address translation circuitry 16 or the PAS filter 20 determines which domain is the current domain, using the approach shown earlier. If the current domain is the non-secure domain then at step 136 the output PAS selected for this memory access request is the non-secure PAS. If the current domain is the secure domain, then at step 138 the output PAS is selected based on the PAS selection information 126 which was included in the block / page descriptor PTE which provided the physical address, where the output PAS will be selected as either secure PAS or non-secure PAS. If the current domain is the realm domain, then at step 140 the output PAS is selected based on the PAS selection information 126 included in the block / page descriptor PTE from which the physical address was derived, and in this case the output PAS is selected as either the realm PAS or the non-secure PAS. If at step 134 the current domain is determined to be the root domain, then at step 142 the output PAS is selected based on the PAS selection information 126 in the root block / page descriptor PTE 114 from which the physical address was derived. In this case the output PAS is selected as any of the physical address spaces associated with the root, realm, secure and non-secure domains. Figure 9 summarises the operation of the address translation circuitry 16 and PAS filter 20. The PAS filtering 20 can be regarded as an additional stage 3 check performed after the stage 1 (and optionally stage 2) address translations performed by the address translation circuitry. Note also that the EL3 translations are based on page table entries which provide two bits of address based selection information (labelled NS,NSE in the example of Figure 9), while a single bit of selection information “NS” is used to select the PAS in the other states. The security state indicated in Figure 9 as input to the granule protection check refers to the Domain ID identifying the current domain of the processing element 4. Figure 10 is a flow diagram illustrating a method for the PAS filter 20 (checking circuitry) to perform the protection check at stage 3 shown in Figure 6. At step 200, the PAS filter 20 obtains protection information, GPT[PA], corresponding to the target physical address (PA) obtained for the memory access request by the address translation circuitry 16. For example, the PAS filter 20 looks up the target PA in the granule protection information cache 22, and if there is a hit for the target PA, determines the protection information associated with the target PA based on cached information specified in a hit entry of the granule protection information cache 22. If the target PA misses in the granule protection information cache 22, then at least one memory access request is sent to the memory system to request that the granule protection entry corresponding to the target PA is returned from memory. For example, the PAS filter 20 may have a register storing a base address of the granule protection table used to define the granule protection information, and may generate the address(es) of the memory access request(s) issued to request the relevant granule protection entry as a function of the base address and the target PA. The right to update the register storing the GPT base address may be restricted to software executing in the root domain (at exception level EL3). Although some implementations may use a linear table structure which can access the required granule protection entry in a single access, other approaches may use a hierarchical table structure similar to multi-level page tables used by the address translation circuitry 16 for accessing address translation mappings, so that it may be required to issue more than one memory access request to step through multiple levels of granule protection table, with each level of granule protection table being indexed based on a respective portion of the target PA, and a pointer provided in an entry in one level of granule protection table providing a base address which can be used to derive the address at which the next level granule protection table is to be accessed. Once the relevant granule protection entry corresponding to the target PA of the original memory access has been returned from memory, then the granule protection information corresponding to the target PA can either be directly read from the granule protection entry or can be retrieved from an attribute storage location corresponding to an index specified by the relevant granule protection entry. Hence, at step 200 information allowing the PAS filter 20 to determine the encoding of the granule protection information corresponding to the target PA is identified by the PAS filter 20. This could be identified either based on cached information in cache 22, or based on information stored in memory. At step 202 the PAS filter 20 determines, based on the information identifying the granule protection information corresponding to the target PA, whether the memory access request is permitted. If the memory access request is not permitted, at step 204 the memory access request is rejected, and a fault is signalled. If the memory access request is determined to be permitted, then at step 206 the memory access request is permitted to proceed. Therefore, as described with reference to Figures 1-10, a mechanism is provided for protecting data stored in memory from malicious access due to compromised translation tables. Figure 11 schematically illustrates a concept of tag-guarded memory accesses. The physical address space used to refer to memory locations within the memory system may be logically partitioned into a number of blocks 330 each comprising a certain number of addressable locations. For conciseness, in the example of Figure 11, each block 330 comprises four memory locations, but other block sizes could be used as well. Each block 330 is associated with a corresponding guard tag 332. The guard tags associated with a certain number of blocks 330 can be gathered together and stored either within a different architecturally accessible memory location 334 within the physical address space, or within additional storage locations provided in main memory which are not architecturally accessible (not mapped to the same physical address space). The use of separate non-architecturally accessible storage may in some cases be preferred to avoid using up space in the data caches for caching guard tag values, which could impact on the performance of the regular code and could make coherency management more complex. An additional tag cache 19 could be provided in the micro architecture for caching tag values from the non-architecturally accessible storage, for faster access than if the tags had to be accessed from main memory. The particular mapping of which tag storage locations 334 correspond to each block 330 may be controlled by the load / store unit and could be hardwired or could be programmable. In general it is a choice for the particular implementation exactly how the guard tags 332 are associated with the corresponding blocks 330 of the physical address space. Hence, when a tag-guarded memory access is required, an address tag 340 is compared against the guard tag 332. The address tag 340 is associated with the target address identifying the addressed location to be accessed, and the guard tag is associated with the block of memory locations 330 which includes the addressed location 344. For example, in Figure 11 the target physical address 342 points to a certain location B1 in memory, marked 344 in the address space of Figure 11. Therefore the guard tag B which is associated with the block of locations B including location B1 is compared against the address tag 340 associated with the target physical address 42. As shown in the top of Figure 11, the address tag 340 may be indicated within selected bits of the target address itself, such that it can be determined as a function of selected bits of the address operand 341 used to derive the target physical address 342. In particular, the address operand may comprise a register having, in a subset of its bits, a pointer for determining a target virtual address and, in a subset of bits not used to indicate the pointer, the address tag 340. For example, in some architectures the top portion of bits of the target address may always have a certain fixed value such as a sign extension (all 0s or all 1s) which are not used to select an addressed location, and therefore could be re-used to store the address tag, and so an address can be tagged with the address tag 340 by overwriting these unused bits with an arbitrary tag value. The address tag may persist through translation such that it is also associated with the target physical address to which the target virtual address is translated, the address tag itself not necessarily being subjected to translation. Hence, when an instruction specifies the address operand 341, then a given address tag may be associated with the downstream memory access requests to addresses derived from that pointer regardless of the value of the address bits themselves, so that the same address tag is specified even if there is a memory error involved in the calculation of the address bits. The particular address tag value is not limited and can be selected by a programmer or compiler for example. The address tag and guard tag 332 can be a relatively small number of bits, e.g. 4 bits, and so need not occupy much space within the memory and within the target address. Providing 4 bits of tag space, i.e. 16 possible values of the tags, can often be enough to detect many common types of memory access errors. Hence, when a memory access is performed, the tag checking circuitry 27 may compare the address tag 340 and the guard tag 332 (associated with a block 330 including the addressed location 344 identified based on the target physical address 342), and determine whether they match. The tag checking circuitry 27 generates a match indication indicating whether the address tag 340 and the guard tag 332 matched. For example, this match indication could be a fault signal which is generated if there is a mismatch between the address tag 340 and the guard tag 332. Alternatively, the match indication may be an indication placed in a status register indicating whether there was a match. Further, the match indication may be an entry added to an error report to indicate the address for which the error was detected and / or the instruction address of the instruction which triggered the error. Memory access requests could be prevented if there is a mismatch between the address tag and guard tag. Alternatively, memory access requests could be allowed to proceed and the error reported for later analysis. Whilst tag checking can be applied to every physical address, in practice only a subset of memory locations are typically protected with tag checking. Hence, to avoid unnecessary tag checks, the tag checking circuitry 27 may access memory tagging attribute information to determine whether or not to perform a tag check for a given target address. In addition, when accessing a target physical address, memory access circuitry may check whether the target physical address is a location for storing guard tags, and if so may enforce controls to limit incorrect modification of the guard tags (e.g. the ability to write to a region storing guard tags may be restricted to certain classes of memory access request which may be generated in response to certain dedicated tag setting instructions). Hence, a variety of behaviours related to memory tagging performed based on guard tags using the tag checking architecture can be expressed using attributes associated with regions of physical addresses, in a similar way to how the granule protection information is associated with physical addresses. The GPT described above for determining the granule protection information provides a particularly convenient mechanism for associating memory tagging attributes with regions of physical addresses. When handling a given memory access, the GPT may be accessed in any case so that granule protection information can be retrieved for PAS checks. Therefore, using the same access to the GPT to determine at least one memory tagging attribute associated with the target physical address avoids the overhead of determining the memory tagging attribute separately, and therefore can improve performance and efficiency of a system making use of the improved security provided by separate physical address spaces and memory tagging. Figure 12 illustrates multi-level table structures which may be used for the translation table structures and physically addressed table structure (e.g., the GPT). The MMU 16 or SMMLI 26 translates virtual addresses to physical addresses based on address mappings. The mappings between virtual addresses and physical addresses are stored in translation tables (sometimes referred to as page tables). Translation tables are stored in memory and are managed by software, typically an OS or hypervisor. The translations tables are not static, and the tables can be updated as the needs of software change. This changes the mapping between virtual and physical addresses. The translation tables can also specify access control attributes such as information on whether a memory region can be accessed by read accesses, write accesses and instruction fetch accesses (for fetching an executable instruction) respectively. For memory accesses performed when the processing circuitry 4 is in a certain subset of execution states (in particular, when the processing circuitry 4 is at ELO or EL1 in the exception model shown in Figure 5), two-stage address translation is used (for other execution states one stage of address translation using the stage-1 page tables can be sufficient). Hence, the virtual addresses from ELO and EL1 are translated using two sets of tables. These tables support virtualization and allow a hypervisor to virtualize the view of physical memory that is seen by a given virtual machine (VM) (the virtual machine corresponding to a guest operating system and the applications controlled by that guest operating system). We call the set of translations that are controlled by the OS, Stage 1. The Stage 1 tables translate virtual addresses (VAs) to intermediate physical addresses (IPAs). In Stage 1, the OS thinks that the IPAs are physical addresses. However, the hypervisor controls a second set of translation mappings, which is called Stage 2. This second set of translation mappings translates IPAs to physical addresses (PAs). Despite their name, the intermediate physical addresses are not physical addresses because they do not correspond to a location in memory, and the name derives from the fact that the OS thinks that the IPAs are PAs. The stage-1 and stage-2 translation tables are implemented as hierarchical multi-level table structures comprising a number of levels of translation tables as shown in Figure 12. In this example, both the stage-1 and stage-2 tables can have up to 4 levels of page tables, namely level 0 (L0), level 1 (L1), level 2 (L2) and level 3 (L3). To locate the physical address mapping for a given address, a translation table walk is performed comprising one or more translation table lookups. The translation table walk is the set of lookups (memory accesses) that are required to translate the virtual address to the physical address. For the EL1&0 translation regime, this set includes lookups for both the stage 1 translation and the stage 2 translation. The information returned by a successful translation table walk using stage-1 and stage-2 lookups is: • The required physical address (translated based on the stage-1 mapping to the intermediate address and the stage-2 mapping to the physical address). • Access permissions and / or memory attributes for the target memory region, which provide information about how to control access to that memory region. These may include stage-1 access permissions and / or attributes defined in the stage-1 table structure and stage-2 access permissions and / or attributes defined in the stage-2 table structure. For traversing a given one of the stage-1 and stage-2 structures, the walk starts with a read of a top-level (L0) translation table for the initial lookup, based on an address specified in a translation table base address register (e.g. TTBR for stage 1, VTTBR_EL2 for stage 2). Each translation table lookup returns a descriptor, that indicates one of the following: • The entry is the final entry of the traversal of the stage-1 or stage-2 structure, which provides the address mapping and memory region permissions / attributes being sought. If the entry is in the final level table L3, this entry is called a Page descriptor (D_Page), while if the entry providing the final entry of the walk is at one of the higher levels it is called a Block descriptor (D_Block). The final entry of the traversal contains the output address (i.e. IPA for stage 1 or PA for stage 2), and the permissions and attributes for the access. If a Block descriptor is found at a higher level of the translation table structure, this means that the Block descriptor represents a memory region of greater size than a 4kB memory page represented by a single entry at L3 (the particular sizes represented by Block descriptors at L1 and L2 being dependent on the number of index bits used to index into the L1 or L2 tables - for example L1 and L2 Block descriptors could represent 1GB and 2MB regions respectively). • An additional level of lookup is required. In this case, the entry is called a Table descriptor (D_Table), since it provides a pointer indicating the translation table base address for that lookup in a further level of table. The Table descriptor can optionally also provide other hierarchical attributes that can be applied to the final translation. An encoding of translation table entries at levels 1 and 2 distinguishes a Block descriptor from a Table descriptor. • The descriptor is invalid. In this case, the memory access generates a Translation fault. Figure 12 illustrates indexing of the stage-1 and stage-2 translation tables using index values derived as a function of bits of the VA (for stage-1) or IPA (for stage-2). The particular entry to select within a given level of stage-1 translation table is determined based on an index value which corresponds to, or is derived from, a certain subset of bits of the VA or IPA provided as input address for the lookup. Each level is indexed based on a different subset of bits of the VA or IPA, with a given level being indexed based on a more significant portion of bits of the VA / IPA than the next level in the structure (e.g. L2 is indexed using a less significant portion of bits than L1). The address of the relevant entry in a given table is obtained by adding a multiple of the index bits to the base address of that given table as determined based on TTBR or the address specified in a Table descriptor at the previous level (the multiplier applied to the index value corresponding to the size of one translation table entry). In practice when the full translation table walk including both stage-1 and stage-2 translation is performed, then each stage-1 table base address obtained from the TTBR and the Table descriptors accessed in the stage-1 L0, L1, L2 translation tables will be an intermediate address which itself needs translating using the stage-2 transition tables. Hence, in cases when the translation table walk does not encounter any Block descriptors, but proceeds all the way to L3 where a Page descriptor is found, then the full page table walk process may include 24 memory accesses (4 lookups for stage-1, and 5*4 lookups for stage-2, where the translation of each of the 4 stage-1 table base addresses (L0-L3) and the final I PA returned by the stage-1 L3 address mapping causes a separate set of 4 lookups to the stage-2 L0-L3 tables for each of those 5 addresses). Hence, without any caching, performing the entire page table walk process can be very slow as it may require a large number of accesses to memory to step through each of the levels of page tables for each of the stages of address translation. This is why it is often desirable to cache information derived from translation table walks in the TLB 18, 28 of the MMU 16 or SMMII 28. The cached information can include any of: a final stage-1 address mapping from VA to IPA, a final stage-2 mapping from IPA to PA a combined stage-1 and stage-2 mapping from VA direct to PA (derived from previous lookups of the stage 1 and stage 2 structures), access permissions and attributes obtained from the stage-1 and stage-2 structures; and translation table pointers derived from entries from higher level page tables of the stage 1 and the stage 2 tables. This can allow at least some steps of the full page table walk to be bypassed even if the final level address mapping for a given target address is not currently in the address translation cache. As shown in Figure 12, the physically addressed table structure may have a similar multi-level structure to the translation tables, although the maximum number of levels may differ from the maximum number of levels for the translation table structures. The physically addressed table structure is accessed based on a physically addressed table structure base address (GPT base) obtained from a register of the processor 4 or SMMII 28 that is writable by software operating at the supervisory execution state EL3 and is not writable in less privileged execution states EL1 and EL2 which are allowed to update the registers storing the base addresses for the stage-1 and stage-2 tables respectively (software operating at EL2 may also be allowed to set the stage-1 base address). Hence, the least privileged state allowed to set the stage-1 base address is EL1, the least privileged state allowed to set the stage-2 base address is EL2, and the least privileged state allowed to set the physically addressed table structure base address is EL3. Unlike the translation tables, the physically addressed table structure is addressed using physical addresses, where the traversal is based on the PA generated in the translation performed by the MMU 16 or SMMU 28 based on the mappings from the translation tables. The physically addressed table structure associates a set of attribute information with each region of physical addresses by identifying an index which points to an attribute storage location storing the attribute information. The attribute information may be associated with a granule of physical addresses of a certain size, e.g. 4KB if the index is defined in the final-level table of the physically addressed table structure. As the corresponding entry of the physically addressed table structure does not need to specify an address translation mapping, the entry for a given 4KB region can be much smaller than the translation table entry providing the address mapping for the region, and so multiple entries for respective 4KB regions can be packed into a single cache line, so that the physically addressed table structure can be more compact than the translation tables and so a structure involving fewer table levels can be practical. For example, Figure 12 shows an example of a physically addressed table structure with a two-level structure, with the L1 physically addressed table structure being accessed based on a table pointer provided by an entry of the L0 physically addressed table structure corresponding to the target PA. The index used for each level of physically addressed table structure is selected based on a respective subset of bits of the target PA, with the L1 table being indexed using a less significant portion of bits of the target PA than the portion of bits used for indexing the L0 table. It will be appreciated that a 2-level physically addressed table structure is just one example, and other examples could have a different number of physically addressed table structure levels depending on the granularity (region size) for which the entries are defined. Entries of the physically addressed table can be used to determine target physical address attributes, comprising both the PAS-based permissions mentioned above in addition to at least one memory tagging attribute. It will be appreciated from the above that a lookup in the multi-level physically addressed table structure may comprise traversals of several sub-tables. Whilst the target physical address attribute information may be directly specified in the corresponding entry of the physically addressed table, Figure 13 illustrates an alternative in which entries of the physically addressed table specify an index, and at least a portion of the target physical address attribute information is specified in an attribute storage location (out of a set of attribute storage locations) identified by the index specified in the corresponding entry. Both of the physically addressed table structure and the set of attribute storage locations may be provided in memory. Alternatively, the set of attribute storage locations may be stored in registers. When stored in memory, the set of attribute storage locations may be cached locally to the attribute determination circuitry for faster access. In examples where the target physical address attribute information is determined from a set of attribute storage locations, a mechanism may be provided to ensure consistency of the set of attribute storage locations in cases where several devices may have access to the physical address space. For example, storing the attribute storage locations in memory (and providing a cache invalidation mechanism for when the attribute storage locations are updated) can ensure that each device sees the same attributes and hence enforces permissions uniformly. Figure 14 is a flow diagram illustrating a method according to the present technique. At step 1400 a memory access request is received specifying a target virtual address, and address translation circuitry 16 translates the target virtual address into a target physical address. For example, the translation circuitry 16 uses address mappings defined using S1 and S2 translation tables as illustrated in Figure 12 to translate the target virtual address to the target physical address (optionally via an intermediate physical address, which is itself a virtual address as it does not directly indicate the addressed location in memory). Note that at the time of the translation, it may not always be necessary to access the translation tables themselves, as address mapping information obtained from the translation tables previously may be cached in the TLB 18. The address translation circuitry 16 (or in some cases separate dedicated circuitry) also provides the function of physical address space selection circuity which selects a physical address space (PAS) for the memory access request based on the translation table entries. The selection of PAS is restricted based on the domain from which the memory access request was issued, so less secure domains are unable to issue memory access requests in the more secure PAS, for example. The selected PAS may be indicated by combining (e.g., concatenating) a number of PAS bits with the target physical address, which prior to the point of physical aliasing (PoPA) will be treated as part of the target physical address but will not be treated as such after the PoPA. At step 1402, if information required for controlling the memory access is not already available in any caching structure (such as the granule protection information cache 22), the target physical address derived from the translation in step 1400 is used by table lookup circuitry to perform a lookup in a physically addressed table structure (such as the one illustrated at the bottom of Figure 12, in some cases referred to as a granule protection table (GPT)). The lookup identifies an entry of the physically addressed table structure (a “corresponding entry”) which corresponds to a granule of physical addresses containing the target physical address. At step 1404, based on the lookup in the physically addressed table structure, the table lookup circuitry 21 is configured to obtain target physical address attribute information comprising both granule protection information (indicating whether the selected PAS is an allowed PAS permitted to access the target physical address) and at least one memory tagging attribute related to the tag checking architecture which supports tag checking as discussed above. The memory tagging attribute may express at least one tag checking behaviour and / or guard tag usage behaviour associated with the granule (region) of physical addresses comprising the target physical address. The table lookup circuitry may obtain the attribute information directly from the corresponding entry of the physically addressed table structure, or may obtain at least a portion of the attribute information from an attribute storage location (e.g., a location in memory or in a register) identified by an index specified by the corresponding entry of the physically addressed table structure. At step 1406, physical address space checking circuitry uses the granule protection information derived from the lookup in the physically addressed table structure to determine whether to reject the memory access request. In particular, it is checked whether the PAS selected for the memory access request is an allowed PAS permitted to access the granule of physical addresses comprising the target physical address. For example, whilst the access request may have been issued from the realm domain and selecting the realm PAS, the target physical address may be located in a granule of memory designated for access by the secure domain, and therefore a granule for which the realms PAS is not an allowed PAS. In this case, the memory access request would be rejected. It will be appreciated that at step 1406, the granule protection information could instead be cached and not necessarily used to determine whether to reject the memory access request, or could both be cached and used to determine whether to reject the memory access request. It is noted that even if the granule protection check (the physical address space check) passes, the memory access request can still be subjected to other checks such as the tag check, checks based on the permissions specified in the translation tables, and in some cases checks based on other permissions specified in the corresponding entry of the physically addressed table structure. On the other hand, at step 1407, the tag checking circuitry 27 (or in some cases the load / store unit of a processor) may control a memory tagging behaviour for the memory access request based on the at least one memory tagging attribute obtained at step 1404. This behaviour could, for example, relate to whether a tag check is performed for this memory access, or whether guard tags are stored in or associated with the region comprising the target physical address. Figure 15 illustrates a first example of use of a memory tagging attribute to control a memory tagging behaviour for the memory access request. At step 1408, the tag checking circuitry determines based on the memory tagging attribute whether the granule of physical addresses comprising the target physical address is a granule for which a tag check is required. If so, then at step 1410 a tag check is performed by the tag checking circuitry 27. An address tag is determined from bits of an address operand from which the target virtual address was derived, where those bits used to determine the address tag are not used for identifying the addressed location in memory (e.g., upper-order bits of a 64 bit memory address which would otherwise be sign extended because the actual address space in use can be represented using fewer than 64 bits). A guard tag is determined based on the target physical address. For example, the guard tag may be at a memory location corresponding to a fixed offset from the target physical address, or the guard tag may be stored in a separate structure indexed based on the target physical address or based on information specified in the memory tagging attributes. In some examples, the corresponding entry of the physically addressed table structure is used to derive the guard tag, for example by providing a base address or offset used to access a location within a guard tag storage region in memory. Regardless of where the guard tag is stored, the address tag and guard tag are compared to determine whether they match. A match may mean that the numeric values of the two tags should be identical. However, this is not always required, as in some cases one of the tags may have an encoding which matches with all other tags regardless of their value (e.g. a “match all” encoding can be supported for one or both of the address tag and guard tag). In some cases, the determined tags may be remapped to take different values, and the match may be determined based on the remapped values such that a match may be determined even for guard and address tags which did not match. In any case, at step 1412 an error handling response is performed if a mismatch is detected. For example, the memory access request may be rejected. Alternatively, the memory access request may be permitted despite the mismatch. In either case the mismatch may be recorded in an error log to provide the programmer an opportunity to remedy the fault leading to the memory error. If a mismatch is not detected, then the memory access request may be permitted to proceed subject to any other access checks. If, instead, at step 1408 it was determined that a tag check is not required, then at step 1414 the tag check is bypassed. This may mean that the guard tag is not retrieved from memory (although the guard tag may be retrieved regardless for performance reasons) and may mean that the comparison is not performed, which both may improve efficiency of the system. Even if the comparison is performed, not performing the tag check means that the result of the comparison does not affect processing and is not reported. Figure 16 shows a second example where a memory tagging attribute determined at step 1404 of Figure 14 is used to express whether a region of physical address space has been used for storing guard tags. At step 1416, memory access circuitry (which may be provided as part of, or separate from, the tag checking circuitry) uses the at least one memory tagging attribute to determine whether the target physical address lies in a region of memory designated for storing guard tags. This can be important because incorrect modification of the guard tags (e.g. because an address pointer for an instruction not intended to modify guard tags was accidentally set to point to a guard tag storage location) can affect the integrity of the tag checks. If it is determined that the target physical address does lie in a region for storing guard tags, then at step 1418 access to the target physical address is controlled to protect those guard tags, by applying a restriction on access that would not be applied to regions not designated as storing guard tags. For example, the access may only be permitted to proceed if the memory access request is a predetermined type of access request for accessing guard tags. The predetermined type of access request may be issued in response to a dedicated class of tag modifying instruction (having a different instruction opcode to other types of memory write instructions which enable generic updates to memory not related to tag modification). If it is determined that the target physical address does not lie in a region for storing guard tags, then at step 1420 the access request is allowed to proceed dependent on other permissions. There is no need to apply the restriction applied at step 1418. As shown in the example of Figure 17, the interconnect 8 may include a system cache 260 which can be an example of a pre-PoPA memory system component which treats aliasing physical addresses from different PASs as if they correspond to different memory system resources. However, as shown in Figure 17, the memory system accessed by such a requester device 4 (e.g. a CPU) may be shared to also be accessible to one or more other devices 252 which may access memory via a system memory management unit (SMMU, also known as an input / output memory management unit or IOMMU) 250. The SMMU 250 may be an example of the other requester device 4 shown in Figure 1. The devices 252 may, for example, include peripheral devices or I / O devices which provide an interface between the CPU 4 and the outside world (e.g. the devices could include display controllers, network controllers, user interface controllers, memory controllers for accessing external off-ship storage, etc.). Also, the devices 252 may include hardware accelerators which are provided to accelerate bespoke processing tasks using specialised hardware which can carry out this task more efficiently than general purpose processor hardware provided by the CPU 4. For example, hardware accelerators can be provided for accelerating functions such as cryptographic operations and machine learning tasks such as neural network processing. Use of a hardware accelerator can also be helpful to offload certain memory-intensive tasks to take place in the background of ongoing processing at the CPU 4. As such devices 252 may not have their own address translation circuitry capable of translating virtual addresses to physical addresses based on the rich memory mappings defined by the page tables used by the CPU 4, the SMMU 250 may be provided as a system component to receive requests from the devices 252 specifying a virtual address, and to perform the required address translations on behalf of the devices. Hence, in some systems, the SMMU 250 may be provided with address translation circuitry 16 and a PAS filter 20 similar to that shown in Figure 1, with the PAS filter 20 acting as checking circuitry for checking the permissions defined by the granule protection information, and one or both of the address translation circuitry 16 and PAS filter 20 of the SMMU 250 providing the PAS selection circuitry described earlier. Hence, the SMMU 250 can also support access to multiple physical address spaces and a third stage of checks based on the granule protection information as shown in Figure 9. The address translation circuitry 16 and PAS filter 20 may therefore operate in the same way as discussed above. The SMMU 250 may have a TLB 18 and / or GPI cache 22 similar to the corresponding cache structures in the requester 4 shown in Figure 1. The SMMU 250 may also provide tag checking circuitry 27, and an associated tag cache 19, for performing tag checks with respect to memory accesses issued by devices 252. The address tags used in said tag checks may be specified in operands that are not provided in the SMMLI itself, but which are provided in registers of the devices 252 issuing the memory access requests. Hence, the SMMLI 250 may not have access to the address tags, and hence may receive from the devices 252 the address tags used in performing the tag checks. In some examples where access requests may be filtered based on the domain issuing the memory access request, the PAS filter 20 of the SMMLI 250 needs information on which domain (security state) is associated with a memory access request received from a device 252. The SMMLI 250 will not have access to the system registers 12 of the CPU which define the register state 14 defining the current domain of operation, and in any case the requests sent by a given device 252 may be related to processing in a domain other than the current domain that is active at the CPU 4. Therefore, in the approach shown in Figure 17, the memory access requests sent to the SMMU 250 by a device 252 may specify a domain identifier which identifies the domain associated with the memory access request. For example, each device 252 may maintain a data structure identifying, for each workload assigned to the device, a corresponding domain identifier (which may be set, for example, at the time of assigning work to the device, based on the current domain 14 associated with the software that caused the work to be assigned to that device). This data structure can be used by the device 252 to select which domain to specify in the domain identifier provided to the SMMU 250 when a memory access request is issued to the SMMU 250. The particular mechanism by which memory access requests from devices are associated with particular domain identifier values may depend on the specific purpose of the device and the mechanism chosen by software developers for assigning workloads to the device 252, so may not be a required feature of the system hardware. However, in general the hardware support for providing signal paths allowing a domain identifier to be provided by the device 252 to the SMMU 250 along with a memory access request means that the PAS filter 20 within the SMMU 250 can implement the protection checking using the domain associated with the memory access request, not just the selected PAS. As shown in the example of Figure 17, the interconnect 8 may include a system cache 260 which can be an example of a pre-PoPA memory system component which treats aliasing physical addresses from different PASs as if they correspond to different memory system resources. Concepts described herein may be embodied in computer-readable code for fabrication of an apparatus that embodies the described concepts. For example, the computer-readable code can be used at one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising the apparatus embodying the concepts. The above computer-readable code may additionally or alternatively enable the definition, modelling, simulation, verification and / or testing of an apparatus embodying the concepts described herein. For example, the computer-readable code for fabrication of an apparatus embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register-transfer-level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying the concepts. The code may define a HDL representation of the one or more logic circuits embodying the apparatus in Verilog, System Verilog, Chisel, or VHDL (Very High-Speed Integrated Circuit Hardware Description Language) as well as intermediate representations such as FIRRTL. Computer-readable code may provide definitions embodying the concept using system-level modelling languages such as SystemC and SystemVerilog or other behavioural representations of the concepts that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts. Additionally or alternatively, the computer-readable code may define a low-level description of integrated circuit components that embody concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. The one or more netlists or other computer-readable representation of integrated circuit components may be generated by applying one or more logic synthesis processes to an RTL representation to generate definitions for use in fabrication of an apparatus embodying the invention. Alternatively or additionally, the one or more logic synthesis processes can generate from the computer-readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purposes of verification and test of the concepts prior to fabrication in an integrated circuit or the FPGA may be deployed in a product directly. The computer-readable code may comprise a mix of code representations for fabrication of an apparatus, for example including a mix of one or more of an RTL representation, a netlist representation, or another computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus embodying the invention. Alternatively or additionally, the concept may be defined in a combination of a computer-readable definition to be used in a semiconductor design and fabrication process to fabricate an apparatus and computer-readable code defining instructions which are to be executed by the defined apparatus once fabricated. Such computer-readable code can be disposed in any known transitory computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductor, magnetic disk, or optical disc. An integrated circuit fabricated using the computer-readable code may comprise components such as one or more of a central processing unit, graphics processing unit, neural processing unit, digital signal processor or other components that individually or collectively embody the concept. Figure 18 illustrates a simulator implementation that may be used. Whilst the earlier described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the techniques concerned, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein which is implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software based implementation of a hardware architecture. Varieties of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 430, optionally running a host operating system 420, supporting the simulator program 410. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple distinct instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations which execute at a reasonable speed, but such an approach may be justified in certain circumstances, such as when there is a desire to run code native to another processor for compatibility or re-use reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality which is not supported by the host processor hardware, or provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 IISENIX Conference, Pages 53 - 63. To the extent that embodiments have previously been described with reference to particular hardware constructs or features, in a simulated embodiment, equivalent functionality may be provided by suitable software constructs or features. For example, particular circuitry may be implemented in a simulated embodiment as computer program logic. Similarly, memory hardware, such as a register or cache, may be implemented in a simulated embodiment as a software data structure. In arrangements where one or more of the hardware elements referenced in the previously described embodiments are present on the host hardware (for example, host processor 430), some simulated embodiments may make use of the host hardware, where suitable. The simulator program 410 may be stored on a computer-readable storage medium (which may be a non-transitory medium), and provides a program interface (instruction execution environment) to the target code 400 (which may include applications, operating systems and a hypervisor) which is the same as the interface of the hardware architecture being modelled by the simulator program 410. Thus, the program instructions of the target code 400 may be executed from within the instruction execution environment using the simulator program 410, so that a host computer 430 which does not actually have the hardware features of the apparatus 2 discussed above can emulate these features. This can be useful, for example, for allowing testing of target code 400 being developed for a new version of a processor architecture before hardware devices actually supporting that architecture are yet available, as the target code can be tested by running within the simulator executing on a host device which does not support that architecture. The simulator code includes processing program logic 412 which emulates the behaviour of the processing circuitry 10, e.g. including instruction decoding program logic which decodes instructions of the target code 400 and maps the instructions to corresponding sequences of instructions in the native instruction set supported by the host hardware 430 to execute functions equivalent to the decoded instructions. The processing program logic 412 also simulates processing of code in different exception levels and domains as described above. Register emulating program logic 413 maintains a data structure in a host address space of the host processor, which emulates architectural register state defined according to the target instruction set architecture associated with the target code 400. Hence, instead of such architectural state being stored in hardware registers 12, it is instead stored in the memory of the host processor 430, with the register emulating program logic 413 mapping register references of instructions of the target code 400 to corresponding addresses for obtaining the simulated architectural state data from the host memory. This architectural state may include the current domain indication 14 and current exception level indication 15 described earlier. The simulation code includes address translation program logic 414, physical address space selection program logic 416, and physical address space checking program logic 418 which emulate the functionality of the address translation circuitry 16, the physical address space selection circuitry, and the physical address space checking circuitry (the PAS filter 20) respectively. The simulation code also comprises tag checking program logic 420 which emulates the functionality of the tag checking circuitry 27. The physical address space checking program logic 418 and the tag checking program logic 420 both reference target physical address attribute information determined in a combined lookup of a physically addressed table structure by table lookup program logic 422. The physical addresses in the simulation embodiment are simulated physical addresses, which from the point of view of the target code refer to physical locations in memory, but actually these simulated physical addresses are mapped onto the (virtual) address space of the host processor by address space mapping program logic 424. In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation. In the present application, lists of features preceded with the phrase “at least one of” mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in 5 combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination. Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be 10 effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. An apparatus, comprising:address translation circuitry to translate a target virtual address of a memory access request to a target physical address;physical address space selection circuitry to select a selected physical address space for the memory access request from among a plurality of physical address spaces;physical address space checking circuitry to determine whether to reject the memory access request based on protection information corresponding to the target physical address, the protection information specifying which of the plurality of physical address spaces is allowed to provide access to the target physical address;tag checking circuitry configured to perform, according to a tag checking architecture supporting definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of physical addresses, a tag check comprising:comparing an address tag, derived from a portion of an address operand from which the target virtual address was derived, with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target physical address;generating an indication of whether a match is detected between the guard tag and the address tag; andselectively performing an error handling response in dependence on the indication of whether a match is detected; andtable lookup circuitry configured to perform a lookup in a physically addressed table structure to identify a corresponding entry corresponding to the target physical address, and based on that lookup obtain target physical address attribute information comprising both the protection information and at least one of said memory tagging attributes associated with a target region of physical addresses including the target physical address.

2. The apparatus according to claim 1, wherein said at least one of said memory tagging attributes indicates whether memory access requests to the target region of physical addresses are to be subject to the tag check.

3. The apparatus according to any preceding claim, wherein said at least one of said memory tagging attributes comprises an indication of a location in memory storing the guard tag corresponding to the target physical address.

4. The apparatus according to any preceding claim, wherein said at least one of said memory tagging attributes indicates whether the target region of physical addresses is for storing guard tags.

5. The apparatus according to claim 4, wherein the tag checking circuitry is configured to permit the memory access request to proceed without being subject to the tag check in response to determining that the target region of physical addresses is for storing guard tags.

6. The apparatus according to any of claims 4 and 5, comprising memory access checking circuitry configured to be responsive to a determination that the target region of physical addresses is for storing guard tags to apply a restriction on accesses to the target region to prevent incorrect modification of the guard tags.

7. The apparatus according to claim 6, in which the restriction comprises controlling access to the target region in dependence on whether the memory access request is a predetermined type of tag modifying memory access request.

8. The apparatus according to any preceding claim, in which, for at least one variant of the error handling response supported by the tag checking circuitry, the error handling response comprises preventing a memory access request from accessing the target physical address when a mismatch is detected between the guard tag and the address tag.

9. The apparatus according to any preceding claim, in which, for at least one variant of the error handling response supported by the tag checking circuitry, the tag checking circuitry permits a memory access to the addressed location irrespective of the outcome of the tag check, and the error handling response comprises generating a report that the guard tag and the address tag did not match.

10. The apparatus according to any preceding claim, wherein the tag checking circuitry is configured to identify the addressed location independent of the address tag.

11. The apparatus according to any preceding claim, in which the table lookup circuitry is configured to determine at least a portion of the target physical address attribute information from a given attribute storage location identified among a set of attribute storage locations, the given attribute storage location identified by an index indicated by the corresponding entry of the physically addressed table structure.

12. The apparatus according to any preceding claim, in which the physically addressed table structure has an encoding capable of assigning, using respective entries, independent attributes to respective granules of physical addresses within a physical address space.

13. The apparatus according to any preceding claim, in which the physically addressed table structure comprises a multi-level table structure comprising a plurality of levels of physically addressed table, the entry corresponding to the target physical address being stored at a memory system location associated with a physical address derived from a portion of the target physical address and a table pointer obtained from a higher-level entry corresponding to the target physical address in a higher-level physically addressed table14. The apparatus according to any preceding claim, in which the memory access request is associated with one of a plurality of domains of processing, and the physical address space selection circuitry is configured to select the selected physical address space in dependence on the domain of processing associated with the memory access request.

15. The apparatus according to claim 14, in which the plurality of domains includes at least a less secure domain associated with a less secure physical address space and a more secure domain associated with a more secure physical address space, and the physical address space selection circuitry is configured to prohibit the more secure physical address space being selected for memory access requests associated with the less secure domain.

16. The apparatus according to any preceding claim, comprising a point of physical aliasing (PoPA) memory system component configured to de-alias a plurality of aliasing physical addresses from different physical address spaces which correspond to a same memory system location, to map any of the plurality of aliasing physical addresses to a de-aliased physical address to be provided to at least one downstream memory system component; andat least one pre-PoPA memory system component provided upstream of the PoPA memory system component, where the at least one pre-PoPA memory system component is configured to treat the aliasing physical addresses from different physical address spaces as if the aliasing physical addresses correspond to different memory system locations.

17. Computer-readable code for fabrication of the apparatus according to any of claims 1 to 16.

18. A method, comprising:translating a target virtual address of a memory access request to a target physical address;selecting a selected physical address space for the memory access request from among a plurality of physical address spaces;determining whether to reject the memory access request based on protection information corresponding to the target physical address, the protection information specifying which of the plurality of physical address spaces is allowed to provide access to the target physical address;performing, according to a tag checking architecture supporting definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of physical addresses, a tag check comprising:comparing an address tag, derived from a portion of an address operand from which the target virtual address was derived, with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target physical address;generating an indication of whether a match is detected between the guard tag and the address tag; andselectively performing an error handling response in dependence on the indication of whether a match is detected; andperforming a lookup in a physically addressed table structure to identify a corresponding entry corresponding to the target physical address, and based on that lookup obtaining target physical address attribute information comprising both the protection information and at least one of said memory tagging attributes associated with a target region of physical addresses including the target physical address.

19. A computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising:address translation program logic to translate a target virtual address of a memory access request to a target simulated physical address;physical address space selection program logic to select a selected physical address space for the memory access request from among a plurality of physical address spaces;physical address space checking program logic to determine whether to reject the memory access request based on protection information corresponding to the target simulated physical address, the protection information specifying which of the plurality of physical address spaces is allowed to provide access to the target simulated physical address;tag checking program logic configured to perform, according to a tag checking architecture supporting definition of memory tagging attributes expressing memory tagging behaviour to be observed for respective regions of simulated physical addresses, a tag check comprising:comparing an address tag, derived from a portion of an address operand from which the target virtual address was derived, with a guard tag stored in simulated memory in association with a block of one or more simulated memory locations comprising an addressed location identified by the target simulated physical address;5 generating an indication of whether a match is detected between the guard tagand the address tag; andselectively performing an error handling response in dependence on the indication of whether a match is detected; andtable lookup program logic configured to perform a lookup in a physically addressed10 table structure to identify a corresponding entry corresponding to the target simulated physical address, and based on that lookup obtain target physical address attribute information comprising both the protection information and at least one of said memory tagging attributes associated with a target region of simulated physical addresses including the simulated target physical address.1520. A computer-readable storage medium storing the computer-readable code of claim 18 or the computer program of claim 19.

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