UV optoelectronic device, p-contact structure and process for preparing the same

Abstract

The device comprises a p-i-n or p-n active junction, a p-AlGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 cm-3 or more, and an interlayer disposed on the p-AlGaN, wherein the interlayer comprises low-dimensional structures such as nanowires, nanotubes, nanopyramids or materials from such as selenides, conductive oxides, graphene or amorphous carbon. The interlayer may also be a p-AlGaN contact barrier regulator layer with a thickness of less than 10nm.

Description

Field of the Invention This invention concerns a UV optoelectronic device comprising a p-i-n or p-n junction, a highly doped p-AIGaN layer, an interlayer and a metallic p-contact; and a process for preparing the same. The invention also concerns a multilayer p-contact structure for a UV optoelectronic device comprising a highly doped group 11 l-V layer, an interlayer and a metallic p-contact, and processes for preparing the same. Background There is a constant need to improve the efficiencies of semiconductor electronic devices based on p-n or p-i-n junctions, such as in LEDs or photodetectors. UV optoelectronic devices, e.g. deep UV light-emitting diodes (DUV LEDs) with light emission in the 200-300 nm wavelength range are in high demand, not only to replace traditional large and toxic mercury lamps, but to serve the fastgrowing market of applications in the biomedical sector, such as sterilisation and water disinfection. Besides the obvious benefit of being non-toxic, nitride-based semiconductor LEDs also have the advantages of being much smaller, costefficient requiring only low voltages and therefore are highly integrable. Electronic devices such as DUV LEDs are commonly based on group-Ill nitride p-n or p-i-n junctions, mostly in thin film heterostructures. Their overall efficiency (wall-plug efficiency, WPE) describes the ability of the device to convert electrical input power to optical output power. Among the factors playing into the WPE are the internal quantum efficiency (IQE), light extraction efficiency (LEE) and electric efficiency (EE). The IQE is depending on the quality and properties of the p-i-n-junction itself, whereas the LEE and EE are more connected to contacting and packaging of the LED. As of today, p-i-n junctions are well developed, achieving recombination efficiencies (RE) of 80% or above (Guo-Dong Hao et al, 2020, J. Phys. D: Appl. Phys., 53, 505107)) resulting in high IQEs. However, improvements can be made. In particular, achieving high electric efficiency (EE) and high light extraction efficiency (LEE) remain challenging for DUV LEDs in particular. One of the most limiting factors for the EE and LEE is the p-side contact material: in order to provide sufficient hole injection, it has to form a good ohmic contact to the p-type (typically wide-gap Ill-nitride semiconductor) underneath, but at the same time, the material of choice has to be transparent, e.g. for the emitting DUV light. The present invention concerns a UV optoelectronic device which aims to increase the EE and LEE by combining an interlayer (e.g. a graphene interlayer) with a highly doped p-AIGaN layer on the p-side of the p-i-n junction. The use of the present device or p-contact layers can enhance the emission intensity (e.g. by lowering contact barrier or improving hole injection) of the UV optoelectronic device which is attributed to a low barrier between the p-doped part of the p-n or p-i-n junction and the metal contact, thus maintaining an efficient vertical tunnelling current and injection of the activated holes into the valence band of the p-doped part of the p-n or p-i-n junction. Summary of Invention Thus, viewed from one aspect, the present invention concerns a UV optoelectronic device comprising: (i) a p-i-n or p-n junction; (ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more; (iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (iv) a metallic p-contact disposed on said interlayer. Viewed from another aspect, the present invention concerns a UV optoelectronic device comprising: (i) a p-i-n or p-n junction; (ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more; (iii) an interlayer having a thickness of 10 nm or less disposed on said p-AIGaN layer, wherein said interlayer is a contact barrier regulator layer; and (iv) a metallic p-contact disposed on said interlayer. Viewed from another aspect, the present invention concerns a multilayer p-contact structure for a UV optoelectronic device comprising: (ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more; (iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (iv) a metallic p-contact disposed on said interlayer. Viewed from another aspect, the present invention concerns a multilayer p-contact structure for a UV optoelectronic device comprising: (ii) a p-AIGaN layer having a doping level of 1016 / cm3or more; (iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (iv) a metallic p-contact disposed on said interlayer. Viewed from another aspect, the present invention concerns a process for preparing a UV optoelectronic device as herein described, comprising the steps of: (a) forming a p-i-n or p-n junction; (b) forming a p-AIGaN layer on the p-side of the p-i-n or p-n junction wherein the p-AIGaN layer has a doping level of 1016 / cm3or more; (c) forming an interlayer on the p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (d) forming a metallic p-contact on said interlayer. Viewed from another aspect, the present invention provides a process for preparing the UV optoelectronic device as herein described, comprising the steps of: (a) forming a p-i-n or p-n junction; (b) forming a p-AIGaN layer on the p-side of the p-i-n or p-n junction wherein the p-AIGaN layer has a doping level of 1016 / cm3or more; (c) forming an interlayer having a thickness of 10 nm or less on said p-AIGaN layer, wherein said interlayer is a contact barrier regulator; and (d) forming a metallic p-contact on said interlayer. Viewed from another aspect, the present invention provides a process for preparing the multilayer p-contact structure as herein described, comprising the steps of: (b) forming a p-AIGaN layer, optionally on the p-side of a p-i-n or p-n junction, wherein the p-AIGaN layer has a doping level of 1016 / cm3or more; (c) forming an interlayer on the p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (d) forming a metallic p-contact on said interlayer. The features of the aspects and / or embodiments indicated herein are useable individually and in combination in all aspects and embodiments of the invention where technically viable, unless otherwise indicated. Brief Description of Figures Figure 1 illustrates an electronic device comprising, from bottom to top, an AIN / sapphire(0001) template (i.e. substrate); a n-current spreader comprising Si-doped Alo.53Gao.47N (1500 nm); a n-contact layer comprising Si-doped Alo.48Gao.52N (400 nm); a multiple quantum well active region comprising a plurality of multiple quantum wells (Alo.4Gao.6N (2 nm)) and multiple quantum barriers (Alo.68Gao.32N (10 nm)); a p-type electron blocking layer comprising Mg-doped Alo.68Gao.32N (20-100 nm); a Mg-doped Alo.67Gao.33N layer (5-50 nm); a graphene interlayer (0-10 nm); and a metallic p-contact. Whilst Figure 1 is shown with ‘graphene interlayer’, it is clear that the invention is not so limited. Detailed Description of Invention Viewed from one aspect, the present invention refers to a UV optoelectronic device comprising: (i) a p-i-n or p-n junction; (ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more; (iii) an interlayer disposed on said p-AIGaN layer of (ii) wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (iv) a metallic p-contact disposed on said interlayer of (iii). The electronic device may comprise (i) to (iv) in this order. Viewed from another aspect, the present invention refers to a multilayer p-contact structure for a UV optoelectronic device comprising (ii) to (iv). The multilayer p-contact structure may comprise (ii) to (iv) in that order. As used herein, the multilayer p-contact structure refers to a plurality of layers which are disposed on the p-side of a p-i-n or p-n junction, wherein at least one layer has p-type doping. The wording “disposed on” refers to the formation of an electrical contact. The term “optoelectronic device” includes, but is not limited to, any of the following: a light emitting diode (LED), a laser, or a photodetector. When used herein the wording “device” should be interpreted as “optoelectronic device”. An optoelectronic device as referred to herein is a semiconductor optoelectronic device. The term “UV optoelectronic device” refers to devices and systems which emit, find, detect and control light in the ultraviolet (UV) range of the electromagnetic spectrum. The UV range of the electromagnetic spectrum refers to light with a wavelength of 10 to 400 nm. The UV optoelectronic device may be selected from an ultraviolet A (UVA), an ultraviolet B (UVB) or an ultraviolet C (UVC) optoelectronic device, preferably a UVC optoelectronic device. As described herein, UVA typically refers to UV light with a wavelength of 315 to 400 nm, UVB typically refers to UV light with a wavelength of 280 to 315 nm and UVC typically refers to light with a wavelength of 100 to 280 nm. A preferable embodiment for the UV optoelectronic device is as an LED, preferably a UVB or UVC LED, especially a UVC LED. The device may act as or be a flip chip device. For an optoelectronic device that can act as a flip chip device, the metallic p-contact layer will typically comprise or be a reflective layer which directs light e.g. all light back towards (and through) the layers / regions underneath, or the device may comprise an additional reflective layer disposed on the p-contact layer For photodetectors, the light goes in the other direction, i.e. the reflective layer reflects light back onto the p-n or p-i-n junction. Therefore, the optoelectronic device may be or act as a flip chip and the metallic p-contact may comprise a reflective layer. Unless otherwise indicated, the term ‘on’ (as in a layer ‘on’ another region or layer) typically means ‘directly on’, i.e. without any intermediate layers or regions. The term also typically means ‘in electrical contact with’. Similarly, ‘in contact with’ typically means ‘in direct contact with’ or ‘in electrical contact with’. Unless otherwise stated, the term ‘bottom’ refers to the substrate side of the device, and the term ‘top’ refers to the p-contact side of the device. The terms are meant as relative terms only and may not reflect final positioning in the device. p-n or p-i-n junction The UV optoelectronic device of the present invention comprises a p-n or a p-i-n junction. The p-n or p-i-n junction is typically composed of a number of regions or layers disposed on a substrate. Whilst the term ‘layer’ is used herebelow, the device is not limited and any discussion of layers may also apply to regions without any particular dimensional limitation, unless otherwise stated. The layers may be in the form of heterostructured thin films (i.e. continuous layers) disposed on a substrate with different types of doping. In an alternative embodiment, the p-n or p-i-n junction may be in the form of or comprise heterostructured nanostructures (e.g. nanowires or nanopyramids) disposed on a substrate. The wording ‘disposed on’ refers to the formation of an electrical contact. It is preferred if the n-side of the p-i-n or p-n junction is disposed on the substrate. The substrate is typically disposed on the underside of the n-side of the p-i-n or p-n junction. The substrate as defined herein is not particularly limited. It is preferred if the substrate is a crystalline substrate. The substrate may comprise a single layer or multiple layers. At least one of the substrate layers is typically semiconducting and is preferably undoped. However, the substrate may be doped. The wording “substrate”, “support” and “template” may be used interchangeably herein. The substrate may have a crystal orientation of

[111] ,

[110] ,

[0001] or

[100] perpendicular to the surface.

[0001] is preferred. The substrate may be selected from: sapphire, silica (SiOz), quartz, alumina (AI2O3), Si, SiC, Ga2O3, graphene, or group 11 l-V semiconducting compounds. As referred herein, “group 11 l-V semiconducting compounds”, “group 11 l-V compounds” and “I I l-V compounds” can all be used interchangeably. For substrate group lll-V semiconducting compounds, group III options are B, Al, Ga, In, and Tl. Preferred options here are Ga, Al, B and In, preferably Ga, Al, and In. Group V options are N, P, As, Sb. N is preferred. The lll-V compounds may be binary, ternary, quaternary, quintinary etc. The substrate may comprise ternary compounds which may be of formula XYZ wherein X is a group III element, Y is a group III different from X, and Z is a group V element. The X to Y molar ratio in XYZ is preferably 0.01-0.99, e.g. 0.1 to 0.9, i.e. the formula is preferably XxYi.xZ where subscript x is 0.01-0.99, e.g. 0.1 to 0.9. The substrate may comprise quaternary compounds and may e.g. be represented by the formula AxBi-xCyDi-y where A and B are group III elements and C and D are group V elements or AxByCi-x-yD where A, B and C are group III elements and D is a group V element. Again, subscripts x and y are typically 0.01-0.99, e.g. 0.1 to 0.9. Other options will be clear to the skilled person. It is preferred if the substrate is selected from AIN or sapphire, or a combination of AIN and sapphire, preferably AIN on sapphire. The thickness of the substrate is not particularly limited, but preferably is in the range of 0.1 to 2000 pm, such as 10 to 1000 pm, especially 100 to 1000 pm. In the preferred case of AIN on sapphire, comprising two layers, the individual thickness of the AIN layer is in the range of 1 to 10000 nm, such as 10 to 1000 nm, especially 20 to 500 nm and the individual thickness of the sapphire is 100 to 2000 pm, especially 100 to 1000 pm The substrate may be transparent or substantially transparent. Transparent as defined herein typically covers transparency across all UV wavelengths (i.e. for UV optoelectronic devices). Preferably the substrate is transparent or substantially transparent to UVC wavelengths. The p-n or p-i-n junction of the present invention comprises a p-type region, an n-type region and optionally an intrinsic (i) region. In the case of the p-i-n junction, when charge carriers (e.g. holes and electrons) are injected into the respective p-type and n-type regions, they recombine in the i-region, wherein the recombination generates light. For the p-n junction, recombination will occur in the space charge region (as there is no intrinsic region). It is therefore preferred if the UV optoelectronic device herein comprises a number of layers comprising group III-V semiconducting compounds which are doped. Doping described below refers to doping with respect to any feature across all aspects of the invention herein, for example the different regions of the p-n or p-i-n junction. Doping typically involves the introduction of impurity ions into the layer, e.g. during epitaxial growth. The doping level can be controlled from ~ 1015 / cm3to 1022 / cm3, preferably 1016 / cm3to 1021 / cm3, especially 1017 / cm3to 1018 / cm3. Typically, the doping level of any regions or layers in the p-n or p-i-n junction is different, and typically less, than the doping level in the p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction. Preferably, therefore, the highly doped p-AIGaN layer has a higher level of doping than the p-side of the p-n or p-i-n junction. The n-type region has a larger electron concentration than hole concentration by doping with donor impurities. Suitable donor impurities for the n-type region include Te, Sn, Si, Ge and C. The n-type region may be in the form of a single layer or multiple layers. It is especially preferred if the n-type region comprises at least one layer which is Si-doped. The p-type region has a larger hole concentration than electron concentration by doping with acceptor impurities. Suitable acceptor impurities for the p-type region include Be, Mg and Zn. The p-type region may be in the form of a single layer or multiple layers. It is especially preferred if the p-type region comprises at least one layer which is Mg-doped. These considerations for the p-type region also apply to the highly doped p-AIGaN layer. Si can be amphoteric and can as a donor or acceptor depending on the site where Si goes to, the orientation of the growing surface and the growth conditions. The intrinsic region may consist of a single layer of material or a heterostructure consisting of multiple quantum wells and barriers. Typically, the intrinsic layer is a multiple quantum well. The intrinsic region typically acts as the light emitting layer, in the case of light emitters (such as LEDs) or as the light absorbing layer, in the cases of absorbers (e.g. photodetectors). The intrinsic region is preferably a multiple quantum well (MQW) comprising a number of quantum well layers and a number of barrier layers alternatively stacked, preferably wherein the multiple quantum well comprises 3-10 repetitions of well and barrier layers. Typically, the intrinsic layer / region is positioned directly between the p-type and n-type regions. The p-n or p-i-n junction may comprise at least one electron blocking layer, preferably disposed directly on the intrinsic region, preferably wherein the electron blocking layer is p-doped. “Directly” as used herein across all aspects of this invention typically refers to direct contact between two regions or layers. The electron blocking layer is selected from a group 11 l-V semiconducting compound as defined herein. The electron block layer typically forms part of the p-type region of the p-n or p-i-n junction. The p-n or p-i-n junction may comprise at least one current spreader or a current spreader layer. Preferably the current spreader will be n-doped, and thus forms part of the n-type region of the p-n or p-i-n junction. The current spreader will also preferably be selected from a group 11 l-V semiconducting compound as defined herein. The n-region may comprise two or more different n-doped 11 l-V regions, differing in their atomic ratios or carrier concentration. The n-region may comprise, for example, two different n-AIGaN regions or layers. One may be an n-contacting region, which is in contact with the light emitting or light absorbing (i.e. intrinsic) region. This n-contacting layer may be disposed on the n-current spreader region. The n-current spreader is typically in contact with the substrate (i.e. located between the substrate and the n-contacting layer). The n-current spreader may have, for example a larger Al concentration than the n-contacting layer. The p-n or p-i-n junction will typically comprise at least one n-type group III-V (preferably 11 l-N) semiconducting compound and at least one p-type group lll-V (preferably Ill-N) semiconducting compound. In addition to the at least one p-type and n-type group lll-V semiconducting compounds, the p-n or p-i-n junction may comprise an undoped group lll-V (preferably Ill-N) semiconducting compound. The group lll-V semiconducting compounds refer to any as described herein across all aspects of the invention. For the group lll-V semiconducting compounds, group III options are B, Al, Ga, In, and Tl. Preferred options here are Ga, Al, B and In, preferably Ga, Al, and In. Group V options are N, P, As, Sb, but N is preferred. The lll-V compounds may be binary, ternary, quaternary, quintinary etc. Ternary is preferred, in particular ternary 11 l-N. Compounds based on Al, Ga and In in combination with N are preferred. Compounds based on Al and Ga in combination with N are particularly preferred. Preferably the lll-V compounds comprise at least Al. For ternary group lll-V compounds of formula XYZ (wherein X is a group III element, Y is a group III different from X, and Z is a group V element) the X to Y molar ratio in XYZ is preferably 0.01 to 0.99, e.g. 0.1 to 0.9, i.e. the formula is preferably XxYi-xZ where subscript x is 0.01 to 0.99, e.g. 0.1 to 0.9. In a preferred embodiment, subscript X is 0.4 to 0.7. AlxGai.xN, wherein x is in the range of 0.4 to 0.7 is particularly preferred, therefore. It is further preferred if the value of x differs between the different regions of the p-i-n or p-n junction. In a preferable embodiment, each region (e.g. p-, n- or optionally i-region) may comprise (or consist of) one or more layers of group lll-V semiconducting compounds of formula XYZ which differ in their value of x. The regions may alternatively or additionally differ in the nature of the dopant or the doping concentration. Quaternary compounds for the p-n or p-i-n junction may be represented by the formula AxBi-xCyDi-y where A and B are group III elements and C and D are group V elements or AxByCi-x-yD where A, B and C are group III elements and D is a group V element. Again subscripts x and y are typically 0.01-0.99, e.g. 0.1 to 0.9. Other options will be clear to the skilled person. AIGaN, InAIN, InAIGaN, and InGaN are most preferred, especially AIGaN. Preferably, for UV applications in particular, the p-n or p-i-n junction does not comprise InGaN, since InGaN is not suitable for IIV / UVC applications. In a preferred embodiment, the p-n or p-i-n junction will comprise (or consist of) at least one layer of p-AIGaN, at least one layer of n-AIGaN and at least one layer of i-AIGaN. Preferably, the p-n junction or p-i-n junction does not comprise GaN, other than an optional thin p-GaN layer (0-1 nm) in the uppermost region of the p-region (see discussion below), e.g. located on top of a p-AIGaN layer in the p-side of the p-n or p-i-n junction. Preferably the device does not comprise a GaN region or layer other than a thin optional p-GaN layer (0-1 nm) located on the uppermost region of the p-region. Preferably any GaN present in the device is limited to a thickness of 2 nm or less, preferably 1 nm or less. The thickness of each region or layer in the p-n or p-i-n junction is not particularly limited, but preferably is in the range of 10 to 2500 nm, such as 1000 to 2000 nm or 50 to 500 nm. In certain embodiments, the p-n junction will comprise at least one layer which is 10 nm or less, such as 0.1 to 5 nm. The thickness of the p-region of the p-n or p-i-n junction may be 20-100 nm. The thickness of the intrinsic region may be 10-100 nm, for example. The thickness of the n-region of the p-n or p-i-n junction may be 500 nm to 2500 nm. The thickness of the n-contacting layer may be 100 nm to 1000 nm. The thickness of the n-current spreader may be 500-2000 nm. In certain cases, the p-n or p-i-n junction may be part of, in the form of or comprise a heterostructured nanostructure or microstructure. ‘Nanostructure’ may herein mean a nanowire (also termed a nanorod, nanopillar, nanocolumn or nanowhisker), a nanopyramid, or a nanoribbon. Any discussion of nanostructures herein equally applies to microstructures, where technically viable. The term nanowire is used herein to describe a solid, wire-like structure of nanometer dimensions. Nanowires preferably have an even diameter throughout the majority of the nanowire, e.g. at least 75% of its length. Nanowires may have tapered end structures. The nanowires can be said to be in essentially in onedimensional form with nanometer dimensions in their width or diameter and their length typically in the range of 100 nm to a few (e.g. 5) pm. Preferably the nanowires are at least 1 micrometer in length. Where a plurality of nanowires are grown, it is preferred if at least 90%, preferably all, meet these dimension requirements. Ideally, at least 90% of the nanowires grown on a substrate will be at least 1 micrometer in length. Preferably substantially all the nanowires will be at least 1 micrometer in length. Ideally the nanowire diameter / width is not greater than 1000 nm. Ideally the nanowire diameter / width is between 10 and 1000 nm, e.g. 50 and 500 nm. Ideally, the diameter at the base of the nanowire and at the top of the nanowire should remain about the same (e.g. within 20% of each other). The term nanopyramid refers to a solid pyramidal type structure. The term pyramidal is used herein to define a structure with a base whose sides taper to a single point generally above the centre of the base. It will be appreciated that the single vertex point may appear chamfered, e.g. such that the pyramid has a flat top. Typically, the chamfered portion is equivalent to less than 50%, e.g. less than 40%, e.g. less than 30%, e.g. less than 20%, e.g. less than 10%, e.g. less than 5% of the total length of the nanopyramid edge. The nanopyramids may have multiple faces, such as 3 to 8 faces, or 4 to 7 faces. Thus, the base of the nanopyramids might be a triangle, square, pentagonal, hexagonal, heptagonal, octagonal and so on. The pyramid is formed as the faces taper from the base to a central point (forming therefore triangular faces). The triangular faces are normally terminated with {1-101} or {1-102} planes. The triangular side surfaces with {1-101} facets could either converge to a single point at the tip or could form a new facets ({1-102} planes) before converging at the tip. These 4-digit indices are typically most appropriate for hexagonal crystals. In some cases, the nanopyramids are truncated with its top terminated with {0001} planes. The base itself may comprise a portion of even cross-section before tapering to form a pyramidal structure begins. The thickness of the base may therefore be up to 500 nm, e.g. up to 200 nm, such as 50 nm. The base of the nanopyramids can be between 50 and 500 nm in diameter across its widest point. In another embodiment, the base of the nanopyramids can be 200 nm to one micrometer in diameter across its widest point. The height of the nanopyramids may be 200 nm to a few (e.g. 5) micrometers, such as 400 nm to 1 micrometer in length. In certain cases, the nanostructure may be etched to form a corrugated / ridged design. For example, the nanostructure may be etched to form a nanopyramid. Etching the nanostructure may, in certain cases, improve the light extraction or absorption efficiency of the device. It is preferred for nanostructures to have an epitaxial relationship with the substrate. The term epitaxy comes from the Greek roots epi, meaning "above", and taxis, meaning "in ordered manner". The atomic arrangement of the nanostructure is typically based on the crystallographic structure of the substrate. Epitaxial growth means herein the growth on the substrate of a nanostructure or microstructures that mimics the orientation of the substrate. Heterostructured nanostructures may be axially heterostructured or radially heterostructured. It is generally preferred for any nanostructure to be axially heterostructured. In an embodiment where at least some of the nanostructures are radially heterostructured, the nanostructures may coalesce, thus having an appearance of a continuous or partially continuous film opposed to individual nanostructures. For any embodiment wherein the p-n or p-i-n junction is in the form of a nanostructure, the n-type region may be in the form of the nanostructure core and the p-type region, and optionally intrinsic region, may be in the form of additional layers on the core or vice versa. The nanostructure core is herein defined as the (innermost) part of the nanostructure which grows first on the substrate, and / or which is in physical contact with the substrate. For embodiments wherein the p-i-n or p-n junction is in the form of a heterostructured film, the film may be planar or non-planar. Any thin film present in the p-i-n or p-n junction preferably has an epitaxial relationship with the substrate. Typically, the regions within the p-n or p-i-n junction are epitaxial with each other. The region of the p-i-n or p-n junction (e.g. n-region) which is in contact with the substrate is typically epitaxial with the substrate. In the case of a thin film which is non-planar, it may have a corrugated structure or parts which are semipolar (e.g. pyramidal). Semipolar as referred herein refers to planes which are not vertical (i.e. non-polar) or horizontal (polar). A non-planar structure may be beneficial in certain case as it can enable good light extraction for transverse-magnetic (TM) polarisation, a larger emitting area, higher doping levels, better tunnelling, or improved strain management by elastic deformation. In alternative cases, a planar thin film is alternatively preferred, as it may improve simplicity and cost structure of device fabrication. The layers or regions of the p-n or p-i-n junction are preferably conformal with each other (i.e. the structure or shape of an upper region / layer matches that of the underlying layer / region) The p-n or p-i-n junction is preferably conformally formed on the substrate. Highly Doped Layer The UV optoelectronic device described herein comprises a p-AIGaN layer disposed on the p-side (i.e. on the p-region or p-layer) of the p-i-n or p-n junction having a doping level of 1016 / cm3or more. This layer may alternatively be referred to as the “highly doped p-AIGaN layer” or “the highly doped layer”. The highly doped p-AIGaN layer is directly in contact with the p-side of the p-i-n or p-n junction. The highly doped p-AIGaN layer is p-doped. Preferably the highly doped p-AIGaN is doped with Mg. The highly doped p-AIGaN layer may alternatively be referred to as a p++ AIGaN layer. A high degree of doping for the p-AIGaN layer is beneficial, especially in combination with a thin interlayer (e.g. a graphene interlayer), because it decreases the thickness of the depletion region (also called space charge region) and lowers the Schottky barrier to the metallic p-contact layer thus maximising the conditions for tunnelling as the preferred mechanism for carrier injection. Semiconducting materials, such as AIGaN as used herein, can accommodate high doping levels, thus increasing current injection and efficiency of the device. To prepare the highly doped p-AIGaN layer, as described herein, doping typically involves the introduction of impurity ions into the layer, e.g. during epitaxial growth. The doping level can be controlled from ~ 1016 / cm3to 1022 / cm3, preferably 1018 / cm3to 1021 / cm3, wherein the numbers refer to the number of doping / impurity ions per cm3. For “high” doping, the doping level is preferably at least 1016 / cm3, preferably of at least 1017 / cm3, preferably of at least 1018 / cm3 (e.g. at least 5 x 1018 / cm3), preferably of at least 1019 / cm3. It is especially preferred if the doping for the highly doped p-AIGaN layer is in the region of 1018-1022 / cm3, such as 1019-1021 / cm3 The thickness of the highly doped p-AIGaN layer is not particularly limited. It is generally preferred if the highly doped p-AIGaN layer has a thickness of 1 to 100 nm, preferably 5 to 50 nm. The p-AIGaN may be of formula AlxGai.xN, wherein x is 0.4-0.9. Subscript x is preferably 0.5 or more, such as 0.55 or more or 0.6 or more, preferably 0.65 or more or 0.67 or more. Subscript x is preferably 0.9 or less, preferably 0.8 or less, preferably 0.7 or less. Suitable ranges forx include 0.4-0.9, especially 0.5-0.8, such as 0.55- 0.7. Without being bound by theory when x is 0.4 or more, in particular 0.55 to 0.7, the highly doped p-AIGaN layer has increased transparency to UV light and thus the emission (or absorption) properties of the device are improved. The geometry of the highly doped p-AIGaN layer is not particularly limited. The highly doped p-AIGaN layer will preferably have a geometry aligned to the p-side of the p-i-n or p-n junction. Typically, the highly doped p-AIGaN layer is planar. Alternatively, the highly doped p-AIGaN layer may be semipolar. A semipolar highly doped p-AIGaN layer may be preferred as it may benefit the light extraction or absorption efficiency. The highly doped p-AIGaN layer may be in the form of a thin film. Alternatively, the highly doped p-AIGaN may be part of, or disposed on nanostructures, as defined herein for any aspect of the invention. The highly doped p-AIGaN layer may completely cover or substantially cover the p-side of the p-i-n or p-n junction. In an alternative embodiment, the highly doped p-AIGaN layer will continuously cover at least a portion of the p-side of the p-i-n or p-n junction, e.g. at least 50% of the p-side of the p-i-n or p-n junction, such as at least 75%, at least 90% or at least 99% of the p-side of the p-i-n or p-n junction. The highly doped p-AIGaN layer is preferably conformally formed on the p-side of the p-n or p-i-n junction. Interlayer The UV optoelectronic device described herein comprises an interlayer which comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon. The interlayer is disposed on the highly doped p-AIGaN layer. For example, there is direct contact between the interlayer and the highly doped p-AIGaN layer. The interlayer may be referred to as a contact barrier regulator or contact barrier reducer, for example. These terms mean interlayers that regulate or lower the electrical contact barrier between the p-doped part of the p-n or p-i-n junction and the metal contact (thus maintaining an efficient vertical tunnelling current and injection of holes into the valence band of the p-doped part of the p-n or p-i-n junction). Any discussion herein relating to the interlayer may apply to ‘the contact barrier regulator’. When used herein, the term one-dimensional material refers to an amorphous, polycrystalline, or crystalline material where any charge carriers are confined to one dimension and cannot move freely in other dimensions, typically due to having a physical size in the nanometer scale in the confined dimensions, with a greater length on the micrometer scale or larger in the free dimension. The two-dimensional material may be graphene, silicene, hexagonal-BN (h-BN), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3 or NiTe2. The one-dimensional material may comprise or be nanotubes or fullerene-type materials. When the interlayer comprises a one-dimensional material, it typically means the interlayer comprises a plurality of nanotubes (or fullerenes) forming a mesh, e.g. a randomly oriented interpenetrating network structure. In other words, the interlayer may be a film of nanotubes and / or fullerenes. Nanotubes may include, but are not limited to, any of the following: carbon nanotubes (CNT), boron nitride nanotubes (BNNT), silicon carbide nanotubes (SiCNT), aluminium nitride nanotubes (AINNT) or combinations thereof, or any fullerene-type structures based on these materials. For amorphous carbon, it is preferable for a thin sheet to be used of thickness 10 nm or less, especially 5 nm or less. The conductive oxide is preferably a transparent conductive oxide. Indium tin oxide (ITO) is preferred as the conductive oxide. Whilst graphene is preferred, other ‘graphene-like’ materials with onedimensional or two-dimensional structures are therefore suitable herein, e.g. silicene, hexagonal-BN, carbon nanotubes (CNT), boron nitride nanotubes (BNNT), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2. The interlayer may therefore comprise or consist of graphene, silicene, hexagonal-BN, carbon nanotubes (CNT), boron nitride nanotubes (BNNT), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2. In certain cases, the interlayer is a graphene interlayer or a graphitic interlayer. The term graphene refers to a planar sheet of sp2-bonded carbon atoms in a honeycomb (hexagonal) crystal structure. It is especially preferred if the graphene interlayer consists of graphene. Whilst it is preferred to use graphene, it is also possible to use derivatives of graphene, such as those with surface modification. Therefore, the graphene interlayer may comprise or consist of a derivative of graphene. For example, hydrogen atoms can be attached to the graphene surface to form graphane. Graphene with oxygen atoms attached to the surface along with carbon and hydrogen atoms is called as graphene oxide. Graphitic herein typically means graphene, graphane or graphene oxide. The surface modification can be also possible by chemical doping or oxygen / hydrogen or nitrogen plasma treatment. The graphene interlayer may comprise or consist of single- or multilayer graphene. Single or multilayer as used herein refers to the number of sheets of graphene. The interplanar spacing in graphene is around 0.3 nm, e.g. 0.335 nm. The interlayer should ideally contain 10 sheets or less of two-dimensional material (e.g. graphene or graphene-like material), preferably 5 sheets or less, preferably 4 sheets or less, preferably 3 sheets or less, preferably 2 sheets or less of two-dimensional material. Preferably the interlayer should contain 1-5 sheets, preferably 1-4 sheets, preferably 1-3 sheets, preferably 1-2 sheets of two-dimensional material most preferably 1 sheet of two-dimensional material). Especially preferred, the graphene interlayer is a one-atom-thick planar sheet of graphene (i.e. a monolayer of graphene or graphene-like material. In the case of graphene or graphene derivatives for the interlayer, particularly efficient tunnelling (see discussion below) through the interlayer is obtained when the interlayer is thin, e.g. one or two atomic layers thick, preferably when the interlayer is a one-atom thick sheet of graphene. In terms of metric thicknesses, it is preferred if the interlayer is 20 nm in thickness or less, preferably 10 nm in thickness or less, preferably 5 nm or less, such as 2 nm or less. The interlayer is ideally less than 1.5 nm in thickness. Even more preferably, the interlayer may be 1 nm or less in thickness, more preferably 0.9 nm or less in thickness, more preferably 0.8 nm or less in thickness, more preferably 0.7 nm or less in thickness, more preferably 0.6 nm or less in thickness, more preferably 0.5 nm or less in thickness. Preferred thickness ranges include 0.1 to 20 nm, such as 0.2 to 10 nm, preferably 0.3-2 nm, preferably 0.3-1.5 nm, e.g. 0.3-1 nm, 0.3-0.9 nm, 0.3-0.8 nm, 0.3-0.7 nm e.g. 0.3-0.5 nm. The interlayer (e.g. graphene interlayer) will preferably have a thickness of 20 nm or less, such as 10 nm or less, in order to reduce absorption of emitted UV light as far as possible. Having a thin interlayer (e.g. graphene interlayer) improves hole tunnelling into the p-side of the device. The highly doped p-AIGaN is a pre-requisite for such tunnelling to occur in the first place. The combination of the highly-doped p-AIGaN and the interlayer is beneficial, therefore. The present concept focuses on vertical hole transport across the interlayer / pAIGaN interface. This is in contrast to most previous work done on lateral hole transport at a graphene-containing interface. Any graphene used in the interlayer is preferably used without surface modification. The interlayer may be doped (e.g. p-doped), as described in relation to any aspect of the invention reported herein. Doping may help to improve the electrical conductivity of the interlayer. For an interlayer which is doped, it is preferable for p-type doping to be used. If the interlayer comprises or consists of graphene, said graphene is preferably undoped. Using undoped graphene for the interlayer is beneficial because it preserves the atomical thinness of graphene, avoids contamination or damage typically associated with doping and facilitates ease of processing. Alternatively, it may be preferable if the graphene is doped as it may allow the contact barrier to be lowered. Graphene is well known for its superior optical, electrical, thermal and mechanical properties. Graphene is very thin but very strong, light, flexible, and impermeable. The graphene interlayer is typically not under biaxial compressive strain, but it may lower the Schottky barrier between the metallic p-contact and the highly doped p-AIGaN layer, reducing the resistance and facilitating tunnelling. Preferably, the interlayer is a graphene or amorphous carbon interlayer. These are preferred because a thin layer of graphene or amorphous carbon (e.g. 10 nm or less thickness) is enough to achieve the desired effect of contact barrier regulation and minimise the absorption of UV light. Furthermore, these materials can be deposited conformally across the semiconductor (i.e. highly doped p-AIGaN) and also be combined with a multitude of different metals as a metallic p-contact. Carbon nanotubes are another polymorph of sp2-bonded carbon closely related to graphene. They can be understood as one or more graphene strips which are rolled and closed into covalently bonded cylinders. The tubes may be single-walled nanotubes (SWCNT), or multi-walled nanotubes (MWCNT) which comprise two or more concentrically nested SWCNTs. CNTs may be open at the end faces of the cylinder, or include fullerene-like geodesic structured end caps. CNTs share many chemical properties with graphene, particularly regarding bonding, passivation, doping, and functionalization of the sidewalls. Additionally, if carbon end caps are not present, open edges of CNT cylinders may be readily functionalized chemically for many purposes including tuning of chemical and electrical properties. SWCNTs have diameters between approximately 0.4 nm - 2.0 nm. MWCNTs may have larger diameters up to approximately 40 nm. The length of CNTs can vary widely from <1 nm to >10 cm, though typical lengths are in the micrometer scale. (0.5 pm - 10 pm). In MWCNTs, the spacing between walls is typically about 0.3 - 0.4 nm, similar to the spacing between layers in multi-layer graphene or bulk graphite. SWCNTs have an extremely high tensile strength in the longitudinal direction of approximately 100 GPa, with MWCNTs and CNT bundles showing lower strength due to shear between non-covalently bonded shells and tubes. However, CNTs are extremely compliant to bending, as the sidewalls can readily form kinks with little strain of their covalent bonds. As a result, CNTs can easily form cable-like bundles, unstructured mats, or more ordered arrangements depending on their processing, and can be conformally applied to non-flat or rough surfaces, e.g. nano-faceted crystals. The electronic and thermal properties of CNTs are distinct from graphene in that they vary widely based on the structure of the tube. While single-layer graphene (SLG) can be understood as a zero-bandgap semiconductor or semimetal which is functionally conductive, SWCNTs may have a bandgap varying from 0 eV to about 2.5 eV, depending on the diameter and orientation of the tube cylinder axis with respect to the symmetry of the graphene lattice comprising the sidewall. CNTs with a zero bandgap are referred to as metallic tubes, while CNTs with a bandgap larger than zero are referred to as semiconducting tubes. MWCNTs may contain shells with differing symmetries, and their electronic properties are a hybrid of all sub-shells, typically close to metallic in nature. CNTs generally exhibit significant optical absorption, particularly at UV wavelengths. However, a well-dispersed and thin mat of CNTs can have a high transparency due to the relatively high void percentage. Thus, CNT coatings can be used to realize optically transparent conductive layers, with a trade-off between in-plane conductivity and transparency. In addition to carbon, nanotubes with comparable structures may be formed from other materials with similar bonding, notably boron nitride (BNNTs), silicon carbide (SiCNTs), and aluminium nitride (AINNTs). BNNTs are functionally insulators, with a wide bandgap around 5.5 eV, while AINNTs are semiconductors and SiCNTs are semimetals or semiconductors. Composite nanotubes have also been formed, notably boron nitride I carbon composites (BNCNTs) with intermediate properties between the two species. In certain cases an encapsulation layer may be present which is disposed on the two-dimensional or one-dimensional material. The encapsulation layer would typically be disposed on the interlayer (e.g. graphene interlayer) on an area of the interlayer which is not covered by a metallic p-contact, e.g. adjacent to the metallic p-contact. Therefore, the encapsulation layer may cover at least a portion of the interlayer, e.g. at least 5% of the interlayer, such as at least 20% of the interlayer, such as at least 50% of the interlayer, at least 75% or at least 90% of the interlayer. The encapsulation layer, where present, typically comprises an oxide, e.g. alumina, silica. The encapsulation layer may prevent degradation of the interlayer (e.g. graphene), and could also be used for indirect p-doping to enhance contact properties. The interlayer, in particular graphene, may be patterned. Patterning may be used to enhance adhesion and / or anchor the metallic p-contact and / or any encapsulation layer. Patterning is a known technique in the art, and includes the formation of voids or defects, e.g. using conventional lithography techniques such as photo / e-beam lithography, nanoimprinting, focussed ion beam technology etc. The skilled person would be familiar with this term. The voids here refer to physical holes with a diameter of 5 pm or less, such as 1 to 5 pm. Ideally the voids have a diameter of 500 nm or less, ideally 20 to 200 nm. Without being bound by theory, when the interlayer is graphene, patterning may enhance carrier transfer in / out of graphene via the altered bonding states at the unterminated edges. The interlayer may be transparent or substantially transparent. Transparent as defined herein cover transparency across all wavelengths of interest, e.g. UV wavelengths, in particular UVC wavelengths. Typically, UV optoelectronic devices as defined herein where the interlayer is transparent or substantially transparent could be used as top emitting structures, flip chip devices with reflecting p-contacts or vertically integrated devices, but the invention is not so limited. In case of hole injection into the highly doped p-AIGaN layer by a tunnelling mechanism the interlayer (e.g. graphene interlayer) acts as a hole reservoir and starting point enabling more effective hole tunnelling from the metal contact through the interlayer and highly doped p-AIGaN layer into the p-side (e.g. p-AIGaN layer) of the p-n or p-i-n junction. The interlayer may further moderate the energy step to the highly doped p-AIGaN layer, thus improving the tunnelling by reducing the barrier height. Preferably the interlayer will not act as the metallic p-contact, as a current spreader or as an electrode. In a certain cases, the interlayer will completely cover or substantially cover the highly doped p-AIGaN layer. In an alternative embodiment, the interlayer will continuously cover at least a portion of the highly doped p-AIGaN layer, e.g. at least 50% of the highly doped p-AIGaN layer, such as at least 75%, at least 90% or at least 99% of the highly doped p-AIGaN layer. The interlayer is preferably conformally formed on the highly doped p-AIGaN layer. P-contact The UV optoelectronic device and multilayer p-contact structure defined herein comprises a metallic p-contact or a metallic p-contact layer disposed on the interlayer. For example, there is a direct contact between the metallic p-contact and the interlayer. “Metallic” defined herein refers to comprising a metal or an alloy. “Metallic” defined herein does not include semiconductor materials, such as group 11 l-V compounds. Preferred metals include: Al, Au, Ni, In, Rh, Pd and / or Pt. Particularly preferred metals include: Al, In, Ni, Au, and / or Pt, especially a Ni / Au stack and / or Pt The metallic p-contact defined herein may have a structure in the form of a single layer or a multi-layered film. The metallic p-contact may be in the form of a strip-like sheet of metal. In some cases, it is preferred if light is emitted (or absorbed) in a direction substantially opposite to the substrate. Alternatively, the metallic p-contact may be reflective or comprise a reflective layer. The metallic p-contact may thus comprise at least one light reflective layer and thus the device may act as a flip chip device. For a UV optoelectronic device which acts as a flip chip device, light will be reflected back in the direction towards the substrate, thus emitting light from the bottom of the device. The flip chip configuration may be preferable when at least one, preferably all of (i) to (iv) are transparent or substantially transparent. The metallic p-contact is preferably 5 nm or more in thickness. It may have at thickness of 5-1000 nm for example. If the reflective layer is separate from the p-contact, then its thickness may also be between 5-1000 nm, though the thickness is preferably thicker than 25% of the optical wavelength emitted by the device. Preferably, the metallic p-contact will completely cover or substantially cover the interlayer. In an alternative embodiment, the p-contact will continuously cover at least a portion of the interlayer, e.g. at least 50% of the interlayer, such as at least 75%, at least 90% or at least 99% of the interlayer. The UV optoelectronic device of the invention will also comprise a n-contact which is disposed on any layer in the n-type region of the p-i-n or p-n junction. The n-contact generally will also be metallic. The n-contact may completely cover or substantially cover at least one layer of the n-type region of the p-i-n or p-n junction. In an alternative embodiment, the n-contact will continuously cover at least a portion of the n-type region of the p-i-n or p-n junction, e.g. at least 50% of the n-type region of the p-i-n or p-n junction, such as at least 75%, at least 90% or at least 99% of the n-type region of the p-i-n or p-n junction. In an alternative embodiment, the n-contact may cover only a small portion of the n-type region of the p-i-n or p-n junction, such as 20% or less, 10% or less or 5% or less. The metallic p-contact, in addition to the n-contact, will be appropriately connected to a power supply to enable the UV optoelectronic device to function. The present invention preferably is directed to a UV optoelectronic device comprising: - An n-type AIGaN region; - A p-type AIGaN region; - A light-emitting region or light-absorbing region position between the n-type AIGaN region and the p-AIGaN region; - A p-AIGaN layer having a doping level of 1016 / cm3or more disposed on the p-type AIGaN region; - A graphene interlayer having a thickness of 10 nm or less disposed on the highly doped p-AIGaN layer; - A metallic p-contact disposed on said graphene interlayer; A metallic n-contact disposed on the n-type AIGaN region. The p-contact is preferably conformally formed on the interlayer. Process Viewed from a yet alternative aspect, the present invention provides a process for preparing a UV optoelectronic device as defined herein, comprising the steps of: (a) forming a p-i-n or p-n junction; (b) forming a p-AIGaN layer on the p-side of the p-i-n or p-n junction wherein the p-AIGaN layer has a doping level of 1016 / cm3or more; (c) forming an interlayer on the p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and (d) forming a metallic p-contact on said interlayer. For step (a), typically the regions of the p-i-n or p-n junction (e.g. AIGaN regions) are formed using metalorganic vapour phase epitaxy (MOVPE) (also referred to as metalorganic chemical vapour deposition (MOCVD)), or molecular beam epitaxy (MBE). In case of MOCVD / MOVPE, the deposition material is supplied in the form of metalorganic precursors, which on reaching the high temperature substrate decomposes leaving atoms on the substrate surface. In addition, this method requires a carrier gas (typically H2 and / or N2) to transport deposition materials (atoms / molecules) across the substrate surface. These atoms reacting with other atoms form an epitaxial layer on the substrate surface. Choosing the deposition parameters carefully results in the formation of a nanowire or thin film. A higher degree of control of the nucleation and growth might be achieved with the MOCVD technique by using pulsed layer growth technique, where e.g. the group III and V elements can be supplied alternatively. Molecular beam epitaxy (MBE) is a method of forming depositions on crystalline substrates. The MBE process is performed by heating a crystalline substrate in a vacuum so as to energize the substrate's lattice structure. Then, an atomic or molecular mass beam(s) is directed onto the substrate's surface. When the directed atoms or molecules arrive at the substrate's surface, the directed atoms or molecules encounter the substrate's energized lattice structure or a catalyst droplet as described in detail below. Over time, the oncoming atoms form a nanowire or thin film. A higher degree of control of the nucleation and growth of the nanowires or thin films on the substrate might be achieved with the MBE technique by using migration-enhanced epitaxy (MEE) or atomic-layer MBE (ALMBE) where e.g. the group III and V elements can be supplied alternatively instead of simultaneously. MBE takes place in ultra-high vacuum, with a background pressure of typically around 10-10 to 10-9 Torr. Nanostructures or films are typically grown slowly, such as at a speed of up to a few, such as about 10, pm per hour. This allows nanostructures or films to grow epitaxially and maximises structural performance. Typically, for step (b) the p-AIGaN layer is also formed using MOCVD or MBE. For step (c), the interlayer may be formed using material-specific deposition methods. For example, if the interlayer is a graphene interlayer, it may be formed using direct growth or it may be formed using growth and transfer. There are many variations of direct growth which may be used, such as variations with a plasma or low temperature. Alternatively, an interlayer (e.g. a graphene interlayer) may be grown in an external environment and transferred (using a variety of methods) and placed on the p-AIGaN layer. For example, the interlayer may be grown on metal catalysts, such as metallic films or foils made of e.g. Cu, Ni or Pt. Graphene may also be grown on a SiC substrate using a thermal sublimation process and then transferred onto the highly doped p-AIGaN layer. In the case of a graphene interlayer, the interlayer may be patterned by a sequence of electron- or photolithography on an electron- or photosensitive resist, followed by an etching step by exposure to oxygen plasma and subsequent removal of the resist. Additional cleaning steps might be appropriate, for example with acetone or other solvents. Alternatively, an interlayer comprising or consisting of a mat or film of carbon nanotubes (CNTs) or other similar nanotubes may be transferred and placed on the hole injector. CNTs may be synthesized using a variety of processes, including chemical vapor deposition (CVD) mediated by metal catalyst nanoparticles (e.g. Fe, Co, Ni); high-pressure carbon monoxide disproportionation (HiPCO); and arc discharge, laser, or thermal ablation of graphite or amorphous carbon. CNTs may be suspended in a variety of liquid solvents or processed in solid or dry particulate state. As a raw material, CNTs may be filtered, purified, and selected for desirable properties such as length, chirality, diameter, and number of walls; furthermore they may be chemically processed to alter chemical, physical, and electrical properties before use. CNTs may be transferred to a substrate using a variety of methods; in the case of CNTs suspended in liquid solvent, they may be coated using e.g. spin coating, spray coating, dip coating, drop casting, or inkjet printing. As used herein, the term “about”, “around” “substantially” or “approximately” in relation to a number or a range of numbers will generally indicate that the number or range specified is preferred but that such a number may be varied to a certain extent without materially affecting the properties of the relevant material, composition, method or product. The skilled worker will typically be able to readily establish the extent by which such numbers may be varied without prejudicing the key advantages of the present invention. As a general guide, such numbers or the ends of such ranges referred to with such terms may be varied by ± 20% or ± 10%, preferably ± 5% and more preferably ±1%. A corresponding meaning may be attributed to compositions “consisting essentially of” certain components, which may include up to 20% or up to 10%, preferably up to 5% and most preferably up to 1% of other components in addition to those specified. Compositions described as comprising or consisting essentially of certain components include the compositions consisting solely of those components. However, ‘consisting of’ does not typically exclude the presence of doping compounds. An interlayer ‘consisting of’ graphene, for example, would not exclude an interlayer consisting of doped graphene. Examples Electronic Device 1 is an optoelectronic device, namely a UV LED, that is fabricated using MOCVD. The p-i-n junction of Electronic Device 1 is in line with that illustrated in Figure 1, and thus comprises a n-current spreader comprising Si- doped Alo.53Gao.47N (1500 nm); a n-contact layer comprising Si-doped Alo.48Gao.52N (400 nm); a multiple quantum well active region comprising a plurality of multiple quantum wells (Alo.4Gao.6N (2 nm)) and multiple quantum barriers (Alo.68Gao.32N (10 nm)); a p-type electron blocking layer comprising Mg-doped Alo.68Gao.32N (20-100 nm); a Mg-doped Alo.67Gao.33N layer (5-50 nm); a graphene interlayer (0-10 nm); and a metallic p-contact. All lll-N layers are grown epitaxially on an AIN / sapphire(0001) template (i.e. substrate) in an Aixtron close-coupled showerhead (CCS) reactor. Growth parameters for the respective layers include a setpoint temperature of 1520 degree Celsius for the AIN and undoped AIGaN layers, 1370 degree Celsius for the Si-doped AIGaN layers, gradings, MQW, EBL and p-GaN layers, as well as reactor pressure of 50 Torr for all mentioned layers. The p-contacting structure of Electronic Device 1 includes a highly Mg-doped Alo.67Gao.33N layer (10 nm); a graphene interlayer (2 nm); and a metallic p-contact disposed on the graphene layer. The highly Mg-doped p-AIGaN layer is epitaxially grown by MOCVD within 250 seconds using 1370 degree Celsius and 50 Torr as reactor parameters. The precursor flux values are 60 seem TMAI, 16 seem TMGa, 500 seem Cp2Mg, and 24 slm NH3. After the highly doped p-AIGaN layer is grown, an in-situ annealing step is performed for 10 min at 1015 degree Celsius (setpoint temperature) to activate Mg acceptors. After removing the wafer from the MOCVD reactor, the graphene interlayer is deposited and a chip process is performed by mesa etching and metal deposition, which includes Ti for the n-contact and Ni / Au for the p-contact.

Claims

1. A UV optoelectronic device comprising:(i) a p-i-n or p-n junction;(ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more;(iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and(iv) a metallic p-contact disposed on said interlayer.

2. A UV optoelectronic device as claimed in claim 1, wherein the p-AIGaN layer (ii) is of formula AlxGai.xN, wherein x is 0.5-0.75, preferably 0.55-0.7.

3. A UV optoelectronic device as claimed in any preceding claim, wherein the UV optoelectronic device is a UVC optoelectronic device, preferably a UVC LED.

4. A UV optoelectronic device as claimed in any preceding claim, wherein the p-i-n or p-n junction comprises at least one region or layer of AIGaN.

5. A UV optoelectronic device as claimed in any preceding claim, wherein the p-i-n or p-n junction comprises a n-type AIGaN region, a p-type AIGaN region and a light-emitting or light-absorbing region positioned between the n-type AIGaN region and the p-type AIGaN region.

6. A UV optoelectronic device as claimed in any preceding claim, wherein the p-AIGaN layer (ii) has a doping level of at least 1017 / cm3, preferably of at least 1018 / cm3, e.g. in the range of 1018 / cm3to 1021 / cm3.

7. A UV optoelectronic device as claimed in any preceding claim, wherein the p-AIGaN layer (ii) has a higher level of doping than the p-side of the p-n or p-i-n junction.

8. A UV optoelectronic device as claimed in any preceding claim, wherein the p-AIGaN layer (ii) has a thickness of 1 to 100 nm, preferably 5 to 50 nm.

9. A UV optoelectronic device as claimed in any preceding claim, wherein the interlayer is 10 nm thick or less.

10. A UV optoelectronic device as claimed in any preceding claim, wherein said two-dimensional material is selected from a graphitic material (e.g. graphene), silicene, hexagonal-BN (h-BN), M0S2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3 or NiTe2.

11. A UV optoelectronic device as claimed in any preceding claim, wherein the interlayer is selected from single or multi-layered graphene or amorphous carbon, especially single or multi-layered graphene.

12. A UV optoelectronic device as claimed in any preceding claim, wherein when said interlayer comprises a one-dimensional material, said interlayer is a film of nanotubes and / or fullerenes.

13. A UV optoelectronic device as claimed in any preceding claim, wherein the interlayer is undoped.

14. A UV optoelectronic device as claimed in any preceding claim, wherein at least one of (i) to (iv) is in the form of, or part of, a nanostructure, such as a nanowire or nanopyramid.

15. A UV optoelectronic device as claimed in any preceding claim, wherein at least one, preferably all of (i) to (iv) is / are transparent or substantially transparent to UV light.

16. A UV optoelectronic device as claimed in any preceding claim, further comprising a support, preferably an AIN and / or sapphire support, especially the (0001) face of sapphire.

17. A UV optoelectronic device as claimed in any preceding claim, wherein at least one of (i) to (iv) is planar, preferably all are planar.

18. A UV optoelectronic device as claimed in any preceding claim, wherein:(iv) is conformally formed on (iii)(iii) is conformally formed on (ii), and(ii) is conformally formed on (i).

19. A UV optoelectronic device as claimed in any preceding claim, comprising:an n-type AIGaN region comprising an n-contact;a p-type AIGaN region;- a light-emitting region or light-absorbing region positioned between the n-type AIGaN region and p-type AIGaN region;a p-AIGaN layer disposed on the p-type AIGaN region comprising a p-AIN layer having a doping level of 1016 / cm3or more;a graphene interlayer disposed on said p-AIGaN layer having a doping level of 1016 / cm3or more; and- a metallic p-contact disposed on said graphene interlayer.

20. A UV optoelectronic device comprising:(i) a p-i-n or p-n junction;(ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more;(iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer is a contact barrier regulator layer having a thickness of 10 nm or less; and(iv) a metallic p-contact disposed on said interlayer.

21. A multilayer p-contact structure for a UV optoelectronic device comprising:(ii) a p-AIGaN layer disposed on the p-side of the p-i-n or p-n junction having a doping level of 1016 / cm3or more;(iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and(iv) a metallic p-contact disposed on said interlayer.

22. A multilayer p-contact structure for a UV optoelectronic device comprising:(ii) a p-AIGaN layer having a doping level of 1016 / cm3or more;(iii) an interlayer disposed on said p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and(iv) a metallic p-contact disposed on said interlayer.

23. A process for preparing the UV optoelectronic device as claimed in any of claims 1-19, comprising the steps of:(a) forming a p-i-n or p-n junction;(b) forming a p-AIGaN layer on the p-side of the p-i-n or p-n junction wherein the p-AIGaN layer has a doping level of 1016 / cm3or more;(c) forming an interlayer on the p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and(d) forming a metallic p-contact on said interlayer.

24. A process for preparing the UV optoelectronic device as claimed in claim 20, comprising the steps of:(a) forming a p-i-n or p-n junction;(b) forming a p-AIGaN layer on the p-side of the p-i-n or p-n junction wherein the p-AIGaN layer has a doping level of 1016 / cm3or more;(c) forming an interlayer on the p-AIGaN layer, wherein said interlayer is a contact barrier regulator layer having a thickness of 10 nm or less; and(d) forming a metallic p-contact on said interlayer.

25. A process for preparing the multilayer p-contact structure as claimed in claim 21 or 22, comprising the steps of:(b) forming a p-AIGaN layer, optionally on the p-side of a p-i-n or p-n junction, wherein the p-AIGaN layer has a doping level of 1016 / cm3or more;(c) forming an interlayer on the p-AIGaN layer, wherein said interlayer comprises a one-dimensional material or is selected from a two-dimensional material, a conductive oxide or amorphous carbon; and(d) forming a metallic p-contact on said interlayer.Application No: GB2401669.3Examiner: Mr Steve MorganClaims searched: 1-19, 21-23 &25Date of search: 29 July 2024Patents Act 1977: Search Report under Section 17Documents considered to be relevant:Category Relevant to claims Identity of document and passage or figure of particular relevance X 1, 3-7, 11, 13-18,21-23 &25 US2013 / 0193408 A (SAMSUNG) See paragraphs 48 &50 X 1, 3-8, 10, 11, 13-18, 21-23 &25 CN104810455 A (NANJING UNI) See paragraphs 50-92 X 1, 3-7, 12-18,21-23 & 25 KR20140036716 A (LG INNOTEK) See paragraphs 35 &36 in particular X 1, 3-7, 9-18,21-23 &25 US2015 / 0171262 A (KOREA UNI) See paragraphs 53 &59 in particular X 1,3-7, 9-18,21-23 &25 CN104659178 A (WUHAN UNI) See paragraph 65 in particular v A 1,3,4, 6, 9, 13-18, 21-23 & 25 CN110890444 A (SHENZEN 3RD GEN) See paragraphs 33-61 A - JP2018022883 A (BOLB INC) See paragraphs 31 &32 A - CN115986022 A (JIANGXI MTC) See paragraph 55 in particularCategories:X Document indicating lack of novelty or inventive step A Document indicating technological background and / or state of the art. Y Document indicating lack of inventive step if P Document published on or after the declared priority date but combined with one or more other documents of same category'. before the filing date of this invention. & Member of the same patent family E Patent document published on or after, but with priority date earlier than, the filing date of this application.Field of Search:International Classification:Subclass Subgroup Valid From HO IL 0033 / 14 01 / 01 / 2010 HO IL 0033 / 32 01 / 01 / 2010 HO IL 0033 / 42 01 / 01 / 2010

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