Semiconductor device

Abstract

A semiconductor device comprising: a first transistor, the first transistor being a III-V high electron mobility transistor (HEMT) comprising a substrate 4 and a source terminal S; and a second transi

Description

FIELD OF INVENTION The present disclosure relates to semiconductor devices. Particularly, but not exclusively, the disclosure relates to a lll-V high electron mobility transistor (HEMT) comprising a substrate and a source terminal, the substrate being switchably connectable and disconnectable from the source terminal. BACKGROUND Gallium Nitride (GaN) is a wide band gap material with properties that make it a suitable candidate for use in several fields of application (e.g. radio-frequency electronics, opto-electronics, power electronics) which require solid-state devices. GaN technology allows transistors with high electron mobility and high saturation velocity to be designed. These properties of GaN have made it a good candidate for high-power and high-temperature microwave applications, for example radar and cellular communications systems. As systems expand in subscribers and desired capacity, interest in increasing their operating frequency and power has grown correspondingly. Higher frequency signals can carry more information (bandwidth) and allow for smaller antennas with very high gain. Additionally, GaN with its wide bandgap offers the potential for emitting light at higher frequencies for example the green, blue, violet, and ultraviolet portions of the electromagnetic spectrum. In the last decade, Gallium Nitride (GaN) has increasingly been considered as a very promising material for use in the field of power devices. The application areas range from portable consumer electronics, solar power inverters, electric vehicles, and power supplies. The wide band gap of the material (Eg=3.39 eV) results in high critical electric field (Ec=3.3 MV / cm) which can lead to the design of devices with a shorter drift region, and therefore lower on-state resistance if compared to a silicon-based device with the same breakdown voltage. The use of an Aluminium Gallium Nitride (AIGaN) / GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface where carriers can reach very high mobility (p=2000 cm2 / (Vs)) values. In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure, results in a high electron density in the 2DEG layer (e.g. 1xio13 cm-2). These properties allow the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. An extensive amount of research has focused on the development of power devices using AIGaN / GaN heterostructures. In GaN HEMTs, in off-state (when the 2DEG is depleted at least under the gate region), during the blocking mode there are three leakage contributions to the off-state current: (i) drain to source leakage (lateral leakage) mainly due to the punch-through leakage in the GaN layer under or through the depletion region formed below the gate, and (ii) drain to substrate leakage (vertical leakage) mainly due to holes from the drain metal or electrons emitted by impact ionization at the interface between the AIN nucleation layer and the substrate or (iii) drain to gate leakage. The drain to gate leakage is in general negligible compared to the first two. The off-state leakage is dominated at low voltages applied between the drain and source terminals by the lateral drain to source leakage, but at higher voltages by the vertical leakage (drain to substrate). In most cases, the vertical leakage limits both the rated voltage of the device and the breakdown voltage. Both leakage contributions grow substantially at high temperatures, but in most cases the limitation remains the vertical leakage. As an example, for a pGaN gate HEMT rated at 650 V, the vertical leakage can become higher than the lateral leakage, at a voltage level in the range of 400V to 600V. SUMMARY It is an object of the present invention to supress or diminish the vertical leakage i.e. minimise the vertical leakage) and as a result increase both the rated voltage and the breakdown voltage of the device. Accordingly, the present disclosure provides a lll-V power semiconductor device that can exhibit improved breakdown voltage by limiting the vertical leakage within the device. Effective isolation of the substrate from the ground can reduce the leakage current between the drain and the substrate, resulting in a better breakdown voltage. However total isolation, without a potential control of the substrate terminal may lead to floating effects, which can affect both the preparation of the power device but also any other low power devices that may be monolithically integrated with the high voltage switch. In the present disclosure, a way to limit the leakage through the substrate but also to control the potential that the substrate terminal can pick up during different modes of operation of the switch is proposed. The present disclosure is applicable to lll-V power devices such as high electron mobility transistors (HEMTs). According to the present disclosure, a substrate terminal can be selectively coupled (or operatively connected) to the source of the power device (bringing the substrate potential to ground or a threshold voltage above ground, or a low voltage when compared to the drain voltage) when the power device is in on-state and decoupled (or operatively disconnected) from the source when the power device is in the off-state such as to reduce the off-state leakage through the substrate terminal. Described herein is a semiconductor device comprising: a first transistor, the first transistor being a lll-V high electron mobility transistor (HEMT) comprising a substrate and a source terminal; and a second transistor, the second transistor being configured selectably to: operatively connect the substrate to the source terminal of the first transistor when the first transistor is in an on-state (e.g. when a gate of the first transistor is on, or when the gate voltage of the first transistor is HIGH, i.e. when the gate voltage of the first transistor is at or above a threshold voltage); and operatively disconnect the substrate from the source terminal of the first transistor when the first transistor is in an off-state (e.g. when the gate of the first transistor is off, or when the gate voltage of the first transistor is LOW, i.e. when the gate voltage of the first transistor is below the threshold voltage). As described herein, devices according to the present disclosure may exhibit reduced current leakage from the drain to the substrate. It will be understood that the substrate may be connected in series with the second transistor. The second transistor may be a low-power transistor, e.g. a low-power HEMT. For example, a drain (e.g. a drain terminal) of the second transistor may be operatively connected to the substrate (e.g. a substrate terminal) of the first transistor. A source (e.g. a source terminal) of the second transistor may be operatively connected to a source (e.g. a source terminal) of the first transistor. In some examples, the first transistor and the second transistor may share a common source (and source terminal). In some examples, a gate terminal of the first transistor (referred to herein as a first gate terminal) and a gate terminal of the second transistor (referred to herein as a second gate terminal) are configured to be driven by a same driving signal. That is, the gate terminal of the first transistor and the gate terminal of the second transistor may be connected together. The semiconductor device may comprise a capacitor arranged in parallel with the second transistor. Advantageously, capacitively connecting the substrate to the source terminal, by arranging a capacitor in parallel with the second transistor, may enable control of the potential at the substrate. The second transistor may be monolithically integrated with the first transistor. The semiconductor device may comprise a third transistor connected between the substrate and the drain terminal of the first transistor. The third transistor may be an enhancement mode HEMT. In some examples, the second transistor is an enhancement mode HEMT. The third transistor may be a depletion mode HEMT. The second transistor and the third transistor may be connected in series in a Cascode configuration. The connection of the substrate to the Cascode may limit the substrate voltage to a threshold voltage of the depletion mode HEMT (third transistor). The third transistor may be monolithically integrated with the first transistor and / or the second transistor. In some examples, the semiconductor device comprises a diode connected between the substrate and the drain terminal of the first transistor. In some examples, the semiconductor device comprises a HEMT configured to behave as a diode connected between the substrate and the drain terminal of the transistor. For example, the HEMT configured to behave as a diode may comprise a gate-source connected enhancement mode HEMT. The diode, or HEMT configured as a diode, may serve to govern the potential between the substrate and the drain. The diode or HEMT configured as a diode may be monolithically integrated with the first transistor and / or the second transistor. In some examples, the first transistor is a bidirectional Ill-V HEMT. The bidirectional III-V HEMT may comprise an additional source terminal, also referred to herein as a second source terminal. The semiconductor device may comprise a fourth transistor configured selectably to: operatively connect the substrate to a second source terminal of the first transistor when a second gate of the first transistor is on; and operatively disconnect the substrate from the second source terminal of the first transistor when the second gate of the first transistor is off. In a particular example described herein, a semiconductor device may comprise: a first transistor, the first transistor being a bidirectional lll-V HEMT, the first transistor comprising a substrate, a first source terminal, a second source terminal, a first gate, and a second gate; a second transistor; and a fourth transistor; wherein the second transistor is configured selectably to: operatively connect the substrate to the first source terminal of the first transistor when the first gate of the first transistor is on (or when the gate voltage of the first gate of the first transistor is HIGH, i.e. when the gate voltage of the first gate of the first transistor is at or above a first threshold voltage); and operatively disconnect the substrate from the first source terminal of the first transistor when the first gate of the first transistor is off (or when the gate voltage of the first gate of the first transistor is LOW, i.e. when the gate voltage of the first gate of the first transistor is below the first threshold voltage); and wherein the fourth transistor is configured selectably to: operatively connect the substrate to the second source terminal of the first transistor when the second gate of the first transistor is on (or when the gate voltage of the second gate of the first transistor is HIGH, i.e. when the gate voltage of the second gate of the first transistor is at or above a second threshold voltage); and operatively disconnect the substrate from the second source terminal of the first transistor when the second gate of the first transistor is off (or when gate voltage of the second gate of the first transistor is LOW, i.e. when the gate voltage of the second gate of the first transistor is below the second threshold voltage). The substrate may be connected in series with the second transistor, and with the fourth transistor. For example, the second and fourth transistors may be low-power transistors, e.g. low-power HEMTs. For example, a drain (e.g. a drain terminal) of the second transistor may be operatively connected to the substrate (e.g. a substrate terminal) of the first transistor. A source (e.g. a source terminal) of the second transistor may be operatively connected to the first source terminal of the first transistor. In some examples, the first transistor and the second transistor may share a common source (i.e. the first source terminal). For example, a drain (e.g. a drain terminal) of the fourth transistor may be operatively connected to the substrate (e.g. the substrate terminal) of the first transistor. A source (e.g. a source terminal) of the fourth transistor may be operatively connected to the second source terminal of the first transistor. In some examples, the first transistor and the fourth transistor may share a common source (i.e. the second source terminal). In some examples, the first gate of the first transistor and a gate of the second transistor are configured to be driven by a first driving signal. In some examples, the second gate of the first transistor and a gate of the fourth transistor are configured to be driven by a second driving signal. In some examples, the semiconductor device comprises a first capacitor arranged in parallel with the second transistor. In some examples, the semiconductor device comprises a second capacitor arranged in parallel with the fourth transistor. Advantageously, as described herein, the capacitor(s) may enable control of the potential at the substrate. The second transistor and the fourth transistor may be monolithically integrated with the first transistor. In some examples, the semiconductor device comprises a third transistor connected between the substrate and the second source terminal of the first transistor. In some examples, the semiconductor device comprises a fifth transistor connected between the substrate and the first source terminal of the first transistor. In some examples, the second and fourth transistors are enhancement mode HEMTs, and the third and fifth transistors are depletion mode HEMTs. In some examples, the second transistor and the third transistor are connected in series in a first Cascode configuration, and the fourth transistor and the fifth transistor are connected in series in a second Cascode configuration. As described herein, the connection of the substrate to the Cascode(s) may limit the substrate voltage to a threshold voltage of the depletion mode HEMT(s). The third transistor and the fifth transistor may be monolithically integrated with the first transistor. The third transistor and the fifth transistor may be monolithically integrated with the second transistor. The third transistor and the fifth transistor may be monolithically integrated with the fourth transistor. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described by way of example only with reference to the following drawings: Figure 1 illustrates an example of a lll-V HEMT switch having a substrate connected to a source; Figure 2 illustrates an l-V curve characteristic of the switch illustrated in Figure 1; Figure 3 (left) illustrates a conventional lll-V HEMT comprising a semiconductor substrate terminal, and Figure 3 (right) illustrates an equivalent schematic of the same device; Figure 4 illustrates an example of a semiconductor device comprising a first transistor and a second transistor according to the present disclosure; Figure 5 illustrates an example of a semiconductor device according to the present disclosure wherein the second transistor is monolithically integrated with the first transistor, and wherein the first transistor and the second transistor share a common source; Figure 6 illustrates a schematic diagram of examples according to the present disclosure wherein the second transistor is an enhancement mode HEMT; Figure 7 illustrates a schematic diagram of examples according to the present disclosure comprising a capacitor connected in parallel with the second transistor; Figure 8 illustrates an example according to the present disclosure comprising a diode connected in an anti-parallel configuration between the drain and the substrate of the first transistor; Figure 9 illustrates an example according to the present disclosure comprising a gatesource connected enhancement mode HEMT connected in an anti-parallel configuration between the drain and the substrate of the first transistor; Figure 10 illustrates an example according to the present disclosure wherein a gate of an enhancement-mode HEMT is connected to the source of the first transistor; Figure 11 illustrates an example according to the present disclosure wherein the substrate is connected to a Cascode switch; Figure 12 illustrates an example of a semiconductor device according to the present disclosure comprising a bidirectional lll-V HEMT; Figure 13 illustrates an equivalent schematic of the semiconductor device illustrated in Figure 12; Figure 14 illustrates an example of a semiconductor device according to the present disclosure comprising a bidirectional lll-V HEMT comprising capacitors in parallel with the low-power transistors; and Figure 15 illustrates an example of a semiconductor device according to the present disclosure comprising a bidirectional lll-V HEMT, wherein the substrate is connected through two Cascode switches between the sources and controlled by respective gates. DETAILED DESCRIPTION Figure 1 illustrates an example of a lll-V high electron mobility transistor (HEMT) switch (e.g. GaN HEMT) comprising a drain 8 (with a drain terminal D), a source 7 (with a source terminal S), and a gate 6 (with a gate terminal G). The gate 6 may comprise a pGaN region 5. The HEMT switch comprises a substrate 4, and may comprise one or more transition or nucleation layers 3 depending on the material of the substrate 4. For example, the substrate 4 may comprise silicon or silicon carbide. While most of the examples described herein refers to a silicon substrate, it will be understood that the present disclosure is applicable to other semiconductors as well. As shown in Figure 1, the HEMT switch may also comprise a substrate metallization or terminal 9, formed on the substrate 4. In the example of Figure 1, a region 1 of lll-V semiconductor material comprising aluminium (e.g. AIGaN) is formed on top of a layer 2 of GaN to form a heterostructure at the interface, resulting in the formation of a two-dimensional electron gas (2DEG) 12. The switch experiences two types of leakages in the off-state: (i) drain 8 to source 7 leakage (lateral leakage) mainly due to the punch-through leakage in the GaN layer 2 under or through the depletion region formed below the gate 6, and (ii) drain 8 to substrate 4 leakage (vertical leakage) mainly due to holes from the drain metal or electrons emitted by impact ionization at the interface between the nucleation layer 3 and the substrate 4. A third path for leakage (not shown) from drain 8 to gate 6 is in general negligible compared to the other contributions. Figure 2 illustrates an l-V curve characteristic of the switch illustrated in Figure 1. As can be seen from the characteristic, the leakage is dominated at low voltages by the lateral leakage (i), but at higher voltages by the vertical leakage (ii). In most cases, the vertical leakage limits both the rated voltage of the device and the breakdown voltage. Both leakage contributions grow substantially at high temperatures, but the limitation remains the vertical leakage. As an example for a pGaN gate HEMT rated at 650 V, the vertical leakage can become higher than the lateral leakage at voltage level within a range of 400V to 600V. Figure 3 (left) illustrates a conventional lll-V HEMT comprising a semiconductor substrate terminal. Traditionally, the substrate is connected to the source as shown in an equivalent schematic of the device (right). Figure 4 illustrates an example according to the present disclosure. A semiconductor device comprises a first transistor 101 (e.g. a lll-V HEMT, also referred to as a “power device”) and a second transistor 102. A substrate 4 the first transistor 101 is connected to the source 7 through a low-power transistor (“second transistor”) 102. Preferably, a gate 6 of the first transistor 101 and a gate of the second transistor that 102 are drivable by a same driving signal. That is to say the gate terminal G of the first transistor 101 and the gate terminal of the second transistor 102 are connected together. According to the example illustrated in Figure 4, a lll-V power device (first transistor 101) with a substrate terminal is coupled to the source terminal S or has a same potential as the source terminal (slightly above that of the source terminal) when the power device is in on-state and is decoupled from source terminal S or kept to a capacitively coupled potential when the first transistor 101 is in the off-state. When the gate voltage is HIGH and the first transistor 101 is turned on, the second transistor 102 is also turned ON and the substrate potential becomes very close to the source voltage which for a low-side device is connected to ground. As the second transistor 102 is low power and may be formed through a single finger in the die, it is expected to have a very insignificant leakage when compared to the drain-substrate leakage of a prior art device that has the substrate connected to source. In the off-state, the substrate 4 is capacitively picking up a potential. In this example, a low capacitance between the substrate 4 and the source terminal S is preferable to ensure that the substrate 4 remains at low voltage (preferably below 100 V). According to the example of Figure 4, the substrate terminal is connected to the source potential (slightly above the source potential) during the steady-state of the device and should not take current. The current leakage occurs in the off-state of the device. When the device is switched off, then the second transistor 102 is also turned off decoupling the substrate from the source and making it float reducing the leakage. Effectively the substrate 4 is in series with the second transistor 102, which limits the leakage current through the second transistor 102. In this example, the gate of the low power transistor 102 is directly connected to the gate of the power HEMT 101. However, it may be connected to an independent driving signal and its switching may be controlled based on the application. The second transistor 102 may be a lll-V group HEMT or any other semiconductor high-voltage low-power transistor. The first transistor (power HEMT) 101 illustrated here is a p-GaN gate enhancement mode HEMT. It may be understood that this is only an example and the HEMT 101 may be any other high power lll-V group HEMT device with a different gate architecture or materials. It will be understood that coupling or connecting the substrate to the source, as described herein, may mean connecting the substrate to the source through a very low on-state resistance between the drain-source terminals of the second transistor. Figure 5 illustrates a specific example according to the present disclosure wherein the second transistor 102 is a lll-V group transistor and is monolithically integrated with the first transistor 101 on a same substrate 4. The source is shared by both the transistors and the drain D2 of the second transistor 102 is connected to the substrate 4. The gates of both the transistors are connected as described in relation to Figure 4. Alternatively, the gates of the second transistor 102 and the first transistor 101 may be controlled separately (not shown). The substrate 4 is common to both the first (high voltage) transistor 101 and the second (low-power) transistor 102. The second transistor 102 may still have some high voltage capability, as it may need to withstand a relatively high voltage when the first transistor 101 is blocking the full voltage. Figure 6 illustrates an equivalent schematic of some examples according to the present disclosure wherein the second transistor 102 is an enhancement mode HEMT (HEMT 2), with a drain D2 connected to the substrate. Here, the gates are open to be connected to a single control terminal or different control terminals. The second transistor substrate may be physically the same (or electrically connected together) to that of first transistor 101. Figure 7 illustrates another example according to the present disclosure wherein a capacitor C1 may be connected in parallel to the second transistor 102. Capacitively connecting the substrate to the source can enable a controlled potential at the substrate that is a function of the capacitance. The smaller the capacitance C1 the closer the potential of the substrate is to the source in the off-state. In the off-state, during a steady-state when the capacitor is charged, it can help to determine the potential of the substrate. The capacitor C1 is discharged (to zero or close to zero voltage drop across it) when the second transistor 102 is in the on-state. As shown in Figure 7, the drain-to-substrate capacitance is denoted as CdSUb. Figure 8 illustrates a further example according to the present disclosure wherein a diode 103a (e.g. a high-voltage diode) may be connected in an anti-parallel configuration between the drain and the substrate of the first transistor 101. The potential between the substrate to the drain would be governed by the voltage sharing between the high-voltage diode 103a and the low power transistor 102. When the gate G is ON, the second transistor (denoted as HEMT 2) will be turned on, connecting the drain D2 of the second transistor to the source S of the first transistor, effectively configuring the high-voltage diode 103a as a body diode of the first transistor. The diode 103a can be external or monolithically integrated with the first transistor. The diode 103a could be made from a HEMT transistor by short-circuiting its gate to one of the main terminals (source or drain). This is known as a HEMT configured in a diode configuration, or configured to behave as a diode (e.g. as shown in Figure 9). Figure 9 illustrates another example of the implementation shown in Figure 8 wherein the high-voltage diode 103a may be replaced by a gate-source connected high-voltage enhancement mode HEMT 103b. Figure 10 illustrates another example according to the present disclosure wherein the gate of a high-voltage enhancement-mode (e-mode) HEMT 104 (or E-HEMT) is connected to the source of first transistor 101. The e-mode HEMT 104 is always off as its gate potential is below its source potential. The maximum voltage at the drain D2 of the second transistor is limited by the breakdown of the gate-source structure of the e-mode HEMT. Figure 11 illustrates another example according to the present disclosure wherein the substrate is connected to the mid-point of a Cascode switch comprising an e-mode low power HEMT, corresponding to the second HEMT 102, connected to a low-power, high voltage depletion mode (d-mode) HEMT (or D-HEMT) 105. The d-mode HEMT may be a Schottky gate device or may have a p+ island gate of the kind described and illustrated in US11081578, the contents of which is hereby incorporated by reference. The potential of the d-mode HEMT 105 is tied to the breakdown voltage of the second HEMT 102. The substrate connection to the Cascode ensures that the substrate cannot pick up a voltage beyond the threshold voltage of the d-mode HEMT 105. The threshold voltage of a p+ island d-mode HEMT is typically in the range of -20 to -40 V, therefore the potential at the substrate (same as the potential of the source of the d-mode HEMT 105) cannot rise beyond the absolute value of the threshold voltage (in the range of 20V to 40V), as this will turn-off the d-mode HEMT 105. Therefore, effectively the potential of the substrate can be modulated between 0V (or close to zero volts) in the on-state (when both the power transistor and the Cascode are in on-state) to a level between 20V and 40V in the off-state without significant leakage. The d-mode HEMT 105 may introduce some leakage itself, however when its source potential reaches the threshold level, the leakage would be largely insignificant. The d-mode HEMT 105 and the second HEMT 102 are relatively low-current low-power devices when compared to the high power switch. Their on-state current capability may be less or much less than 10 times the main power switch and hence, their leakages are minimal in comparison to the leakage through the substrate of a prior-art HEMT. The Cascode structure may be monolithically integrated with the power switch. Figure 12 illustrates an example of a semiconductor device according to the present disclosure comprising a bidirectional lll-V HEMT 201, also referred to as a bidirectional switch. The bidirectional lll-V HEMT 201 shown in Figure 12 has a common drain architecture with the potentials at gates G1 and G2 modulated against the source S1, S2 potentials, respectively. High-voltage low-power transistors 202, 203 may be operatively connected between the substrate 4 and each source S1 and S2, respectively, to provide selectable switching similarly to the previously described examples. The transistor 202, 203 connected to each source would be driven through the respective gate signal or, alternatively, through an independent driving signal. An equivalent schematic of the device illustrated in Figure 12 is illustrated in Figure 13. As described herein, the transistors 202, 203 may be monolithically integrated with the bidirectional HEMT and may be formed through one finger each as they are low power devices. Figure 14 illustrates an example of the bidirectional switch according to the present disclosure with additional capacitances, similar to the example illustrated in Figure 7, comprising capacitors C2, C3 in parallel with the low-power transistors 202, 203. Capacitively connecting the substrate to either source, S1, S2 can enable a controlled potential at the substrate that is a function of such capacitances. Figure 15 illustrates a further example of the bidirectional switch according to the present disclosure, wherein the substrate is connected through two Cascode switches between sources S1, S2 and controlled by gates G1, G2 respectively. This example is similar to the example illustrated in Figure 11, extended to a bidirectional switch. It will also be appreciated that terms such as "top" and "bottom", "above" and "below", "lateral" and "vertical", and “under” and “over”, “front” and “behind”, “underlying”, etc. may be used in this specification by convention and that no particular physical orientation of the device as a whole is implied. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

1. A semiconductor device comprising:a first transistor, the first transistor being a lll-V high electron mobility transistor (HEMT) comprising a substrate and a source terminal; anda second transistor, the second transistor being configured selectably to: operatively connect the substrate to the source terminal of the first transistor when the first transistor is in an on-state; andoperatively disconnect the substrate from the source terminal of the first transistor when the first transistor is in an off-state.

2. A semiconductor device according to claim 1, wherein the first transistor comprises a first gate terminal, and wherein the second transistor comprises a second gate terminal; andwherein the first gate terminal and the second gate terminal are configured to be driven by a same driving signal.

3. A semiconductor device according to claim 1 or 2, comprising a capacitor arranged in parallel with the second transistor.

4. A semiconductor device according to any one of the preceding claims, comprising a third transistor connected between the substrate and a drain terminal of the first transistor.

5. A semiconductor device according to claim 4, wherein the third transistor is an enhancement mode HEMT.

6. A semiconductor device according to claim 4, wherein the second transistor is an enhancement mode HEMT and the third transistor is a depletion mode HEMT.

7. A semiconductor device according to claim 6, wherein the second transistor and the third transistor are connected in series in a Cascode configuration.

8. A semiconductor device according to any one of the preceding claims, comprising a diode, connected between the substrate and a drain terminal of the first transistor.

9. A semiconductor device according to any one of the preceding claims, comprising a HEMT configured as a diode connected between the substrate and a drain terminal of the first transistor.

10. A semiconductor device according to any one of the preceding claims, wherein the second transistor is monolithically integrated with the first transistor.

11. A semiconductor device according to any one of claims 4 to 7, wherein the third transistor is monolithically integrated with the first transistor and / or the second transistor.

12. A semiconductor device comprising:a first transistor, the first transistor being a bidirectional 11 l-V HEMT, the first transistor comprising a substrate, a first source terminal, a second source terminal, a first gate, and a second gate;a second transistor; anda fourth transistor;wherein the second transistor is configured selectably to:operatively connect the substrate to the first source terminal of the first transistor when the first gate of the first transistor is on; andoperatively disconnect the substrate from the first source terminal of the first transistor when the first gate of the first transistor is off; andwherein the fourth transistor is configured selectably to:operatively connect the substrate to the second source terminal of the first transistor when the second gate of the first transistor is on; andoperatively disconnect the substrate from the second source terminal of the first transistor when the second gate of the first transistor is off.

13. A semiconductor device according to claim 12, wherein the first gate of the first transistor and a gate of the second transistor are configured to be driven by a first driving signal.

14. A semiconductor device according to claim 12 or 13, wherein the second gate of the first transistor and a gate of the fourth transistor are configured to be driven by a second driving signal.

15. A semiconductor device according to any one of claims 12 to 14, comprising: a first capacitor arranged in parallel with the second transistor; and / or a second capacitor arranged in parallel with the fourth transistor.

16. A semiconductor device according to any one of claims 12 to 15, further comprising:a third transistor connected between the substrate and the second source terminal of the first transistor; anda fifth transistor connected between the substrate and the first source terminal of the first transistor.

17. A semiconductor device according to claim 16, wherein the second and fourth transistors are enhancement mode HEMTs, and wherein the third and fifth transistors are depletion mode HEMTs.

18. A semiconductor device according to claim 17, wherein the second transistor and the third transistor are connected in series in a first Cascode configuration, and wherein the fourth transistor and the fifth transistor are connected in series in a second Cascode configuration.

19. A semiconductor device according to any one of claims 12 to 18, wherein the second transistor and the fourth transistor are monolithically integrated with the first transistor.

20. A semiconductor device according to any one of claims 16 to 18, wherein the third transistor and the fifth transistor are monolithically integrated with the first transistor, the second transistor, and the fourth transistor.

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