Semiconductor structures

Abstract

Semiconductor structure 300 (e.g., a HEMT) comprising substrate 110 (e.g., Si or SiC), first semiconductor layer 115, second semiconductor layer 120 and an interlayer 315 between the first semiconduct

Description

Technical field The present application relates to a semiconductor structure. The present application also relates to a semiconductor device, a radio frequency (RF) module, and electronic device and a method for forming a semiconductor structure. Background Forming semiconductor devices from lll-N semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, lll-N semiconductor materials, such as GaN, possess desirable electronic and photonic properties, outperforming Si in many aspects. The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from lll-N materials. lll-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of lll-N HEMTs has therefore found use in power and radio frequency (RF) communications applications. HEMTs exhibit high electron mobility due to the formation of a two-dimensional electron gas (2DEG) in the channel layer of the HEMT. Typically, an AIGaN barrier layer is formed over a GaN channel layer. The AIGaN barrier layer induces the formation of a 2DEG in the GaN channel layer. The formation of a HEMT typically involves the epitaxial growth of lll-N semiconductor layers on a substrate. For example, a lll-N barrier layer and lll-N channel layer are formed on the substrate using an epitaxial growth technique, such as molecular beam epitaxy (MBE) or metal organic chemical vapour deposition (MOCVD). However, the epitaxial growth of the lll-N layers is typically a heteroepitaxial process where the substrate comprises a material, which is not a lll-N semiconductor. Common substrates for the epitaxial growth of lll-N HEMT layers include Si and SiC because these substrates are widely available in larger diameters than lll-N substrates. The heteroepitaxial nature of the formation of the lll-N channel layer and lll-N barrier layer means that these layers are not formed directly on the substrate. If they were, the lll-N channel layer and lll-N barrier layer would be of poor quality and contain many defects. Instead, typically nucleation and buffer layers are first formed on the substrate. The nucleation and buffer layers provide a transition between the substrate, and the III-N channel layer and lll-N barrier layer, which minimise defects and improve the formation of the lll-N channel layer and lll-N barrier layer. Epitaxial processes for the formation of nucleation and buffer layers have developed to produce high quality lll-N HEMTs. However, the increasing demands of RF communication systems mean that improvements in this technology are desired. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure. The semiconductor structure comprises: a substrate; a first semiconductor layer over the substrate; a second semiconductor layer over the first layer; and an interlayer between the first semiconductor layer and the second semiconductor layer, wherein the interlayer comprises a surfactant. According to a second aspect there is provided a semiconductor device comprising the semiconductor structure according to the first aspect. According to a third aspect there is provided a radio frequency module comprising the semiconductor device according to the second aspect. According to a fourth aspect there is provided an electronic device comprising the radio frequency module according to the third aspect. According to a fifth aspect there is provided a method of forming a semiconductor structure comprising: forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming an interlayer between the first semiconductor layer and the second semiconductor layer, wherein interlayer comprises a surfactant. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a semiconductor structure; Figure 2 is another example of a semiconductor structure; Figure 3 is another example of a semiconductor structure; Figure 4 is another example of a semiconductor structure; Figure 5 is another example of a semiconductor structure; Figure 6 is another example of a semiconductor structure; Figures 7a and 7b are examples of atomic force microscopy (AFM) results; Figure 8 is a flow illustrating process steps in a method. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out-of-plane is used to mean perpendicular to the surface of the substrate. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), silicon carbide (SiC), sapphire (AI2O3), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100 crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional techniques suffer from. Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals. Figure 1 is an example of a HEMT 100. HEMT 100 comprises a substrate 110 and a buffer layer 120, a channel layer 130 and a barrier layer 140 formed on the substrate 110. The buffer layer 120, channel layer 130 and barrier layer 140 comprise semiconductor material. In one example, the buffer layer 120, channel layer 130 and barrier layer 140 comprise lll-N semiconductor material. However, in other examples, the buffer layer 120, channel layer 130 and barrier layer 140 comprise other lll-V materials such as GaAs-based materials. The buffer layer 120, channel layer 130 and barrier layer 140 may thus be epitaxially grown on the substrate 110. In some examples, the substrate 110 may comprise a material for the epitaxial growth of semiconductor material thereon, such as, Si, SiC or Sapphire. The nucleation layer 115 is configured to transition from the substrate 110 to the semiconductor materials forming the HEMT 100. In some examples, the nucleation layer 115 may comprise AIN. The buffer layer 120, is configured to eliminate defects and provide isolation between the substrate 110 and the channel layer 130 above the buffer layer 120. In some examples, the buffer layer 120 may comprise GaN. Channel layer 130 provides the channel in the HEMT for charge carriers to flow. A 2-dimensional electron gas (2DEG) 132 is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The 2DEG 132 is formed in the channel layer 130 due to a polarization discontinuity between the barrier layer 140 and the channel layer 130. In some examples, the channel layer 130 comprises GaN and the barrier layer 140 comprises AIGaN. HEMT 100 further comprises a source electrode 150, a drain electrode 160 and a gate electrode 170. As illustrated in Figure 1, the 2DEG 132 is continuous between the source electrode 150 and the drain electrode 160. As such, with no bias voltage applied to the gate electrode 170, the formation of the 2DEG 132 results in current flow between the source electrode 150 and drain electrode 160. A negative bias voltage is applied to the gate electrode 170 to turn the HEMT 100 to the ‘off’ state where the formation of the 2DEG is interrupted. As described above, the nucleation layer 115 and buffer layer 120 are included to minimize defects and result in the high-quality epitaxial formation of the channel layer 130 and barrier layer 140. In particular, the nucleation layer 115 and buffer layer 120 are configured to comprise high crystallinity and provide smooth surface for the formation of the channel layer 130 and barrier layer 140, thereon. Conventionally, to form a surface for the channel layer 130 and barrier layer 140, which has high crystallinity and a smooth surface, a thick buffer layer 120 is formed. The buffer layer 120 may comprise a thickness of 800 nm or more. At this thickness, defects present at the substrate 110 surface are effectively smoothed out and thus the upper surface of the buffer layer 120 provides an appropriate platform for the growth of the channel layer 130 and barrier layer 140 thereon. Increasingly, however, it is desirable to reduce the thickness of the buffer layer 120. The buffer layer 120 is commonly formed from GaN or AIGaN. These materials have poor thermal conductivity and therefore a thick buffer layer 120 formed from GaN or AIGaN can lead to a HEMT with poor thermal performance. There is a trend in the HEMT industry to reduce the thickness of the buffer layer 120 to 250 nm or less. However, reducing the thickness of the buffer layer 120 leads to a buffer layer 120 surface with reduced crystal quality and a rougher surface. This, in turn, leads to the formation of a poor-quality channel layer 130 and barrier layer 140 with poor electrical and physical properties. In particular, the surface properties of the buffer layer 120 have a large impact on the formation of the channel layer 130 and barrier layer 140. It is desirable for the buffer layer 120 to comprise a route mean square (RMS) surface roughness of less than 1 nm. However, buffer layers 120 with a thickness of 250 nm or less commonly comprise a RMS surface roughness of greater than 2 nm, for example, up to about 2.8 nm. Additionally, the buffer layer 120 surface commonly includes 3D islands. The 3D islands result from a combination of gas phase pre-reactions resulting in the formation of AIN particles and surface energy differences between the substrate 110 and nucleation layer 115. Growth of the channel layer 130 and barrier layer 140 on the islands greatly reduces the quality of the channel layer 130 and barrier layer 140. The islands are typically formed at the upper surface of the nucleation layer 115. A thicker buffer layer 120 can cause the islands to eventually coalesce resulting a smooth surface for the formation of the channel layer 130 and barrier layer 140. A thicker buffer layer 120 can thus effectively cover the islands with a smooth surface. However, for a thinner buffer layer 120, the presence of the islands transitions from the nucleation layer 115 surface to the buffer layer 120 surface. Examples according to the present disclosure provide an interlayer between the nucleation layer 115 and the buffer layer 120. The interlayer comprises a surfactant. The surfactant is configured to result in a buffer layer with an improved surface. The improved surface results in a smoother buffer layer 120 which does not comprise the formation of 3D islands, and results in the improved formation of the channel layer 130 and barrier layer 140. As will be described in more detail below, the surfactant improves the lateral mobility of atoms deposited on to the epitaxial growth surface. In some examples, the surfactant is deposited with the interlayer material which improves the surface morphology and crystal quality of the epitaxially formed interlayer. The buffer layer may be deposited on the interlayer to result in an improved buffer layer with a smooth surface and high crystallinity. In some examples, the interlayer may be deposited on the nucleation layer and a transition layer may be deposited on the interlayer, between the interlayer and the buffer layer. As the transition layer is deposited, the surfactant present in the interlayer may aid the deposition of the transition layer to result in a transition layer with a smooth surface and high crystallinity. The buffer layer may thus be formed on the transition layer, where the buffer layer additionally comprises a smooth surface and high crystallinity. Figure 2 is an example of a HEMT 200. HEMT 200 comprises corresponding elements to HEMT 100. HEMT 200 further comprises an interlayer 215 between the nucleation layer 115 and the buffer layer 120. In some examples, the nucleation layer 115 comprises AIN and the buffer layer 120 comprises (AI)GaN. In some examples, the interlayer 215 may comprise AIN and a surfactant. In some examples, as Al and N atoms are epitaxially deposited on the nucleation layer 115 to form the interlayer 215 the surfactant may also be released into the reactor. The surfactant improves the lateral mobility of the Al and N atoms deposited on to the nucleation layer 115, which in turn, improves the surface morphology and crystal quality of the interlayer 215. In particular, the interlayer 215 comprises a smooth surface. The interlayer 215 thus provides a smooth and high-quality surface for the formation of the buffer layer 120 thereon. In some examples, the surfactant may thus be incorporated into the interlayer 215. Although the surfactant is primarily used to promote the lateral mobility of the materials used to form the interlayer 215, the surfactant may itself may also be incorporated into the interlayer215. In some examples, the interlayer215 comprises a lll-V semiconductor material and the surfactant comprises a group III or group V element. For example, the surfactant may comprise In, Sb or Bi. In some examples, the surfactant may comprise less than 3% of the group III elements of the lll-V semiconductor interlayer 215. In some examples, the surfactant may comprise less than 3% of the group V elements of the III-V semiconductor interlayer 215. In some examples, the surfactant may comprise less than 1% of the group III elements of the lll-V semiconductor interlayer 215. In some examples, the surfactant may comprise less than 1% of the group V elements of the III-V semiconductor interlayer 215. In some examples, the surfactant may comprise In. In can promote the lateral mobility of some lll-V semiconductor materials such as Al and N. In such examples, Al and N may thus be deposited on to the nucleation layer 115 to form AIN and In may be used as a surfactant in the formation of the interlayer 215. The In surfactant may be present in the interlayer 215. As such the interlayer215 may form comprising InAIN. In some examples, the interlayer 215 may comprise lnxAli.xN, where x <0.03. In some examples, the interlayer 215 may comprise InxAli.xN, where x <0.02. In some examples, the interlayer 215 may comprise lnxAli.xN, where x <0.01. In some examples, the interlayer 215 may comprise a thickness between 0.5 nm and 20 nm. In such examples, the interlayer 215 may thus be relatively thin. For example, the nucleation layer 115 may comprise a thickness between 10 and 1000 nm. In some examples, the nucleation layer 115 may thus be thicker than the interlayer 215. In some examples, interlayer 215 may thus be a thin layer which is configured to improve surface morphology of the buffer layer 120 grown on the nucleation layer 115. For example, the nucleation layer 115 may comprise AIN and the interlayer 215 may comprise a thin InAIN formed on the AIN nucleation layer 115. The buffer layer 120 may comprise a thickness of between 25 nm to 250 nm. In some examples, the interlayer 115 may thus comprise a thin layer between the nucleation layer 115 and buffer layer 120, which may effectively cap the nucleation layer 115. As described above, in some examples, the nucleation layer 115, interlayer 215 and buffer layer 120 may be formed by MOCVD on the substrate 110. As further described above, in some examples, the nucleation layer 115 comprises AIN, the interlayer 215 comprises InAIN and the buffer layer 120 comprises GaN. In some examples, the nucleation layer 115 may be formed with a high temperature. In some examples, the nucleation layer 115 may be formed with a temperature of between about 1000-1200 °C. In some examples, forming the nucleation layer 115 at a high temperature may enable materials, such as AIN, to nucleate on a substrate such as Si orSiC with high crystallinity. In some examples, the interlayer 215 may be formed at a low temperature. In some examples, the interlayer 215 may be formed at a lower temperature than the nucleation layer 115. In some examples, the interlayer 215 growth temperature may be about 200-300 °C lower than the nucleation layer 115 growth temperature. In some examples, the interlayer 215 growth temperature may be about 700-900 °C. In some examples, the low temperature for the formation of the interlayer 215 may reduce the growth rate of the interlayer 215. In some examples, the combination of the reduced temperature and therefore reduced growth rate may further help prevent the formation of 3D islands. In some examples, the buffer layer 120 may be formed using any suitable epitaxial growth technique. In some examples, the buffer layer may comprise GaN. In some examples, the GaN buffer layer 120 may formed at a temperature of 950-1100 °C. In some examples, the growth rate of the buffer layer 120 may thus be higher than the growth rate of the nucleation interlayer 215. As the interlayer 315 forms with a smooth surface free and 3D islands, the buffer layer 120 can thus similarly be formed with a smooth surface free from 3D islands. In some examples, the channel layer 130 and barrier layer 140 may be formed by MOCVD on the buffer layer 120. The high-quality surface provided by the buffer layer 120 may thus result in the high-quality epitaxial formation of the channel layer 130 and barrier layer 140. Figure 3 is an example of a HEMT 300. HEMT 300 comprises corresponding elements toHEMTslOO, 200. As described above, in some examples, a surfactant may be deposited the nucleation layer 115, along with elements used to form the nucleation layer to result in a smooth upper surface for the growth of the buffer layer 120 thereon. For example, the nucleation layer 115 may comprise AIN and the interlayer 315 may comprise InAIN. However, in other examples, an interlayer comprising the surfactant may be deposited on the nucleation and a transition layer may be formed over the interlayer, where the surfactant in the interlayer may help smooth the transition layer. The transition layer may thus provide a smooth surface for the formation of the buffer layer 120 thereon. HEMT 300 thus comprises an interlayer 315 and a transition layer 325. Interlayer 315 comprises a surfactant. In one example, the interlayer 315 may comprise InN. As described above, the nucleation layer 115 may comprise a rough upper surface with 3D islands. For example, the nucleation layer 115 may comprise AIN. In such examples, the interlayer 315 may thus be deposited on the nucleation layer 115 where the interlayer 315 may also comprise a rough surface with 3D islands in a similar fashion to the nucleation layer 115. The transition layer 325 may be deposited on the interlayer 315. The surfactant present in the interlayer 315 may alter the surface energy to improve the lateral mobility of the deposited elements to result in a smooth surface for the formation of the transition layer 325. For example, the transition layer 325 may comprise AIN. Al and N atoms may thus be deposited on the interlayer 315. The surfactant, such as In, present in the interlayer 315 may promote the lateral mobility of the Al and N atoms deposited on the interlayer 315. As such, the transition layer 325 may form with a smooth surface. In particular, the interlayer 315 promotes nucleation of the transition layer 315 material on side faces of rough features and 3D islands of the surface of the interlayer 315. As such, the transition layer 325 may form a coalescent layer over the interlayer 315 to result in a smooth surface. Buffer layer 120 may thus be formed on the smooth surface of the transition layer 325. In some examples, the interlayer 315 and transition layer 325 may comprise a relatively thin thickness. The interlayer 315 and transition layer 325 may effectively cap the nucleation layer 115 to smooth the rough surface and 3D islands of the nucleation layer 115. In some examples, the interlayer 315 and transition layer 325 may sum to a thickness of 5-20 nm. In some examples, the thickness of the interlayer 315 and transition layer 325 may be thin to cap the nucleation layer 115 to remove rough and 3D artefacts present on the surface of the nucleation layer 115. Therefore, in some examples, the thickness sum of the interlayer 315 and transition layer 325 may be thinner than the nucleation layer 115. In other examples, however, the interlayer 315 and transition layer 325 may comprise thicker layers. In some examples, the interlayer 315 may comprise a thin layer with a thickness of 1-20 nm and the transition layer 325 may comprise a thicker layer with a thickness of up to 200 nm. Although the examples according to the present disclosure have been described for a HEMT where thin layers are desired. In other examples, a structure comprising a nucleation layer 115, interlayer 325 and transition layer 325 may be formed where thicker layers are desired. As described above, in some examples, the nucleation layer 115 may comprise AIN. In some examples, the AIN nucleation layer 115 may again be formed at a high temperature. In some examples, the nucleation layer 115 may be formed with a temperature of between about 1000-1200 °C. In a similar manner to interlayer 215 described above, interlayer 315 may again be formed at a lower temperature than nucleation layer 115. In some examples, the interlayer 315 may comprise InN. In some examples, the interlayer 315 growth temperature may be about 750 °C. In some examples, the transition layer 325 may be formed at a low temperature. In a similar manner to the interlayer 215 described above, the low temperature for the formation of the transition layer 325 may reduce the growth rate of the transition layer 325. In some examples, the reduced temperature and therefore reduced growth rate may further help prevent the formation of 3D islands. In some examples, the transition layer 325 may be formed at temperature of about 700-900 °C. In some examples, the growth temperature for the transition layer 325 may thus be 200-300 °C lower than the nucleation layer 115 growth temperature. In some examples, the growth temperature for the transition layer 325 may be ramped. For example, the growth temperature for the transition layer 325 may start at a cold temperature and ramp to a hotter temperature. For example, the temperature may ramp from a colder temperature to the temperature used to form the buffer layer 120. For example, the growth temperature for the transition layer 325 may ramp from about 700- 900 °C to about 950-1100 °C, which may comprise the growth temperature for the buffer layer 120. In this way, the growth rate for the transition layer 325 can be increased due to the increase in temperature. In some example, the temperature may be ramped in a step-wise or linear manner. Figure 4 is an example of a HEMT 400. HEMT 400 comprises corresponding elements to HEMTs 100, 200, 300. HEMT 400 comprises a superlattice 405 between the nucleation layer 115 and buffer layer 120. Superlattice 405 comprises a plurality of units 401a-c. Each unit 401a-c comprises an interlayer and transition layer. For example, as illustrated in Figure 4, first unit 401a comprises interlayer 415 and transition layer 425. Interlayer 415 and transition layer 425 may comprise substantially corresponding features and functionality to interlayer 315 and transition layer 325 described above. Thus, in some examples, the interlayer 415 may comprise InN and the transition layer 425 may comprise AIN. In some examples, superlattice 405 may be configured to form a layer with a smooth surface over the rough surface and 3D islands formed on nucleation layer 115. For example, interlayer 415 and transition layer 425 of unit 401a may be configured to form a smoother surface than the nucleation layer 415, due to the surfactant present in the interlayer 415. However, in some examples, the upper surface of the unit 401 a, may still be relatively rough. Second unit 401b may thus be formed over the first unit 401a, where second unit 401b comprises an interlayer and transition layer in a similar manner to first unit 401a. Second unit 401b is configured to have a smoother surface than first unit 401a. The surfactant present in the interlayer of the second unit 401b is again configured to result in the second unit comprising a smoother upper surface than first unit 401a. In a similar manner again third unit 401c is configured to comprise smoother upper surface than the second unit 401b, due to the surfactant present in the interlayer of third unit 401c. Thus, in some examples, the rough surface and 3D islands present at the surface of the nucleation layer 115 may be covered using a superlattice structure 405, which has a smooth upper surface. Each unit 401 a-c of the superlattice may become progressively smoother from the surface of the nucleation layer 115 to the buffer layer 120. The surfactant present in the interlayer of each unit 401 a-c again promotes the lateral mobility of atoms deposited on the interlayer to form the units 401 a-c to result in the progressively smoother surface. In some examples, the thickness of the superlattice 405 may be relatively thin. The superlattice may cap the nucleation layer 115 to remove the rough surface and 3D islands. In some examples, the superlattice 405 may thus be thinner than the nucleation layer 115. Buffer layer 120 may thus be formed on the superlattice 415 with a smooth surface which is free from 3D islands. Figure 5 is an example of a HEMT 500. HEMT 500 comprises corresponding elements to HEMTs 100, 200, 300, 400. As described above, an interlayer comprising a surfactant may be deposited between a nucleation layer and a buffer layer to provide an improved surface for the formation of the buffer layer thereon. In particular, the interlayer may be formed between an AIN nucleation layer and a GaN buffer layer to result in a smooth GaN buffer layer. However, in other examples, buffer layer material may be formed on the rough nucleation layer surface, and the interlayer may be present between the buffer layer material and the buffer layer. HEMT 500 thus comprises a buffer layer 505 formed on the nucleation layer 115. In some examples, the buffer layer 505 may comprise GaN. As buffer layer 505 is formed on the rough nucleation layer 115 surface, the buffer layer 505 additionally comprises a rough surface with 3D islands. However, HEMT 500 further comprises interlayer 515 and transition layer 525. In a similar manner to interlayer 315 and transition layer 325 described above in relation to HEMT 300, interlayer 515 and transition layer 525 can act to smooth the surface between the buffer layer 505 and the transition layer 525 to provide a smooth surface for the formation of the buffer layer 120 thereon. As such, buffer layer 120 may form on the high-quality transition layer 525 surface which is smooth and free from 3D islands. HEMT 500 thus comprises interlayer 515 comprising a surfactant. In some examples, the surfactant may comprise In. In some examples, the interlayer 515 may comprise InN. Interlayer 515 may thus be formed on the buffer layer 505. In some examples, the buffer layer 505 may comprise corresponding buffer layer material to the buffer layer 120. For example, buffer layer 505 may comprise GaN and the buffer layer 120 may comprise GaN. In a similar manner to interlayer 315 above, the surfactant present in the interlayer 515 may improve the lateral mobility of atoms deposited to form the transition layer 525. The interlayer 515 may thus be formed on the buffer layer 505 and may still improve the lateral mobility of atoms deposited thereon, in a similar manner to interlayer 315 formed on the nucleation layer 115. HEMT 500 thus further comprises transition layer 525. In some examples, transition layer 525 may comprise GaN. In a similar manner to that described above, the surfactant present in the interlayer 515 may promote the lateral mobility of atoms deposited on the interlayer 515, such as Ga and N, to form the transition layer 525. As such, the transition layer 525 may form with a smooth surface, which is free from 3D islands. The interlayer 515 may comprise a rough surface with 3D islands due to the formation of these features on the nucleation layer 115. The surfactant present in the interlayer 515 then helps atoms, such as Ga and N, nucleate on the sides of the 3D islands and rough features of the interlayer 515. As such, the rough surface and 3D islands can be covered with a transition layer 525 comprising a smooth surface. Buffer layer 120 is subsequently deposited over the transition layer 525. The transition layer 525 provides a smooth surface for the formation of the buffer layer 120 thereon. Buffer layer 525 thus forms with a smooth surface, which is free from 3D islands. In some examples, the buffer layer 505 may thus comprise GaN, the interlayer 515 may comprise InN and the transition layer 525 may comprise GaN. In some examples, the buffer layer 505 may be formed at a growth temperature of about 950-1100 °C. In some examples, the interlayer 515 may be formed at a growth temperature of about 700 °C. In some examples, the transition layer 315 may be formed at a temperature of about 950-1100 °C. Figure 6 is an example of a HEMT 600. HEMT 600 comprises corresponding elements to HEMTs 100, 200, 300, 400, 500. HEMT 600 comprises a superlattice 605 between the buffer layer 505 and buffer layer 120. Superlattice 605 comprises a plurality of units 601 a-c. Each unit 601 a-c comprises an interlayer and transition layer. For example, as illustrated in Figure 6, first unit 601a comprises interlayer 615 and transition layer 625. Interlayer 615 and transition layer 625 may comprise substantially corresponding features and functionality to interlayer 515 and transition layer 525 described above. Thus, in some examples, the interlayer 615 may comprise InN and the transition layer 625 may comprise GaN. In some examples, superlattice 605 may be configured to form a structure with a smooth surface over the rough surface and 3D islands formed on buffer layer 505. For example, interlayer 615 and transition layer 625 of unit 601a may be configured to form a smoother surface than the buffer layer 505, due to the surfactant present in the interlayer 615. However, in some examples, the upper surface of the unit 601a, may still be relatively rough. Second unit 601b may thus be formed over the first unit 601a, where second unit 601b comprises an interlayer and transition layer in a similar manner to first unit 601 a. Second unit 601b is configured to have a smoother surface than first unit 601a. The surfactant present in the interlayer of the second unit 601b is again configured to result in the second unit comprising a smoother upper surface than first unit 601a. In a similar manner again, third unit 601c is configured to comprise a smoother upper surface than the second unit 601b, due to the surfactant present in the interlayer of third unit 601c. Thus, in some examples, in a similar manner to superlattice 405 described above, the rough surface and 3D islands present at the surface of the buffer layer 405 may be covered using a superlattice structure 605, which has a smooth upper surface. Each unit 601 a-c of the superlattice may become progressively smoother from the surface of the buffer layer 505 to the buffer layer 120. The surfactant present in the interlayer of each unit 601 a-c again promotes the lateral mobility of atoms deposited on the interlayer to form the units 601 a-c to result in the progressively smoother surface. In some examples, the thickness of the superlattice 605 may be relatively thin. The superlattice may be configured to remove the rough surface and 3D islands over a relatively small thickness. In some examples, the superlattice 605 may thus be thinner than the nucleation layer 115. Buffer layer 120 may thus be formed on the superlattice 615 with a smooth surface which is free from 3D islands. Figures 7a and 7b are atomic force microscopy (AFM) images 700a, 700b, showing surface roughness results of semiconductor structures. AFM image 700a illustrates a surface of a conventional semiconductor structure. AFM image 700a was taken over a 20 pm x 20 pm area. AFM image 700a was taken for a semiconductor structure comprising a 150 nm thick GaN layer formed on an AIN nucleation layer. The surface of the GaN layer is rough comprising a route mean square (RMS) roughness value of 2.3 nm. Furthermore, as illustrated in image 700a, the surface is non-uniform and comprises a 3D island 701. AFM image 700b illustrates a surface of a semiconductor structure according to examples of the present disclosure. AFM image 700b was taken over a 20 pm x 20 pm area. AFM image 700b was taken for a semiconductor structure comprising a 150 nm GaN layer formed on an InAIN interlayer and AIN nucleation layer. The surface of the GaN layer is greatly improved and comprises a RMS roughness value of 0.8 nm. This is therefore below the desirable RMS roughness value of 1 nm for HEMT structures. Furthermore, the surface is more uniform and does not comprise 3D islands, as illustrated in image 700b. The smooth surface for GaN layer may thus be imparted on to semiconductor layers formed on the GaN layer. For example, a channel layer and barrier layer formed on the GaN buffer layer may also comprise a RMS roughness value of less than 1 nm. Figure 8 is a flowchart illustrating steps in a method 800 for forming a semiconductor structure. The method 800 comprises, in a first step 810, forming a first semiconductor layer over a substrate. The method 800 further comprises, in a second step 820, forming a second semiconductor layer over the first semiconductor layer. The method 800 further comprises, in a third step 830, forming an interlayer between the first semiconductor layer and the second semiconductor layer, wherein interlayer comprises a surfactant. Examples according to the present disclosure have been described with a In surfactant. However, in other examples, any suitable surfactant may be used, such as, Sb, Bi, Si or Mg. Examples according to the present disclosure have been described in relation to a HEMT. However, it will be appreciated that the examples according to the present disclosure may be applicable for any semiconductor device, for example, optoelectronic semiconductor devices. The interlayer according to examples of the present disclosure may form an improved buffer layer for the formation of any semiconductor device. Examples according to the present disclosure may thus provide a suitable template for the formation of any electronic or optoelectronic device thereon. In one example, the examples according to the present disclosure may be applied to a template comprising a Si substrate with a (100) crystal orientation and a bixbyite oxide, such as, Sc2O3, with a (111) crystal orientation. It has been observed that when a crystalline bixbyite oxide is deposited on a substrate, or another layer, at sufficient surface temperature, low enough oxygen concentration and slow enough growth rate it does not match the crystal orientation of the previous layer, depending on the orientation of the substrate or previous layer. Instead it grows in a different orientation, a process called “epi Twist™” by the inventors. When growing most crystalline bixbyite oxides on Si (100) the bixbyite oxide material grows in

[111] orientation which has lower surface energy than

[100] orientation. It has further been observed that it is energetically favorable for lll-N semiconductor materials, such as AIN or GaN, to form on the bixbyite oxide surface with a

[0001] orientation. The polar

[0001] orientation of lll-N semiconductor materials is desirable for many electronic and optoelectronic devices. The bixbyite oxide may thus provide a technique for forming polar GaN on Si (100) substrate. 11 l-N materials formed on the bixbyite oxide buffer, however, commonly possess a rough surface with 3D islands. Examples according to the present disclosure may thus be applied to structures comprising a Si (100) substrate and bixbyite oxide buffer with a

[111] crystal orientation, with lll-N materials formed thereon. The examples, according to the present disclosure may result in smoother formation of the lll-N materials to result in improved electronic and optoelectronic devices. The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for wireless radio frequency (RF) communication. In some examples the semiconductor device may comprise one of: a field-effect transistor (FET), a heterojunction bipolar transistor (HBT) or a high electron mobility transistor (HEMT). In some examples the semiconductor device may comprise an optoelectronic semiconductor device. In some examples the optoelectronic semiconductor device may comprise one of: a light emitting diode (LED) or a micro LED (pLED). The present disclosure further provides an RF module comprising a semiconductor device according to examples of the present disclosure. In some examples the RF module may comprise one of: a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module. The present disclosure further provides power management device comprising a semiconductor device according to examples of the present disclosure. In some examples the power management device may manage or transfer power for an electronic device for user operation, for example a mobile phone, cell phone, smart phone, tablet computer, wearable computer such as a watch, or similar. In some examples the power management device may comprise a charging device such as a charger, an adapter, a wireless charger, or similar for charging a battery or on-board power source of an electronic device. In some examples the power management device may comprise a power supply housed in an electronic device for user operation, such as a power converter, for example a DC-DC converter, an AC-DC converter, a DC-AC converter or similar. The present disclosure further provides an electronic device comprising an RF module according to examples of the present disclosure or a power management device according to examples of the present disclosure. In some examples the electronic device may comprise a communication device for user operation such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a communications infrastructure device, such as a communication infrastructure device for a base station, a cell tower or similar. In some examples the electronic device may comprise a communication hub, such as a Wi-Fi router or switch. In some examples the electronic device may comprise a communications device for a radar device, such as a radar transmitter, radar receiver, radar transceiver or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A semiconductor structure comprising:a substrate;a first semiconductor layer over the substrate;a second semiconductor layer over the first layer; andan interlayer between the first semiconductor layer and the second semiconductor layer, wherein the interlayer comprises a surfactant.10 2. The semiconductor structure according to claim 1 wherein a surface of thesecond semiconductor layer comprises a root mean square, RMS, roughness value of less than 1 nm as measured over a 20 pm x 20 pm area.

3. The semiconductor structure according to claim 1 or 2 further comprising one or04 04 25more semiconductor layers over the second semiconductor layer.

4. The semiconductor structure according to claim 3 wherein a surface of the one or more semiconductor layers comprises a root mean square, RMS, roughness value of less than 1 nm as measured over a 20 pm x 20 pm area.

5. The semiconductor structure according to claim 3 or 4 wherein the one or more semiconductor layers comprise a barrier layer and a channel layer.

6. The semiconductor structure according to any preceding claim wherein thesurfactant comprises In.

7. The semiconductor structure according to any preceding claim wherein the interlayer comprises a 11 l-V semiconductor material and the surfactant comprises 3% or less of the group III elements or 3% or less of the group V elements.

8. The semiconductor structure according to any preceding claim wherein the interlayer comprises a thickness of 0.5 nm to 20 nm.

9. The semiconductor structure according to any preceding claim wherein the firstsemiconductor layer comprises a nucleation layer.

10. The semiconductor structure according to any preceding claim wherein the first semiconductor layer comprises AIN.04 04 2511. The semiconductor structure according to any preceding claim wherein the second semiconductor layer comprises a buffer layer.5 12. The semiconductor structure according to any preceding claim wherein thesecond semiconductor layer comprises a thickness of 250 nm or less.

13. The semiconductor structure according to any preceding claim wherein the second semiconductor layer comprises GaN.1014. The semiconductor structure according to any preceding claim wherein the interlayer comprises InN.

15. The semiconductor structure according to claim 13 wherein the interlayer 15 comprises I nAIN.

16. The semiconductor structure according to any preceding claim further comprising a transition layer between the interlayer layer and the buffer layer.20 17. The semiconductor structure according to claim 16 wherein the transition layercomprises AIN.

18. The semiconductor structure according to claim 16 wherein the transition layer comprises GaN.2519. The semiconductor structure according to any preceding claim wherein the substrate comprises Si or SiC.

20. A semiconductor device comprising the semiconductor structure according to any 30 preceding claim.

21. A radio frequency module comprising the semiconductor device according to claim 20.35 22. An electronic device comprising the radio frequency module according to claim20.

23. A method of forming a semiconductor structure comprising: forming a first semiconductor layer over a substrate;forming a second semiconductor layer over the first semiconductor layer; forming an interlayer between the first semiconductor layer and the second semiconductor layer, wherein interlayer comprises a surfactant.5 24. The method according to claim 23 comprising forming a nucleation layer at a firsttemperature and forming the interlayer layer at a second temperature, wherein the first temperature is greater than the second temperature.

25. The method according to claim 24 wherein the first temperature is 200-300 °C10 greater than the second temperature.LDCM

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