Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises a plurality of pixel driving circuits and a base substrate, wherein the plurality of pixel driving circuits are arranged in a plurality of rows and columns; each of the plurality of pixel driving circuits comprises a plurality of transistors; and the array substrate further comprises a light-shielding layer, a semiconductor layer, and a first gate layer. The light-shielding layer is arranged on one side of the base substrate, and comprises a plurality of first-type light-shielding wirings; the semiconductor layer is arranged on the side of the light-shielding layer distant from the base substrate, and comprises active layer patterns of the plurality of transistors; the first gate layer is arranged on the side of the semiconductor layer distant from the base substrate, and comprises a plurality of scanning signal lines; each scanning signal line passes through the active layer pattern of at least one transistor; the plurality of scanning signal lines transmit scanning signals; each of the plurality of first-type light-shielding wirings passes through the active layer pattern of at least one transistor; and the first-type light-shielding wirings transmit the scanning signals.

Description

[0001] This application claims priority to Chinese Patent Application No. 202310996423.2, filed on August 8, 2023, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display apparatus. BACKGROUND

[0003] Organic light-emitting diode (OLED) display panels have gradually become one of mainstreams in the display field due to excellent performances thereof such as low power consumption, high color saturation, wide viewing angle, small thickness and capability of realizing flexibility. SUMMARY

[0004] In an aspect, an array substrate is provided. The array substrate includes a plurality of pixel driving circuits, the plurality of pixel driving circuits are arranged in multiple rows and multiple columns, and each of the plurality of pixel driving circuits includes a plurality of transistors. The array substrate includes: a base substrate, a light-shielding layer, a semiconductor layer, and a first gate layer. The light-shielding layer is disposed on a side of the base substrate, and the light-shielding layer includes a plurality of first light-shielding wires. The semiconductor layer is disposed on a side of the light-shielding layer away from the base substrate, and the semiconductor layer includes active layer patterns of the plurality of transistors. The first gate layer is disposed on a side of the semiconductor layer away from the base substrate; the first gate layer includes a plurality of scan signal lines, and each of the scan signal lines crosses over an active layer pattern of at least one transistor; and the plurality of scan signal lines transmit scan signals. Each of the plurality of first-type lightshielding wires crosses over an active layer pattern of at least one transistor. A first-type light-shielding wire and a scan signal line that cross over an active layer pattern of a same transistor transmit a same scan signal.

[0005] In some embodiments, the transistors of each pixel driving circuit include a compensation transistor and a data writing transistor, and the plurality of scan signal lines include first scan signal lines. Orthographic projections of active layer patterns of compensation transistors and data writing transistors in a row of pixel driving circuits on the base substrate overlap with an orthographic projection of a first scan signal line on the base substrate. The plurality of first-type light-shielding wires include first light-shielding wires. The orthographic projections of the active layer patterns of the compensation transistors and the data writing transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a first light-shielding wire on the base substrate. The first light-shielding wire and the first scan signal line both transmit a first scan signal.

[0006] In some embodiments, the transistors of each pixel driving circuit further include a first reset transistor, and the plurality of scan signal lines include second scan signal lines. Orthographic projections of active layer patterns of first reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a second scan signal line on the base substrate. The plurality of first-type lightshielding wires include second light-shielding wires. The orthographic projections of the active layer patterns of the first reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic 1 projection of a second light-shielding wire on the base substrate. The second light-shielding wire and the second scan signal line both transmit a second scan signal.

[0007] In some embodiments, the first scan signal line and the second scan signal line that overlap with the same row of pixel driving circuits transmit a same signal. The array substrate includes a display area and a peripheral area; the plurality of first-type metal wires extend along a row direction and extend to the peripheral area; and regions of the peripheral area located on both sides of the display area along the row direction are a first region and a second region, respectively. The first light-shielding wire and the second light-shielding wire that overlap with the same row of pixel driving circuits are electrically connected in the first region and / or the second region.

[0008] In some embodiments, the array substrate further includes at least one gate driving circuit located in the peripheral area. The gate driving circuit includes a plurality of shift registers, and each of the shift registers is configured to transmit a scan signal to a row of pixel driving circuits. Each shift register includes an output terminal, and the output terminal is electrically connected to a first scan signal line and a second scan signal line that correspond to the row of pixel driving circuits. The array substrate further includes a source-drain metal layer located on a side of the first gate layer away from the light-shielding layer, and the source-drain metal layer includes a plurality of first connection lines; an end of each of the first connection lines is electrically connected to one output terminal, and another end of each first connection line is electrically connected to a first light-shielding wire or second light-shielding wire.

[0009] In some embodiments, the first light-shielding wire is electrically connected to the first scan signal line, and the second light-shielding wire is electrically connected to the second scan signal line.

[0010] In some embodiments, the array substrate includes a display area and a peripheral area; the plurality of first-type light-shielding wires extend along a row direction and extend to the peripheral area; and regions of the peripheral area located on both sides of the display area along the row direction are a first region and a second region, respectively. The first light-shielding wire is electrically connected to the first scan signal line in the first region and / or the second region, and the second light-shielding wire is electrically connected to the second scan signal line in the first region and / or the second region.

[0011] In some embodiments, the transistors of each pixel driving circuit further include a second reset transistor, and the plurality of scan signal lines include third scan signal lines. Orthographic projections of active layer patterns of second reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a third scan signal line on the base substrate. The plurality of first-type lightshielding wires include third light-shielding wires. The orthographic projections of the active layer patterns of the second reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a third light-shielding wire on the base substrate. The third light-shielding wire and the third scan signal line both transmit a third scan signal.

[0012] In some embodiments, a third scan signal line corresponding to an nth row of pixel driving circuits and a second scan signal line corresponding to an (n-1)th row of pixel driving circuits are a same signal line.

[0013] In some embodiments, the transistors of each pixel driving circuit further include a driving transistor, and the light-shielding layer includes a plurality of second-type light-shielding wires. Orthographic projections of active layer patterns of driving transistors in a row of pixel driving circuits on the base substrate overlap with 2 an orthographic projection of a second-type light-shielding wire on the base substrate. The second-type lightshielding wire transmits a first voltage signal.

[0014] In some embodiments, a source-drain metal layer disposed on a side of the first gate layer away from the light-shielding layer. The source-drain metal layer includes first voltage signal lines, and a firstvoltage signal line is electrically connected to the second-type light-shielding wire.

[0015] In some embodiments, each of the second-type light-shielding wires overlaps with driving transistors in a row of pixel driving circuits, and each column of pixel driving circuits is connected to a corresponding first voltage signal line. At least three adjacent pixel driving circuits in each row of pixel driving circuits form a pixel driving circuit group, and a first voltage signal line connected to at least one pixel driving circuit in the pixel driving circuit group is connected to the second-type light-shielding wire.

[0016] In some embodiments, the array substrate includes a display area and a peripheral area, and the first voltage signal lines are electrically connected to each other in the peripheral area.

[0017] In some embodiments, the second-type light-shielding wire includes a plurality of light-shielding patterns and a plurality of connection patterns that are alternately arranged, and each of the connection patterns is connected to two adjacent light-shielding patterns; and an orthographic projection of each light-shielding pattern on the base substrate covers an orthographic projection of a driving transistor in a pixel driving circuit on the base substrate.

[0018] In another aspect, a display panel is provided. The display panel includes the array substrate as described in any one of the above embodiments.

[0019] In yet another aspect, a display apparatus is provided. The display apparatus includes the display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to describe technical solutions in the present disclosure more clearly, the accompanying drawings to be used in some embodiments of the present disclosure will be introduced briefly. Obviously, the accompanying drawings to be described below are merely accompanying drawings of some embodiments of the present disclosure, and a person of ordinary skill in the art can obtain other accompanying drawings according to those accompanying drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, but are not limitations on actual sizes of products, actual processes of methods and actual timings of signals involved in the embodiments of the present disclosure.

[0021] FIG. 1 is a plan view showing a structure of a display apparatus, in accordance with some embodiments;

[0022] FIG. 2 is a sectional view showing a structure of an array substrate, in accordance with some embodiments;

[0023] FIG. 3 is a structural diagram of an equivalent circuit of a pixel driving circuit, in accordance with some embodiments;

[0024] FIG. 4Ais a structural diagram of a pixel driving circuit, in accordance with some embodiments;

[0025] FIG. 4B is a plan view showing a structure of a light-shielding layer of an array substrate, in accordance with some embodiments;

[0026] FIG. 4C is a structural diagram of a semiconductor layer of an array substrate, in accordance with 3 some embodiments;

[0027] FIG. 4D is a structural diagram of a first gate layer of an array substrate, in accordance with some embodiments;

[0028] FIG. 4E is a structural diagram of a second gate layer of an array substrate, in accordance with some embodiments;

[0029] FIG. 5A is a structural diagram showing a connection between a light-shielding wire and a shift register of an array substrate, in accordance with some embodiments;

[0030] FIG. 5B is a structural diagram showing another connection between a light-shielding wire and a shift register of an array substrate, in accordance with some embodiments;

[0031] FIG. 5C is a structural diagram showing yet another connection between a light-shielding wire and a shift register of an array substrate, in accordance with some embodiments;

[0032] FIG. 6Ais a structural diagram showing a connection between a light-shielding wire and a scan signal line of an array substrate, in accordance with some embodiments;

[0033] FIG. 6B is a structural diagram showing another connection between a light-shielding wire and a scan signal line of an array substrate, in accordance with some embodiments;

[0034] FIG. 6C is a structural diagram showing yet another connection between a light-shielding wire and a scan signal line of an array substrate, in accordance with some embodiments;

[0035] FIG. 7 is a sectional view showing a structure of another array substrate, in accordance with some embodiments;

[0036] FIG. 8Ais a structural diagram showing a connection between a firstvoltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0037] FIG. 8B is a structural diagram showing another connection between a first voltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0038] FIG. 8C is a structural diagram showing yet another connection between a first voltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0039] FIG. 9Ais a structural diagram showing yet another connection between a firstvoltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0040] FIG. 9B is a structural diagram showing yet another connection between a first voltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0041] FIG. 9C is a structural diagram showing yet another connection between a first voltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0042] FIG. 9D is a structural diagram showing yet another connection between a first voltage signal line and a second-type light-shielding wire of an array substrate, in accordance with some embodiments;

[0043] FIG. 10 is a structural diagram of first voltage signal lines of an array substrate, in accordance with some embodiments; and

[0044] FIG. 11 is a sectional view showing a structure of a display panel, in accordance with some embodiments. DETAILED DESCRIPTION

[0045] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings, and obviously, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present disclosure shall be included in the protection scope of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and the claims, the term "comprise" and other forms thereof such as the third-person singular form "comprises" and the present participle form "comprising" are construed as an open and inclusive meaning, i.e., "including, but not limited to". In the description of the specification, the terms such as "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples" are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0047] Hereinafter, the terms such as "first" and "second" are used for descriptive purposes only, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the term "a / the plurality of' means two or more unless otherwise specified.

[0048] In the description of some embodiments, the terms "coupled", "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, the term "connected" may represent a fixed connection, a detachable connection, or a one-piece connection; alternatively, the term "connected" may represent a direct connection, or an indirect connection through an intermediate medium. The term "coupled", for example, indicates that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also indicate that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the context herein.

[0049] The phrase "at least one of A, B and C" has the same meaning as the phrase "at least one of A, B or C", and they both include following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

[0050] The phrase "A and / or B" includes following three combinations: only A, only B, and a combination of A and B.

[0051] The phrase "applicable to" or "configured to" used herein means an open and inclusive expression, which does not exclude devices that are applicable to or configured to perform additional tasks or steps.

[0052] In addition, the phrase "based on" used is meant to be open and inclusive, since a process, step, calculation or other action that is "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values exceeding those stated.

[0053] As used herein, the term such as "about", "substantially" or "approximately" includes a stated value 5 and an average value within an acceptable range of deviation of a particular value, and the acceptable range of deviation is determined by a person of ordinary skill in the art in view of measurement in question and errors associated with measurement of a particular quantity (i.e., limitations of a measurement system).

[0054] The term such as "parallel", "perpendicular" or "equal" as used herein includes a stated case and a case similar to the stated case within an acceptable range of deviation, and the acceptable range of deviation is determined by a person of ordinary skill in the art, considering measurement in question and errors associated with measurement of a particular quantity (i.e., limitations of a measurement system). For example, the term "parallel" includes absolute parallelism and approximate parallelism, and an acceptable range of deviation of the approximate parallelism may be, for example, a deviation within 5°; the term "perpendicular" includes absolute perpendicularity and approximate perpendicularity, and an acceptable range of deviation of the approximate perpendicularity may also be, for example, a deviation within 5°; and the term "equal" includes absolute equality and approximate equality, and an acceptable range of deviation of the approximate equality may be a difference between two equals being less than or equal to 5% of either of the two equals.

[0055] It should be understood that, when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the another layer or substrate, or it may be that intervening layer(s) exist between the layer or element and the another layer or substrate.

[0056] Exemplary embodiments are described herein with reference to sectional views and / or plan views as idealized exemplary drawings. In the accompanying drawings, thicknesses of layers and sizes of regions are enlarged for clarity. Variations in shape relative to the accompanying drawings due to, for example, manufacturing technologies and / or tolerances may be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but including shape deviations due to, for example, manufacturing. For example, an etched region shown to have a rectangular shape generally has a feature of being curved. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to show actual shapes of regions in apparatuses, and are not intended to limit the scope of the exemplary embodiments.

[0057] As shown in FIG. 1, some embodiments of the present disclosure provide a display apparatus 1000. The display apparatus 1000 provided in the embodiments of the present disclosure may be any apparatus that displays images whether in motion (e.g., videos) or stationary (e.g., static images), and whether textual or graphical. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic apparatuses. The variety of electronic apparatuses may include (but are not limited to), for example, mobile phones, wireless apparatuses, personal digital assistants (PDAs), hand-held or portable computers, global positioning system (GPS) receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (such as odometer displays), navigators, cockpit controllers and / or displays, camera view displays (such as rear view camera displays in vehicles), electronic photos, electronic billboards or indicators, projectors, building structures, packaging and aesthetic structures (such as displays for an image of a piece of jewelry), etc. The specific form of the display apparatus 1000 is not specifically limited in the embodiments of the present disclosure.

[0058] Specifically, as shown in FIG. 1, embodiments of the present disclosure are described by taking an 6 example where the display apparatus 1000 is a mobile phone.

[0059] As shown in FIG. 2, the display apparatus 1000 includes a display panel 100. The display apparatus 1000 further includes: a frame, a circuit board, a driving chip and other electronic components. The display panel 100 is disposed in the frame, and the driving chip is used to drive the display panel 100 to perform display.

[0060] As shown in FIG. 2, considering an example in which the display panel 100 is an organic light-emitting diode (OLED) display panel, the display panel 100 includes an array substrate 1, and the array substrate 1 includes a base substrate 101 and a pixel circuit stack layer 40 that is disposed on the base substrate 101.

[0061] For example, a material of the base substrate 101 includes any one of glass, metal, or a flexible material.

[0062] The pixel circuit stack layer 40 has a plurality of pixel driving circuits 10. For example, the pixel circuit stack layer 40 includes: a light-shielding layer 11, a buffer layer 12, a semiconductor layer 13, a first gate insulation layer 14, a first gate layer 15, a second gate insulation layer 16, a second gate layer 17, an interlayer dielectric layer 18, a source-drain metal layer 19, and a planarization layer 21 that are stacked in sequence.

[0063] For example, a material of the semiconductor layer 13 includes any one of low-temperature polysilicon silicon, indium gallium zinc oxide, or low-temperature polycrystalline oxide.

[0064] For example, a material of the planarization layer 21 includes polyimide; and materials of the buffer layer 12, the first gate insulation layer 14 and the second gate insulation layer 16 each include any one of silicon nitride and silicon oxide, so as to achieve an effect of blocking moisture, oxygen and alkaline ions.

[0065] In some embodiments, the pixel driving circuit 10 in some embodiments of the present disclosure may be a circuit of 7T1C, 8T1C or 9T1C, where T represents a transistor, and the number in front of T represents the number of transistors; C represents a capacitor, and the number in front of C represents the number of capacitors.

[0066] In some embodiments, a structure of the pixel driving circuit 10 shown in FIG. 3 is introduced, and the pixel driving circuit 10 is a pixel driving circuit of 7T1C. The pixel driving circuit 10 includes: a second reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first lightemitting control transistor T5, a second light-emitting control transistor T6, and a first reset transistor T7.

[0067] For example, as shown in FIG. 3, the second reset transistor T1 includes a gate, a first electrode, and a second electrode; the gate of the second reset transistor T1 is electrically connected to a third scan signal line Gate3, the first electrode of the second reset transistor T1 is electrically connected to a first initialization signal line Vinitl, and the second electrode of the second reset transistor T1 is electrically connected to a first node N1. The second reset transistor T1 is configured to reset a gate of the driving transistor T3 (the first node N1) in response to a reset signal received at the third scan signal line Gate3.

[0068] For example, as shown in FIG. 3, the compensation transistor T2 includes a gate, a first electrode, and a second electrode; the gate of the compensation transistor T2 is electrically connected to a first scan signal line Gatel, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to a third node N3. The compensation transistor T2 is configured to perform reset or threshold compensation on the driving transistor T3 in response to a scan signal received at the first scan signal line Gatel.

[0069] For example, as shown in FIG. 3, the driving transistor T3 includes the gate, a first electrode, and a 7 second electrode; the gate of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to a second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0070] For example, as shown in FIG. 3, the data writing transistor T4 includes a gate, a first electrode, and a second electrode; the gate of the data writing transistor T4 is electrically connected to the first scan signal line Gatel, the first electrode of the data writing transistor T4 is electrically connected to a data signal line Data, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2. The data writing transistor T4 is configured to transmit a data signal received at the data signal line Data to the driving transistor T3 in response to the scan signal received at the first scan signal line Gatel.

[0071] For example, as shown in FIG. 3, the first light-emitting control transistor T5 includes a gate, a first electrode, and a second electrode; the gate of the first light-emitting control transistor T5 is electrically connected to a light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T5 is electrically connected to a power supply signal line ELVDD, and the second electrode of the first lightemitting control transistor T5 is electrically connected to the second node N2. The first light-emitting control transistor T5 is configured to transmit a power supply signal received at the power supply signal line ELVDD to the driving transistor T3 in response to a light-emitting control signal received at the light-emitting control signal line EM.

[0072] For example, as shown in FIG. 3, the second light-emitting control transistor T6 includes a gate, a first electrode, and a second electrode; the gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM, the first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light-emitting control transistor T6 is electrically connected to a fourth node N4. The second light-emitting control transistor T6 is configured to, in response to the light-emitting control signal received at the light-emitting control signal line EM, transmit the driving current signal to a light-emitting device L for driving the light-emitting device L to emit light.

[0073] For example, as shown in FIG. 3, the first reset transistor T7 includes a gate, a first electrode, and a second electrode; the gate of the first reset transistor T7 is electrically connected to a second scan signal line Gate2, the first electrode of the first reset transistor T7 is electrically connected to a second initialization signal line Vinit2, and the second electrode of the first reset transistor T7 is electrically connected to the fourth node N4. The first reset transistor T7 is configured to transmit an initial signal received at the second initialization signal line Vinit2 to the light-emitting device L in response to a reset signal received at the second scan signal line Gate2, so as to reset the light-emitting device L.

[0074] For example, an anode of the light-emitting device L is electrically connected to the fourth node N4, and a cathode of the light-emitting device L is electrically connected to a reference voltage line ELVSS.

[0075] It should be noted that, in the present disclosure, the first electrode of the transistor is one of a source and a drain of the transistor, and the second electrode of the transistor is the other of the source and the drain of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, there may be no difference in structure between the source and the drain of the transistor. That is, there may be no difference 8 in structure between the first electrode and the second electrode of the transistor in the embodiments of the present disclosure. For example, in a case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode of the transistor is the drain. For example, in a case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode of the transistor is the source.

[0076] In the circuit provided in the embodiments of the present disclosure, nodes do not represent actual components, but represent junctions of relevant electrical connections in the circuit diagram. That is, these nodes are nodes that are equivalent to the junctions of the relevant electrical connections in the circuit diagram.

[0077] For example, as shown in FIG. 3, the pixel driving circuit further includes a capacitor Cst. The capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2; the first electrode plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second electrode plate Cst2 of the capacitor Cst is electrically connected to the power supply signal line ELVDD.

[0078] In some embodiments, the pixel driving circuit 10 adopts a low-temperature polycrystalline oxide (LTPO) circuit. That is, a single pixel driving circuit 10 includes both a low-temperature polysilicon (LTPS) thin film transistor and an oxide thin film transistor. The low-temperature polysilicon thin film transistor has strong load capacity, and the oxide thin film transistor has a small off-state current and has a stronger charge retention capability than the low-temperature polysilicon thin film transistor. Thus, high charge mobility and good stability of the pixel driving circuit 10 may be achieved.

[0079] For example, as shown in FIG. 3, the compensation transistor T2 adopts an oxide thin film transistor and is an N-type transistor, which is turned on at a high level. The second reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 are all low-temperature polysilicon thin film transistors of a P-type, which are turned on at a low level. The compensation transistor T2 adopts the oxide thin film transistor, which may effectively prevent the current leakage of the first node N1.

[0080] In some embodiments, in a process of adopting the low-temperature polysilicon thin film transistor and the oxide thin film transistor in the pixel driving circuit 10, illumination will cause characteristic shifts of the thin film transistors. For example, in the pixel driving circuit 10 of 7T1C, the second reset transistor T1 and the compensation transistor T2 are connected to the first node N1, the data writing transistor T4 is connected to the second node N2, and the second reset transistor is connected to the fourth node N4; when illumination causes characteristic shifts of the second reset transistor T1, the compensation transistor T2, the data writing transistor T4 and the first reset transistor T7, current leakage may occur, causing voltages of the first node N1, the second node N2 and the third node N3 to change. The driving transistor T3 is configured to generate the driving current signal; when the characteristic shift occurs due to the driving transistor T3 being illuminated, it will directly affect the driving current of the pixel driving circuit 10, and ultimately cause the display panel to have uneven display brightness.

[0081] Based on the above problems, as shown in FIGS. 2 and 4Ato 4E, some embodiments of the present disclosure provide an array substrate 1, and the array substrate 1 includes a plurality of pixel driving circuits 10 and a base substrate 101. The plurality of pixel driving circuits 10 are arranged in multiple rows and columns, and each of the plurality of pixel driving circuits 10 includes a plurality of transistors. 9

[0082] For example, the pixel driving circuits 10 are arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are both parallel to a surface of the base substrate 101. For example, the first direction X is perpendicular to the second direction Y, the first direction X is a row direction in which the plurality of pixel driving circuits 10 are arranged, and the second direction Y is a column direction in which the plurality of pixel driving circuits 10 are arranged.

[0083] For example, the plurality of transistors included in each pixel driving circuit 10 are a second reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first lightemitting control transistor T5, a second light-emitting control transistor T6, and a first reset transistor T7. For connections between the transistors, reference can be made to the above description.

[0084] As shown in FIGS. 2 and 4Ato 4E, the array substrate 1 provided in the embodiments of the present disclosure includes: a light-shielding layer 11 disposed on a side of the base substrate 101, a semiconductor layer 13 disposed on a side of the light-shielding layer 11 away from the base substrate 101, and a first gate layer 15 disposed on a side of the semiconductor layer 13 away from the base substrate. The light-shielding layer 11 includes a plurality of first-type light-shielding wires 110, the semiconductor layer 13 includes active layer patterns of the plurality of transistors, and the first gate layer 15 includes a plurality of scan signal lines Gate. Each of the scan signal lines Gate crosses over an active layer pattern of at least one transistor, and the plurality of scan signal lines Gate transmit scan signals. Each of the plurality of first-type light-shielding wires 110 crosses over an active layer pattern of at least one transistor. A first-type light-shielding wire 110 and a scan signal line Gate that cross over the active layer pattern of the same transistor transmit the same scan signal.

[0085] For example, referring to FIGS. 2 and 4Ato 4E, each scan signal line Gate crosses over an active layer pattern of at least one transistor, which means that an orthographic projection of a single scan signal line Gate on the base substrate 101 overlaps with an orthographic projection of the active layer pattern of at least one transistor on the base substrate 101. For example, a portion of a single scan signal line crossing over the active layer pattern of a transistor serves as a gate of the transistor, referring to the description of FIG. 3, which is equivalent to the scan signal line being electrically connected to the gate of the transistor. Each first-type light-shielding wire 110 crosses over an active layer pattern of at least one transistor, which means that an orthographic projection of a single first-type light-shielding wire 110 on the base substrate 101 overlaps with an orthographic projection of the active layer pattern of at least one transistor on the base substrate 101. The first-type light-shielding wire can shield the active layer pattern of the transistor and prevent external light from entering the semiconductor from the side of the base substrate (when the external light enters the semiconductor, illumination causes the characteristic shift of the active layer pattern of the transistor, which affects the stability of the driving current generated by the pixel driving circuit, and ultimately causes the display panel to have uneven display).

[0086] A first-type light-shielding wire and a scan signal line that cross over the active layer pattern of the same transistor transmit the same scan signal, which means that the first-type light-shielding wire and the scan signal line that overlap with the active layer pattern of the same transistor transmit the same scan signal. It can be understood that the first-type light-shielding wire and the scan signal line overlap, and are respectively 10 located below and above the active layer pattern of the transistor.

[0087] In the array substrate provided in some embodiments of the present disclosure, the first-type lightshielding wire receives a scan signal, and the scan signal line Gate and the first-type light-shielding wire 110 that overlap with the active layer pattern of the same transistor transmit the same scan signal, so that signals received by the upper and lower layers of the active layer pattern of the same transistor can be synchronized. Thus, it improves the signal transmission capability, avoids the generation of excessive parasitic capacitance caused by the overlap between the scan line and the light-shielding wire that transmit different signals, and avoids causing interference between signals, thereby improving the stability of the scan signal transmitted by the scan signal line, making the scan signal received by the gate of the transistor more stable, and ensuring the normal turn-on and turn-off of the transistor. In addition, the light-shielding metal layer can block external light, which prevents the characteristic shift of the active layer pattern of the transistor caused by the external light, thereby ensuring the normal operation of the pixel driving circuit and ameliorating the uneven display of the display panel.

[0088] The following takes a row of pixel driving circuits as an example to introduce positional relationships of transistors of the pixel driving circuits, a scan signal line and a light-shielding wire.

[0089] In some embodiments, as shown in FIGS. 4Aand 4C, the transistors of each pixel driving circuit 10 include the compensation transistor T2 and the data writing transistor T4, and the plurality of scan signal lines Gate include first scan signal lines Gatel. Orthographic projections of active layer patterns of the compensation transistors T2 and the data writing transistors T4 in the row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a first scan signal line Gatel on the base substrate 101. The plurality of first-type light-shielding wires 110 include first light-shielding wires 110a, and the orthographic projections of the active layer patterns of the compensation transistors T2 and the data writing transistors T4 in the row of pixel driving circuits on the base substrate 101 overlap with an orthographic projection of a first light-shielding wire 110a on the base substrate 101. The first light-shielding wire 110a and the first scan signal line Gatel both transmit a first scan signal.

[0090] It can be understood that, in the multiple pixel driving circuits 10 arranged along the first direction X, orthographic projections of active layer patterns of the compensation transistor T2 and the data writing transistor T4 in each pixel driving circuit 10 on the base substrate 101 overlap with the orthographic projection of the first scan signal line Gatel on the base substrate 101. Here, the overlap means that an orthographic projection of the active layer pattern of the compensation transistor T2 on the base substrate 101 partially coincides with the orthographic projection of the first scan signal line Gatel on the base substrate 101, an orthographic projection of the active layer pattern of the data writing transistor T4 on the base substrate 101 partially coincides with the orthographic projection of the first scan signal line Gatel on the base substrate 101, and the overlapping portions of the first scan signal line Gatel serve as gate patterns of the compensation transistor T2 and the data writing transistor T4 (that is, the gates of the compensation transistor T2 and the data writing transistor T4 receive the same first scan signal).

[0091] The description "the orthographic projections of the active layer patterns of the compensation transistors T2 and the data writing transistors T4 in the row of pixel driving circuits on the base substrate 101 overlap with an orthographic projection of the first light-shielding wire 110a on the base substrate 101" may 11 include that each of the orthographic projections of the active layer patterns ofthe compensation transistors T2 and the data writing transistors T4 in the row of pixel driving circuits 10 on the base substrate 101 partially coincides with the orthographic projection ofthe first light-shielding wire 110a on the base substrate 101, or may include that the orthographic projections ofthe active layer patterns ofthe compensation transistors T2 and the data writing transistors T4 in the row of pixel driving circuits on the base substrate 101 are all located within the orthographic projection ofthe first light-shielding wire 110a on the base substrate 101, or may include that a border of each ofthe orthographic projections ofthe active layer patterns ofthe compensation transistors T2 and the data writing transistors T4 in the row of pixel driving circuits on the base substrate 101 completely coincides with a border ofthe orthographic projection ofthe first light-shielding wire 110a on the base substrate 101.

[0092] It can be understood that, the first light-shielding wire 110a overlaps with the first scan signal line Gatel, and a width ofthe first light-shielding wire 110a is greater than that ofthe first scan signal line Gatel, which ensures that the first light-shielding wire 110a shields the active layer patterns of the compensation transistor T2 and the data writing transistor T4.

[0093] As shown in FIG. 4C, the compensation transistor T2 is a dual-gate transistor. The active layer pattern ofthe compensation transistor T2 is in a shape of "L", and has two channel regions G1 and G2 and a connection region N1 between the two channel regions. The first scan signal line Gatel overlaps with the two channel regions, but does not overlap with the connection region. By setting the compensation transistor T2 as the dualgate transistor, the current leakage may be reduced. The first light-shielding wire 110a overlaps with the two channel regions and the connection region ofthe active layer pattern ofthe compensation transistorT2 (that is, the first light-shielding wire 110a completely shields the active layer pattern ofthe compensation transistor T2), which further ensures the light-shielding effect on the compensation transistor T2.

[0094] In the array substrate provided in some embodiments ofthe present disclosure, the first light-shielding wire 110a receives the first scan signal, and both the first light-shielding wire 110a and the first scan signal line Gatel that overlap with the active layer patterns of the compensation transistor T2 and the data writing transistor T4 transmit the first scan signal, which can ensure that signals received by the upper and lower layers ofthe active layer patterns, the orthographic projections ofwhich on the base substrate 101 each overlap with orthographic projections ofthe first light-shielding wire 110a and the first scan signal line Gatel on the base substrate 101, ofthe compensation transistor T2 and the data writing transistor T4 can be synchronized. Thus, it improves the signal transmission efficiency, avoids the generation of excessive parasitic capacitance caused by the overlap between the scan line and the light-shielding wire that transmit different signals, and avoids causing interference between signals, thereby improving the stability ofthe scan signal transmitted by the scan signal line, making the scan signal received by the gate ofthe transistor more stable, and ensuring the normal turn-on and turn-off of the transistor. In addition, the light-shielding metal layer can block external light, which prevents the characteristic shift ofthe active layer pattern ofthe transistor caused by the external light, thereby ensuring the normal operation of the pixel driving circuit and ameliorating the uneven display of the display panel.

[0095] In some embodiments, with continued reference to FIGS. 4A and 4C, the transistors of each pixel driving circuit 10 further include the first reset transistor T7, and the plurality of scan signal lines Gate include 12 second scan signal lines Gate2. Orthographic projections of active layer patterns of the first reset transistors T7 in the row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a second scan signal line Gate2 on the base substrate 101. The plurality of first-type light-shielding wires 110 include second light-shielding wires 110b, and the orthographic projections of the active layer patterns of the first reset transistors T7 in the row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a second light-shielding wire 110b on the base substrate 101. The second lightshielding wire 110b and the second scan signal line Gate2 both transmit a second scan signal.

[0096] It can be understood that, in the multiple pixel driving circuits 10 arranged along the first direction X, an orthographic projection of the active layer pattern of the first reset transistor T7 in each pixel driving circuit 10 on the base substrate 101 overlaps with the orthographic projection of the second scan signal line Gate2 on the base substrate 101. Here, the overlap means that the orthographic projection of the active layer pattern of the first reset transistor T7 on the base substrate 101 partially coincides with the orthographic projection of the second scan signal line Gate2 on the base substrate 101, and the overlapping portion of the second scan signal line Gate2 serves as a gate pattern of the first reset transistor T7 (that is, the gate of the first reset transistor T7 receives the second scan signal).

[0097] The description "the orthographic projections of the active layer patterns of the first reset transistors T7 in the row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a second light-shielding wire 110b on the base substrate 101" may include that each of the orthographic projections of the active layer patterns of the first reset transistors T7 in the row of pixel driving circuits 10 on the base substrate 101 partially coincides with the orthographic projection of the second light-shielding wire 110b on the base substrate 101, or may include that the orthographic projections of the active layer patterns of the first reset transistors T7 in the row of pixel driving circuits 10 on the base substrate 101 are located within the orthographic projection of the second light-shielding wire 110b on the base substrate 101, or may include that a border of each of the orthographic projections of the active layer patterns of the first reset transistors T7 in the row of pixel driving circuits 10 on the base substrate 101 completely coincides with a border of the orthographic projection of the second light-shielding wire 110b on the base substrate 101.

[0098] It can be understood that, the second light-shielding wire 110b overlaps with the second scan signal line Gate2, and a width of the second light-shielding wire 110b is greater than that of the second scan signal line Gate2, which ensures that the second light-shielding wire 110b shields the active layer pattern of the first reset transistor T7.

[0099] In the array substrate provided in some embodiments of the present disclosure, the second lightshielding wire 110b receives the second scan signal, and both the second light-shielding wire 110b and the second scan signal line Gate2 that overlap with the active layer pattern of the first reset transistor T7 transmit the second scan signal, which can ensure that signals received by the upper and lower layers of the active layer pattern, the orthographic projection of which on the base substrate 101 overlaps with orthographic projections of the second light-shielding wire 110b and the second scan signal line Gate2 on the base substrate 101, of the first reset transistor T7 can be synchronized. Thus, it improves the signal transmission efficiency, avoids the generation of excessive parasitic capacitance caused by the overlap between the scan line and the light-shielding wire that transmit different signals, and avoids causing interference between signals, thereby 13 improving the stability of the scan signal transmitted by the scan signal line, making the scan signal received by the gate of the transistor more stable, and ensuring the normal turn-on and turn-off of the transistor. In addition, the light-shielding metal layer can block external light, which prevents the characteristic shift of the active layer pattern of the transistor caused by the external light, thereby ensuring the normal operation of the pixel driving circuit and ameliorating the uneven display of the display panel.

[0100] In some embodiments, referring to FIGS. 4A, 4C, and 5Ato 5C, the first scan signal line Gatel and the second scan signal line Gate2 that overlap with the same row of pixel driving circuits 10 transmit the same signal. That is, the compensation transistor T2, the data writing transistor T4, and the first reset transistor T7 in a single pixel driving circuit all receive the same scan signal. Similarly, the first light-shielding wire 110a and the second light-shielding wire 110b that overlap with the same row of pixel driving circuits 10 also transmit the same signal.

[0101] The array substrate 1 includes a display area AA and a peripheral area BB, and regions of the peripheral area BB located on both sides of the display area BB along the row direction are a first region B1 and a second region B2, respectively. The plurality of first-type light-shielding wires 110 extend along the row direction (first direction X) and extend to the peripheral area BB; and the first light-shielding wire 110a and the second light-shielding wire 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the first region B1 and / or the second region B2.

[0102] For example, referring to FIG. 5A, in the row direction, two ends of the first light-shielding wire 110a extend to the first region B1 and the second region B2 respectively, and two ends of the second light-shielding wire 110b extend to the first region B1 and the second region B2 respectively; and first ends of the first lightshielding wire 110a and the second light-shielding wire 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the first region B1.

[0103] For example, referring to FIG. 5B, in the row direction, two ends of the first light-shielding wire 110a extend to the first region B1 and the second region B2 respectively, and two ends of the second light-shielding wire 110b extend to the first region B1 and the second region B2 respectively; and second ends of the first light-shielding wire 110a and the second light-shielding wire 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the second region B2.

[0104] For example, referring to FIG. 5C, in the row direction, two ends of the first light-shielding wire 110a extend to the first region B1 and the second region B2 respectively, and two ends of the second light-shielding wire 110b extend to the first region B1 and the second region B2 respectively; first ends of the first light-shielding wire 110a and the second light-shielding wire 110b that overlap with the same row of pixel driving circuits 10 are electrically connected in the first region B1; and second ends of the first light-shielding wire 110a and the second light-shielding wire 110b are electrically connected in the second region B2.

[0105] For example, the first scan signal lines Gatel and second scan signal lines Gate2 extend along the row direction (first direction X) and extend to the peripheral area BB, and the first scan signal line Gatel and the second scan signal line Gate2 that overlap with the same row of pixel driving circuits 10 are electrically connected in the first region B1 and / or the second region B2. For details, reference may be made to the above description for the first light-shielding wire 110a and the second light-shielding wire 110b.

[0106] An embodiment of inputting a scan signal to the first-type light-shielding wire is introduced below. 14

[0107] In some embodiments, as shown in FIGS. 5Ato 5C, the array substrate 1 further includes at least one gate driving circuit 20 located in the peripheral area BB. The gate driving circuit 20 includes a plurality of shift registers 201, and each of the shift registers 201 is configured to transmit a scan signal to a row of pixel driving circuits 10. Each shift register 201 includes an output terminal 201a, and the output terminal 201a is electrically connected to the first scan signal line Gatel and the second scan signal line Gate2 that correspond to the row of pixel driving circuits 10. The array substrate 1 further includes a source-drain metal layer 19 located on a side of the first gate layer 15 away from the light-shielding layer 11, and the source-drain metal layer 19 includes a plurality of first connection lines 191; one end of each first connection line 191 is electrically connected to one output terminal 201a, and the other end of each first connection line 191 is electrically connected to a first light-shielding wire 110a or second light-shielding wire 110b. A1 represents the region where the pixel driving circuit is located, and the corresponding relationship between the region A1 where the pixel driving circuit is located and the signal line is used to represent the corresponding relationship between the pixel driving circuit and the signal line.

[0108] It should be noted that, referring to FIGS. 2 and 5A, the output terminal 201a of the shift register 201 is electrically connected to the first scan signal line Gatel and the second scan signal line Gate2 that correspond to the row of pixel driving circuits 10, which may be that the output terminal 201a of the shift register 201 is located in the source-drain metal layer 19, and is electrically connected to the first scan signal line Gatel and the second scan signal line Gate2 through a first via hole K1 penetrating through the second gate insulation layer 16 and the interlayer dielectric layer 18. Here, the via hole may be connected to the first scan signal line Gatel through penetration, or connected to the second scan signal line Gate2 through penetration.

[0109] For example, referring to FIGS. 2 and 5Ato 5C, one end of each of the plurality of first connection lines 191 located in the source-drain metal layer 19 is electrically connected to one output terminal 201 a, and the other end of each first connection line 191 is electrically connected to the first light-shielding wire 110a or the second light-shielding wire 110b through a second via hole K2 that penetrates through the buffer layer 12, the first gate insulation layer 14, the second gate insulation layer 16, and the interlayer dielectric layer 18.

[0110] It can be understood that the second via hole K2 may be connected to the first light-shielding wire 110a through penetration, or connected to the second light-shielding wire 110b through penetration.

[0111] In some embodiments, the position of the first via hole for connecting the output terminal of the shift register to the first scan signal line Gatel or the second scan signal line Gate2 is located on a side, away from the display area, of the position of the second via hole for connecting the output terminal of the shift register to the first light-shielding wire 110a or the second light-shielding wire 110b through the first connection line.

[0112] In some examples, there may or may not be an electrical connection between the first light-shielding wire 110a and the first scan signal line Gatel, and there may or may not be an electrical connection between the second light-shielding wire 110b and the second scan signal line Gate2.

[0113] By arranging the first connection line in the source-drain metal layer, the first light-shielding wire 110a and the second light-shielding wire 110b are directly connected to the output terminal of the corresponding shift register through the first connection line, so that the scan signal output by the shift register is directly input to the first light-shielding wire 110a and the second light-shielding wire 110b. Thus, the stable scan signal may be transmitted in the first light-shielding wire 110a and the second light-shielding wire 110b, and the connection 15 position between the shift register and both the first light-shielding wire 110a and the second light-shielding wire 110b does not conflict with the connection position between the shift register and the first scan signal line Gatel or second scan signal line Gate2, which does not affect the transmission of the scan signal in the first scan signal line Gatel and the second scan signal line Gate2.

[0114] Another embodiment of inputting a scan signal to the first-type light-shielding wire is introduced below.

[0115] In some embodiments, referring to FIGS. 6Ato 6C, the first light-shielding wire 110a is electrically connected to the first scan signal line Gatel, and the second light-shielding wire 110b is electrically connected to the second scan signal line Gate2.

[0116] For example, the first light-shielding wire 110a is electrically connected to the first scan signal line Gatel, so that the first light-shielding wire 110a and the first scan signal line Gatel can transmit the same signal to a corresponding transistor, thereby avoiding the generation of excessive parasitic capacitance due to signal asynchrony, and avoiding causing interference between signals. Similarly, the second light-shielding wire 110b is electrically connected to the second scan signal line Gate2, so that the second light-shielding wire 110b and the second scan signal line Gate2 can transmit the same signal to a corresponding transistor, thereby avoiding the generation of excessive parasitic capacitance due to signal asynchrony, and avoiding causing interference between signals.

[0117] In some embodiments, referring to FIGS. 6A to 6C, the array substrate 1 includes a display area AA and a peripheral area BB, and the plurality of first-type light-shielding wires 110 extend along the row direction and extend to the peripheral area BB; regions of the peripheral area BB located on both sides of the display area AA along the row direction are a first region B1 and a second region B2, respectively; the first lightshielding wire 110a is electrically connected to the first scan signal line Gatel in the first region B1 and / or the second region B2, and the second light-shielding wire 110b is electrically connected to the second scan signal line Gate2 in the first region B1 and / or the second region B2. A1 represents the region where the pixel driving circuit is located, and the corresponding relationship between the region A1 where the pixel driving circuit is located and the signal line is used to represent the corresponding relationship between the pixel driving circuit and the signal line.

[0118] For example, referring to FIG. 6A, the first light-shielding wire 110a and the first scan signal line Gatel are electrically connected to each other through a third via hole K3 in the first region B1, and the second lightshielding wire 110b and the second scan signal line Gate2 are electrically connected to each other through a fourth via hole K4 in the first region B1.

[0119] For example, referring to FIG. 6B, the first light-shielding wire 110a and the first scan signal line Gatel are electrically connected to each other through a fifth via hole K5 in the second region B2, and the second light-shielding wire 110b and the second scan signal line Gate2 are electrically connected to each other through a sixth via hole K6 in the second region B2.

[0120] For example, referring to FIG. 6C, the first light-shielding wire 110a and the first scan signal line Gatel are electrically connected to each other through the third via hole K3 in the first region B1, and are electrically connected to each other through the fifth via hole K5 in the second region B2; the second light-shielding wire 110b and the second scan signal line Gate2 are electrically connected to each other through the fourth via hole K4 in the first region B1, and are also electrically connected to each other through the sixth via hole K6 in the 16 second region B2.

[0121] For example, the first light-shielding wire 110a and the first scan signal line Gatel are electrically connected to each other through via hole(s) in the first region B1 / the second region B2, and the second lightshielding wire 110b and the second scan signal line Gate2 are electrically connected to each other through via hole(s) in the second region B2 / the first region B1.

[0122] It should be noted that the third via hole K3, the fourth via hole K4, the fifth via hole K5 and the sixth via hole K6 all penetrate through the buffer layer 12, the semiconductor layer 13, the first gate insulation layer 14, the first gate layer 15, the second gate insulation layer 16, the second gate layer 17 and the interlayer dielectric layer 18, which are shown in FIG. 2.

[0123] In the above embodiment, the first scan signal line Gatel and the second scan signal line Gate2 are electrically connected to the output terminal of a corresponding shift register to receive the scan signal output by the shift register; the first light-shielding wire 110a is electrically connected to the first scan signal line Gatel, and the second light-shielding wire 110b is electrically connected to the second scan signal line Gate2, and the scan signal is transmitted to the first light-shielding wire 110a and the second light-shielding wire 110b through the first scan signal line Gatel and the second scan signal line Gate2. Thus, there is no need to connect the first light-shielding wire 110a and the second light-shielding wire 110b to the shift register, which simplifies wiring and the manufacturing process.

[0124] In some embodiments, referring to FIGS. 4A and 4C, the transistors of each pixel driving circuit 10 further include a second reset transistor T1, and the plurality of scan signal lines Gate include third scan signal lines Gate3. Orthographic projections of active layer patterns of the second reset transistors T1 in a row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a third scan signal line Gate3 on the base substrate 101. The plurality of first-type light-shielding wires 110 include third light-shielding wires 110c, and the orthographic projections of the active layer patterns of the second reset transistors T1 in the row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a third light-shielding wire 110c on the base substrate 101. The third light-shielding wire 110c and the third scan signal line Gate3 both transmit a third scan signal.

[0125] It can be understood that, in the multiple pixel driving circuits 10 arranged along the first direction X, an orthographic projection of the active layer pattern of the second reset transistor T1 in each pixel driving circuit 10 on the base substrate 101 overlaps with the orthographic projection of the third scan signal line Gate3 on the base substrate 101. Here, the overlap means that the orthographic projection of the active layer pattern of the second reset transistor T1 on the base substrate 101 partially coincides with the orthographic projection of the third scan signal line Gate3 on the base substrate 101, and the overlapping portion of the third scan signal line Gate3 serves as a gate pattern of the second reset transistor T1 (that is, the gate of the second reset transistor T1 receives the third scan signal).

[0126] The description "the orthographic projections of the active layer patterns of the second reset transistors T1 in the row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a third light-shielding wire 110c on the base substrate 101" may include that each of the orthographic projections of the active layer patterns ofthe second reset transistors T1 in the row of pixel driving circuits 10 on the base substrate 101 partially coincides with the orthographic projection ofthe third light-17 shielding wire 110c on the base substrate 101, or may include that the orthographic projections of the active layer patterns of the second reset transistors T1 in the row of pixel driving circuits 10 on the base substrate 101 are located within the orthographic projection of the third light-shielding wire 110c on the base substrate 101, or may include that a border of each of the orthographic projections of the active layer patterns of the second reset transistors T1 in the row of pixel driving circuits 10 on the base substrate 101 completely coincides with a border of the orthographic projection of the third light-shielding wire 110c on the base substrate 101.

[0127] In the array substrate provided in some embodiments of the present disclosure, the third lightshielding wire 110c receives the third scan signal, and both the third light-shielding wire 110c and the third scan signal line Gate3 that overlap with the active layer pattern of the second reset transistor T1 transmit the third scan signal, which can ensure that signals received by the upper and lower layers of the active layer pattern, the orthographic projection of which on the base substrate 101 overlaps with orthographic projections of the third light-shielding wire 110c and the third scan signal line Gate3, of the second reset transistor T1 can be synchronized. Thus, it improves the signal transmission efficiency, avoids the generation of excessive parasitic capacitance caused by the overlap between the scan line and the light-shielding wire that transmit different signals, and avoids causing interference between signals, thereby improving the stability of the scan signal transmitted by the scan signal line, making the scan signal received by the gate of the transistor more stable, and ensuring the normal turn-on and turn-off of the transistor. In addition, the light-shielding metal layer can block external light, which prevents the characteristic shift of the active layer pattern of the transistor caused by the external light, thereby ensuring the normal operation of the pixel driving circuit and ameliorating the uneven display of the display panel.

[0128] It should be noted that, the plurality of pixel driving circuits 10 in the array substrate are arranged in an array, and are arranged into multiple rows and columns. For example, the plurality of pixel driving circuits 10 are arranged into multiple rows along the second direction, and the active layer pattern of the second reset transistor T1 of the pixel driving circuit in a current row is located on a side, in the row direction, of the active layer pattern ofthe first reset transistor T7 of the pixel driving circuit in a previous row. A scan signal line crosses over both the second reset transistor in the current row and the first reset transistor in the previous row. That is, the third scan signal line Gate3 connected to the gate ofthe second reset transistor T1 in the current row can be the same scan signal line Gate as the second scan signal line Gate2 connected to the gate ofthe first reset transistor T7 in the previous row (as shown in FIG. 4A). When a scan signal is input into the scan signal line Gate, the scan signal line Gate transmits the scan signal to the second reset transistor T1 in the current row and the first reset transistor T7 in the previous row simultaneously.

[0129] In some embodiments, referring to FIG. 4A, the third scan signal line Gate3 corresponding to an nth row of pixel driving circuits and the second scan signal line Gate2 corresponding to an (n-1 )th row of pixel driving circuits are the same signal line.

[0130] It can be understood that, as shown in FIG. 4A, the third scan signal line Gate3 connected to the gates ofthe second reset transistors T1 corresponding to the nth row of pixel driving circuits can be the same scan signal line Gate as the second scan signal line Gate2 connected to the gates ofthe first reset transistors T7 corresponding to the (n-1)th row of pixel driving circuits. That is, when a scan signal is input into the scan signal line Gate, the scan signal line Gate transmits the scan signal to the second reset transistor T1 in the 18 current row and the first reset transistor T7 in the previous row simultaneously.

[0131] In some embodiments, referring to FIGS. 4A to 4C, the transistors of each pixel driving circuit 10 further include a driving transistor T3, and the light-shielding layer 11 includes a plurality of second-type lightshielding wires 120. Orthographic projections of active layer patterns of the driving transistors T3 in a row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a second-type light-shielding wire 120 on the base substrate 101. The second-type light-shielding wire 120 transmits a first voltage signal.

[0132] Referring to FIGS. 4A to 4C, the second-type light-shielding wire 120 includes a plurality of lightshielding patterns 121 and a plurality of connection patterns 122 that are alternately arranged, and each connection pattern 122 is connected to two adjacent light-shielding patterns 121; an orthographic projection of each light-shielding pattern 121 on the base substrate 101 covers an orthographic projection of the driving transistor T3 in a single pixel driving circuit 10 on the base substrate 101.

[0133] For example, the second-type light-shielding wire 120 shown in FIGS. 4Ato 4C is a second-type lightshielding wire 120 in one pixel driving circuit 10, and the second-type light-shielding wire 120 includes a lightshielding pattern 121 and a connection pattern 122 that are connected. An orthographic projection of the lightshielding pattern 121 on the base substrate 101 is larger than an orthographic projection of the connection pattern 122 on the base substrate 101. Referring to FIGS. 4Ato 4C, the orthographic projection of the lightshielding pattern 121 on the base substrate 101 covers the orthographic projection of the active layer pattern of the driving transistor T3 in a corresponding pixel driving circuit 10 on the base substrate 101. That is, the orthographic projection of the active layer pattern of the driving transistor T3 on the base substrate 101 is located within a range of the orthographic projection of the light-shielding pattern 121 on the base substrate 101.

[0134] It can be understood that "orthographic projections of active layer patterns of the driving transistors T3 in a row of pixel driving circuits 10 on the base substrate 101 overlap with an orthographic projection of a second-type light-shielding wire 120 on the base substrate 101" may include that each of the orthographic projections of the active layer patterns of the driving transistors T3 in the row of pixel driving circuits 10 on the base substrate 101 partially coincides with the orthographic projection of the second-type light-shielding wire 120 on the base substrate 101, or may include that the orthographic projections of the active layer patterns of the driving transistors T3 in the row of pixel driving circuits 10 on the base substrate 101 are located within the orthographic projection of the second-type light-shielding wire 120 on the base substrate 101, or may include that a border of each of the orthographic projections of the active layer patterns of the driving transistors T3 in the row of pixel driving circuits 10 on the base substrate 101 completely coincides with a border of the orthographic projection of the second-type light-shielding wire 120 on the base substrate 101.

[0135] The second-type light-shielding wire 120 overlaps with the driving transistor, which can block external light from being directed to the driving transistor, thereby avoiding the characteristic shift of the driving transistor due to illumination, and ensuring the stability of the driving current generated by the driving transistor. The first voltage signal is a constant voltage signal, and the first voltage signal is transmitted in the second-type lightshielding wire 120, which can prevent signals transmitted in other signal lines from interfering with the signal of the second-type light-shielding wire 120, and avoid affecting the gate voltage of the driving transistor T3, 19 thereby further ensuring the stability of the driving current generated by the driving transistor and improving the display uniformity.

[0136] In some embodiments, referring to FIGS. 2, 6C and 7, the array substrate 1 further includes a sourcedrain metal layer 19 disposed on a side of the first gate layer 15 away from the light-shielding layer 11, and the source-drain metal layer 19 includes first voltage signal lines 192; the first voltage signal line 192 is electrically connected to the second-type light-shielding wire 120.

[0137] For example, referring to FIGS. 2, 6C and 7, the first voltage signal line 192 is located in the sourcedrain metal layer 19, and the first voltage signal line 192 is electrically connected to the second-type lightshielding wire 120 through a via hole that penetrates through the buffer layer 12, the first gate insulation layer 14, the second gate insulation layer 16, and the interlayer dielectric layer 18.

[0138] In some embodiments, with continued reference to FIGS. 5Ato 5C, 6Ato 6C, and 8Ato 8C, each second-type light-shielding wire 120 overlaps with the driving transistors T3 in a row of pixel driving circuits 10, and each column of pixel driving circuits 10 is connected to a corresponding first voltage signal line 192; at least three adjacent pixel driving circuits 10 in each row of pixel driving circuits 10 form a single pixel driving circuit group 30, and the first voltage signal line 192 connected to at least one pixel driving circuit 10 in a pixel driving circuit group 30 is connected to the second-type light-shielding wire 120. A1 represents the region where the pixel driving circuit is located, and the corresponding relationship between the region A1 where the pixel driving circuit is located and the signal line is used to represent the corresponding relationship between the pixel driving circuit and the signal line.

[0139] For example, referring to FIGS. 8Ato 8C, the pixel driving circuits 10 in one row and three columns are introduced. Each column of pixel driving circuits 10 is correspondingly connected to one first voltage signal line 192, and the first light-emitting control transistor T5 and the storage capacitor in each column of pixel driving circuits are electrically connected to one first voltage signal line. The pixel driving circuits 10 in each column all transmits a first voltage signal. Three adjacent pixel driving circuits 10 in a row of pixel driving circuits 10 form a single pixel driving circuit group 30, and the first voltage signal line 192 connected to one pixel driving circuit 10 in each pixel driving circuit group 30 is electrically connected to the second-type light-shielding wire 120 through a seventh via hole K7 that penetrates through the buffer layer 12, the first gate insulation layer 14, the second gate insulation layer 16, and the interlayer dielectric layer 18. It should be noted that the three adjacent pixel driving circuits 10 in the single pixel driving circuit group 30 can, for example, drive a red subpixel, a green sub-pixel and a blue sub-pixel, respectively.

[0140] For example, referring to FIGS. 9Ato 9D, the pixel driving circuits 10 in one row and four columns are introduced. Each column of pixel driving circuits 10 is correspondingly connected to one first voltage signal line 192, and the pixel driving circuits 10 in each column all transmits a first voltage signal. Four adjacent pixel driving circuits 10 in a row of pixel driving circuits 10 form a single pixel driving circuit group 30, and the first voltage signal line 192 connected to any one pixel driving circuit 10 in each pixel driving circuit group 30 is electrically connected to the second-type light-shielding wire 120 through a seventh via hole K7 that penetrates through the buffer layer 12, the first gate insulation layer 14, the second gate insulation layer 16, and the interlayer dielectric layer 18. It should be noted that the four adjacent pixel driving circuits 10 in the single pixel driving circuit group 30 can, for example, drive a red sub-pixel, a green sub-pixel, a blue sub-pixel and another 20 green sub-pixel, respectively.

[0141] It can be understood that, the first voltage signal lines 192 that are respectively connected to any two or three pixel driving circuits 10 in a pixel driving circuit group 30 are all electrically connected to the second-type light-shielding wire 120, or the first voltage signal lines 192 connected to all pixel driving circuits 10 in a pixel driving circuit group 30 are all electrically connected to the second-type light-shielding wire 120, which is not specifically limited here.

[0142] Since the second-type metal wire extends along the row direction and overlaps with the driving transistor T3 of each pixel driving circuit 10 in a row of pixel driving circuits, and the first voltage signal is input into the second-type metal wire 120, it is considered to divide three / four adjacent pixel driving circuits into one group. In each pixel driving circuit group 30, it is only necessary to connect the first voltage signal line 192 connected to at least one pixel driving circuit 10 to the second-type metal wire through a via hole, and there is no need to connect the first voltage signal lines connected to all pixel driving circuits to the second-type metal wire through via holes. In this way, on the basis of ensuring that the first voltage signal is input into the second-type metal wire, the layout space design is optimized, space is saved, and the manufacturing process is simplified.

[0143] In some embodiments, referring to FIG. 10, the array substrate 1 includes the display area AA and the peripheral area BB, and the first voltage signal lines 192 are electrically connected to each other in the peripheral area BB. A1 represents the region where the pixel driving circuit is located, and the corresponding relationship between the region A1 where the pixel driving circuit is located and the signal line is used to represent the corresponding relationship between the pixel driving circuit and the signal line.

[0144] For example, each column of pixel driving circuits 10 shown in FIG. 10 is connected to one first voltage signal line 192, and the plurality of first voltage signal lines 192 are electrically connected to each other on the same side of the first voltage signal lines 192 extending along the column direction. For example, the plurality of first voltage signal lines 192 are electrically connected in the peripheral area BB through a voltage signal connection line 193. That is, each column of pixel driving circuits 10 transmits the first voltage signal to ensure the transmission efficiency.

[0145] Embodiments of the present disclosure further provide a display panel 100, and the display panel 100 includes the array substrate 1 provided in any one of the above embodiments. Therefore, the display panel 100 provided in the present disclosure has all the beneficial effects of the array substrate 1 provided in any one of the above embodiments, which will not be repeated here.

[0146] In some embodiments, referring to FIG. 11, the display panel 100 further includes a light-emitting device layer 50 and an encapsulation layer 60 that are disposed on the array substrate 1. The array substrate 1 includes the base substrate 101 and the pixel circuit stack 40, the pixel circuit stack 40 includes a plurality of transistors TFT, and the light-emitting device layer 50 and the encapsulation layer 60 are stacked on the pixel circuit stack 40 in sequence.

[0147] The light-emitting device layer 50 includes an anode layer 22, a pixel defining layer 23, a light-emitting layer 24, and a cathode layer 25 that are disposed on the planarization layer 21.

[0148] The anode layer 22 includes a plurality of anodes 221, and the plurality of anodes 221 are electrically connected to the source-drain metal layer 19 through via holes. The light-emitting layer 24 includes a plurality 21 of light-emitting portions, and each light-emitting portion overlaps with an anode 221. The pixel defining layer 23 is provided with a plurality of pixel openings therein, and each pixel opening exposes a portion of an anode. The light-emitting portions in the light-emitting layer 24 are arranged in the pixel openings in one-to-one correspondence, so that an edge of the light-emitting portion coincides with an edge of the pixel opening.

[0149] The cathode layer is located on a side of the pixel defining layer 23 and the light-emitting layer 24 away from the array substrate 1.

[0150] The light-emitting device L as shown in FIG. 11 includes an anode, a cathode, and a light-emitting layer sandwiched between the anode and the cathode. Voltages are applied to the anode and the cathode to generate an electric field between the two, which can drive holes in the anode and electrons in the cathode to recombine in the light-emitting layer, and enable the light-emitting layer to emit light. The anode is disposed on the array substrate 1 and can be electrically connected to the pixel driving circuit 10.

[0151] The encapsulation layer 60 is located on a side of the cathode layer 25 away from the array substrate 1. For example, the encapsulation layer 60 includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer. The encapsulation layer 60 is used to encapsulate the light-emitting devices to protect the light-emitting devices L, thereby avoiding corrosion caused by external water and oxygen.

[0152] Some embodiments of the present disclosure provide a display apparatus 1000, and the display apparatus may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, or a wearable display apparatus. The embodiments of the present disclosure do not particularly limit a specific form of the display apparatus. As shown in FIG. 1, the display apparatus 1000 includes the display panel 100 provided in any one of the above embodiments. Therefore, the display apparatus 1000 provided in the present disclosure has all the beneficial effects of the display panel 100 provided in any one of the above embodiments, which will not be repeated here.

[0153] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and any person skilled in the art may conceive of variations or replacements within the technical scope of the present disclosure, which shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Claims

1. An array substrate, comprising:a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in multiple rows and multiple columns, and each of the plurality of pixel driving circuits includes a plurality of transistors;a base substrate;a light-shielding layer disposed on a side of the base substrate, wherein the light-shielding layer includes a plurality of first-type light-shielding wires;a semiconductor layer disposed on a side of the light-shielding layer away from the base substrate, wherein the semiconductor layer includes active layer patterns of the plurality of transistors; anda first gate layer disposed on a side of the semiconductor layer away from the base substrate, wherein the first gate layer includes a plurality of scan signal lines, and each of the scan signal lines crosses over an active layer pattern of at least one transistor; and the plurality of scan signal lines transmit scan signals, whereineach of the plurality of first-type light-shielding wires crosses over an active layer pattern of at least one transistor; anda first-type light-shielding wire and a scan signal line that cross over an active layer pattern of a same transistor transmit a same scan signal.

2. The array substrate according to claim 1, wherein the transistors of each pixel driving circuit include a compensation transistor and a data writing transistor, and the plurality of scan signal lines include first scan signal lines; orthographic projections of active layer patterns of compensation transistors and data writing transistors in a row of pixel driving circuits on the base substrate overlap with an orthographic projection of a first scan signal line on the base substrate;the plurality of first-type light-shielding wires include first light-shielding wires; the orthographic projections of the active layer patterns of the compensation transistors and the data writing transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a first light-shielding wire on the base substrate; andthe first light-shielding wire and the first scan signal line both transmit a first scan signal.

3. The array substrate according to claim 2, wherein the transistors of each pixel driving circuit further include a first reset transistor, and the plurality of scan signal lines include second scan signal lines; orthographic projections of active layer patterns of first reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a second scan signal line on the base substrate;the plurality of first-type light-shielding wires include second light-shielding wires; the orthographic projections of the active layer patterns of the first reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a second light-shielding wire on the base substrate; andthe second light-shielding wire and the second scan signal line both transmit a second scan signal.

4. The array substrate according to claim 3, wherein the first scan signal line and the second scan signal line that overlap with the same row of pixel driving circuits transmit a same signal;23the array substrate comprises a display area and a peripheral area; the plurality of first-type light-shielding wires extend along a row direction and extend to the peripheral area; and regions of the peripheral area located on both sides of the display area along the row direction are a first region and a second region, respectively; andthe first light-shielding wire and the second light-shielding wire that overlap with the same row of pixel driving circuits are electrically connected in the first region and / or the second region.

5. The array substrate according to claim 4, wherein the array substrate further comprises at least one gate driving circuit located in the peripheral area; the gate driving circuit includes a plurality of shift registers, and each of the shift registers is configured to transmit a scan signal to a row of pixel driving circuits;each shift register includes an output terminal, and the output terminal is electrically connected to a first scan signal line and a second scan signal line that correspond to the row of pixel driving circuits; andthe array substrate further comprises a source-drain metal layer located on a side of the first gate layer away from the light-shielding layer, and the source-drain metal layer includes a plurality of first connection lines; an end of each of the first connection lines is electrically connected to one output terminal, and another end of each first connection line is electrically connected to a first light-shielding wire or second light-shielding wire.

6. The array substrate according to any one of claims 3 to 5, wherein the first light-shielding wire is electrically connected to the first scan signal line, and the second light-shielding wire is electrically connected to the second scan signal line.

7. The array substrate according to claim 6, wherein the array substrate comprises a display area and a peripheral area; the plurality of first-type light-shielding wires extend along a row direction and extend to the peripheral area; and regions of the peripheral area located on both sides of the display area along the row direction are a first region and a second region, respectively; andthe first light-shielding wire is electrically connected to the first scan signal line in the first region and / or the second region, and the second light-shielding wire is electrically connected to the second scan signal line in the first region and / or the second region.

8. The array substrate according to claim 3, wherein the transistors of each pixel driving circuit further include a second reset transistor, and the plurality of scan signal lines include third scan signal lines; orthographic projections of active layer patterns of second reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a third scan signal line on the base substrate;the plurality of first-type light-shielding wires include third light-shielding wires; the orthographic projections of the active layer patterns of the second reset transistors in the row of pixel driving circuits on the base substrate overlap with an orthographic projection of a third light-shielding wire on the base substrate; andthe third light-shielding wire and the third scan signal line both transmit a third scan signal.

9. The array substrate according to claim 8, wherein a third scan signal line corresponding to an nth row24of pixel driving circuits and a second scan signal line corresponding to an (n-1)th row of pixel driving circuits are a same signal line.

10. The array substrate according to any one of claims 1 to 9, wherein the transistors of each pixel driving circuit further include a driving transistor, and the light-shielding layer includes a plurality of second-type lightshielding wires; orthographic projections of active layer patterns of driving transistors in a row of pixel driving circuits on the base substrate overlap with an orthographic projection of a second-type light-shielding wire on the base substrate; andthe second-type light-shielding wire transmits a first voltage signal.

11. The array substrate according to claim 10, further comprising:a source-drain metal layer disposed on a side of the first gate layer away from the light-shielding layer, wherein the source-drain metal layer includes first voltage signal lines, and a first voltage signal line is electrically connected to the second-type light-shielding wire.

12. The array substrate according to claim 11, whereineach of the second-type light-shielding wires overlaps with driving transistors in a row of pixel driving circuits, and each column of pixel driving circuits is connected to a corresponding first voltage signal line; andat least three adjacent pixel driving circuits in each row of pixel driving circuits form a pixel driving circuit group, and a first voltage signal line connected to at least one pixel driving circuit in the pixel driving circuit group is connected to the second-type light-shielding wire.

13. The array substrate according to claim 12, wherein the array substrate comprises a display area and a peripheral area, and the first voltage signal lines are electrically connected to each other in the peripheral area.

14. The array substrate according to any one of claims 10 to 13, wherein the second-type light-shielding wire includes a plurality of light-shielding patterns and a plurality of connection patterns that are alternately arranged, and each of the connection patterns is connected to two adjacent light-shielding patterns; and an orthographic projection of each light-shielding pattern on the base substrate covers an orthographic projection of a driving transistor in a pixel driving circuit on the base substrate.

15. A display panel, comprising the array substrate according to any one of claims 1 to 14.

16. A display apparatus, comprising the display panel according to claim 15.

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