Time delay relay

Abstract

An electronic time delay relay comprising: a set of timing resistors arranged in a series circuit between a first, input node and a second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a set of contacts; a microcontroller configured to receive as an input said digital output voltage, said microcontroller including: a processor; and storage means for storing a mathematical equation and computer-readable instructions that when executed on the processor perform the steps of: utilising said digital output voltage as an input parameter to said mathematical equation to calculate a time delay implemented by the positioning of each said strap; and changing the state of at least one of said contacts when said time delay expires.

Description

TIME DELAY RELAYRelated Application

[0001] The present application is related to Australian Provisional Patent Application No. 2023901424 entitled “Time Delay Relay” and filed 10 May 2023 in the name of David Stuckey Investments Pty Ltd, the entire content of which is incorporated by reference as if fully set forth herein.Technical Field

[0002] The present disclosure generally relates to a time delay relay. In particular, the present disclosure relates to a digitally controlled, programmable time delay relay that may be used in railway applications. More particularly, the present disclosure relates to a programmable time delay relay, which may be used in retro-fitting to replace an existing electromechanical relay. Even more particularly, some embodiments of the present disclosure relate to a specific type of relay, in which a time delay may be set using external connections between dedicated pins. It will be convenient to hereinafter describe various embodiments in relation to this particular application. It should be appreciated, however, that the present disclosure is not limited to that application only.Background

[0003] A relay is an electrically operated switch that is actuated by changes in an electric circuit to open or close contact terminals, which are often referred to simply as “contacts”. Changes in an electric circuit may relate, for example, to the presence of a current or voltage above or below a predefined threshold. As switches, relays are often used to control the activation of other electrical devices in a circuit.

[0004] Electromechanical relays typically use an electromagnet to control a set of signalling contacts. Such signalling contacts include normally open (NO) (front) and normally closed (NC) (back) signalling contacts.

[0005] Some relays include the further functionality of a time delay, by which the relay includes a delay in operation between receiving an actuation signal and changing the state of the contacts. Such a time delay relay utilises a set of input pins by which to configure the delay. The input pins utilised to set the delay are referred to as “strapping contacts” and the connections between the strapping pins are referred to as “straps”. In addition to thestrapping contacts, the time delay relay also has a pair of dedicated contacts known as a “stick contact” that is used to prematurely abort the delay.

[0006] Electromechanical relays use a conventional resistor-capacitor (RC) timing circuit to set the time delay. In order to set the time delay, an imprecise voltage was applied to one end of a chain of resistors and, by adjusting the position of the strap, the value of the resistance could be altered. The change in resistance meant that the charging rate of the capacitor could be varied, which ultimately determined the delay time. The higher the resistance, the lower the charging current, and the longer it took to charge the capacitor and thus the longer the delay time.

[0007] Some electromechanical relays provide three adjustment settings, namely, (i) a coarse strapping, and (ii) a fine strapping, both of which could be set in the field, and, (iii) an internal fine adjustment potentiometer, which could only be adjusted during production.

[0008] A drawback of using RC timing circuits is that the resistor and capacitor values are nominal only, which prevents an accurate prediction of the resultant time delay and the circuits often require fine adjustments to achieve a desired time delay. Further, it is difficult to develop practical RC circuits, which provide accurate and predictable timing, because the rate of current discharge from the capacitor is exponential, rather than linear with time. In practice, setting the time delay for a particular relay is a matter of trial and error in order to achieve a desired time delay.

[0009] A further drawback of RC timing circuits is that the values of the discrete resistor and capacitor components can be affected by both temperature and ageing.

[0010] Existing electromechanical relays, such as those used by British Rail, for example, often experience a number of problems, such as high contact resistance, mechanical wear and tear, susceptibility to environmental conditions, and variability of performance based on mechanical and material variation, such as, for example, of the contact spring tension and the like.

[0011] Thus, a need exists to provide an improved time delay relay.Summary

[0012] The present disclosure provides an electronic time delay relay.

[0013] A first aspect of the present disclosure provides an electronic time delay relay comprising: a set of timing resistors arranged in a series circuit between a first, input node and a second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a set of contacts; a microcontroller configured to receive as an input said digital output voltage, said microcontroller including: a processor; and storage means for storing a mathematical equation and computer-readable instructions that when executed on the processor perform the steps of: utilising said digital output voltage as an input parameter to said mathematical equation to calculate a time delay implemented by the positioning of each said strap; and changing the state of at least one of said contacts when said time delay expires.

[0014] A second aspect of the present disclosure provides a composite, fail-safe electronic time delay relay comprising: a set of relay contacts and a corresponding set of activation inputs; a set of timing resistors arranged in a series circuit between a first, input node and a second, output node, at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node;an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a high current FET board for controlling states of the respective relay contacts, based on states of the respective activation inputs; a first system board that includes: a first microcontroller configured to receive as an input said digital output voltage, said first microcontroller including: a first processor; and first storage means for storing a mathematical equation and computer- readable instructions that when executed on the first processor perform the steps of: utilising said digital output voltage as an input parameter to said stored mathematical equation to calculate a first coarse time delay implemented by the positioning of each said strap; and determining a first total time delay based on said first coarse time delay; a second system board that includes: a second microcontroller configured to receive as an input said digital output voltage, said second microcontroller including: a second processor; and second storage means for storing said mathematical equation and computer- readable instructions that when executed on the second processor perform the steps of: utilising said digital output voltage against as an input parameter to said stored mathematical equation to calculate a second coarse time delay implemented by the positioning of each said strap; and determining a second total time delay based on said second coarse time delay; and a display module for displaying an overall time delay based on said first total time delay and said second total time delay; wherein, upon detection of an activation voltage at one of said activation inputs, said first microcontroller and said second microcontroller detect said activation voltage and send a corresponding activation signal to said FET board to change the state of a contact associated with the activation input to which the activation voltage was applied.

[0015] A third aspect of the present disclosure provides an electronic time delay relay comprising: a time delay unit with an associated set of time delay controls, said time delay unit being positioned between a first, input node and a second, output node; a set of contacts; a microcontroller including a processor; and storage means for storing computer-readable instructions that when executed on the processor perform the steps of: determining an overall time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; upon receipt of an activation control corresponding to one of said contacts, changing the state of that contact when said determined overall time delay expires.

[0016] A fourth aspect of the present disclosure provides a composite, fail-safe electronic time delay relay comprising: a set of relay contacts and a corresponding set of activation inputs; a time delay unit with an associated set of time delay controls, said time delay unit being positioned between a first, input node and a second, output node; a high current FET board for controlling states of the respective relay contacts, based on states of the respective activation inputs; a first system board that includes: a first microcontroller including: a first processor; and first storage means for storing computer-readable instructions that when executed on the first processor perform the steps of: determining a first total time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; a second system board that includes: a second microcontroller configured to receive as an input said digital output voltage, said second microcontroller including: a second processor; andsecond storage means for storing computer-readable instructions that when executed on the second processor perform the steps of: determining a second total time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; a display module for displaying an overall time delay based on said first total time delay and said second total time delay; wherein, upon detection of an activation voltage at one of said activation inputs, said first microcontroller and said second microcontroller detect said activation voltage and send a corresponding activation signal to said FET board to change the state of a contact associated with the activation input to which the activation voltage was applied, once the overall time delay has expired.

[0017] According to another aspect, the present disclosure provides methods associated with implementing any one of the aforementioned apparatuses.

[0018] Other aspects of the present disclosure are also provided.Brief Description of the Drawings

[0019] One or more embodiments of the present disclosure will now be described by way of specific examples with reference to the accompanying drawings, in which:

[0020] Figure 1 is a circuit drawing depicting strapping for an electromechanical time delay relay;

[0021] Figure 2 is a circuit drawing depicting strapping to adjust a time delay for a microcontroller-based time delay relay, in accordance with one or more embodiments of the present disclosure;

[0022] Figure 3A is a schematic representation of a strapping detection circuit suitable for use in embodiments of an electronic time delay relay;

[0023] Figure 3B is a graph of 1 / Vout vs. time;

[0024] Figure 4A is a circuit diagram of an ADC analogue reference;

[0025] Figure 4B is a circuit diagram illustrating an analogue voltage and analogue reference signal;

[0026] Figure 5 shows circuit schematics relating to implementation of a status LED display for showing the time delay;

[0027] Figure 6 is schematic representation of a circuit for implementing a bank of switches for fine-tuning the time delay of an electronic time delay relay;

[0028] Figure 7 is a circuit diagram of a driver for a seven-segment LED driver;

[0029] Figure 8 is a circuit for a fault reset;

[0030] Figure 9 is a circuit diagram of an I2C header for connecting two system boards;

[0031] Figure 10 illustrates circuitry associated with MOSFETs, wherein the circuitry includes pull down resistors that blow the safe state fuse, ensuring that the MOSFETs are always in an off condition at power on;

[0032] Figure 11 is a circuit diagram of filter inductors placed in series with resistors R1 and R2, respectively, at the front end of the power supply;

[0033] Figures 12A and 12B are schematic representations of copper track layouts;

[0034] Figure 13A is a system architecture of a composite, fail-safe solid state time delay relay;

[0035] Figure 13B is a legend showing the relationships among Figures 13D to 13N relative to Figure 13 A;

[0036] Figure 13C is a legend for Figures 13D to 13N;

[0037] Figures 13D to 13N are expanded views of portions of the system architecture of Figure 13 A.

[0038] Figure 14 is a schematic block diagram representation of functional modules of a system board of an electronic time delay relay;

[0039] Figure 15 is a schematic block diagram representation of the functional modules of the display module 1310 of Figure 13A;

[0040] Figure 16 is a schematic block diagram representation of the high current FET driver board 1350 of Figure 13A;

[0041] Figure 17 illustrates one embodiment of a suitable front contact that includes four enhancement mode MOSFETs wired in series;

[0042] Figure 18 illustrates one embodiment of a suitable back contact that includes four depletion mode MOSFETs wired in series;

[0043] Figure 19 illustrates connections between each of the drivers 1610. .. 1670 and the set of relay contacts 1356 of Figure 13 A;

[0044] Figure 20 is a flow diagram illustrating an overview of a method 2000 for how the strapping positioning functions in an electronic relay device implemented using two system boards; and

[0045] Figure 21 is a flow diagram of a method 2100 for resetting a relay. The method 2100 starts with the main loop 2010.

[0046] Method steps or features in the accompanying drawings that have the same reference numerals are to be considered to have the same function(s) or operation(s), unless the contrary intention is expressed or implied.Detailed DescriptionBackground

[0047] The present application relates to a specific type of relay, wherein a time delay associated with the relay may be set by utilising external connections among a set of dedicated pins. The present application is to be read in conjunction with United States Patent No. 10,672,578 B2 filed 2 June 2020 in the name of Stuckey et al., the entire content of which is incorporated by reference as if fully set forth herein.

[0048] In an electromechanical timer relay, the time delay between applying power and switching the contacts is controlled by a conventional analogue resistor-capacitor (RC) timing circuit. By adjusting the resistance, the rate at which the capacitor is charged can be used to set the time. An external strap is connected between pins on the relay to adjust the resistance and hence control the time. This is inherently inaccurate and varies between relays due to component tolerances and environmental factors, such as temperature.

[0049] The present disclosure provides a solid-state electronic time delay relay, in which the RC timing circuit of the electromechanical relay is replaced by a microcontroller that is inherently more accurate and predictable. Embodiments of the electronic time delay relay of the present disclosure utilise a time delay unit to control the time delay utilised by the relay, wherein the time delay unit has a set of time delay controls.

[0050] Rather than relying on the rate at which a capacitor is charged, software executing on the microcontroller utilises one or more mathematical equations, one or more look-up tables, or any combination thereof, to determine a time delay for the relay as set by the time delay controls. The time delay controls vary depending on the particular application. Some examples of suitable time delay controls include, for example, but are not limited to, sets of resistors and associated strappings, a General Purpose Input / Output (GPIO), a bank of switches, or any combination thereof in any number thereof.

[0051] In some embodiments in which the time delay controls are implemented using a set of resistors and one or more associated external straps, the microcontroller receives an input from an analogue-to-digital converter (ADC) coupled to an output of the time delay controls and utilises a mathematical equation (e.g., linear equation, quadratic equation, etc.), a stored look-up table, or a combination thereof to determine a position of the external strap(s) and then converts the determined position of the external strap(s) into a time delay in seconds.

[0052] In some embodiments in which the time delay controls are implemented using a GPIO, the microcontroller receives an input from an analogue-to-digital converter (ADC) coupled to an output of the GPIO and utilises a stored look-up table to determine a time delay in seconds.

[0053] In some embodiments in which the time delay controls are implemented using a bank of switches, such as dual in-line (DIP) switches, the microcontroller reads the state of the switches to determine a time delay or utilises a stored look-up table to determine the time delay based on the particular permutation of the settings of the individual switches.

[0054] Some embodiments of the electronic time delay relay have time delay controls that include a coarse time delay control to implement a coarse time delay and a fine time delay control to implement a fine time delay, wherein an overall time delay for the relay is the sum of the coarse time delay and the fine time delay. In some implementations, the coarse time delay control is set by a set of resistors and associated straps and / or a GPIO, and the fine time delay control is a user-controlled bank of switches, such as DIP switches.

[0055] In some embodiments, some of the time delay controls determine one or more coarse time delays and some of the time delay controls determine one or more fine time delays, wherein an overall time delay for the relay is the sum of the coarse time delays and fine time delays for the particular embodiment. For example, some embodiments utilise a set of timing resistors and associated strappings to determine a coarse time delay and a bankof switches, which may be user-selectable or pre-set, to determine a fine time delay, with the overall time delay being the sum of the coarse time delay and the fine time delay.

[0056] Whereas an electromechanical time delay relay uses a mechanical potentiometer to make fine adjustments to the resistance and thus the resultant time delay, some embodiments of the electronic time delay of the present disclosure replace the mechanical potentiometer with a microcontroller executing software code that reads the state of a set of discrete switches (such as dual in-line (DIP) switches), resulting in a more accurate and predictable time delay. Such an implementation removes any variation between different instances of the time delay relays.

[0057] In some embodiments, the microcontroller utilises a stored look-up table to convert the state of the set of discrete switches to a fine time delay. The microcontroller adds the fine time delay to the coarse time delay to determine a total (z.e., overall) time delay for the solid-state electronic time delay relay.

[0058] Embodiments of the solid-state electronic time delay relay of the present disclosure are capable of being utilised as drop-in replacements for existing electromechanical relays. In particular, some embodiments of the time delay relay utilise the same number of switch contacts and the same external strapping inputs as existing electromechanical relays to adjust the time delay. As such, a time delay for the electronic time delay relay is able to be set based on existing strapping connections. Using the time delay relay, an installer is able to remove an old relay and fit a new time delay relay without having to alter any wiring.

[0059] From a functionality point of view, the physical operation of the relay remains the same as electromechanical time delay relays, but embodiments of the electronic time delay relay of the present disclosure include features that ensure the time delay relay is safer, more reliable, and easier to operate.

[0060] In some embodiments, the electronic time delay relay includes a visual display, such as a seven-segment LED display, an LCD display, LED display, OLED display, or the like. In such embodiments, the visual display displays a visual indication of the time remaining between when power is applied to coil pins of the time delay relay and when the relay contacts change state. Depending on the implementation of the visual display, the visual indication may be a countdown of the time remaining in seconds, a graphical indicator (such as change in colour), or any combination thereof. In order for the relay to change the states of contacts, the applied power must meet (or exceed) a predefined pick threshold forthe duration of the countdown period. If the applied power dips below the pick threshold during the countdown period, the countdown terminates and the relay returns to a dropped state.

[0061] When power is first applied to the time delay relay, software executing on the microcontroller reads an ADC to determine the position of the strap and calculates the time delay. The software then displays this calculated time delay value as a timer on the visual display, such as a seven-segment LED display, and decrements the timer until the time has expired, at which point the contacts are switched. The user can simply look at the display to determine the length of time remaining. In the electromechanical relay, there is no way of determining the amount of time remaining before the contacts change state.

[0062] Being of an entirely solid-state design, with no moving mechanical parts, the time delay relay of the present disclosure is inherently more reliable than electromechanical relays and offers an increase in operational cycles, as there is no potential for contacts wearing out due to arcing, friction, vibration, or corroding over time due to environmental exposure.

[0063] In some embodiments, the time delay relay includes a self-diagnostic capability that ensures that the relay permanently defaults to a safe state, when an internal problem is detected. In contrast, electromechanical relays are not capable of performing a self-diagnostic test and a fault could potentially result in an unsafe situation. The solid-state relay uses diagnostic software to check the status of the contacts, ensuring that the respective contacts are in the intended state(s). If the diagnostic software determines that the state of any contact is incorrect, the relay shuts down gracefully and issues an alert by indicating the presence of a fault on the display. Electromechanical relays are not capable of doing this.

[0064] Similarly, the software also performs internal self-tests, checking parameters, such as supply voltages, oscillator frequencies, memory corruption, and CPU register status. Some embodiments utilise two independent microcontrollers, so that a fault in one system can be detected by the other system.Description of Embodiments

[0065] Figure 1 is a circuit drawing depicting a time delay unit 100 for an electromechanical time delay relay, wherein the time delay unit is implemented using time delay controls in the form of strapping among a set of resistors. The circuit 100 includes three different levels of adjustment of time delay for an associated relay. An input current is presented at a first node 150 from an imprecise step-up voltage converter. A first, coarseadjustment is implemented using a first set of resistors 110 between a second node 160 and a third node 170. A second, fine adjustment is implemented using a second set of resistors 120 between the first node 150 and the second node 160. A third, internal final adjustment is implemented using a potentiometer 130 between the third node 170 and an output of the circuit 100 that is presented to activate an output switch 180. It will be appreciated that the positions of the coarse, fine, and internal fine adjustments may change without affecting the circuit, as the adjustments are arranged in series.

[0066] In the example of Figure 1, there are 16 contact pins provided to implement the coarse adjustment and the fine adjustment between the first node 150 and the third node 170. The contact pins are denoted Al, Al, A2, A3, A4, A5, A6, A7, A8, Bl, B2, B3, B4, B5, B6, B7, B8. A strapping denoted A1-B3 indicates that an external wire (z.e., a strap) is connected from pin (i.e., contact) Al to pin B3.

[0067] Depending on the implementation, each strapping can be implemented using a shorting link or a conductive link between two points in a circuit, wherein each strapping effectively provides an alternative path in the circuit to exclude one or more resistors from the circuit, thus changing the resistance and consequential voltage drop and associated time delay.

[0068] In the example of Figure 1, the first set of resistors includes 13 x 1MQ resistors in series. A user selects a coarse resistance value by connecting a first strap in one of thirteen possible strap arrangements connected between a first node 150 and a second node 160 to determine which of the thirteen coarse resistors are coupled in series to the electric circuit and which of the thirteen coarse resistors are by-passed by the first strap.

[0069] For example, if the first strap is connected in arrangement A1-B7, then the first strap creates a parallel coarse strapping circuit that avoids all of the 13 x 1MQ resistors between the second node 160 and a third node 170. In another arrangement, the first strap is connected in arrangement A1-B4, in which scenario, the bottom 6 x 1MQ resistors form part of the circuit and the top 7 x 1MQ resistors are by-passed by the first strap.

[0070] The second set of resistors includes a 470kQ resistor and a 220kQ resistor. A user selects a fine resistance value by using a second strap to connect one of three possible fine resistor permutations between the second node 160 and a third node 170. A first combination B7-B8 utilises the second strap between the first node 150 and second node 160, by-passing both resistors. A second combination B7-A8 engages the 220kQ resistor in the circuit andby-passes the 470kQ resistor. A third combination A8-B8 engages the 470kQ resistor and by-passes the 220kQ resistor.

[0071] An internal fine adjustment is effected by changing the value of the potentiometer 130. The output of the internal fine adjustment is connected to a set of capacitors 140, which in this example is implemented using three 6.8pF capacitors in parallel. By changing the straps utilised in relation to the coarse and fine adjustment, in conjunction with adjusting the potentiometer 130, the time delay of the relay can be finetuned. However, variance across component values and degradation of components over time can result in variance in the time delay across similar relays and even for the same relay over time.

[0072] The electronic time delay relay of the present disclosure utilises a plurality of resistors in series with an associated set of straps to set a time delay. Rather than charging a capacitor, as occurs in electromechanical time delay relays, the time delay relay uses software running on a microcontroller to determine an instantaneous voltage from an analogue-to-digital converter. The circuit uses a conventional voltage-divider approach, with a fixed resistor referenced to ground, and a series of resistors connected to a precision voltage reference.

[0073] Figure 2 is a schematic representation of an example of a suitable circuit architecture 200 of a time delay unit for setting a time delay of an electronic time delay relay in accordance with one or more embodiments of the present disclosure. The circuit 200 includes a precision reference voltage 230 that is coupled to a third node 270. The precision voltage reference 230 presents a fixed (i.e.. constant) voltage to the circuit 200.

[0074] In some embodiments, the precision voltage reference device 230 is implemented using the Texas Instruments, LM4040AIM3X-4.1 / NOPB, which is accurate, small, readily available and cost effective. It will be appreciated that many different precision voltage reference devices may equally be utilised within the scope of this disclosure.

[0075] A first, coarse adjustment is implemented using a first set of resistors 210 and a first strap between the third node 270 and a second node 260. A second, fine adjustment is implemented using a second set of resistors 220 and a second strap between the second node 260 and a first node 250. In the example of Figure 2, the coarse adjustment is implemented using the first strap to select one of thirteen possible positions for use in relation to the first set of resistors 210 and the fine adjustment is implemented using the second strap to selectone of three possible positions for use in relation to the second set of resistors 220. In embodiments in which the time delay relay is adapted to be suitable for replacing existing electromechanical time delay relays of the form of Figure 1, then the same number of potential straps are utilised for the respective coarse and fine adjustments. It will be appreciated, however, that any number of resistors and any resistor values may be practised in different embodiments of time delay units for different applications. Further, different applications may utilise any number of sets of adjustment resistors and associated straps, and any circuit architecture that enables different resistance values to be set.

[0076] As the positions of the first and second strap are changed, the value of the resistance between the first node 250 and third node 270 changes. Consequently, an input voltage applied to an analogue-to -digital converter (ADC) 280 at the first node 250 varies based on the settings of the first and second straps. The output of the ADC 280 is presented as a digital input to a micro-controller 285.

[0077] In some embodiments, software running on the microcontroller 285 reads the voltage of the digital input and utilises the voltage as an input parameter to a stored mathematical equation to determine a time delay set by the positioning of the first and second straps. The actual mathematical equation used can vary, depending on the implementation and mathematical characterisation of the circuit 200. In some implementations, the mathematical equation is a linear equation. In other implementations, the mathematical equation is a quadratic equation, a cubic equation, a quartic equation, or the like, or a combination thereof.

[0078] In alternative embodiments, software running on the microcontroller 285 reads the voltage of the digital input and reads a stored look-up table to determine a time delay corresponding to the read voltage, thus determining the time delay set by the positioning of the first and second straps.

[0079] Figure 20 is a flow diagram illustrating an overview of a method 2000 for how the strapping positioning functions in an electronic relay device implemented using two system boards. The method starts at step 2002, which applies power to the system. Step 2004 executes a self-test. The self-test may include, for example, EEPROM checksum validation and will fault if the EEPROM has been corrupted. If, at any point after writing the strapping times, a difference between channels is detected, the relay should fault.

[0080] At step 2006, each of the first and second system boards, denoted SysA and SysD, check respective associated EEPROMs for strapping configuration flags. Decision step 2008 determines whether the strapping flag configuration exists in each respective EEPROM. If Yes, control passes to step 2010, in which each of the first and second system boards read a strapping time stored in the respective EEPROMs.

[0081] In step 2012, first and second microcontrollers on the first and second system boards, respectively, read values of a set of associated DIP switches. That is, the first system board is associated with a first set of DIP switches and the second system board is associated with a second set of DIP switches.

[0082] Decision step 2014 determines whether the settings of the first and second sets of DIP switches are the same. If the settings are not the same, control passes to a fault state 2016 and the process terminates. If the settings are the same, control passes from step 2014 to step 2018, which adds the strapping time to the DIP switch time for each of the first and second systems to generate first and second overall delay times.

[0083] Step 2020 determines whether the first and second overall delay times are the same. If there is a difference between the first and second overall times that is greater than a predefined threshold (e.g., 20%), Yes, control passes to a fault state at step 2022 and the process terminates. If there is not a difference between the first and second overall times that is greater than the predefined threshold, No, control passes to step 2024 to continue the process.

[0084] Returning to step 2008, if the strapping configuration flag does not exist in the EEPROM, No, control passes to step 2026, in which both the first system board and second system board read the strapping settings and determine a first coarse time delay time and a second coarse time delay time, respectively, by using a stored mathematical equation. Step 2028 compares the first coarse time delay time and the second coarse time delay time. Step 2030 determines if there is more than a predefined threshold variation between the first coarse time delay time and the second coarse time delay time. If there is, Yes, control passes to a fault state 2032. Fault state is defined as being a critical fault state, so the system blows fuses to place the relay in a safe state. If there is not, No, control passes to step 2034, in which the first and second systems both write the higher value of the first coarse time delay time and the second coarse time delay time into the respective EEPROMs.

[0085] In step 2036, the first and second systems write the strapping configuration flag into the respective EEPROMs and control passes to step 2010.

[0086] Figure 21 is a flow diagram of a method 2100 for resetting a relay. The method 2100 starts with the main loop 2110. Step 2120 determines if one or more fault -reset pads / switches on a display board module are connected. If Yes, control passe to step 2130, which clears the strapping configuration flag from the EEPROMs on the first and second system boards. Control passes from step 2130 to step 2140 to continue the main loop. If Step 2120 determines that there are no pads / switches connected, No, control passes directly from step 2120 to step 2140.

[0087] In some embodiments, the ADC and microcontroller are optionally integrated in a single integrated circuit, as illustrated by the dotted line surrounding the ADC 280 and microcontroller 285 in Figure 2. For example, the ATmega324PB is an Advanced Virtual RISC (AVR) microcontroller from MicrochipTechnology Incorporated that incorporates an ADC and a microcontroller and is suitable for use in various embodiments of the present disclosure. For such embodiments, it will be appreciated that any suitable microcontroller with a built-in ADC may be utilised.

[0088] In some embodiments, ADCs with a resolution of at least 10 bits are utilised, such as in the integrated ADC present in the ATmega324PB chip. In other embodiments, ADCs with a resolution in the range of 4 to 64 bits are utilised, with some embodiments using 4 bits, 8 bits, 12 bits, 14 bits, 24 bits, 28 bits, 32 bits, or 64 bits. The greater the number of bits used in the analogue to digital conversion, the finer the resolution. It will be appreciated that any suitable resolution can be utilised, depending on the particular application and depending on the availability of particular ADCs.

[0089] In other embodiments, the ADC and microcontroller are discrete components.

[0090] In the example of Figure 2, the microcontroller 285 is coupled to a visual display 290 for displaying the time delay. In some embodiments, the visual display 290 is a sevensegment LED display that displays the time delay, wherein the microcontroller 285 utilises a timer to decrement the time delay displayed on the visual display 290 as time passes. Depending on the implementation, the LED display can include any number of sevensegment LED display units, each capable of displaying a single integer value. The LED display shows the remaining time delay in accordance with a predefined resolution, such as seconds, tenths of a second, hundredths of a second, milliseconds, or a combination thereof.

[0091] Some embodiments relate to a time delay greater than 99.9 seconds and utilise three seven-segment LED display units and a 1 second resolution (e.g., 125, 195, 307, etc.) Other embodiments relate to a time delay of 99.9 seconds or less and utilise three seven-segment LED display units and a 0.1 second resolution (e.g., 13.5, 26.9, 58.4, etc.). Further embodiments relate to a time delay of 99.9 seconds or less and utilise four seven-segment LED display units and a 0.01 second resolution (e.g., 13.15, 26.69, 58.24, etc.)

[0092] Each strapping combination corresponds to a specific entry in the look-up table, where an analogue voltage is converted into a time delay. The time delay is determined immediately after the application of power and is indicated on the display. This provides an installer with instant visual feedback as to the strapping configuration, without the need to wait until the time expires, thus reducing installation time and effort. The original electromechanical relay was not able to provide any visual indication of the time remaining.

[0093] Electromechanical time delay relays, such as that described above with reference to Figure 1, use external straps and an internal potentiometer to adjust the time delay. The external straps provide separate coarse and fine adjustments of the time delay, but due to inherent component tolerances, the exact time delay could not always be met. A potentiometer, internal to the relay, was provided to allow a technician to precisely adjust the time. Adjusting the internal potentiometer requires some disassembly of the relay and may require particular tools and / or expertise of the technician.

[0094] The electronic time delay relay of the present disclosure does not use a potentiometer for fine adjustment, thereby ameliorating the issues associated with the internal potentiometer of electromechanical relays. In the example of Figure 2, the microcontroller is optionally associated with a bank of one or more discrete switches 295 to allow precise adjustment of the time delay. The bank of switches may be implemented, for example, using dual in-line (DIP) switches, jumper blocks, or the like, or any combination thereof. Software running on the microcontroller 285 reads the settings from the bank of discrete switches 295 to allow a precise adjustment of the fine time delay. The position of the switches 295 provides a visual indication of the fine time delay, without the need to power on the relay.

[0095] An electromechanical relay uses what is known as a stick contact to abort the time delay. This allows the installer to test that the signalling contacts would change state without having to wait until the time had expired. The installer would temporarily connect a pair of dedicated contacts together, effectively by-passing the charging capacitor. This meant thatthe relay would switch immediately, regardless of the resistance value set using the strapping.

[0096] The electronic relay also provides a stick contact feature, but it does not incorporate a timing capacitor. The pair of dedicated contacts are configured as a digital abort switch input to the microcontroller. Software running on the microcontroller detects when the abort switch is closed, causing the software to abort the time delay and switch the conventional front and back signalling contacts immediately. Front signalling contacts are normally open (NO) and back signalling contacts are normally closed (NC). The front and back signalling contacts will be described in greater detail later in this document.

[0097] Figure 3A is a schematic representation of a strapping detection circuit 300. The circuit 300 includes a set of time delay adjustment resistors 320, wherein each resistor is associated with a corresponding pair of strapping pins or contacts. By installing a strap, such as a short length of conductor, between the strapping pins, an installer sets a time delay to be applied by the relay. For the particular example of Figure 3, the adjustment resistors and the associated strapping pins are set out in Table 1 below:Table 1

[0098] A precision input voltage VCC0 is presented to a resistor R148, being 330Q. The resistor R148 is coupled to a reverse biased Zener diode U107, which is coupled to ground. A resistor R102 is connected to the node between the resistor R148 and the diode U107. The resistor R148 is connected in series to the set of adjustment resistors 320. The set ofadjustment resistors is connected in series to a resistor R164, being I MQ, which connects to ground. A resistor R163, being 0.1Q, is connected to the node between the resistor R147 and resistor R164. Resistor R 163 is coupled to a pin STR_ADC0, which presents an output analogue voltage to an ADC, which in turn presents a digital output as input to the microcontroller 285 in order to determine the time delay implemented by the strapping(s) applied to the adjustment resistors 320.

[0099] Figure 3B is a graph of 1 / Vout vs. time. As described above, the microcontroller receives a voltage from an ADC and utilises the received voltage as an input parameter (x) to a mathematical equation to calculate the associated time delay. In the example of Figure 3B, the mathematical equation is a linear equation in the form of y = 0.0104x + 0.2193. Alternative embodiments use a 16-bit input / output (I / O) expander, which is a separate integrated circuit that expands the number of pins available on the microcontroller. In such embodiments, the strapping contacts are coupled to the VO expander and the VO expander is, in turn, coupled to the microcontroller via an inter-integrated circuit (I2C) bus.

[0100] As described above, embodiments of the electronic time delay relay utilise a precision voltage reference to improve the precision of the determined time delay. Using a precision voltage reference makes analogue measurements independent of any variations in vcc.

[0101] Figure 4A is a circuit diagram of an ADC analogue reference. In the example of Figure 4, the reference voltage is 4.096V. Figure 4B is a circuit diagram illustrating an analogue voltage AVCC0 and an analogue reference signal AREF0 being presented as inputs to an AVCC module. The AVCC PE4 pin is a separate analogue voltage supply input to the microcontroller. The analogue and digital power supplies are preferably separated to reduce the impact of digital switching noise from affecting the analogue voltage reading.

[0102] Figure 5 shows circuit schematics relating to implementation of a status LED display for showing the time delay. In the example of Figure 5, GPIO pin 19 on the microcontroller 285 is routed to the display board connector and the A / D status LEDs on the display board are driven by software executing on the system microcontroller. In some embodiments, the LEDs of the status LED display are active high (write 1 to turn on), in order to eliminate the possibility of a faulty LED dragging down VCC.

[0103] Figure 6 is schematic representation of a circuit for implementing a bank of switches for fine tuning the time delay of an electronic time delay relay. As described above,the bank of switches may be implemented using a set of DIP switches. The state of the bank of switches is read by the microcontroller, which utilises a look-up table stored in a computer-readable storage medium to determine a fine delay value corresponding to the read state. In some embodiments, the look-up table is stored in memory of the same chip as the microcontroller, such as ROM or RAM. In particular implementations, the mathematical equation and look-up table are stored in FLASH memory on the microcontroller. In other embodiments, one or more of the mathematical equation(s) and the look-up table are stored in external memory that the microcontroller accesses. The microcontroller adds the fine delay value to the coarse delay value calculated from the strapping to determine a total (z.e., overall) time delay for a current setting of the time delay relay.

[0104] In the example of Figure 6, the bank of switches is implemented using a set of 8 DIP switches SW0... SW7, which are connected to pins P0...P7, respectively, of an 8-bit GPIO expander 650, which in the example of Figure 6 is implemented using the PCA9545APW,118 by NXP USA Inc. In this particular example, internal pull up resistors are enabled. The GPIO expander 650 is a dedicated chip that is utilised to increase the number of I / O pints available to the microcontroller. In this example, there are 8 pins P0.. ,P7 that are read by the GPIO expander 650.

[0105] Each of the DIP switches SW0. . . SW7 has an open position and a closed position. The GPIO expander 650 determines the positions of the respective switches SW0... SW7 and presents outputs SCL0 and SDA0 as inputs to the microcontroller. Such an arrangement allows a microcontroller with fewer inputs to be used, yet the number of input pins available can be increased as required by using one or more GPIO expanders. As will be appreciated, different combinations of switches, GPIO expanders, and microcontrollers can be utilised.

[0106] Alternative embodiments utilise GPIO pins on a microcontroller to determine the DIP switch setting.

[0107] Figure 7 is a circuit diagram of a driver for a seven-segment LED driver. A 24-bit GPIO expander 750 is utilised to drive first, second, and third LED displays 760a, 760b, 760c. Each segment of each of the displays 760a, 760b, 760c is driven from a dedicated IO port of the expander 750, without requiring any multiplexing. In the example of Figure 7, the IO expander is addressed via an I2C bus from the microcontroller 285. As described above, the resolution of the numbers displayed by the LED displays 760a, 760b, 760c depends on the particular application.

[0108] Alternative embodiments utilise multiplexed GPIO pins on a microcontroller to drive a seven- segment LED display.

[0109] Figure 8 is a circuit for a fault reset. In this embodiment, GPIO pin 20 of the microcontroller 285 is routed to a display board connector and one or more pads or switches are made available to enable a user to clear a fault condition. Such pads or switches may be placed, for example, on top of the display board. In the circuit of Figure 8, an internal, software -programmable pull up resistor is provided.

[0110] In some embodiments, an electronic time delay relay is implemented using two system boards. Two system boards, each equipped with a microcontroller, can be used to provide a composite, fail-safe relay and to perform diagnostic analysis of the other board. Each system board has an I2C bus and the I2C bus from each of the respective system boards is coupled to the display board. Figure 9 is a circuit diagram of an I2C header 950 that is used to connect two system boards in such embodiments. In the example of Figure 9, the I2C header is implemented using the TSM-110-01-T-DH-A chip from Samtec. Outputs I2C SDA (data) and I2C SDL (clock) connect the I2C header 950 to the I2C bus of a system board.

[0111] Figure 10 illustrates circuitry associated with MOSFETs, wherein the circuitry includes pull-down resistors that blow the safe state fuse, ensuring that the MOSFETs are always in an off condition at power on.

[0112] Figure 11 is a circuit diagram of filter inductors placed in series with resistors R1 and R2, respectively, at the front end of the power supply.

[0113] Figures 12A and 12B are schematic representations of copper track layouts. Figure 12A shows a copper track 0.475mm from the edge of a printed circuit board, whereas Figure 12B shows a copper track placed 0.7mm from the edge of printed circuit boards.Modular Construction

[0114] Some embodiments of the electronic time delay relay include a combination of modules to implement a composite, fail-safe solid state relay. The modules include: a base module, a first system module, a second system module, a high current field-effect transistor (FET) module, and a display module. The first system board is configured to activate a first set of solid state contacts and to check a second set of solid state contacts. The second system board is configured to activate the second set of solid state contacts and to check the first set of solid state contacts. Each individual contact is driven by a corresponding activation input,wherein software executing on microcontrollers on the respective system boards controls the state of the contacts.

[0115] Some embodiments are compatible with a Q-style form-factor plug board and are shaped to prevent incorrect insertion.

[0116] Some embodiments include a housing to protect the modules of the relay. In some implementations, the housing is perforated to enable a user to view inside the relay. A perforated housing also enables the dissipation of heat. In implementations in which the housing is metal, the housing acts as a Faraday cage to reduce external electromagnetic radiation from affecting the relay. In some embodiments, some or all of the housing has a rating of IP20 or above. In some embodiments, the housing includes one or more transparent regions to enable a user to view inside the relay, thus facilitating visual performance assessment.

[0117] Some embodiments utilise a “two-out-of-two voting” (2oo2) architecture, also referred to as “2 on 2”, that uses two separate processors to provide a fault-tolerant system. In such a system, both of the processors must separately activate a respective output signal to change the state of the relay contacts. If only one of the processors activates an output signal, then the relay contacts do not change state.

[0118] Further, embodiments that utilise two system boards are able to check the accuracy of calculated time delays, based on strapping and switch positions. Each system board includes a microcontroller that calculates a time delay. The two system boards then compare the calculated respective time delays. If there is a discrepancy between the time delays calculated by the respective microcontroller, then the display indicates an error and the relay will not change the state of the contacts, thus defaulting to a safe state.

[0119] Figure 13 A is a schematic block diagram representation of an architecture of a solid state time delay relay 1300. In the example of Figure 13 A, the architecture shown is of a composite, fail-safe solid state time delay relay 1300. The relay 1300 includes a base board 1340. In the example of Figure 13A, the base board 1340 includes three female back plane connectors 1342, 1344, 1346 for coupling to a first system board 1320, a second system board 1330, and a high current FET driver board 1350. The base board 1340 also includes a coil contact 1348, a stick contact 1352, a set of strapping contact pins 1354, and a set of relay contacts 1356. The respective states of the set of relay contacts 1356 is controlled bythe FET driver board 1350, which receives an activation signal corresponding to each relay contact from each of the first system board 1320 and the second system board 1330.

[0120] The first system board 1320 and second system board 1330 are mounted on separate, electrically isolated plug-in cards to provide a composite, fail-safe relay system, wherein both system boards 1320, 1330 need to be active and working correctly for the overall relay system to operate. The first system board 1320 and the second system board 1330 each include a power supply, a microcontroller, contact feedback monitoring circuitry, FET drivers, and circuitry to blow a fuse to ensure that the relay 1300 fails in a permanent safe state. The first system board 1320 and second system board 1330 are coupled to enable communication therebetween. In the example of Figure 13A, the first and second system boards 1320, 1330 are coupled via the back plane on the base board.

[0121] Further, each of the first and second system boards 1320, 1330 is coupled to a display module 1310 and to the high current FET board 1350. In particular, the display module 1310 includes a first header 950a and a second header 950b. The first header 950a couples the display board 1310 to a third header 950c on the first system board 1320 and the second header 950b couples the display board 1310 to the second system board 1330.

[0122] Figures 13D to 13N are expanded views of portions of the system architecture of Figure 13A. Figure 13B is a legend showing the relationships among Figures 13D to 13N relative to Figure 13A. Figure 13C is a legend for Figures 13D to 13N.

[0123] Figure 14 is a schematic block diagram representation of the functional modules of the first system board 1320. The first system board 1320 includes a microcontroller 1410, an optically isolated UART 1420, an optically isolated contact feedback module 1430, a strapping detection module 1440, a power supply 1450, a fuse 1460, and a boost module 1470. The functional modules of the second system board 1330 are identical to those of the first system board 1320.

[0124] The microcontroller 1410 is programmed to activate the output contacts and monitor the feedback voltage to detect failures. Software executing on the microcontroller 1410 ensures that all normally closed back contacts are open before closing the normally open front contacts. The software prevents any normally open contact from closing while a normally closed contact is closed. Similarly, the software prevents any normally closed contact from closing while a normally open contact is closed. This provides break-before-make functionality. The software operates to ensure that the contacts changestate within a maximum predefined time period. The maximum predefined time period may be, for example, in the range of 1ms to 1 second, or preferably in the range of 1ms to 100ms, or more preferably, in the range of 1ms to 20ms, such as 10 milliseconds. The microcontroller switches the relay to a pre-defined safe state upon the detection of a failure.

[0125] The microcontroller 1310 is clocked from an external crystal oscillator and uses an internal analogue reference for the ADC inputs. Two of the Port A pins (PA2 and PA3) are used as analogue inputs to monitor the coil voltage in order to determine at which voltage levels the relay contacts should be activated or deactivated. Once the coil voltage exceeds the activation voltage, normally closed contacts shall open and normally open contacts shall close. When the coil voltage falls below the deactivation voltage, normally open contacts shall open and normally closed contacts shall close.

[0126] The time delay for the relay 1300 of Figure 13A may be implemented using any suitable time delay unit and associated time delay controls, as described above. In some embodiments, the time delay unit is implemented using the strapping illustrated and described with reference to Figure 2 and Figure 3A. In such embodiments, an installer connects a short length of cable to act as a strap between contacts, wherein each contact is connected to an analogue resistor chain. Software executing on the microcontroller 1410 determines which strapping configuration has been set, based on a received voltage. Each system board 1320, 1330 determines the strapping and consequent time delay and communicates the determined time delay to the other board to ensure that both system boards 1320, 1330 has configured the same time delay.

[0127] Figure 15 is a schematic block diagram representation of the functional modules of the display module 1310 of Figure 13A. The purpose of the display board is to provide a visual indication of the real-time status of the relay. The display module 1310 includes a 7-segment LED module 1510, which is coupled to a first I2C I / O expander 1520. The first I2C I / O expander 1520 is coupled to the first system board 1320 via the first header 950a. In the example of Figure 15, the first I2C I / O expander 1520 is implemented using a 24-Bit I2C-bus I / O Expander in the form of the KTS1620 integrated circuit from Kinetic Technologies.

[0128] The display module 1310 also includes a first set of DIP switches 1530, which is coupled to a second I2C I / O expander 1540. The second I2C I / O expander 1540 is coupled to each of 8 switch outputs from the first set of DIP switches 1530. The second I2C I / Oexpander 1540 is also coupled to VCCO and GNDO, as well as SDA and SCL outputs of the first I2C I / O expander.

[0129] The display module 1310 also includes a second set of DIP switches 1550, which is coupled to a third I2C I / O expander 1560. The third I2C I / O expander 1560 is coupled to each of 8 switch outputs from the second set of DIP switches 1550. The third I2C I / O expander 1560 is also coupled to the second system board 1330, via the second header 950b. The settings of the first set of DIP switches 1530 and the second set of DIP switches 1550 must agree, otherwise the system generates a fault. In some embodiments, the system generates a fault by blowing a fuse on each of the system boards 1320, 1330, wherein the respective fuses are part of circuits that provide power to the FET board 1350. When the fuses blow, no power can be provided to the relevant part of the FET board 1350, resulting in the contacts defaulting to a power-off state and the contacts being unable to switch again until the blown fuses are replaced. In some embodiments, the display board indicates the fault by flashing the status LEDs. In some embodiments in which the display module 1310 is implemented using a seven-segment LED matrix, the message ‘Err’ is displayed.

[0130] In the example of Figure 15, each of the second and third I / O expanders 1540, 1560 is implemented using a PCA9554 integrated circuit, such as the PCA9544 by Texas Instruments.

[0131] In some embodiments, the display module 1310 optionally includes two visual status indicators, such as LEDs, corresponding to the first system board 1320 and the second system board 1330, to indicate a relay picked status. A “picked state” is when all back contacts are open and all front contacts are closed. The picked state is the operation state of a relay when sufficient power has been applied and any initial time delay has expired.

[0132] The LED display 1510 indicates the remaining pick delay time. When coil power is applied to the relay, system software executing on the microcontrollers of the respective first and second system boards 1320, 1330 determine the strapping and set the appropriate pick delay. This pick delay value is sent via I2C to the display module 1310, which counts down the remaining time on the display. Once the pick delay time has expired, the status LEDs change to the picked state. The operation of the visual display is considered non-safety related. If the display fails to operate correctly, the relay should still pick and drop as expected.

[0133] Figure 16 is a schematic block diagram representation of the high current FET driver board 1350 of Figure 13A. The FET driver board 1350 is coupled to each of the first system board 1320 and the second system board 1330. The FET driver board 1350 is coupled to VCCO_SAFE and VCC1_SAFE, which are “fused” power rails from the first and second system boards 1320, 1330. In the event of a fault, the fuses are blown, thus disconnecting all power from the FET driver board 1350. Consequently, the contacts are latched into a default safe state.

[0134] In some embodiments, each of the relay contacts 1356 is associated with a corresponding set of two pairs of MOSFETs in series (4 in total), wherein each microcontroller drives one pair of MOSFETs. This is the same regardless of whether it is a front or back contact. In the example of Figure 13A, the set of relay contacts 1356 includes seven relay contacts. Five of the relay contacts 1356 are front contacts (normally open). Figure 17 illustrates one embodiment of a suitable front contact that includes four enhancement mode MOSFETs wired in series. Two of the relay contacts 1356 are back contacts (normally closed). Figure 18 illustrates one embodiment of a suitable back contact that includes four depletion mode MOSFETs wired in series.

[0135] In this example, The FET driver board 1350 in the example of Figure 16 includes seven drivers 1610, 1620, 1630, 1640, 1650, 1660, 1670. Each driver 1610... 1670 controls a corresponding contact in the set of relay contacts 1356. Figure 19 illustrates connections between each of the drivers 1610... 1670 and the set of relay contacts 1356 of Figure 13A. A first driver 1610 controls a first back contact 1910, a second driver 1620 controls a second back contact 1920, a third driver 1630 controls a first front contact 1930, a fourth driver 1640 controls a second front contact 1940, a fifth driver 1650 controls a third front contact 1950, a sixth driver 1660 controls a fourth front contact 1960, and a seventh driver 1670 controls a fifth front contact 1970.

[0136] The first driver 1610 receives a first activation input from the first system board 1320 and a second activation input from the second system board 1330. As the system of Figure 13A is a composite, fail-safe system, each contact is driven by two separate microcontroller systems residing on the first system board 1320 and the second system board 1330, respectively. The first driver 1610 is coupled to a back contact 1910. As described above, the back contacts are normally closed, so the driver 1610 may be embodied using the arrangement of Figure 18. Only when both the first and second activation inputs are highdoes the driver 1610 change the state of the contact 1910. Similar arrangements are implemented for the other driver / contact combinations.Industrial Applicability

[0137] The arrangements described are applicable to the electronic, transport, and railway industries.

[0138] The foregoing describes only some embodiments of the present invention, and modifications and / or changes can be made thereto without departing from the scope and spirit of the invention, the embodiments being illustrative and not restrictive.

[0139] Further advantages and improvements may very well be made to the present invention, without deviating from its scope. Although the invention has been shown and described in what is considered to be the most practical and preferred embodiment(s), it is recognized that departures may be made therefrom within the scope and spirit of the invention, which is not to be limited to the details disclosed herein, but is to be accorded the full scope of the Claims, so as to embrace any and all equivalent devices and apparatus. Any discussion of the prior art throughout the Specification should in no way be considered as an admission that such prior art is widely known, or forms part of the common general knowledge in this field.

[0140] Reference throughout this specification to “one embodiment”, “an embodiment,” “some embodiments”, or “embodiments” means that a particular feature, stmcture or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may be. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0141] While some embodiments described herein include some, but not other, features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0142] Furthermore, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computersystem or by other means of carrying out the function. Thus, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the invention.

[0143] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practised without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0144] Note that when a method is described that includes several elements, e.g., several steps, no ordering of such elements, e.g., of such steps, is implied, unless specifically stated.

[0145] In the context of this specification, the word “comprising” and its associated grammatical constructions mean “including principally, but not necessarily solely” or “having” or “including”, and not “consisting only of’. Variations of the word "comprising", such as “comprise” and “comprises” have correspondingly varied meanings.

[0146] Similarly, it is to be noticed that the term “coupled” should not be interpreted as being limitative to direct connections only. The terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other, but may be. Thus, the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems, wherein an input or output of device A is directly connected to an output or input of device B . It means that there exists a path between device A and device B, which may be a path including other devices or means in between. Furthermore, “coupled to” does not imply direction. Hence, the expression “a device A is coupled to a device B” may be synonymous with the expression “a device B is coupled to a device A”. “Coupled” may mean that two or more elements are either in direct physical or electrical contact, or that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0147] As used throughout this specification, unless otherwise specified, the use of ordinal adjectives "first", "second", "third", “fourth”, etc., to describe common or related objects, indicates that reference is being made to different instances of those common or related objects, and is not intended to imply that the objects so described must be provided orpositioned in a given order or sequence, either temporally, spatially, in ranking, or in any other manner.

[0148] Although the invention has been described with reference to specific examples, it will be appreciated by those skilled in the art that the invention may be embodied in many other forms.

Claims

AMENDED CLAIMS received by the International Bureau on 18 September 2024 (18.09.2024)We claim:

1. An electronic time delay relay comprising: a set of timing resistors arranged in a series circuit between a first, input node and a second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a set of contacts; a microcontroller configured to receive as an input said digital output voltage, said microcontroller including: a processor; and storage means for storing a mathematical equation and computer-readable instructions that when executed on the processor perform the steps of: utilising said digital output voltage as an input parameter to said mathematical equation to calculate a time delay implemented by the positioning of each said strap; and changing the state of at least one of said contacts when said time delay expires.

2. The electronic time delay relay of claim 1, wherein said voltage input is a precision voltage input.

3. The electronic time delay relay of either one of claim 1 or claim 2, wherein said set of timing resistors includes: a set of coarse timing resistors and an associated coarse adjustment strap, wherein positioning of said coarse adjustment strap defines a coarse adjustment electrical path including at least one of said coarse timing resistors; and a set of fine timing resistors and an associated fine adjustment strap, wherein positioning of said fine adjustment strap defines a fine adjustment electrical path including at least one of said fine timing resistors.AMENDED SHEET (ARTICLE 19)4. The electronic time delay relay of claim 3, wherein there are 13 coarse timing resistors and 2 fine timing resistors.

5. The electronic time delay relay of either one of claim 3 or claim 4, wherein the timing resistors have resistances in the range of 220kQ to 1MQ.

6. The electronic time delay relay of any one of claims 1 to 5, further comprising: a fine-tuning adjustment including a bank of at least one user-selectable switch.

7. The electronic time delay relay of claim 6, wherein said fine tuning adjustment includes a bank of DIP switches.

8. The electronic time delay relay of either one of claims 6 and 7, wherein: said storage means further stores a look-up table providing an association between permutations of the positions of each user- selectable switch and a corresponding fine time delay; and said computer-readable instructions when executed on the processor perform the further steps of: receiving switch values for each user-selectable switch; determining a fine time delay value based on said received switch values and said look-up table; and adding said fine time delay to said calculated time delay to determine an overall time delay.

9. The electronic time delay relay of any one of claims 1 to 8, further comprising: a visual display configured to display said determined time delay.

10. The electronic time delay relay according to claim 9, wherein said visual display is selected from the group consisting of: seven-segment LED display, LCD screen, or LED screen.AMENDED SHEET (ARTICLE 19)11. The electronic time delay relay according to either one of claim 9 or claim 10, wherein said microcontroller is programmed to control the visual display, said microcontroller decrementing a displayed time as time passes.

12. The electronic time delay relay according to any one of claims 9 to 11, wherein said visual display includes a plurality of seven-segment LED displays.

13. The electronic time delay relay of any one of claims 1 to 12, further comprising: diagnostic software executing on said microcontroller to determine a fault status of the relay.

14. The electronic time delay relay of any one of claims 1 to 13, wherein: said set of contacts is associated with a corresponding set of FET drivers, wherein an activation signal received by one of said FET drivers causes a change of state of a corresponding contact.

15. A composite, fail-safe electronic time delay relay comprising: a set of relay contacts and a corresponding set of activation inputs; a set of timing resistors arranged in a series circuit between a first, input node and a second, output node, at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between a first input node and a second output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; a voltage input providing an input voltage to said first input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said set of timing resistors and outputting a digital output voltage; a high current FET board for controlling states of the respective relay contacts, based on states of the respective activation inputs; a first system board that includes: a first microcontroller configured to receive as an input said digital output voltage, said first microcontroller including: a first processor; andAMENDED SHEET (ARTICLE 19)first storage means for storing a mathematical equation and computer- readable instructions that when executed on the first processor perform the steps of: utilising said digital output voltage as an input parameter to said stored mathematical equation to calculate a first coarse time delay implemented by the positioning of each said strap; and determining a first total time delay based on said first coarse time delay; a second system board that includes: a second microcontroller configured to receive as an input said digital output voltage, said second microcontroller including: a second processor; and second storage means for storing said mathematical equation and computer-readable instructions that when executed on the second processor perform the steps of: utilising said digital output voltage against as an input parameter to said stored mathematical equation to calculate a second coarse time delay implemented by the positioning of each said strap; determining a second total time delay based on said second coarse time delay; and a display module for displaying an overall time delay based on said first total time delay and said second total time delay; wherein, upon detection of an activation voltage at one of said activation inputs, said first microcontroller and said second microcontroller detect said activation voltage and send a corresponding activation signal to said FET board to change the state of a contact associated with the activation input to which the activation voltage was applied.

16. The relay of claim 15, wherein: the first system board further includes a first fine adjustment device, wherein the first microcontroller reads the first fine adjustment device to determine a fine time delay and adds the first fine time delay to the first coarse time delay to determine said first total time delay; andAMENDED SHEET (ARTICLE 19)the second system board further includes a second fine adjustment device, wherein the second microcontroller reads the second fine adjustment device to determine a second fine time delay and adds the second fine time delay to the second coarse time delay to determine said second total time delay.

17. The relay of claim 16, wherein each of the first fine adjustment device and the second fine adjustment device is implemented using a bank of switches, wherein the bank of switches is implemented using at least one of dual in-line (DIP) switches, and jumper blocks.

18. The relay of claim 16, wherein said first and second system boards communicate with each other to confirm the accuracy of the determined time delay by utilising software executing on the first microcontroller and the second microcontroller to comparing the first total time delay and the second total time delay, wherein the overall time delay corresponds to one of the first total time delay and the second total time delay when the difference between the first total time delay and the second total time delay is within a predefined margin for error.

19. The relay of claim 18, wherein the first microcontroller blows a first fuse on the first system board when the first microcontroller determines that the first total time delay and the second total time delay differ by more than said predefined margin for error.

20. The relay of claim 18, wherein the second microcontroller blows a second fuse on the second system board when the second microcontroller determines that the first total time delay and the second total time delay differ by more than said predefined margin for error.

21. The relay of any one of claims 15 to 20, wherein: the first system board further includes a first fuse configured to blow when an error state occurs on said first system board; and the second system board further includes a second fuse configured to blow when an error state occurs on said second system board; and further wherein the FET board returns each of the relay contacts to a default safe state when at least one of the first fuse or the second fuse blows.AMENDED SHEET (ARTICLE 19)22. The relay of any one of claims 15 to 21, wherein said high current FET board includes a set of two pairs of MOSFETs in series for each relay contact, wherein the first microcontroller controls a first pair of MOSFETs for each relay contact and the second microcontroller controls a second pair of MOSFETs for each relay contact, and wherein when the first microcontroller activates the first pair of MOSFETs for a particular relay contact and the second microcontroller activates the second pair of MOSFETs for that particular relay contact, then the FET board changes the state of that particular relay contact.

23. The relay of any one of claims 15 to 22, wherein the set of relay contacts includes at least one normally open contact and the FET board includes at least one enhancement mode MOSFET associated with each normally open contact.

24. The relay of any one of claims 15 to 23, wherein the set of relay contacts includes at least one normally closed contact and the FET board includes at least one depletion mode MOSFET associated with each normally closed contact.

25. An electronic time delay relay comprising: a time delay unit with an associated set of time delay controls, said time delay unit being positioned between a first, input node and a second, output node; a set of contacts; a microcontroller including a processor; and storage means for storing computer-readable instructions that when executed on the processor perform the steps of: determining an overall time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; upon receipt of an activation control corresponding to one of said contacts, changing the state of that contact when said determined overall time delay expires; wherein said electronic time delay relay further comprises: a display unit for displaying said determined time delay; andAMENDED SHEET (ARTICLE 19)wherein said time delay controls include at least one of: a set of resistors and associated strappings; a General Purpose Input / Output (GPIO); a bank of switches; and a voltage input providing an input voltage to said first, input node; an analogue to digital converter (ADC) for receiving an analogue output voltage from said time delay unit at said second, output node and outputting a digital output voltage.

26. The electronic time delay relay according to claim 25, wherein said time delay controls include a set of timing resistors arranged in a series circuit between said first, input node and said second, output node; at least one strap for selecting a subset of said timing resistors to provide an electrical pathway between said first, input node and said second, output node, wherein positioning of each said strap determines a voltage drop across said set of timing resistors; and further wherein said computer-readable instructions, when executed on the processor perform the further step of: determining a first coarse time delay associated with said set of timing resistors by utilising said digital output voltage derived from said second, output node as an input to one of: a first look-up table stored in said storage means; and a mathematical equation, wherein said overall time delay is based on said first coarse time delay.

27. The electronic time delay relay according to claim 26, wherein said mathematical equation is selected from the group consisting of: linear equation; quadratic equation; cubic equation; and quartic equation.

28. The electronic time delay relay according to any one of claims 25 to 27, wherein said time delay controls include a GPIO positioned between said first, input node and said second, output node, and further wherein said computer-readable instructions, when executed on the processor perform the further steps of: determining a second coarse time delay associated with said GPIO by utilising said digital output voltage as an input to a second look-up table stored in said storage means, wherein said overall time delay is based on said second coarse time delay.

28. The electronic time delay relay according to any one of claims 25 to 27, wherein:AMENDED SHEET (ARTICLE 19)said time delay controls include bank of switches; said storage means further stores a third look-up table providing an association between permutations of the positions of each switch and a corresponding fine time delay; and further wherein said computer-readable instructions, when executed on the processor perform the further step of: receiving switch values for each user-selectable switch; and determining a fine time delay value based on said received switch values and said third look-up table, wherein said overall time delay is based on said fine time delay.

29. The electronic time delay relay of claim 28, wherein said bank of switches includes at least one bank of DIP switches.

30. A composite, fail-safe electronic time delay relay comprising: a set of relay contacts and a corresponding set of activation inputs; a time delay unit with an associated set of time delay controls, said time delay unit being positioned between a first, input node and a second, output node; a high current FET board for controlling states of the respective relay contacts, based on states of the respective activation inputs; a first system board that includes: a first microcontroller including: a first processor; and first storage means for storing computer-readable instructions that when executed on the first processor perform the steps of: determining a first total time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; a second system board that includes: a second microcontroller configured to receive as an input said digital output voltage, said second microcontroller including: a second processor; and second storage means for storing computer-readable instructions that when executed on the second processor perform the steps of:AMENDED SHEET (ARTICLE 19)determining a second total time delay for the relay as set by the time delay controls by utilising one or more mathematical equations, one or more look-up tables, or any combination thereof; a display module for displaying an overall time delay based on said first total time delay and said second total time delay; wherein, upon detection of an activation voltage at one of said activation inputs, said first microcontroller and said second microcontroller detect said activation voltage and send a corresponding activation signal to said FET board to change the state of a contact associated with the activation input to which the activation voltage was applied, once the overall time delay has expired.AMENDED SHEET (ARTICLE 19)

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