Semiconductor structures

Abstract

A semiconductor structure 200 comprising: a first semiconductor layer 110 (e.g. SiC substrate); a second semiconductor layer 115 (e.g. AlN nucleation layer); and an interlayer region 210 (e.g. carbon

Description

Technical field The present application relates to semiconductor structures. The present application also relates to a semiconductor device, a radio frequency (RF) module, an electronic device and a method of forming a semiconductor device. Background Forming semiconductor devices from lll-N semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, lll-N semiconductor materials, such as GaN, possess desirable electronic and photonic properties, outperforming Si in many aspects. The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from lll-N materials. lll-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of lll-N HEMTs has therefore found use in power and radio frequency (RF) communications applications. HEMTs exhibit high electron mobility due to the formation of a two-dimensional electron gas (2DEG) in the channel layer of the HEMT. Typically, an AIGaN barrier layer is formed over a GaN channel layer. The AIGaN barrier layer induces the formation of a 2DEG in the GaN channel layer. The formation of a HEMT typically involves the epitaxial growth of lll-N semiconductor layers on a substrate. For example, a lll-N barrier layer and lll-N channel layer are formed on the substrate using an epitaxial growth technique, such as molecular beam epitaxy (MBE) or metal organic chemical vapour deposition (MOCVD). However, the epitaxial growth of the lll-N layers is typically a heteroepitaxial process where the substrate comprises a material, which is not a lll-N semiconductor. Common substrates for the epitaxial growth of lll-N HEMT layers include Si and SiC because these substrates are widely available of high quality and in larger diameters compared to lll-N substrates. The heteroepitaxial nature of the formation of the lll-N channel layer and lll-N barrier layer means that these layers are not formed directly on the substrate. If they were, the lll-N channel layer and lll-N barrier layer would be of poor quality and contain many defects. Instead, typically nucleation and buffer layers are first formed on the substrate. The nucleation and buffer layers provide a transition between the substrate, and the III-N channel layer and lll-N barrier layer, which minimise defects and improves the formation of the lll-N channel layer and lll-N barrier layer. Epitaxial processes for the formation of nucleation and buffer layers have developed to produce high quality lll-N HEMTs. However, the increasing demands of RF communication systems mean that further improvements in this technology are desired. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure comprising: a first semiconductor layer; a second semiconductor layer; and an interlayer region between the first semiconductor layer and the second semiconductor layer. The interlayer region comprises a bond energy higher than the first semiconductor layer and the second semiconductor layer. In some examples, the interlayer region comprises a first monolayer. In some examples, the first monolayer comprises C. In some examples, the interlayer region comprises a first element and the first semiconductor layer comprises the first element. In some examples, the interlayer region comprises a second monolayer. In some examples, the second monolayer comprises N. In some examples, the first semiconductor layer comprises a substrate and the second semiconductor layer comprises a nucleation layer. In some examples, the substrate comprises SiC and the nucleation layer comprises AIN. In some examples, the semiconductor structure further comprises a buffer layer over the nucleation layer; wherein the buffer layer comprises a thickness of less than or equal to 500 nm. In some examples, the interlayer region comprises a plurality of terraced steps. In some examples, a height between a pair of the terraced steps is between 0.5-1 nm. In some examples, the interlayer region comprises an interfacial region between the first semiconductor layer and the second semiconductor layer. According to a second aspect there is provided a semiconductor device comprising the semiconductor structure according to the first aspect. According to a third aspect there is provided a radio frequency module comprising the semiconductor device according to the second aspect. According to a fourth aspect there is provided an electronic device comprising the radio frequency module according to the third aspect. According to a fifth aspect there is provided a method of forming a semiconductor structure comprising: providing a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming an interlayer region between the first semiconductor layer and the second semiconductor layer comprising a bond energy higher than the first semiconductor layer and the second semiconductor layer. In some examples, forming the interlayer region comprises forming a first monolayer. In some examples, forming the first monolayer comprises annealing the first semiconductor layer. In some examples, forming the first monolayer comprises depositing a first element on the first semiconductor layer. In some examples, depositing the first element comprises releasing a precursor gas comprising a second element. In some examples, the first element comprises C and the second element comprises Al. In some examples, the method further comprises responsive to releasing the precursor gas, annealing the first monolayer. In some examples, forming the interlayer region further comprises forming a second monolayer. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a semiconductor structure; Figure 2 is another example of a semiconductor structure; Figure 3 is another example of a semiconductor structure; Figure 4 is another example of a semiconductor structure; Figure 5a-e are examples of process steps in a method of manufacturing a semiconductor structure; Figure 6 is an example of an atomic force microscopy (AFM) image. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition and where a crystalline structure of the grown material is defined by the underlying substrate. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metal-organic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out-of-plane is used to mean perpendicular to the surface of the substrate. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), silicon carbide (SiC), sapphire (AI2O3), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100 crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional techniques suffer from. Figure 1 is an example of a HEMT 100. HEMT 100 comprises a substrate 110 and a nucleation layer 115, a buffer layer 120, a channel layer 130 and a barrier layer 140 formed on the substrate 110. The nucleation layer 115, buffer layer 120, channel layer 130 and barrier layer 140 comprise semiconductor material. In one example, the nucleation layer 115 buffer layer 120, channel layer 130 and barrier layer 140 comprise lll-N semiconductor material. However, in other examples, the nucleation layer 115, buffer layer 120, channel layer 130 and barrier layer 140 comprise other lll-V materials such as GaAs-based materials. The buffer layer 120, channel layer 130 and barrier layer 140 may thus be epitaxially grown on the substrate 110. In some examples, the substrate 110 may comprise a material for the epitaxial growth of semiconductor material thereon, such as, Si, SiC, GaN or Sapphire. The nucleation layer 115 is configured to transition from the substrate 110 to the semiconductor materials forming the HEMT 100. In some examples, the nucleation layer 115 may comprise AIN. The buffer layer 120, is configured to eliminate defects and provide isolation between the substrate 110 and the channel layer 130 above the buffer layer 120. In some examples, the buffer layer 120 may comprise (AI)GaN. Channel layer 130 provides the channel in the HEMT 100 for charge carriers to flow. A 2-dimensional electron gas (2DEG) 132 is formed in the channel, which confines the electrons and results in the HEMT exhibiting high electron mobility properties. The 2DEG 132 is formed in the channel layer 130 due to a polarization discontinuity between the barrier layer 140 and the channel layer 130. In some examples, the channel layer 130 comprises GaN and the barrier layer 140 comprises AIGaN. HEMT 100 further comprises a source electrode 150, a drain electrode 160 and a gate electrode 170. As illustrated in Figure 1, the 2DEG 132 is continuous between the source electrode 150 and the drain electrode 160. As such, with no bias voltage applied to the gate electrode 170, the formation of the 2DEG 132 results in current flow between the source electrode 150 and drain electrode 160. A negative bias voltage is applied to the gate electrode 170 to turn the HEMT 100 to the ‘off’ state where the formation of the 2DEG is interrupted. As described above, the nucleation layer 115 and buffer layer 120 are included to minimize defects and enable the epitaxial formation of a high-quality channel layer 130 and barrier layer 140 on substrate 110. In particular, the nucleation layer 115 and buffer layer 120 are configured to comprise high crystallinity and provide a smooth surface with low detectivity for the formation of the channel layer 130 and barrier layer 140, thereon. Conventionally, to form a channel layer 130 and barrier layer 140, which has high crystallinity and a smooth surface, a thick buffer layer 120 is formed. The buffer layer 120 may comprise a thickness of 800 nm or more. At this thickness, defects present at the substrate 110 surface are gradually reduced along the growth direction of the thick buffer layer 120 and thus the upper surface of the buffer layer 120 provides an appropriate platform for the growth of the channel layer 130 and barrier layer 140 thereon. Increasingly, however, it is desirable to reduce the thickness of the buffer layer 120. The buffer layer 120 is commonly formed from GaN or AIGaN. These materials have relatively low thermal conductivity and therefore a thick buffer layer 120 formed from GaN or AIGaN can lead to a HEMT with poor thermal performance. Additionally, thicker buffer layers can contain a large number of electron trapping sites, which can trap carriers during the operation of the HEMT. These trapping sites or ‘traps’ contribute to drain lag and current collapse, which are a common problem in many HEMTs. There is therefore a trend in the HEMT industry to reduce the thickness of the buffer layer 120 to 500 nm or less. However, reducing the thickness of the buffer layer 120 leads to a buffer layer 120 with reduced crystal quality and increased detectivity. A thinner buffer layer 120 can also reduce the isolation between the 2DEG 132 and substrate 110, leading to the poor confinement of carriers into the 2DEG 132. The poor confinement can lead to carriers migrating through the buffer layer 120 and interacting with defects present at the interface between the substrate 110 and nucleation layer 115. Examples according to the present disclosure provide a semiconductor structure for reducing defects present in a semiconductor layer epitaxially formed over another semiconductor layer. For example, for reducing defects in a nucleation layer 115 formed over a substrate 110, which in turn, reduces the detectivity of layers formed over the nucleation layer 115. The semiconductor structure according to examples of the present disclosure comprises an interlayer region between two semiconductor layers that comprises a high energy chemical bond that is higher than the chemical bond energy of the semiconductor layers either side of the interlayer region. For example, the high bond energy of the interlayer region may result in the interlayer region comprising a shorter bond length than the layers either side of the interlayer region. The formation of the interlayer region with a high energy bond results in defect formation within the interlayer region. For example, point defects and in-plane extended defects can form within the interlayer region. The defects formed within the interlayer region can at least partially relieve stress in the layers grown over the interlayer region, which would otherwise be present due to lattice mismatch between the layers above and below the interlayer region. The interlayer region can thus reduce the detectivity of the layers formed over the interlayer region. For example, the lattice constants of a SiC substrate 110 and a AIN nucleation layer 115 are mismatched. The lattice mismatch causes stress which results in the formation of defects at the SiC substrate 110 and AIN nucleation layer 115 interface, which propagate through the AIN nucleation layer 115 and further into semiconductor layers formed on the nucleation layer 115. The inclusion of an interlayer region, according to examples of the present disclosure, results in the formation of a highly defective interlayer region. The formation of the interlayer region provides the interlayer region with a high bond energy, which is energetically unfavourable. The process of forming the interlayer region is therefore a high energy process which means that the interlayer region forms with several defects within the crystal structure of the interlayer region. The defective nature of the interlayer region means that the AIN nucleation layer 115 may form on the interlayer region and include some defects. However, the highly defective crystal structure of the interlayer region relieves stress between the AIN nucleation layer and the SiC substrate 110 resulting in fewer defects being imparted into the AIN nucleation layer 115 due to lattice mismatch with the SiC substrate 110. The AIN nucleation layer 115 can thus be formed on the interlayer region with a reduced defect density compared to when the AIN nucleation layer 115 is formed directly on a SiC substrate 110. An AIN nucleation layer 115 with reduced defect density enables the use of a thin buffer layer 120 and improved formation of the channel layer 130 and barrier layer 140 thereon. Figure 2 is an example of a semiconductor structure 200. Semiconductor structure 200 comprises elements in common with HEMT 100 described above. In some examples, semiconductor structure 200 may comprise a semiconductor wafer. Semiconductor structure 200 illustrates nucleation layer 115, buffer layer 120, channel layer 130 and barrier layer 140 formed on substrate 110. As described above, the nucleation layer 115, buffer layer 120, channel layer 130 and barrier layer 140 may be epitaxially formed on the substrate 110. Semiconductor structure 200 further comprises interlayer region 210 between the substrate 110 and nucleation layer 115. In some examples, the interlayer region 210 may comprise an interfacial region, which contacts the substrate 110 and the nucleation layer 115. As described above, the interlayer region 210 comprises a high energy bond that is higher than the bond energy of the substrate 110 and the nucleation layer 115. Interlayer region 210 comprises a first monolayer 202 and a second monolayer 204. For the purposes of the present disclosure a ‘monolayer’ may refer to a substantially 2D layer. In some examples, the monolayer may be substantially one atom thick. In some examples, the monolayer may comprise a homogenous layer comprising one type of element at every lattice position in the monolayer. In some examples, a homogenous monolayer may consist essentially of a given element, where the monolayer may additionally include one or more additional elements. In some examples, said one or more additional elements in a homogeneous monolayer may comprise defects. In other examples, a monolayer may comprise an inhomogeneous monolayer and may comprise a plurality of elements at different lattice positions. The first monolayer 202 and the second monolayer 204 may thus be bonded together to form the interlayer region 210. As will be described in more detail below, the interlayer region 210 may be formed in a high energy process to form an interlayer region 210 with a high energy bond. In some examples, the first monolayer 202 may comprise C and the second monolayer 204 may comprise N. The first monolayer 202 and second monolayer 204 may thus be bonded together to form a C-N bond. The C-N bond, may thus provide the interlayer region 210 with a high energy bond configured to relieve stress between the substrate 110 and nucleation layer 115. For example, the substrate 110 may comprise SiC and the nucleation layer 115 may comprise AIN. In such examples, the C-N bond between the first monolayer 202 and the second monolayer 204 may thus be of higher energy than the Si-C bond of the substrate 110 and Al-N bond of the nucleation layer 115. In such examples, the high energy process used in the formation of the C-N bonded interlayer region 210 may result in a defective interlayer region 210 that may help to relieve stress due to lattice mismatch between the substrate 110 and nucleation layer 115. This, in turn, reduces the defects formed in nucleation layer 115 and the layers formed thereon. In some examples, the high energy bond of the interlayer region may additionally result in the interlayer region 210 comprising a short bond length. For example, the C-N bond length is about 22% shorter than the S-C bond length of a SiC substrate and the Al-N bond length of the AIN nucleation layer. Thus, in some examples, the interlayer region 210 may comprise a shorter bond length than the substrate 110 and nucleation layer 115. The high bond energy of the interlayer region 210 may result in the localized formation and release of defects in the interlayer region 210, which is at the interface of the substrate 110. That localized formation of defects reduces the stress and defect formation in the subsequently grown nucleation layer 115, and the layers formed thereon. In some examples, the first monolayer 202 thus may comprise a first element. In such examples, the monolayer may thus consist essentially of the first element. In one example, the first element may comprise C. C is a relatively thermally and chemically stable element and therefore may be more suitable for the formation of first monolayer 202 compared to other elements. Furthermore, C sources for epitaxial growth processes are widely available. In some examples, the substrate 110 may additionally comprise the first element comprised in the first monolayer 202. For example, the substrate 110 may comprise SiC and the monolayer 202 may comprise C. In such examples, the first monolayer 202 may be formed from substrate 110 material. In one example, and as will be described in more detail below, the substrate 110 may be annealed, which may result in in the formation of the first monolayer 202. Thus, in such examples where the substrate 110 comprises SiC, the annealing step may result in the formation of the first monolayer 202. However, in other examples, the monolayer 202 may be formed on the substrate 110 by an alternative fabrication technique, such as, deposition. In such examples, the element of the monolayer 202 may comprise an element also present in the substrate 110. However, alternatively the monolayer 202 may comprise an element that is not present in the substrate 110. In some examples, the second monolayer 204 may thus comprise N. In some examples, the second monolayer may thus consist essentially of N. As will be described in more detail below, in some examples, the second monolayer 204 may be epitaxially deposited on the first monolayer 204. In some examples, the second monolayer 204 may comprise an element contained in the nucleation layer 115. For example, the second monolayer 204 may comprise N and the nucleation layer 115 may comprise AIN. As will be described in more detail below, prior to the formation of the nucleation layer 115, second monolayer 204 comprising N may be formed. Figure 3 is another example of a semiconductor structure 300. Semiconductor structure 300 comprises an interlayer region 210 comprising first monolayer 202. In Figure 3, interlayer region 210 thus comprises a singular monolayer and does not comprise the second monolayer 204. In such examples, the presence of a singular monolayer in the interlayer region 210 may provide the interlayer region 210 with a high bond energy sufficient to result in the formation of defects, which can relieve stress between the substrate 110 and the nucleation layer 115. For example, the first monolayer 202 may comprise C. In some examples, the first monolayer 202 may comprise a monolayer comprising C as similarly described above. The C-C bond energy is higher than the Si-C bond of a SiC substrate 110 and a Al-N bond of the AIN nucleation layer 115. Thus, the interlayer region 210 comprising a singular monolayer 202 may form with a high number of defects configured to relieve stress between the substrate 110 and the nucleation layer 115. Figure 4 is another example of a semiconductor structure 400. Semiconductor structure 400 comprises an interlayer region 210 comprising a first terraced step 212a and a second terraced step 212b. In some examples, the interlayer region 210 may thus comprise a plurality of terraced steps 212a, 212b. In some examples, the interlayer region 210 may comprise a step height 214 between the terraced steps 212a, 212b. The step height 214, between the terraced steps 212a, 212b thus staggers the terraced steps 212a, 212. Furthermore, the terraced steps 212a, 212b may be aligned along a particular direction. Referring briefly to Figure 6, an atomic force microscope (AFM) image 600 of a SiC substrate taken over a 2x2 pm area is presented. As illustrated in Figure 6, a plurality of terraced steps 212a, 212b are formed on the surface of the SiC substrate. The plurality of terraced steps 214 are substantially aligned in a direction. In some examples, the terraced steps 212a, 212b are aligned in a direction defined by a misorientation of the substrate 110 surface plane. In some examples, the step height 214 and the width of the steps 212a, 212b may be at least partly defined by the misorientation angle of the substrate 110. In one example, the terraced steps 212a, 212b may be formed following annealing of the SiC substrate, as will be described in more detail below. Referring again to Figure 4, in some examples, a step height 214 between the first terraced step 212a and the second terraced step 212b may be between 0.5-1 nm. In some examples, the step height 214 may be greater than or equal to a thickness of a given step 212a, 212b. In some examples, the step height 214 may be configured to confine defects within the interlayer region 210, which may result in a nucleation layer 115 with reduced detectivity. In some examples, the step height 214 may be controlled during the manufacturing method of the interlayer region 210, as will be described in more detail below. In some examples, the plurality of terraced steps 212a, 212b may additionally reduce the defect density of the nucleation layer 115 formed on the interlayer region 210. The staggered terraced steps 212a, 212b of the interlayer region 210 reduce in-plane strain, due to lattice mismatch between the substrate 110 and the nucleation layer 115, by splitting the interlayer region 210, and thus the interface between the substrate 110 and the nucleation layer 115 into a plurality of terraced steps 212a, 212b. During the deposition of the nucleation layer 115 on the terraced steps 212a, 212ba force is created due to lattice mismatch within the plane of the interlayer region 210. A vector of this force is directed parallel to the steps 212a, 212b. The force bends extended defects running from the substrate 110 and the nucleation layer 115 interface in the perpendicular direction, towards the interface and into the plane of the interlayer region 210. The bending of the extended defects in the nucleation layer 115 confines the defects to the interface with the interlayer region 210, which reduces the defect density in the nucleation layer 115 and the subsequently grown layers thereon. Thus, a low defect density is formed in the subsequently formed buffer layer 120, channel layer 130 and barrier layer 140. As further illustrated in Figure 4, first terraced step 212a comprises a first portion 202a of first monolayer 202 and a first portion 204a of second monolayer 204. The second terraced step 212b comprises a second portion 202b of first monolayer 202 and a second portion 204b of second monolayer 204. Although the first and second portions 202a, 202b of first monolayer 202 and first and second portions 204a, 204b of second monolayer 204 are illustrated as staggered and substantially disconnected, said portions 202a-b, 204a-b are still considered as forming part of first and second monolayers 202, 204. Thus, first monolayer 202 and second monolayer 204 may be staggered into terraces. However, as illustrated above, in other examples the first monolayer 202 and second monolayer 204may be planar. It will additionally be appreciated that although Figure 4 illustrates first terraced step 212a and second terraced step 212b, in other example, interlayer region 210 may comprise more than two terraced steps. Figures 5a-e illustrate process steps in a method for manufacturing semiconductor structure 200 according to examples of the present disclosure. Figure 5a illustrates a first step 500a in which substrate 110 is provided. In some examples, the substrate may comprise any suitable material for the epitaxial formation of semiconductor material thereon. In some examples, the substrate 110 may comprise a material for the formation of 11 l-N semiconductor material thereon. In some examples, the substrate may comprise Si, SiC, GaN or sapphire. Figure 5b illustrates a second step in which first monolayer 202 is formed on the substrate 110. The first monolayer 202 comprises a first element. In some examples, the first monolayer 202 is epitaxially deposited on the substrate 110. For example, the first monolayer 202 may be deposited on the substrate 110 using epitaxial techniques, such as atomic layer epitaxy (ALE), MBE or MOCVD techniques. In some examples, the substrate 110 is annealed to form the first monolayer 202. In such examples, the first monolayer 202 may comprise an element comprised in the substrate 110. For example, the substrate 110 may comprise SiC and the first monolayer 110 may comprise C. SiC substrates are commonly Si-faced. The annealing step may thus remove Si atoms from the surface of the SiC substrate to expose a C monolayer. As described above, in some examples, the annealing step may additionally result in the first monolayer 202 forming with a plurality of staggered terraced steps. The staggered terraces are divided by a step height. In some examples, the step height between the terraced steps may be at least partially controlled during the annealing process. For example, the step height may be controlled based on the temperature and / or duration of the annealing step. The formation of the first monolayer 202 with a stepped profile may be maintained in the final fabrication of the interlayer region 210. In some examples, the annealing step may be performed under a H2 atmosphere with a H2 flow rate of between 1-500 slm. In some examples, the annealing step may be performed at a temperature range of 1100-1500 °C. In some examples, the annealing step may be performed at a pressure range of 10-760 Torr. In some examples, the annealing step may be performed for a duration of 10-60 minutes. As described above, the annealing temperature and / or duration may be controlled to achieve a desired step height. In some examples, forming the first monolayer 202 may comprise depositing the first element of the first monolayer, following the annealing step. For example, the annealing step may be performed to expose a C monolayer of a SiC substrate. Subsequently, C atoms may be deposited on the substrate 110 to form the first monolayer 202. In some examples, depositing a first element to form the first monolayer 202 may comprise releasing a precursor gas comprising a second element. For example, forming the C atoms for forming the first monolayer 202 may comprise releasing a precursor gas comprising Al on to the substrate 110. As one skilled in the art will be familiar with, the release of an Al precursor gas such as TMAI or TEAI in an epitaxial process such as MOCVD may result in the formation of C atoms on the substrate 110. In some examples, the Al precursor gas to form a first monolayer comprising C may be released on to the substrate 110 in a H2 atmosphere at a dose of 10-100 pmol. In some examples, forming the first monolayer 202 may comprise annealing the first monolayer 202, following the release of the precursor gas. In some examples, the element comprised in the precursor gas may be deposited on to the first monolayer 202, which would contaminate the interlayer region 210 if it were not removed. For example, in the release of the precursor gas comprising Al to form a first monolayer comprising C, some Al atoms may be deposited on the first monolayer 202. An annealing step may thus be performed to remove the Al atoms. In some examples, the annealing step may be performed in a H2 atmosphere at a temperature of 1000-1200 °C and a pressure of 10-760 Torr. Figure 5c illustrates a third step in which the second monolayer 204 is formed over the first monolayer 202. The second monolayer 204 comprises a second element. As described above, the first monolayer 202 and the second monolayer 204 may bond together to form the interlayer region 210. In some examples, the second monolayer 204 is deposited on the first monolayer 202. For example, the second monolayer 204 may be deposited using ALE, MBE or MOCVD techniques. In some examples, the second monolayer 204 may comprise N. In some examples, the N-containing second monolayer 204 may be deposited using a mixture of H2, N2 and NH3 gases. In some examples, the H2 / N2 / NH3 gas mixture may comprise a H2 mole fraction of 0.2-0.9 and a NH3 mole fraction of 0.01-0.2. In some examples, the N-containing second monolayer 204 may be deposited using a temperature range of 1000-1200 °C. Figure 5d illustrates a fourth step 500d in which the nucleation layer 115 is formed over the interlayer region 210. In some examples, the nucleation layer 115 may comprise AIN. The AIN-containing nucleation layer 115 may be formed using known epitaxial techniques by mixing Al and N precursor gases. In one example, TMAI may be used as the Al-containing precursor gas for the nucleation layer 115. Figure 5e illustrates a fifth step in which the buffer layer 120, channel layer 130 and barrier layer 140 are formed over the nucleation layer 115. As the nucleation layer 115 comprises a low defect density due to the presence of the interlayer region 210, the buffer layer 120, channel layer 130 and barrier layer 140 may additionally be formed with a low defect density. The low defect density formation of the buffer layer 120, channel layer 130 and barrier layer 140 may thus lead to a HEMT with improved device performance and improved drain lag performance. Figures 5a-e illustrate process steps in a method of manufacturing a semiconductor structure including an interlayer region 210 comprising two monolayers 202, 204. However, it will be appreciated that a semiconductor structure according to examples of the present disclosure may be formed comprising any suitable number of monolayers. Examples according to the present disclosure have been described applicable for a HEMT. However, it will be appreciated that the examples according to the present disclosure may be applicable for any semiconductor structure or semiconductor device. Examples according to the present disclosure have further been described for forming an interlayer region between a substrate and a nucleation layer. However, it will be appreciated that the examples according to the present disclosure may be configured to form an interlayer region between any two semiconductor layers. The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for wireless radio frequency (RF) communication. In some examples the semiconductor device may comprise one of: a field-effect transistor (FET), a heterojunction bipolar transistor (HBT) or a high electron mobility transistor (HEMT). The present disclosure further provides an RF module comprising a semiconductor device according to examples of the present disclosure. In some examples the RF module may comprise one of: a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module. The present disclosure further provides an electronic device comprising an RF module according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar. In some examples the electronic device may comprise a communications infrastructure device, such as a communication infrastructure device for a base station, a cell tower or similar. In some examples the electronic device may comprise a communication hub, such as a Wi-Fi router or switch. In some examples the electronic device may comprise a communications device for a radar device, such as a radar transmitter, radar receiver, radar transceiver or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A semiconductor structure comprising:a first semiconductor layer;a second semiconductor layer; andan interlayer region between the first semiconductor layer and the second semiconductor layer comprising a bond energy higher than the first semiconductor layer and the second semiconductor layer.

2. The semiconductor structure according to claim 1 wherein the interlayer region comprises a first monolayer.

3. The semiconductor structure according to claim 2 wherein the first monolayer comprises C.

4. The semiconductor structure according to any preceding claim wherein the interlayer region comprises a first element and the first semiconductor layer comprises the first element.

5. The semiconductor structure according to any of claims 2-4 wherein the interlayer region comprises a second monolayer.

6. The semiconductor structure according to claim 5 wherein the second monolayer comprises N.

7. The semiconductor structure according to any preceding claim wherein the first semiconductor layer comprises a substrate and the second semiconductor layer comprises a nucleation layer.

8. The semiconductor structure according to claim 7 wherein the substrate comprises SiC and the nucleation layer comprises AIN.

9. The semiconductor structure according to claim 7 or 8 further comprising a buffer layer over the nucleation layer; wherein the buffer layer comprises a thickness of less than or equal to 500 nm.

10. The semiconductor structure according to any preceding claim wherein the interlayer region comprises a plurality of terraced steps.

11. The semiconductor structure according to claim 10 wherein a height between a pair of the plurality of terraced steps is between 0.5-1 nm.

12. The semiconductor structure according to any preceding claim wherein the interlayer region comprises an interfacial region between the first semiconductor layer and the second semiconductor layer.

13. A semiconductor device comprising the semiconductor structure according to any preceding claim.

14. A radio frequency module comprising the semiconductor device according to claim 13.

15. An electronic device comprising the radio frequency module according to claim 14.

16. A method of forming a semiconductor structure comprising:providing a first semiconductor layer;forming a second semiconductor layer over the first semiconductor layer;forming an interlayer region between the first semiconductor layer and the second semiconductor layer comprising a bond energy higher than the first semiconductor layer and the second semiconductor layer.

17. The method according to claim 16 wherein forming the interlayer region comprises forming a first monolayer.

18. The method according to claim 17 wherein forming the first monolayer comprises annealing the first semiconductor layer.

19. The method according to claim 17 or 18 wherein forming the first monolayer comprises depositing a first element on the first semiconductor layer.

20. The method according to claim 19 wherein depositing the first element comprises releasing a precursor gas comprising a second element.

21. The method according to claim 20 wherein the first element comprises C and the second element comprises Al.

22. The method according to any of claims 20-21 further comprising responsive to releasing the precursor gas, annealing the first monolayer.

23. The method according to any of claims 18 to 22 wherein forming the interlayer 5 region further comprises forming a second monolayer.

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