Method and system for tuning the resistance of a josephson junction

Abstract

A system for tuning the resistance of a Josephson Junction (JJ) (Fig. 2: Rjj) comprises a source of tuning voltage (Fig. 2: 11) and a measurement unit, the source being configured to apply the tuning

Description

FIELD Embodiments described herein relate to methods and systems for tuning the room temperature resistance of the material stack which at ciyogenic temperatures will form a Josephson Junction. BACKGROUND Josephson Junctions are the building blocks of many quantum devices such as qubits. However, they are not limited to qubits and are also used for measurement devices such as superconducting quantum interference devices (SQUIDs). It is difficult to make Josephson Junctions with perfectly repeatable characteristics. BRIEF DESCRIPTION OF THE FIGURES Fig. 1 is a schematic diagram of a Josephson Junction; Fig. 2 is a schematic of an example system that can be used in a method in accordance with an embodiment; Fig. 3 is a plot of voltage against tuning time, temperature againsttuningtime and resistance against tuning time to demonstrate a method in accordance with an embodiment; Figs. 4(a) to 4(d) are a selection of plots showing the potential against distance across the barrier; Figs. 5(a) to 5(d) are a selection of plots showing the effects of tuning voltage, stage temperature and tuning frequency and the time to achieve tuning; Figs. 6(a) to 6(f) are a series of plots showing the change in resistance to, the standard deviation and the drift in the tuning after the tuning voltage has been removed, the plots also show the effect of using a different protocol to reduce the effect drifts in the resistance after tuning voltage has been removed; Fig. 7 is a plot of the percentage change in the tuning resistance for various conditions which also demonstrates the breakdown of the barrier under certain conditions; Fig. 8 is a plot of the inverse IV characteristics to demonstrate how to compare resistances measured at different voltage values; Fig.9 is a plot of tuning speed against yield for 4 different frequencies; Fig. 10 is a plot of the change in the resistance during tuning against time for room temperature tuning; Figs. 11(a) to 11(d) are a selection of plots showing the breakdown characteristics of a Josephson junction investigated in terms of the physical properties of junction; Fig. 12 is a schematic diagram of a plurality of qubits on a substrate; and Fig. 13 is a schematic to explain the need for tuning qubit resistances. DETAILED DESCRIPTION In a first aspect, a system for tuning the resistance of a Josephson Junction is provided, the system comprising a source of tuning voltage and a measurement unit, the source being configured to apply the tuning voltage which is an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, the measurement unit being configured to measure the resistance of the Josephson Junction using the tuning voltage. The above system allows the tuning of a Josephson junction. As will be described later, it is difficult to control the properties of a Josephson junction. Further, in uses such as quantum computing, the energy levels of neighbouring qubits are restricted to allow qubits to ensure high fidelity quantum gates. In the above system, the tuning voltage is used both to tune the resistance of the Josephson junction but is also used as a probe voltage to determine the resistance of the Josephson junction. This means that during the tuning process, it is possible to continually monitor the resistance of the Josephson junction. The source may allow for the amplitude and the frequency of the tuning voltage provided across the Josephson Junction as parameters which affect the tuning. In a second aspect, a system for tuning the resistance of a Josephson Junction is provided, the system comprising a source of tuning voltage, the source being configured to apply the tuning voltage which is an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, wherein the source of alternating voltage is configured to control the amplitude and the frequency of the tuning voltage provided across the Josephson Junction. The ability to use frequency as a tuning parameter allows the yield of the Josephson Junctions which survive the tuning process to be potentially improved. The above system provides a method for tuning qubits after their fabrication. The source of the tuning voltage is configured to control the amplitude and the frequency of the tuning voltage provided across the Josephson Junction. In an embodiment further comprising a load resistance provided in series with the Josephson Junction, the source of alternating voltage being provided across the load resistance and the Josephson Junction that are arranged in series, the measurement device being provided to measure the voltage drop across the load resistance in order to determine the resistance of the Josephson Junction. The load resistance and the Josephson junction together act as a voltage divider. As the resistance of the Josephson junction increases during tuning, the voltage drop across the Josephson junction varies. In an embodiment, there is a tuning voltage profile for the tuning voltage, the source being configured to adjust the tuning voltage in accordance with the tuning voltage profile using the measured voltage drop across the load resistor as a feedback signal. Thus, the voltage drop across the Josephson junction can be carefully controlled. Different tuning voltage profiles may be applied. For example, in one embodiment, the tuning voltage is kept at a fixed amplitude throughout the tuning process. However, in other embodiments, the tuning voltage may be lowered towards the end of the tuning process. This may be a gradual decrease of the tuning voltage or two or more fixed amplitude levels are used for the tuning voltage and the tuning voltage is stepped down through these levels as it reaches its target resistance. It has been realised that, some tuning voltages, the resistance of the Josephson junction continues to increase after the tuning voltage has been removed. This has been found to be more of an effect at higher tuning voltages. Therefore, to mitigate this drift in the resistance, the tuning voltage may be lowered as described above towards the end of the tuning process. Thus, in a third aspect, a system for tuning the resistance of a Josephson Junction is provided, the system comprising a source of tuning voltage, the source being configured to apply the tuning voltage in accordance with a tuning voltage profile, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, wherein the voltage profile has a first portion followed in time by a second portion, wherein the amplitude of the tuning voltage in the second portion is reduced compared to the amplitude of the tuning voltage in the first portion. In an embodiment, the voltage at the end profile would result in a tuning speed at least 30% lower than the voltage at its highest level, wherein tuning speed indicates the time taken to tune the junction by 10% of its original voltage. In an embodiment, the voltage at the end of the voltage profile is at least 10% lower than the voltage at its highest level. In other embodiments, which may be combined with a tuning voltage which has a varying amplitude, the system is configured to remove the tuning voltage applied to Josephson Junction before the Josephson Junction reaches its target resistance. It is possible to determine a suitable resistance, a stop resistance, where tuning voltage is removed which will allow the target resistance to be reached using the drifting of the resistance. The above system allows a tuning voltage to be applied and controlled to allow fast tuning while allowing a high yield of Josephson junctions to survive the tuning process. The tuning may be performed at room temperature. However, in other embodiments, a temperature control unit is provided which is configured to maintain the Josephson Junction at a predetermined temperature when the tuning voltage is applied. The temperature control unit may be configured to raise the temperature of the JJ to a tuning temperature prior to the application of the tuning voltage. In a further embodiment, the system is configured to tune a plurality of Josephson Junctions. Such a system may comprise a probe card which is configured to allow each Josephson Junction to be tuned to be connected to tuning voltage source. The system may be configured to sequentially tune each Josephson Junction or tune a plurality of junctions in parallel. The source of tuning voltage and measurement unit is provided by a lock-in amplifier. The yield of the JJs, i.e. the number of JJs that survive the training has been found to be dependent on the frequency of the tuning voltage. Higher frequencies tend to result in a higher yield. In an embodiment, the frequency of the tuning voltage is 9Hz or more. In other embodiments, 100Hz or more. In a further embodiment, the system is configured to apply a tuning voltage across the Josephson junction and a probe voltage, the probe voltage being lower than the tuning voltage, the probe voltage being configured to allow the resistance of the Josephson Junction to be measured without increasing its resistance. The probe voltage is less than the tuning voltage. In an embodiment, the probe voltage may be less than 50% of the tuning voltage at its highest voltage level, in further embodiments, less than 10% of the tuning voltage at its highest voltage level. The probe voltage and tuning voltage may also be used to determine the resistance at which tuning stops as this may be computed from the target resistance by assuming that the fractional change in reported resistance between high and low voltage regimes is the same at both high and low temperature. In a fourth aspect, a method for tuning the resistance of a Josephson Junction is provided, the method comprising: determining calibration data by measuring the resistance of the Josephson Junction at a probe voltage and a tuning voltage, the tuning voltage being larger than the probe voltage; applying the tuning voltage, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance. The probe voltage is less than the tuning voltage. In an embodiment, the probe voltage may be less than 50% of the tuning voltage at its highest voltage level, in further embodiments, less than 10% of the tuning voltage at its highest voltage level. The above method may be performed at room temperature. In a further embodiment, the JJ is heated to a tuning temperature for tuning. Therefore, the method may further comprise: increasing the temperature to a tuning temperature after performing calibration; and cooling the temperature to room temperature after the application of the tuning voltage. In an embodiment, the tuning temperature may be 25°C or more, in further embodiments 40°C or more, in further embodiments 65°C or more. In a fifth aspect, a method for tuning the resistance of a Josephson Junction is provided, the method comprising: applying a tuning voltage, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance and monitoring the resistance of the Josephson Junction using the tuning voltage. JJs have non-linear IV characteristics. In an embodiment, the resistance measured at the tuning voltage is converted to a resistance value for a lower voltage to determine if the resistance has reached its target value. The resistance may be converted to a zero-bias resistance, or any resistance for which the target resistance is expressed. To perform the conversion, the IV characteristics of the JJ may be determined. This can be done by taking at least two measurements at different voltages and fitting a curve for the expected JJ IV characteristics. In a sixth aspect, a method for tuning the resistance of a Josephson Junction is provided, the method comprising: applying a tuning voltage, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, wherein the Josephson Junction is held at room temperature. Fig. 1 is a schematic of a Josephson Junction (JJ) 1. In its simplest form, a JJ comprises a first superconducting region 3 and a second superconducting region 5 which are separated by a non-superconducting region 7. JJs are used to form many types of superconducting qubits as the element that adds non-linearity to the qubit. In some examples JJs are based on stacks of Al / AlOx / Al and are made by shadow angle evaporation where a bottom layer of thin-film aluminium is oxidised before being coated by a second layer of aluminium is deposited. The Josephson Energy (EJ) of the junctions is inversely proportional to their area and exponentially dependent on the barrier thickness. The difficulty in their manufacture arises because of their small lateral dimensions (which may, in some examples, ~ 200 nm) and the thin amorphous barrier (which may, in some examples,~ 1 nm). Controlling lateral dimensions to be consistent across wafer scale manufacture is difficult, with variations arising due to resist thickness profiles and those naturally arising because of the shadowevaporation geometry. Even if lateral dimensions were to be perfectly controlled, the barrier is formed by oxidising the surface of a Al lead with the critical current density exponentially sensitive to its thickness. The Al lead is typically granular and has some surface roughness and consequently the resultant oxide is not uniform across the junction. In these non-uniform barriers, the thinnest regions of the JJ contribute most to EJ which induces uncontrolled junction-to-junction variations. Fig. 2 shows a system in accordance with an embodiment of the invention which can be used to tune the resistance of the JJ of Fig. 1 after fabrication. The system of Fig. 2 comprises a voltage source 11 which is an alternating current voltage source. In this embodiment, the voltage source is a lock-in amplifier and a so-called source measure unit (SMU). The source 11 provides an alternating voltage across Josephson junction 13 voltage is applied via first voltage terminal 15 which is in electrical communication with one side of the Josephson junction and second voltage terminal 17 which is in communication with the other side of Josephson junction 13. This allows a potential difference to be applied between the first superconducting region 3 and the second superconducting region 5. The first voltage terminal 15 is connected to the Josephson junction 13 via a resistive load 19 such that the Josephson junction 13 and resistive load 19 are in series with one another. The potential drop across the load resistor 19 is then measured using terminals 21 and 23 of the lock in amplifier of the SMU 11. By measuring the potential drop across the load resistor 19, it is possible to determine the resistance of the Josephson junction 13. A temperature controller 25 is provided to allow the temperature of the Josephson junction 13 to be varied. The temperature controller 25 can be on the form of a heated stage on which the Josephson Junction sits. In an embodiment, a stage is used which is based on a PID-controlled Peltier heating element. The temperature may be measured using a K-type thermocouple and validated using an IR thermometer. Using an IR thermometer allows a comparison of the temperature at the top of the stage relative to the substrate on which the JJs are provided. For example, during experiments it has been found that a stage temperature of 88°C, the substrate temperature is ~ 81°C. The system shown in Fig. 2 allows the resistance of the Josephson junction 13 to be monitored during the application of the voltage from terminals 15 and 17. The load resistor 19 and JJ 13 act as a potential divider. Knowing the resistance of the load resistor 19, it is possible to determine the resistance of the JJ 13 from the potential drop across either of the two elements, 13 and 19. The system of Fig. 2 uses a lock-in amplifier to perform the tuning. Using a lock-in amplifier naturally incorporates alternating bias, and allows for fast measurements of resistance in a feed-back loop. The resistance of Josephson Junction 13 can be continually monitored during the tuning using the same alternating voltage used in the tuning. This simplifies and speeds up the tuning process. The nonlinear current voltage characteristics (IV characteristics) of the non-superconducting material 7, which functions as a tunnel barrier, means that the reported resistance depends on the voltage used to probe the junction. Therefore, in an embodiment, two different voltages are used to measure the Josephson Junction 13 (via the load resistance 19) which will be referred to as Vp and Vt, where Vp is a small voltage used to probe the resistance of the JJ and Vt is a larger voltage used to induce junction tuning. Fig. 3 will be used to discuss the tuning method / protocol possible by the system of Fig. 2. The upper panel of Fig. 3 shows the oscillating AC voltage applied by the source 11 over time. In this example, 3 voltage levels are used, 0V, Vp and Vt. The middle pane is a plot of the temperature of a stage which supports the Josephson Junction and therefore is an indication of the temperature of the Josephson junction over time. The lower panel is a plot of the resistance against time. In the tuning protocol described with reference to Fig. 3, there are three parameters that can be varied voltage, temperature, and frequency. These parameters can be tuned to effect tuning speed and yield. In the example of Fig. 3, the tuning protocol has three phases: (i) an initial calibration; (ii) a tuning stage; and (iii) a final measurement of the JJ resistance. In the initial calibration stage, the as-fabricated junction resistance is measured using both a low-voltage probe measurement 31 and a high voltage measurement 33 representative of the tuning voltage. The measurement of the resistance of the Josephson Junction is performed by measuring the load resistance as explained above. In the Example of Fig. 3, the initial calibration is performed without heating, i.e. at room temperature. Next, the applied voltage is returned to 0 and, in this example, the temperature is increased 35 up to 80°C and held 37 at 80°C. The resistance is then measured at the elevated temperature 37 using the probe voltage Vp 39, before switching to the tuning voltage 41 to tune the JJ to a target resistance. In this example, the voltage is left at Vt and maintained at this level to allow the resistance of the Josephson Junction to reach the target resistance. The resistance is then measured at the probe voltage Vp 43. Next, the Josephson Junction is cooled 45 to room temperature. The final resistance of the Josephson Junction is measured at the probe voltage 47. The above has described a three stage process. However, it is possible for one or more of these stages to be omitted. For example, it is possible that calibration could be determined that maps the resistance measured at room temperature with Vp to the nominal resistance expected at elevated temperature and voltage. This would avoid the need to additionally measure with a larger voltage. Further, as will be described later, it is also possible to tune Josephson junction without heating LT keep in the Josephson junction at room temperature. The apparatus of Fig. 2 when performing tuning uses a feedback loop. As the load resistor 19 and Josephson Junction 13 act as a potential divider, as the Josephson Junction tunes and becomes more resistive, it becomes a larger fraction of the total circuit resistance. Thus, if constant voltage is output from the source 11, the voltage dropped across the Josephson Junction 13 will increase across during the tuning protocol. Therefore, in some embodiments, the voltage output by the source 11 is adjusted in real time so that the voltage drop across the Josephson Junction 13 remains constant In some embodiments, a delay in time is inserted between the end of the application of the tuning voltage Vt and the start of the cooling of the Josephson Junctions. This is because the resistance can continue to increase after the tuning voltage Vt has been removed. The resistance at which tuning stops Rstopmay be different to the target resistance. Thus, a pause may be inserted at the elevated temperature after the application of the tuning voltage. The resistance at which tuning stops can be computed from the target resistance by assuming that the fractional change in reported resistance between high and low voltage regimes is the same at both high and low temperature: R(Vp,Tt) R(Vp,20°C) R(y,„20°C) R(VP, 20° C1) U Fig. 4 shows a toy model of the barrier under an applied voltage to provide an explanation consistent with the observed results of the tuning protocol. Fig. 4(a) shows the potential barrier of the AlOx between two metal electrodes. Fig. 4(b) shows the electric field by applying a potential difference to the two different electrodes, the tuning voltage. Fig. 4(c) is an example random potential associated with the amorphous material. The inset to Fig. 4(c) is a cartoon showing the amorphous nature where an aluminium ion with two sites it can tunnel between is shown. Fig. 4(d) is the summation of the three contributions. The figures show a cartoon indicating the thermal energy of ions located at stable local minima and an enlarged section where there is a shallow well where thermal energy may allow a tunneling event to occur. .The total potential across the tunnel junction is made up of the summation of a potential barrier (Fig. 4(a)), a tuning potential across the barrier (Fig. 4(b)) and a random potential due to the amorphous charged material that constitutes the barrier (Fig. 4(c)). Due to the amorphous nature of the barrier (non-superconducting layer 7), some ions will find that there are multiple low-energy configurations that they can occupy, separated by local potential barriers. Increasing the temperature provides the ion with more energy to overcome the barrier, whereas applying a large tuning voltage can tilt the total potential landscape and lower the local barrier height. When the thermal energy is appreciable relative to the barrier height an ion can move to a new position leaving its previous location empty. This will then cause a local rearrangement of many atoms which move in response to the modification of the random potential. As many atoms move, the height of other potential barriers will be modified, and some barriers that previously were high, will become lower allowing more atomic motion. Whilst this provides a model for atomic motion in the barrier activated by temperature, it is plausible that the result of this motion is an increase in the resistance of the barrier. This toy model resembles the barriers simulated by molecular-dynamics simulations of amorphous barriers (P. Koppinen, L. V aist" o, and I. Maasilta, Complete stabilization and improvement of the characteristics of tunnel junctions by thermal annealing, Applied physics letters 90 (2007). The model also suggests that changes in configuration are thermally activated jumps over potential barriers. The rate of these processes is exponential with respect to the ratio of the barrier height to the temperature. The results provided herein demonstrate an explicit measurement of the tuning rate as a function of voltage at fixed temperature and show that this also exponentially increases with increasing voltage (Fig. 3(a)), again in accordance with the prediction of the toy model. This model can account for other observations like the fact that junctions increase in resistance after fabrication over a relatively long timescale (colloquially known as aging). The as-grown barrier can form a meta-stable state and ambient temperatures will cause the reconfiguration of the barrier. The rate of this will slow as all energetically-available jumps will be taken leaving only large barriers. Heating the junction up will accelerate this aging. In an embodiment, in order to optimize the speed of the tuning protocol the tuning voltage Vt and the temperature of the sample during the tuning stage Tt are increased which is as predicted by the model and shown in Figs. 5 (a) to 5(d). FIG. 5. (a) shows the time for 10% junction tuning as a function of tuning voltage at a stage temp of 87°C and a lock-in frequency of 1 kHz. Fig. 5(b) shows the breakdown voltage of barriers as a function of stage temp with lock in frequency of 200 Hz and a lock-in time constant of 10 ms. Fig. 5(c) shows the nominal resistance of a tunnel barrier as a function of frequency and Fig. 5(d) shows the tuning of three junctions at a stage temperature of 90°C with, Vt = 0.95 V for three different frequencies. There are limits to both the voltage and temperature that can be applied. These are probed in Figs 5(a) to 5(d) by measuring the resistance of a barrier as a function of lock-in voltage, ramping linearly from low to high bias voltage. At high bias voltages the junction breaks down, failing by short circuiting. The value of this breakdown voltage depends on the temperature of the junction as shown in Fig. 5 (b) with lower voltage breakdown at higher temperature. This limits the parameter space that can be used for this protocol. At higher temperatures, the junction starts tuning before breaking down. It should be noted that the breakdown voltage varies between junctions, sometimes by as much as 50 mV. This junction-to-junction variation in breakdown voltage is explicit evidence that the barrier make-up (either thickness or compositional) is varying between junctions. The above has largely focussed on the measurement of a single JJ. However, when tuning a QPU, many qubits are fabricated on the same chip. These qubits are collectively heated and their constituent parts may be universally modified by this heat Heating a metal in ambient can result in the growth of an oxide layer on superconducting pads. Such oxide layers are ubiquitously identified with loss in superconducting circuits and so it is desirable to either limit the highest temperatures used, or alternatively performing these experiments in a controlled atmosphere. Furthermore, heating JJs above ~150°C results in a drop in JJ resistance and further heating continues to modify the JJ resistance. Understanding how the JJs are modified by this heating will be important if processes at these elevated temperatures are to be run. The results presented herein investigate the effect of lock-in frequency on the tuning rate. In Figs. 5(a) - (d) the resistance of the JJ is measured using the same probe voltage as a function of lock-in frequency where the integration time on the lock in is always much longer than the inverse of the lock in frequency. The nominal resistance of the junction is independent of measurement frequency below a critical frequency (~10 kHz) and above this frequency nominal resistance increases. This suggests that some the impedance of the circuit is such that the junction is not fully biased In the results presented here, tuning is performed tuning at 8, 81 and 811 Hz (all frequencies below this up-turn in nominal resistance) and show the results in Fig. 5 (d). It is shown that there is a strong dependence of tuning speed on the frequency of the lock-in with tuning speed increasing speed with decreasing frequency. As the measured resistance is constant across these frequencies it is unlikely that there are RLC filtering effects reducing the peak voltage getting to the junction. The reduction in tuning rate with increasing frequency can potentially give insight to the ionic motion inside the barriers. With reference to Fig. 3, it was explained that the tuning in the active tuning section (when Vt is applied to the JJ) of the protocol was 30%, but it was found that there was a total of 37.4% tuning when comparing the full end-to-end protocol. The following figures show that this drift is repeatable and can be predicted. Thus, in an embodiment, this extra drift is accounted for to allow accurate tuning. Figs. 6 (a) and (b) show the result of 34 junctions being tuned, where all junctions are measured at 27°C temperature, before all being heated to 87°C and tuned, before all being cooled back to 27°C for final measurements. The tuning voltage Vtis applied to increase the resistance by 30%. Fig. 6(a) shows the resistance of the JJs resistance before and after the protocol of and Fig. (b) shows a histogram of their tuning. It can be seen that the junctions tune on average 36.3% with a standard deviation of 0.9%. If the resistance of the JJ are measured immediately after the tuning process finishes using Vp, it is found that the junctions continue to increase in resistance even though the voltage applied is suffciently small to not affect the junctions. This is attributed to the settling of the barriers after the relatively violent tuning process. Fig. 6(c) shows the drift in the resistance (the transients) for different tuning voltages: 1.0V (upper 3 traces), 0.9 Vand 0.8V (lower three traces). It can be seen that the transient is smaller in magnitude for smaller tuning voltages. This observation of transients with timescales of ~10s is consistent with our observation shown in Fig. 5(c) that timescales of the junction modification are long relative to 1 / 811 Hz (~ 1ms). In Fig. 6(c) a transient totalling a few % of JJ resistance of extra aging is shown for each of the three tuning voltages. If a plurality of JJs are being tuned, then a wait time, for example, at least 5 mins is left after the final JJ is tuned to allow all JJs to reach their target resistance before the temperature is reduced. As can be seen from Fig. 6(c), the increase in resistance is lower for lower tuning voltages. Thus, as it is shown that post-tuning transients increase with the tuning voltage, in variations on the above, protocols are used where the tuning voltage Vt is modified during the tuning. As transients decrease in magnitude with Vt, in a further embodiment, a hybrid protocol is performed with a large value of Vt for the first part of the tuning, in this instance the first 25%, before swapping to a lower tuning voltage for the final stages, a subsequent 5%, totalling a target of 30% resistance tuning. This is shown in Fig. 6(d). The large step in reported resistance is caused by the non-linear IVs of the junctions which means that the reported resistance depends on the probe voltage This is a compromise between maintaining speed allowed by the high tuning voltage and reducing the magnitude of transients after the tuning protocol ends, aiming for better precision. The plot of Fig. 8 explains how the resistance at the tuning voltage may be converted to a 0 bias level for comparison. Figs. 6(e) and (f) show results from performing this protocol on 17 junctions. Fig. 6(e) shows their resistance before and after and Fig. 6(f) shows a histogram of their tuning. It is shown that the tuning fraction of 32.4% is closer to the target of 30%. Thus, a protocol where the tuning voltage is reduced demonstrates higher accuracy than with the constant high-voltage-only protocol. However, it should be noted that these overshoots for either algorithm can be calibrated out by adjusting targets. Further, it is shown in Fig. 6(f) that the standard deviation of final tuning fraction is smaller, reaching 0.5% in an end-to-end process. This shows, in principle, how modifying the tuning voltage over time can give a more precise process. it is noted that when junctions fail during tuning it is always by suddenly becoming short circuited. To investigate this failure mechanism, the tuning protocol was run on ensembles of junctions where the stopping condition is either (i) 300 s elapses without the junction failing (shown by triangles) or (ii) the junction fails by becoming short circuited (shown by circles). The tuning parameters are varied to understand what parameters are important in this failure and present the results in Fig. 7 where the cumulative distribution of junctions vs. the value of tuning upon reaching one of the stopping conditions is plotted. In more detail, Fig. 7 is a plot showing the tuning % for four different combinations of amplitude, frequency and temperature: IV, 200Hz,, 80°C; IV, 1000Hz, 80°C; 0.95V, 1000Hz, 80°C; and 0.95V, 1000Hz, 85°C. The dots show the tuning at breakdown and the triangles show the tuning (which represents the change in resistance) at 300s. This plot shows that it is possible to engineer different tuning ranges and yields using these three parameters as control knobs. It is shown that moving from IV, 200Hz,, 80°C; to IV, 1000Hz, the average tuning fraction @ failure is increased by increasing the frequency. This allow shows that the fraction of JJs that survive is increased by increasing the frequency. The plots for 0.95V, 1000Hz, 80°C; and 0.95V, 1000Hz, 85°C show that increasing the number of JJs that survive can also be realised by dropping voltage. Thus, by changing the frequency of the source, it is possible to change the tuning rate whilst maintaining the same voltage drop and temperature experienced by the junction as shown in Figs. 5(a) to (d). It can be seen that, on average, the junctions break down at lower tuning fractions for a faster tuning protocol, with one low-tuning outlier. Fig. 8 is a plot of fraction of 0 bias resistance (%) against AC voltage. A JJ has non-linear IV characteristics. This means that the resistance will change dependent on the voltage applied. To report the resistance in a meaningful manner, the 0 bias resistance is used. In order to establish the 0 bias resistance, the IV characteristics of the JJ are determined for the region where the JJ is not being tuned and these results are then interpolated for the tuning region as shown in Fig. 8. This then means that the plot of Fig. 8 can be used to convert a resistance measurement performed at high voltages to a 0 bias value. The plot of Fig. 8 can be thought of as an inverse IV plot Fig. 9 is a plot of a "fitted parameter” which indicates the speed of the tuning against the fraction of JJs that survive to 150s of application of tuning voltage for 4 different frequencies. It can be seen that at the highest frequency (8009Hz) all JJs survive. However, even at frequencies as low as 9 Hz, a significant number, 0.7 of the devices survive at lower tuning speeds. Fig. 10 is a plot of the fractional increase in resistance against time. In this example, the JJ is held at room temperature which shows that tuning is possible even without the use of a heating stage. Figs. 11(a) to 11(d) show results of an investigation of the effect of tuning on the DC IVs and breakdown of JJs. Fig. 11 (a) shows an example IV (plot of current against voltage) of a D C IV where voltage is ramped up from 0 V up to a large value above the breakdown voltage. Breakdown is characterised by the junction becoming short circuited after a maximum voltage is reached. In Fig. 11(a) the junction becomes short circuited and this is recorded as VBD, the breakdown voltage (which is shown by a star). The nonlinear IV collected prior to breakdown can be fitted to a model of a tunnel barrier / 2171 6 where A is the junction area, f the junction thickness, <p the barrier height and K = he ■ An example IV fit to this model is shown in Fig. 11(a). Here, ¢), t and A were fitted as free parameters. Breakdown is extracted where the current suddenly jumps and is indicated. In Fig. 11(b) - (d) the effect of the tuning process on the parameters extracted from the IV shown in Fig. 8(a) is investigated. Figs. 11(b) to (d) show the extracted values of thickness (t), breakdown voltage and barrier height (¢)) respectively for JJs which have been tuned 54.6 + 0.4% and junctions which have undergone the same heat treatment but not been tuned. Fig. 11(b) demonstrates that the fitted thickness shows no substantial change. However, as demonstrated in both Fig. 11(c) and Fig. 11(d), both the breakdown voltage and the barrier height are, on average, changed by the tuning process. The fitted thickness is interpreted as an average thickness value. This average thickness of the barrier is not changed by the tuning process. Breakdown of dielectrics depends on the electric field across the dielectric and the critical field at which dielectric breakdown occurs. Possible interpretations for the increase in breakdown voltage are: (i) Breakdown occurs at the thinnest point of the barrier where the electric fields are strongest As the tuning is driven by electric fields, this is also a local tuning hotspot, and therefore the tuning has resulted in the barrier becoming slightly thicker at the thinnest points only. (ii) The critical field for breakdown depends on the material properties. Having reconfigured the composition of the barrier, the application of the tuning voltage modifies the critical field. The above has demonstrated how an alternating bias scheme can be used to tune tunnel barriers in a JJ, for example, Al / AlOx / Al and how by varying the parameters used to tune these barriers it is possible to optimise the process against criteria including precision, tuning speed, yield and consequently absolute tuning range. Based on these different optimisations a microphysical model for tuning is proposed. Tuning occurs by ion tunneling within an amorphous barrier. It requires several neighbouring ions to tunnel on a timescale faster than the frequency of the alternating bias, in order that the ions don’t tunnel back upon reversal of bias. It has been observed how the tuning process changes the junctions both at room temperature and cryogenic temperatures. At room temperature, it is believed that the tuning process results in a homogenisation of the amorphous barrier resulting in an increase in barrier height and consequent increase in breakdown voltage. After the resistance has been tuned as described above, if it is desired to cool the JJ to cryogenic temperatures, the JJ can be cooled and still maintain the tuned resistance value. The JJ may be thermally cycled and still retain the same tuned resistance value. The above discussion has concentrated on the tuning of a single JJ. A single JJ may be used, for example in a superconducting quantum interference device (SQUID) and also potentially in a single qubit. However, on a QPU, there will be multiple qubits. Fig. 12 schematically illustrates a quantum computing chip 110. The chip 110 has multiple qubits 112 arranged on a substrate 111. Each qubit 112 is configured to store a quantum state. Each qubit 112 comprises a first and second superconducting electrode 112a, 112b with a Josephson junction 112c between the electrodes 112a, 112b. The electrodes 112a, 112b may be made from, for example, aluminium, niobium, tantalum, titanium nitride, aluminium nitride or niobium nitride. In an embodiment, a plurality of chips will be provided on a wafer and the wafer will be processed. The chips are then cut from the wafer after processing. In other embodiments, chips are cut from the wafer prior to or part way through processing. The qubits 112 are coupled together with a coupling 114. The coupling 114 in Fig. 12 is illustrated as a capacitive coupling, but other forms of coupling may also be implemented (for example a resonant coupling comprising an inductor and a capacitor). In Fig. 12, the qubits 112 are displayed in a hexagonal array, however a hexagonal array is only one example and other arrangements of qubits are possible including grid-like arrays, circular arrays or other planar arrangements. The chip 110 depicted in Fig. 12 may be a portion of a larger computing chip. For example, the portion of substrate 111 shown in Fig. 12 may be only a portion of a larger substrate, with further qubits arranged elsewhere on the substrate. Additionally, or alternatively, the chip 110 depicted in Fig. 12 may be (or form part of) a ‘chiplet’, wherein multiple smaller chips form modular blocks of a larger overall chip. The chip 110 depicted in Fig. 12 also includes a through-substrate via 115. The via 115 extends from a first face of the substrate 111 (on which the qubits are arranged) to a rear face of the substrate 111 (not shown). Vias maybe provided to reduce unwanted modes in the chip. The via 115 takes the form of an aperture through the substrate 111. The via 115 is therefore a void or hole within the substrate 111. The via 111 may contain air, or be held at a vacuum, depending on the environment in which the chip is provided in. In this arrangement, the via 115 is positioned generally centrally to the hexagonal array of qubits 112. However, it should be understood that other arrangements are possible. For example, more than one via 115 may be positioned in the central region of the hexagonal array or the via may be positioned off-centre. Additionally, with other qubit arrangements vias may be arranged differently. With a grid-like array of qubits, a corresponding grid-like array of vias may be provided, wherein the via array is offset from the qubit array such that each via is positioned within the space between four adjacent qubits, for example. The qubits have an energy which can also be expressed as a frequency. It is necessary in quantum computing to be able to create qubits that can communicate with each other. However, there are some restrictions on the allowable energy ranges for neighbouring qubits. The qubit energy is linked to its resistance, therefore by varying the resistance of the JJ, it is possible to vary the energy of the qubit If the qubits are too far away in energy, then there is little interaction between them. However, if the qubits are too close in energy, there is high crosstalk between the qubits. Fig. 13 shows a schematic of two qubits, A and B and with an energy diagram showing the energy levels of qubit A and the allowed energy levels (which are the non-shaded areas) to which the qubit be can be tuned to allow a high fidelity quantum gate to be produced between qubits A and B. The method taught in Fig. 3 may be used to tune a plurality of the qubits in a QPU. In an embodiment, a probe card is provided which allows each of the qubits to be individually contacted for tuning. The probe card is configured to place the JJ to be tuned in the circuit described with reference to Fig. 2. As noted above, it is possible to tune the JJs without needingto heat the JJ. However, if heating is used, the entire substrate upon which the QPUs sit may be heated and then each of the JJs tuned. The JJs may be tuned at the same time using a probe card with multiple connections which allows each JJ to be individually addressed and an AC voltage applied. However, in other embodiments, the JJs are tuned sequentially. The QPU may be maintained at an elevated temperature until all QPUs have been tuned. It is not necessary to cool and reheat the QPU for the tuning of each JJ. As explained above, if the tuning gives rise to transients, the QPU should be maintained at the elevated temperature to allow the finally tuned JJ to reach its target resistance before the QPU is cooled. The above description refers to a QPU, but the principle of tuning multiple JJs on a substrate while maintaining the substrate at an elevated temperature for the tuning of all JJs, can apply to any device where the tuning of multiple JJs are required. For a QPU, the target resistances will be calculated by taking into account a plurality of the qubits. In an embodiment, a target resistance might be determined by: Measuring the resistances of all qubits of a plurality of qubits; Computing the expected qubit frequencies based on measured resistances Identifying the junction that is the above it's target resistance by the largest amount, or the junction closest to 2 standard deviations from the median resistance, whichever is lowest in resistance (this acknowledges that we'll have finite tuning range). Computing the change in resistance required for each junction so that it has the correct delta in resistance between the junction as fabricated and the high-resistance junction identified above. For example: 1. Design three qubits with target resistance 4k0hm, 4.2k0hm, 4.4k0hm. 2. Measure the qubits and find 3.95kOhm, 4.46kOhm, 4.53kOhm. (this is a 3% spread process so they are all within 2 standard deviations of their target). 3. Resistance deltas are -0.05 kOhm, +0.24 kOhm, +0.13 kOhm. 4. +0.24kOhm is the largest resistance delta there, and thus all junctions are tuned to reach this delta 5. Junction 1 gets tuned (0.24 - 0.05)k0hm = 0.29 kOhm, (0.24 - 0.24) kOhm = 0 kOhm, (0.24 - 0.13) kOhm - 0.11 kOhm. Whilst certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices, and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices, methods and products described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A system for tuning the resistance of a Josephson Junction, the system comprising a source of tuning voltage and a measurement unit, the source being configured to apply the tuning voltage which is an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, the measurement unit being configured to monitor the resistance of the Josephson Junction using the tuning voltage.

2. A system according to claim 1, wherein the source of alternating voltage is configured to control the amplitude and the frequency of the tuning voltage provided across the Josephson Junction.

3. A system according to either of claims 1 or 2, further comprising a load resistance provided in series with the Josephson Junction, the tuning voltage being provided across the load resistance and the Josephson Junction that are arranged in series, the measurement device being provided to measure the voltage drop across the load resistance in order to monitor the resistance of the Josephson Junction during tuning.

4. A system according to claim 3, wherein there is a tuning voltage profile for the tuning voltage, the source being configured to adjust the tuning voltage in accordance with the tuning voltage profile using the measured voltage drop across the load resistor as a feedback signal.

5. A system according to claim 4, wherein the tuning voltage profile is a fixed amplitude voltage to be applied across the Josephson Junction.

6. A system according to claim 4, wherein the voltage profile has a first portion followed in time by a second portion, wherein the amplitude of the tuning voltage in the second portion is reduced compared to the amplitude of the tuning voltage in the first portion.

7. A system according to any preceding claim, wherein the system is configured to remove the tuning voltage applied to Josephson Junction before the Josephson Junction reaches its target resistance.

8. A system according to claim 8, where the tuning voltage applied causes the resistance of the Josephson Junction to continue to increase for a first duration and settle at a final resistance after the tuning voltage is removed, the tuning voltage being removed at a time such that the final resistance will equal the target resistance.

9. A system according to any preceding claim, further comprising a temperature control unit configured to maintain the Josephson Junction at a predetermined temperature when the tuning voltage is applied.

10. A system according to claim 9, wherein the temperature control unit is configured to raise the temperature of the JJ to a tuning temperature prior to the application of the tuning voltage.

11. A system according to any preceding claim, configured to tune a plurality of Josephson Junctions.

12. A system according to any preceding claim, wherein the source of tuning voltage and measurement unit is provided by a lock-in amplifier.

13. A system according to any preceding claim, wherein the frequency of the tuning voltage is 9Hz or more.

14. A system according to any preceding claim, wherein the system is configured to apply a tuning voltage across the Josephson junction and a probe voltage, the probe voltage being lower than the tuning voltage, the probe voltage being configured to allow the resistance of the Josephson Junction to be measured without increasing its resistance.

15. A system for tuning the resistance of a Josephson Junction, the system comprising a source of tuning voltage, the source being configured to apply the tuning voltage in accordance with a tuning voltage profile, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, wherein the tuning voltage profile has a first portion followed in time by a second portion, wherein the amplitude of the tuning voltage in the second portion is reduced compared to the amplitude of the tuning voltage in the first portion.

16. A method for tuning the resistance of a Josephson Junction, the method comprising: determining calibration data by measuring the resistance of the Josephson Junction at a probe voltage and a tuning voltage, the tuning voltage being larger than the probe voltage;applying the tuning voltage, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance.

17. A method according to claim 16, further comprising:increasing the temperature to a tuning temperature after performing calibration; andcooling the temperature to room temperature after the application of the tuning voltage.

18. A method for tuning the resistance of a Josephson Junction, the method comprising: applying a tuning voltage, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance and monitoring the resistance of the Josephson Junction using the tuning voltage.

19. A method according to claim 18, wherein the resistance measured at the tuning voltage is converted to a resistance value for a lower voltage to determine if the resistance has reached its target value.

20. A method for tuning the resistance of a Josephson Junction, the method comprising: applying a tuning voltage, the tuning voltage being an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, wherein the Josephson Junction is held at room temperature.

21. A system for tuning the resistance of a Josephson Junction, the system comprising a source of tuning voltage, the source being configured to apply the tuning voltage which is an alternating voltage across the Josephson Junction to allow the Josephson Junction to reach a target resistance, wherein the source of alternating voltage is configured to control the amplitude and the frequency of the tuning voltage provided across the Josephson Junction.12 22. A method for tuning the resistance of a Josephson Junction, the method comprising:3 applying a tuning voltage, in accordance with a tuning voltage profile, the tuning4 voltage being an alternating voltage across the Josephson Junction to allow the Josephson 5 Junction to reach a target resistance, wherein the tuning voltage profile has a first portion 6 followed in time by a second portion, wherein the amplitude of the tuning voltage in the 7 second portion is reduced compared to the amplitude of the tuning voltage in the first 8 portion.A

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