Display device

Abstract

An organic display device comprising a display area and non display area, wherein the non display area NDA has a pad area and power lines 210, 220 between the pad area and the display area. The power

Description

CROSS REFERENCE TO RELATED APPLICATION This application claims priority and benefit from Korean Patent Application No. 10-20240201196, filed on December 30, 2024 in the Korean Intellectual Property Office, which is hereby incorporated by reference for all purposes as if fully set forth herein. TECHNICAL FIELD [1] The present disclosure relates to electronic devices, and more specifically, to display devices with improved reliability. BACKGROUND [2] As display technology has been advanced, display devices have been developed to provide increased functions, such as an image capture function, a sensing function, and the like, as well as an image display function. To provide these functions, display devices have been equipped with optical electronic devices, such as a camera, a sensor for detecting an image, a light receiving device, and the like. [3] To effectively receive light passing through the front surface of a display device, it may be desirable for such an optical electronic device to be located in an area of the display device where incident light coming through the front surface can be increasingly received and detected. According to these considerations, display devices may have a structure in which an optical electronic device such as a camera (or an image sensor or camera lens), a detection sensor, and the like is located in a front portion of the display devices to allow the optical electronic device to be effectively exposed to incident light. In this structure, to install the optical electronic device, a bezel of the display device may be increased, or a notch or a hole for accommodating the optical electronic device may be needed in a display area of a display panel. [4] Among display devices, organic light emitting display devices using self-emissive organic light emitting diodes (OLED) exhibit high response speed and have advantages in contrast ratio, emission efficiency, luminance, viewing angle, and the like, compared with other types of display devices such as a liquid crystal display (LCD) device and the like. [5] The light emitting diodes may be implemented with inorganic or organic materials. [6] The description provided in the discussion of the related art section should not be assumed to be prior art merely because it is mentioned in or associated with that section. The discussion of the related art section may include information that describes one or more aspects of the subject technology, and the description in this section does not limit the disclosure. SUMMARY [7] Since structures, layers, and components included in display devices are vulnerable to moisture, the reliability of the display devices can be lowered when moisture enters the display devices. Therefore, there is a need to block the penetration or propagation of moisture into the display devices. [8] To address these issues, one or more aspects of the present disclosure may provide a display device with improved reliability. [9] One or more aspects of the present disclosure may provide a display device including at least one moisture preventing structure disposed in a power line area and an optical area.

[10] One or more aspects of the present disclosure may provide a display device that includes at least one moisture preventing structure disposed in a power line area and an optical area, and is capable of causing a moisture flowing path to lengthen.

[11] One or more aspects of the present disclosure may provide a display device that includes a moisture preventing structure, and is capable of reducing or preventing moisture from entering a display area from an area outside of the display area.

[12] Purposes according to the present disclosure are not limited to the above-mentioned purpose. Other purposes and advantages according to the present disclosure that are not mentioned may be understood based on following descriptions, and may be more clearly understood based on embodiments according to the present disclosure. Further, it will be easily understood that the purposes and advantages according to the present disclosure may be realized using means shown in the claims or combinations thereof.

[13] Aspects, examples, and embodiments provided in the present disclosure are not limited to the foregoing description, and additional aspects, examples, and embodiments provided in the present disclosure will become apparent to those skilled in the art from the following description.

[14] According to one or more example embodiments of the present disclosure, a display device can be provided that includes a substrate including a display area including at least one light emitting element, a non-display area including at least one power line extending from a pad area and surrounding the display area, and an optical area comprising an open area and located in the display area, a first moisture preventing structure extending from a portion of the power line and including a first metal layer, and a second moisture preventing structure disposed between the display area and an open area and including a second metal layer.

[15] According to one or more example embodiments of the present disclosure, a display device can be provided that includes a substrate including a display area comprising at least one light emitting element, a non-display area comprising a power line area extending from a pad area and surrounding the display area, and an optical area located in the display area; at least one moisture preventing structure disposed in the power line area or the optical area, and the light emitting element may comprise an intermediate layer extending from the display area to the optical area, and a plurality of portions of the intermediate layer may be disposed to be spaced apart.

[16] According to one or more aspects of the present disclosure, a display device may be provided with improved reliability.

[17] According to one or more aspects of the present disclosure, a display device may be provided including at least one moisture preventing structure disposed in a power line area and an optical area.

[18] According to one or more aspects of the present disclosure, a display device may be provided that is capable of causing a moisture flowing path to lengthen by including at least one moisture preventing structure disposed in a power line area and an optical area.

[19] According to one or more aspects of the present disclosure, a display device may be provided that is capable of reducing or preventing moisture from entering a display area from an area outside of the display area by including a moisture preventing structure.

[20] According to one or more aspects of the present disclosure, a display device may be provided that is capable of reducing or preventing moisture from entering a display area from an area outside of the display area, which may cause the lifetime of light emitting elements to be reduced or cause defects in the light emitting elements, and thereby, enabling the display device to be driven with low power.

[21] Effects or advantages from aspects, examples, and embodiments described herein are not limited thereto, and additional effects or advantages will become apparent to those skilled in the art from the following description.

[22] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[23] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a portion of the disclosure, illustrate aspects of the disclosure and together with the description serve to explain principles of the disclosure. It should therefore be understood that aspects, examples, and embodiments described herein are not limited to the illustrations of the accompanying drawings. In the drawings: FIG. 1 illustrates an example system configuration of a display device according to aspects of the present disclosure; FIG. 2 is an example plan view of the display device according to aspects of the present disclosure; FIG. 3 is an example cross-sectional view taken along line A-B of FIG. 2 in the display device according to aspects of the present disclosure; FIG. 4 is an example enlarged view of area SA of FIG. 2 in the display device according to aspects of the present disclosure; FIG. 5 is an example cross-sectional view taken along line C-D of FIG. 4 in the display device according to aspects of the present disclosure; FIG. 6 is an example enlarged view of area OA of FIG. 2 in the display device according to aspects of the present disclosure; FIG. 7 is an example cross-sectional view taken along line E-F of FIG. 6 in the display device according to aspects of the present disclosure; FIG. 8 illustrates a phenomenon in which a seam occurs in at least one metal layer of a moisture preventing structure; FIG. 9 is example cross-sectional views of a first moisture preventing structure and a second moisture preventing structure included in the display device according to aspects of the present disclosure; FIGS. 10 to 12 are example views illustrating a process of manufacturing the first moisture preventing structure and the second moisture preventing structure in the display device according to aspects of the present disclosure; FIGS. 13 to 15 are other example cross-sectional views of a first moisture preventing structure and a second moisture preventing structure included in the display device according to aspects of the present disclosure; FIG. 16 is another example cross-sectional view of a first moisture preventing structure and a second moisture preventing structure included in the display device according to aspects of the present disclosure; FIGS. 17 to 22 are example views illustrating a process of manufacturing the first moisture preventing structure and the second moisture preventing structure in the display device according to aspects of the present disclosure; and FIGS. 23 to 25 are other example cross-sectional views of a first moisture preventing structure and a second moisture preventing structure included in the display device according to aspects of the present disclosure.

[24] Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[25] Reference will now be made in detail to example embodiments of the present disclosure, examples or aspects of which may be illustrated in the accompanying drawings. In the following description, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments set forth herein and may be changed as is known in the art, unless otherwise specified. Like reference numerals designate like elements throughout, unless otherwise specified. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may thus be different from those used in actual products. Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following example embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art to fully understand the scope of the present disclosure. Further, the protected scope of the present disclosure is defined by claims and their equivalents. In the following description, where the detailed description of the relevant known function or configuration may unnecessarily obscure aspects of the present disclosure, a detailed description of such known function or configuration may be omitted.

[26] The shapes, sizes, ratios, angles, numbers, and the like, which are illustrated in the drawings to describe various example embodiments of the present disclosure, are merely given by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings. The terms such as “including”, “having”, “containing”, “constituting” “make up of’, and “formed of’ used herein are generally intended to allow other components to be added unless the terms are used with the term “only”. As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[27] In construing an element, the element is construed as including an error although there is no explicit description. Any implementation described herein as an “example” is not necessarily to be construed as preferred or advantageous over other implementations.

[28] Although the terms “first,” “second,” A, B, (a), (b), and the like may be used herein to describe various elements, these elements should not be interpreted to be limited by these terms as they are not used to define a particular order or precedence. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[29] When it is mentioned that a first element "is connected or coupled to", “contacts”, “ overlaps with”, or the like a second element, it should be interpreted that, not only can the first element “be directly connected or coupled to”, “directly contact”, or “directly overlap with” the second element, but a third element can also be "interposed" between the first and second elements, or the first and second elements can "be connected or coupled to", “contact”, “overlap with”, or the like each other via a fourth element. Here, the second element may be included in at least one of two or more elements that "are connected or coupled to", “contact”, “overlap with”, or the like each other.

[30] Where positional relationships are described, for example, where the positional relationship between two parts is described using “on,” “over,” “under,” “above,” “below,” “beside,” “next,” or the like, one or more other parts may be located between the two parts unless a more limiting term, such as “immediate(ly),” “direct(ly),” or “close(ly)” is used. For example, where an element or layer is disposed “on” another element or layer, a third element or layer may be interposed therebetween. Furthermore, the terms “left,” “right,” “top,” “bottom, “downward,” “upward,” “upper,” “lower,” and the like refer to an arbitrary frame of reference.

[31] In addition, when any dimensions, relative sizes etc. are mentioned, it should be considered that numerical values for an elements or features, or corresponding information (e.g., level, range, and the like) include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external impact, noise, and the like) even when a relevant description is not specified. Further, the term “may” fully encompasses all the meanings of the term “can”.

[32] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning for example consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, the term “part” or “unit” may apply, for example, to a separate circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform a described function as should be understood to one of ordinary skill in the art.

[33] The features of the various embodiments of the present disclosure may be partially or entirely combined with each other, and may be technically associated with each other or operate with each other. The embodiments may be implemented independently of each other and may be implemented together in an association relationship.

[34] In the following description, various example aspects of the present disclosure are described in detail with reference to the accompanying drawings. With respect to reference numerals to elements of each of the drawings, the same elements may be illustrated in other drawings, and like reference numerals may refer to like elements unless stated otherwise. The same or similar elements may be denoted by the same reference numerals even though they are depicted in different drawings. In addition, for convenience of description, a scale, dimension, size, and thickness of each of the elements illustrated in the accompanying drawings may be different from an actual scale, dimension, size, and thickness, and thus, aspects of the present disclosure are not limited to a scale, dimension, size, and thickness illustrated in the drawings.

[35] FIG. 1 illustrates an example system configuration of a display device 100 according to aspects of the present disclosure.

[36] Referring to FIG. 1, in one or more example embodiments, the display device 100 may include a display panel 110 and at least one display driving circuit, as elements for display images. The at least one display driving circuit may be a circuit for driving the display panel 110, and include a data driving circuit 120, a gate driving circuit 130, a controller 140, and other circuit components.

[37] The display panel 110 may include a display area DA and a non-display area ND A. The display area DA may also be referred to as an active area, and a plurality of subpixels SP for displaying images may be disposed in the display area DA. The non-display area NDAmay be an area outside of the display area DA.

[38] The non-display area NDA may be an area in which an image is not presented, and be also referred to as a bezel. In one or more aspects, the display panel 110 may be configured to have a very small non-display area NDA. The non-display area NDA may also be referred to as a nonactive area and include a pad area PA. In one or more aspects, all or at least part of the non-display area NDA may be an area visible in front of the display device 100, or an area that is bent and invisible in front of the display device 100 or an area that is covered by a case or housing (not shown) of the display device 100. The non-display area NDA may include a first non-display area ND Al and a second non-display area NDA2.

[39] Referring to FIG. 1, in one or more aspects, the display device 100 may include one or more optical areas OA. The optical area OA may include an open area or a camera hole from which at least a portion of a substrate Illis removed. One or more optical electronic components or devices included in the display device 100 may be located in an area overlapping with at least a portion of the optical area OA. One or more optical electronic components or devices may include, for example, one or more of a photographing device such as a camera or an image sensor, a detection sensor such as a proximity sensor, a face recognition sensor, an illuminance sensor, etc., and the like. For example, a camera may be located under the substrate of the display panel 110, and the camera may be located such that it is overlapped with the optical area OA in a plan view.

[40] FIG. 1 illustrates that one optical area OA is included in the display panel 110, but aspects of the present disclosure are not limited thereto. For example, one or more optical areas OA included in the display panel 110 may be disposed in various configurations. For example, one or two optical areas OA may be disposed inside of the display area DA. In the example where two optical areas OA are disposed therein, an image capturing device such as a camera or an image sensor may be disposed in a first optical area OA, and a detection sensor or another camera may be disposed in a second optical area OA.

[41] FIG. 1 illustrates that the optical area OA has a circular shape, but aspects of the present disclosure are not limited thereto. For example, the optical area OA may have various shapes such as a circular, oval, square, hexagonal, or octagonal shape. In an example when a plurality of optical areas OA are disposed inside of the display area DA, a first optical area OA and one or more remaining optical area OA (e.g., a second optical area OA2) may have different sizes. For example, the first optical area OA where the image capturing device such as a camera or an image sensor is disposed may have a greater size than the second optical area OA2 where the detection sensor or the like is disposed, but is not limited thereto.

[42] For example, each of the first optical area OA and the second optical area OA2 may have various shapes such as a circular, oval, square, hexagonal, or octagonal shape.

[43] In one or more aspects, one or more optical areas OA may be located in an area where the substrate 111 is removed. In this configuration, the one or more optical areas OA may be located in the non-display area NDA where subpixels SP are not disposed. The optical area OA located in the display area DA may also be referred to as a hole-in-active area (HiAA). In examples where this HiAA technology is applied to the display device 100, a notch for camera exposure may not be formed in the display panel 110.

[44] The second non-display area NDA2 may be located such that it surrounds the display area DA. The second non-display area NDA2 may be a bezel area located outside of the display area DA of the display device 100. The second non-display area NDA2 may be a bezel area located outside of the display area DA and may be referred to as an outer bezel area. At least one driving circuit such as a data driving circuit and / or a gate driving circuit for driving a plurality of light emitting elements located in the display area DA may be disposed in the second non-display area NDA2. Further, signal lines such as at least one data line and at least one gate line may be disposed in the second non-display area NDA2.

[45] In one or more aspects, the display device 100 may have a structure where one or more optical areas OA is located in the display area DA, and thereby, can provide advantages of reducing an area of the second non-display area NDA2, which is an outer bezel area, and increasing or maximizing the display area DA.

[46] Referring to FIG. 1, the display panel 110 may include the substrate 111 and a plurality of subpixels SP disposed on the substrate 111.

[47] Several types of signal lines for driving the plurality of subpixels SP may be disposed on the substrate 111 of the display panel 110. Also, the display panel 110 may include one or more optical areas.

[48] In one or more aspects, the display device 100 may be a liquid crystal display device (LCD), a plasma display device (PDP), a field emission display device (FED), or the like, or a selfemissive display device in which light is emitted from the display panel 110 itself, such as an organic light-emitting display device (OLED), and a micro LED (Micro Light Emitting Diode) display device. In an example where the display device 100 is the self-emissive display device, each of the plurality of subpixels SP may include a light emitting element.

[49] For example, the display device 100 according to aspects of the present disclosure may be an organic light emitting display device in which light emitting elements are implemented using organic light emitting diodes (OLED). In another example, the display device 100 according to aspects of the present disclosure may be an inorganic light emitting display device in which light emitting elements are implemented using inorganic material-based light emitting diodes. In another example, the display device 100 according to aspects of the present disclosure may be a quantum dot display apparatus in which the light emitting element is implemented using quantum dots, which are self-emission semiconductor crystals. But aspects of the present disclosure are not limited thereto.

[50] The structure of each or at least one of a plurality of subpixels SP included in the display device 100 may depend on types of the display device 100. For example, when the display device 100 is a self-emissive display device including self-emissive subpixels SP, each subpixel SP may include a self-emissive light emitting element, one or more transistors, and one or more capacitors.

[51] Referring to FIG. 1, each or at least one of the plurality of subpixels SP disposed in the display panel 110 may include a light emitting element ED and a subpixel circuit SPC configured to drive the light emitting element ED.

[52] Referring to FIG. 1, the subpixel circuit SPC may include a plurality of transistors and at least one capacitor for driving the light emitting element ED. The subpixel circuit SPC can drive the light emitting element ED by supplying a driving current to the light emitting element ED at a predetermined timing. The light emitting element ED can emit light by being driven by the driving current.

[53] The plurality of transistors may include a driving transistor DT configured to drive the light emitting element ED and a scan transistor ST configured to be turned on or off by a scan signal SC.

[54] The driving transistor DT can supply a driving current to the light emitting element ED. When the driving transistor DT is turned on, the driving transistor DT can supply a driving current to the light emitting element ED.

[55] The scan transistor ST may be configured to control an electrical state of a corresponding node in the subpixel circuit SPC or to control the state or operation of the driving transistor DT. The scan transistor ST may be configured to control the state or operation of the driving transistor DT in response to the scan signal SC.

[56] The at least one capacitor may include a storage capacitor Cst configured to maintain a voltage at a constant level during a display frame or a period of the display frame.

[57] To drive at least one subpixel SP, at least one data signal VDATA, which is an image signal, and at least one scan signal SC, which is a gate signal, may be applied to the at least one subpixel SP. Further, to drive one or more subpixels SP, at least one common driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the one or more subpixels SP.

[58] The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[59] For example, the pixel electrode PE may be an electrode disposed in each subpixel SP, and the common electrode CE may be an electrode disposed commonly in all or some of a plurality of subpixels SP. For example, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. In another example, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode. Hereinafter, for convenience of explanation, discussions may be provided based on examples where the pixel electrode PE is an anode electrode, and the common electrode CE is a cathode electrode. The pixel electrode PE may be referred to as a first electrode, and the common electrode CE may be referred to as a second electrode.

[60] In an example where the light emitting element ED is an organic light emitting diode, the intermediate layer EL may include an emission layer EML, a first common intermediate layer C0M1 between the pixel electrode PE and the emission layer EML, and a second common intermediate layer COM2 between the emission layer EML and the common electrode CE. A layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be referred to as a common intermediate layer ELCOM. The emission layer EML may be an organic emission layer EML containing an organic material, without being limited thereto.

[61] For example, the emission layer EML may be disposed for each subpixel SP, and the common intermediate layer EL COM may be commonly disposed across all or some of a plurality of subpixels SP.

[62] For example, the emission layer EML may be disposed for each light emitting area, and the common intermediate layer EL COM may be commonly disposed across a plurality of light emitting areas and a non-light emitting area.

[63] For example, the emission layer EML and the common intermediate layer EL COM may be commonly disposed across all or some of a plurality of subpixels SP.

[64] For example, the emission layer EML and the common intermediate layer EL COM may be commonly disposed across a plurality of light emitting areas and a non-light emitting area.

[65] For example, the first common intermediate layer C0M1 may include a hole injection layer (EHL), a hole transfer layer (HTL), and the like. The second common intermediate layer COM2 may include an electron transport layer (ETL), an electron injection layer (EIL), and the like.

[66] The hole injection layer can inject holes from the pixel electrode PE to the hole transport layer, the hole transport layer can transport holes to the emission layer EML. The electron injection layer can inject electrons from the common electrode CE to the electron transport layer, and the electron transport layer can transport electrons to the emission layer EML.

[67] For example, the common electrode CE may be electrically connected to a second common driving voltage line VSSL. A second common driving voltage VSS may be applied to the common electrode CE through the second common driving voltage line VSSL. The pixel electrode PE may be electrically connected directly or indirectly (via another transistor) to a first node N1 of the corresponding driving transistor DT of each subpixel SP. Herein, the second common driving voltage VSS may also be referred to as a “base voltage”, and the second common driving voltage line VSSL may also be referred to as a “low power supply voltage line”, a “low voltage line”, or a “base voltage line.

[68] Each light emitting element ED may be configured by overlapping of a pixel electrode PE, an emission layer EML in an intermediate layer EL, and a common electrode CE. A respective light emitting area may be formed by each light emitting element ED. For example, a respective light emitting area of each light emitting element ED may include an area where a pixel electrode PE, an emission layer EML in an intermediate layer EL, and a common electrode CE overlap with each other

[69] In one or more aspects, each or at least one of a plurality of light emitting elements ED included in the display panel 110 or the display device 100 may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED), a quantum dot (QD) light emitting element, a micro light emitting diode, a mini light emitting diode, or the like, but aspects of the present disclosure are not limited thereto. In the example where each light emitting element ED is an organic light emitting diode (OLED), the intermediate layer EL of a corresponding light emitting element ED may be a layer including an organic material.

[70] For example, the display device 100 according to aspects of the present disclosure may be an organic light emitting display device in which light emitting elements are implemented using organic light emitting diodes (OLED). In another example, the display device 100 according to aspects of the present disclosure may be an inorganic light emitting display device in which light emitting elements are implemented using inorganic material-based light emitting diodes. In further another example, the display device 100 according to aspects of the present disclosure may be a quantum dot display device implemented with quantum dots, which are self-emission semiconductor crystals, as light emitting elements. However, the present disclosure is not limited thereto.

[71] The driving transistor DT may be a transistor configured to supply a driving current to the light emitting element ED. The driving transistor DT may be electrically connected between the first common driving voltage line VDDL and the light emitting element ED.

[72] The driving transistor DT may include a first node Nl, a second node N2, and a third node N3. The first node Nl may be electrically connected to the light emitting element ED. A data signal VDATA may be applied to the second node N2. A first common driving voltage VDD delivered through the first common driving voltage line VDDL may be applied to the third node N3. The driving transistor DT may be connected between the first node Nl and the second node N2.

[73] In the driving transistor DT, the second node N2 may be a gate node, the first node Nl may be a source node or a drain node, and the third node N3 may be the drain node or the source node. Hereinafter, for merely convenience of explanation, discussions may be provided based on examples where the first, second, and third nodes (Nl, N2, and N3) of the driving transistor DT are source, gate, and drain nodes, respectively. However, aspects of the present disclosure are not limited thereto.

[74] In the aspects of the present disclosure, a source electrode and a drain electrode are distinguished from each other, for convenience of description. However, the source electrode and the drain electrode are used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode in any one aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any one aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[75] The scan transistor ST included in the subpixel circuit SPC illustrated in FIG. 1 may be a switching transistor for transferring a data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the driving transistor DT. When the scan transistor ST is turned on, the data signal VDATA is transferred to the driving transistor DT.

[76] The scan transistor ST can be turned on or turned off by a scan signal SC, which is a type of gate signal, applied through a scan line SCL, which is a type of gate line GL, and control an electrical connection between the second node N2 of the driving transistor DT and a data line DL. The drain electrode or source electrode of the scan transistor ST may be electrically connected to the data line DL. The source electrode or drain electrode of the scan transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate electrode of the scan transistor ST may be electrically connected to the scan line SCL. The scan transistor ST may be connected between the data line DL and the second node N2 of the driving transistor DT.

[77] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[78] The storage capacitor Cst may be an external capacitor intentionally designed to be located outside of the driving transistor DT, and therefore, be different from an internal capacitor such as a parasitic capacitor (e.g., a Cgs, a Cgd) that may be formed between the first node N1 and the second node N2 of the driving transistor DT.

[79] Each of the driving transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.

[80] The display panel 110 may have a top emission structure or a bottom emission structure.

[81] In an example where the display panel 110 has the top emission structure, at least a portion of the subpixel circuit SPC may overlap with at least a portion of the light emitting element ED in the vertical direction. In this configuration, the area or size of a corresponding light emitting area can increase, and a corresponding aperture ratio can increase.

[82] In an example where the display panel 110 has the bottom emission structure, the subpixel circuit SPC may not overlap with the light emitting element ED in the vertical direction.

[83] As shown in FIG. 1, the subpixel circuit SPC may include two transistors (2T: DT and ST) and one capacitor (IC: Cst) (which may be referred to as a “2T1C structure”), and in some implementations, may further include one or more transistors, or further include one or more capacitors.

[84] For example, the subpixel circuit SPC may have an 8T1C structure including 8 transistors and 1 capacitor. In another example, the subpixel circuit SPC may have an 6T2C structure including 6 transistors and 2 capacitor. In another example, the subpixel circuit SPC may have an 7T1C structure including 7 transistors and 1 capacitor. However, aspects of the present disclosure are not limited to such specific structures. For example, 3T1C, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C structures, etc. are also possible. And more or less transistors and capacitors could be included.

[85] The types and number of signals supplied to a subpixel SP, and / or the types and number of lines connected to the subpixel SP may vary depending on a structure of a corresponding subpixel circuit SPC. Further, the types and number of common driving voltages supplied to a subpixel SP may vary depending on a structure of a corresponding subpixel circuit SPC.

[86] The several types of signal lines may include, for example, a plurality of data lines DL for carrying data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for carrying gate signals (which may be referred to as scan signals), and the like.

[87] For example, the plurality of data lines DL and the plurality of gate lines GL may intersect one another. Each of the plurality of data lines DL may be configured to extend in a first direction, and each of the plurality of gate lines GL may be configured to extend in a second direction. For example, the first direction may be the column direction or vertical direction, and the second direction may be the row direction or horizontal direction. In another example, the first direction may be the row direction or horizontal direction, and the second direction may be the column direction or vertical direction. Hereinafter, for merely convenience of explanation, discussions are provided based on examples where the first direction is the column direction and the second direction is the row direction. Hereinafter, for convenience of explanation, discussions may be provided based on examples where each of a plurality of data lines DL is disposed in the column direction, and each of a plurality of gate lines GL is disposed in the row direction, but aspects of the present disclosure are limited thereto.

[88] The data driving circuit 120 may be a circuit configured to drive a plurality of data lines DL and can output data signals to the plurality of data lines DL.

[89] The data driving circuit 120 can receive image data DATA in digital form from the controller 140, convert the received image data DATA into data signals in analog form, and output the resulting data signals to the plurality of data lines DL.

[90] For example, the data driving circuit 120 may be electrically connected to the display panel 110 by a tape-automated-bonding (TAB) technique, or electrically connected to a conductive pad such as a bonding pad of the display panel 110 by a chip-on-glass (COG) technique or a chip-on-panel (COP) technique, or electrically connected to the display panel 110 by a chip-on-film (COF) technique. However, aspects of the present disclosure are not limited thereto.

[91] In one or more aspects, the data driving circuit 120 may be disposed in, and / or connected to, but not limited to, only one side or edge (e.g., an upper portion or a lower portion) of the display panel 110. In one or more aspects, the data driving circuit 120 may be disposed in, and / or connected to, but not limited to, two sides or edges (e.g., an upper portion and a lower portion) of the display panel 110 or at least two of four sides or edges (e.g., the upper portion, the lower portion, a left portion, and a right portion) of the display panel 110 according to driving schemes, panel design schemes, or the like.

[92] The data driving circuit 120 may be connected to an area outward from the display area DA of the display panel 110, or be disposed in the display area DA of the display panel 110.

[93] The gate driving circuit 130 may be a circuit configured to drive a plurality of gate lines GL and can output gate signals to the plurality of gate lines GL.

[94] The gate driving circuit 130 can receive several types of gate driving control signals GCS, and further, receive a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage. Thereby, the gate driving circuit 130 can generate gate signals and supply the generated gate signals to the plurality of gate lines GL. the gate driving circuit 130 can supply gate signals to the plurality of gate lines GL according to timing control of the controller 140.

[95] For example, the gate driving circuit 130 may be electrically connected to the display panel 110 by a tape-automated-bonding (TAB) technique, or electrically connected to a conductive pad such as a bonding pad of the display panel 110 by a chip-on-glass (COG) technique or a chip-on-panel (COP) technique, or electrically connected to the display panel 110 by a chip-on-film (COF) technique. However, aspects of the present disclosure are not limited thereto.

[96] In one or more aspects, the gate driving circuit 130 included in the display device 100 may be embedded into the display panel 110 by a gate-in-panel (GIP) technique. In an example where the gate driving circuit 130 is implemented by the gate-in-panel (GIP) technique, the gate driving circuit 130 may be disposed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110 or display device 100.

[97] In one or more aspects, the gate driving circuit 130 may be disposed in the nondisplay area NDA of the display panel 110. The gate driving circuit 130 may be connected to the substrate 111 in an example where the gate driving circuit 130 is implemented by the chip-on-glass (COG) technique, the chip-on-film (COF) technique, or the like.

[98] In one or more aspects, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. In this implementation, for example, the gate driving circuit 130 may be disposed in, and / or connected to, but not limited to, a first area (e.g., a left area or a right area) of the display area DA of the display panel 110. In one or more aspects, the gate driving circuit 130 may be disposed in, and / or connected to, but not limited to, a first area (e.g., a left area or a right area) of the display area DA and a second area (e.g., the right area or the left area) of the display area DA.

[99] Herein, the gate driving circuit 130 embedded in the display panel 110 by the gatein-panel (GIP) technique may also be referred to as a “gate-in-panel circuit.”

[100] The controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130, and can control driving timing for the plurality of data lines DL and driving timing for the plurality of gate lines GL.

[101] The controller 140 can supply a data control signal DCS to the data driving circuit 120 to control the data driving circuit 120, and supply a gate control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[102] The controller 140 can receive image data input from a host system 150 and supply image data DATA readable by the data driving circuit 120 based on the input image data to the data driving circuit 120.

[103] The controller 140 may be implemented in a separate component from the data driving circuit 120, or integrated with the data driving circuit 120, so that the controller 140 and the data driving circuit 120 can be implemented in a single integrated circuit.

[104] The controller 140 may be a timing controller used in the typical display technology or a control apparatus / device capable of additionally performing other control functionalities in addition to the typical function of the timing controller. In one or more embodiments, the controller 140 may be one or more other control circuits different from the timing controller, or a circuit or component in the control apparatus / device. The controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, and / or the like. However, aspects of the present disclosure are not limited thereto.

[105] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, and / or the like.

[106] The controller 140 can transmit signals to, and receive signals from, the data driving circuit 120 via one or more predetermined interfaces. For example, such interfaces may include a low voltage differential signaling (LVDS) interface, an embedded clock point-point interface (EPI), a serial peripheral interface (SPI), and the like. However, aspects of the present disclosure are not limited thereto. Similarly, the controller 140 can transmit signals to, and receive signals from, the gate driving circuit 130 via one or more predefined interfaces.

[107] In one or more aspects, to provide a touch sensing function, as well as an image display function, the display device 100 may further include a touch sensor, and a touch sensing circuit configured to sense the touch sensor and detect whether a touch is applied by an object such as a finger, a pen, or the like, or a location of the touch (or touch coordinates).

[108] The touch sensing circuit may include a touch driving circuit configured to drive and sense the touch sensor and generate and output touch sensing data, and a touch controller configured to detect whether a touch is applied or a location of the touch (or touch coordinates) based on the touch sensing data, and one or more other components.

[109] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit. [HO] The touch sensor may be disposed outside of the display panel 110 in the form of a touch panel or may be disposed inside of the display panel 110. The touch sensor disposed outside of the display panel 110 may be referred to as an add-on type touch sensor. In the example where the add-on type of touch sensor is disposed in the display device 100, the touch panel and the display panel 110 may be separately manufactured and combined in an assembly process. The add-on type of touch panel may include a touch panel substrate and a plurality of touch electrodes disposed on the touch panel substrate. [Ill] In the example where the touch sensor is disposed inside of the display panel 110, the touch sensor may be formed on the substrate along with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[112] The touch driving circuit can supply a touch driving signal to at least one of a plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[113] The touch sensing circuit can perform touch sensing. For example, the touch sensing circuit can perform touch sensing by a self-capacitance sensing technique or a mutual-capacitance sensing technique, without being limited thereto.

[114] In the example where the touch sensing circuit performs touch sensing by the selfcapacitance sensing technique, the touch sensing circuit can perform touch sensing based on capacitance between each touch electrode and a touch object (e.g., a finger, a pen, and the like). According to the self-capacitance sensing technique, each of a plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit may drive all, or one or more, of a plurality of touch electrodes and sense all, or one or more, of the plurality of touch electrodes.

[115] In the example where the touch sensing circuit performs touch sensing by the mutualcapacitance sensing technique, the touch sensing circuit can perform touch sensing based on a capacitance between touch electrodes. According to the mutual-capacitance sensing technique, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[116] In one or more aspects, the touch driving circuit and touch controller included in the touch sensing circuit may be implemented in separate devices or in a single device. In one or more aspects, the touch driving circuit and the data driving circuit may be implemented in separate devices or in a single device.

[117] The display device 100 may further include a power supply circuit configured to supply various types of power (e.g., voltages or currents) to the display driving circuit and / or the touch sensing circuit.

[118] In one or more aspects, the display device 100 may be a mobile terminal such as a notebook computer, a smart phone, a tablet, or the like, or a monitor, a television (TV), or the like, without being limited thereto.. Further, the display device 100 may be configured with various types, sizes, and shapes to display information or images. For example, the display device 100 may be applied to mobile devices, video phones, smart watches, watch phones, wearable apparatuses, foldable apparatuses, rollable apparatuses, bendable apparatuses, flexible apparatuses, stretchable apparatuses, curved apparatuses, sliding apparatuses, variable apparatuses, electronic notebooks, e-books, portable multimedia players (PMP), personal digital assistants (PDA), MP3 players, mobile medical apparatuses, desktop PCs, laptop PCs, netbook computers, workstations, navigation apparatuses, car navigation apparatuses, vehicle display apparatuses, vehicle apparatuses, theater apparatuses, theater display apparatuses, televisions, wallpaper apparatuses, signage apparatuses, game apparatuses, notebook computers, monitors, cameras, camcorders, and home appliances, and the like.

[119] In one or more aspects, the display device 100 may further include an electronic device such as a camera (e.g., an image sensor), an electronic unit or device such as a sensor capable of detecting an object, ambient light, etc., and the like. For example, the sensor may be a sensor capable of detecting an object or a human body by receiving light such as infrared light, ultrasonic light, ultraviolet light or the like.

[120] FIG. 2 is an example plan view of the display device 100 according to aspects of the present disclosure. In discussions that follow for configuration of FIG. 2, discussions for features and examples equal, substantially equal, or similar to the features and examples described with reference to FIG. 1 are omitted or briefly described for convenience of description.

[121] Referring to FIG. 2, the second non-display area NDA2 may include a bending area BA and a pad area PA. The bending area BA may be disposed adjacent to an edge of the display area DA, and the pad area PA may be disposed on one side of the bending area BA. The bending area BA is an area where the substrate 111 can be bent, and may be located between the pad area PA and the display area DA. An area located between the pad area PA and the display area DA and allowing several connection lines and power lines are to be disposed may be referred to as a link area.

[122] For example, several signal lines or pads electrically connected to the data drive circuit 120 may be disposed in the pad area PA. For example, pads for providing external signals to the display panel 110, such as probe pads for lighting inspection, pads for bonding, and the like may be disposed in the pad area PA.

[123] The power lines may be at least one low voltage line for delivering a low voltage, at least one high voltage line for delivering a high voltage, and / or at least one initialization voltage line for delivering an initialization voltage.

[124] The power lines may include at least one first power line 210 and at least one second power line 220. For example, the first power line 210 may include a second common driving voltage line VSSL or a first common driving voltage line VDDL, and the second power line 220 may include the first common driving voltage line VDDL or the second common driving voltage line VSSL. In another example, the first power line 210 may include one of a low voltage line, a high voltage line, and an initialization voltage line, and the second power line 220 may include a voltage line different from the first power line 210 among the low voltage line, the high voltage line, and the initialization voltage line. For example, if the first power line 210 includes the low voltage line, the second power line 220 may include a voltage line among the high voltage line and the initialization voltage line.

[125] For convenience of description, discussions are provided based on the example where that the first power line 210 includes the second common driving voltage line VSSL, and the second power line 220 includes the first common driving voltage line VDDL.

[126] The first power line 210 can deliver a low voltage to the common electrode CE. For example, a portion of the first power line 210 may be disposed in the second non-display area NDA2 adjacent to an lower edge of the display area DA.

[127] The second power line 220 can deliver a high voltage higher than the low voltage. For example, a portion of the second power line 220 may be disposed in parallel with the first power line 210 in the second non-display area NDA2. For example, the first power line 210 and the second power line 220 may be disposed such that the first power line 210 and the second power line 220 are spaced apart from each other and face each other.

[128] FIG. 3 is an example cross-sectional view taken along line A-B of FIG. 2 in the display device 100 according to aspects of the present disclosure. In discussions that follow for the configuration of FIG. 3, discussions for features and examples equal, substantially equal, or similar to the features and examples described with reference to FIGS. 1 and 2 are omitted or briefly described for convenience of description.

[129] Referring to FIG. 3, in one or more example embodiments, in terms of stack-up structure, the display panel 110 may include a transistor part, a light emitting element part, and an encapsulation part.

[130] The substrate 111 may include a single layer or a multilayer. In an example where the substrate 111 includes a multilayer, the substrate 111 may include a first substrate 301, a substrate intermediate layer 302, and a second substrate 303. The substrate intermediate layer 302 may be located between the first substrate 301 and the second substrate 303. For example, the substrate intermediate layer 302 may be disposed on the first substrate 301, and the second substrate 303 may be disposed on the substrate intermediate layer 302, without being limited thereto. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer. The first substrate 301 may be referred to as a first primary PI substrate, and the second substrate 303 may be referred to as a second PI substrate. The substrate intermediate layer 302 may be an inorganic insulating layer. When electric charges are stored on the first substrate 301, which is a polyimide (PI) layer, the substrate intermediate layer 302 can block the charges from affecting transistors on the second substrate 303 through the second substrate 303, which is a poly imide (PI) layer.

[131] The substrate intermediate layer 302 can block moisture from moving upwardly through the first substrate 301. For example, the substrate intermediate layer 302 may be in the form of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) and / or silicon oxide (SiOx), or be in the form of a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx), but aspects of the present disclosure are not limited thereto.

[132] The transistor part may include the substrate 111, and several types of insulating layers (311, 312, 313, 321, 322, and 323), several types of transistors (TFT1 and TFT2), a storage capacitor Cst, and various electrodes or signal lines, which are disposed on the substrate 111.

[133] The transistors (TFT1 and TFT2) included in the transistor part may include a first transistor TFT1 and a second transistor TFT2.

[134] The first transistor TFT1 may include a first active layer ACT1, a first electrode Ela, a second electrode Elb, and a third electrode Elc. The first active layer ACT1 may be a first semiconductor layer, but aspects of the present disclosure are not limited thereto. For example, the first active layer ACT1 may include an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like, but aspects of the present disclosure are not limited thereto. The first transistor TFT1 may be a p-channel transistor or an n-channel transistor, but aspects of the present disclosure are not limited thereto.

[135] The first electrode Ela may be a gate electrode, the second electrode Elb may be a source electrode or a drain electrode, and the third electrode Elc may be the drain electrode or the source electrode. Hereinafter, for convenience of explanation, discussions may be provided based on examples where the first, second, and third electrodes (Ela, Elb, and Elc) are a first gate electrode Ela, a first source electrode Elb, and a first drain electrode Elc, respectively. However, aspects of the present disclosure are not limited thereto.

[136] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, but aspects of the present disclosure are not limited thereto. For example, the second active layer ACT2 may include an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like, but aspects of the present disclosure are not limited thereto. The second transistor TFT2 may be a p-channel transistor or an n-channel transistor, but aspects of the present disclosure are not limited thereto.

[137] For example, one of the first transistor TFT1 and the second transistor TFT2 may include an active layer including an oxide semiconductor. For example, one of the first transistor TFT1 and the second transistor TFT2 may include an active layer including a low-temperature polysilicon (LTPS). For example, each of the first transistor TFT1 and the second transistor TFT2 may include an active layer including an oxide semiconductor. For example, each of the first transistor TFT1 and the second transistor TFT2 may include an active layer including a low-temperature polysilicon (LTPS). For example, among the first transistor TFT1 and the second transistor TFT2, a driving transistor DT may include an active layer including an oxide semiconductor , and a scan transistor ST may include an active layer including a low-temperature polysilicon. For example, among the first transistor TFT1 and the second transistor TFT2, a driving transistor DT may include an active layer including a low-temperature polysilicon, and a scan transistor ST may include an active layer including an oxide semiconductor. For example, a transistor included in the gate driving circuit 130 implemented by the gate-in-panel (GIP) technique may include an active layer including an oxide semiconductor or a low-temperature polysilicon. For example, all transistors disposed on the substrate 111 and all transistors included in the gate driving circuit 130 implemented by the gate-in-panel (GIP) technique may include active layers including an oxide semiconductor.

[138] The fourth electrode E2a of the second transistor TFT2 may be a gate electrode, the fifth electrode E2b may be a source electrode or a drain electrode, and the sixth electrode E2c may be the drain electrode or the source electrode. Hereinafter, for convenience of explanation, discussions may be provided based on examples where the fourth, fifth, and sixth electrodes E2a, E2b, and E2c are a second gate electrode E2a, a second source electrode E2b, and a second drain electrode E2c, respectively. However, aspects of the present disclosure are not limited thereto.

[139] The second active layer ACT2 of the second transistor TFT2 may be disposed higher from the substrate 111 than the first active layer ACT1 of the first transistor TFT1. The second gate electrode E2a of the second transistor TFT2 may be disposed higher from the substrate 111 than the first gate electrode Ela of the first transistor TFT1.

[140] A first buffer layer 311 may be disposed under the first active layer ACT1 of the first transistor TFT1, and a second buffer layer 321 may be disposed under the second active layer ACT2 of the second transistor TFT2. For example, the first active layer ACT1 of the first transistor TFT1 may be disposed on the first buffer layer 311, and the second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 321. The second buffer layer 321 may be disposed higher from the substrate 111 than the first buffer layer 311. For example, the second buffer layer 321 may be disposed over the first buffer layer 311.

[141] A storage capacitor Cst may be disposed in several metal layers in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[142] The light emitting element part may include a plurality of light emitting elements ED disposed on at least one planarization layer (331 and / or 332). Each of the plurality of light emitting elements ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[143] The encapsulation part may include an encapsulation layer 340 on the plurality of light emitting elements ED. The encapsulation layer 340 may be in the form of a single layer or a multilayer. The encapsulation part may further include a dam structure in addition to the encapsulation layer 340.

[144] The encapsulation layer 340 may include a plurality of encapsulating layers including at least one inorganic encapsulating layer and at least one organic encapsulating layer, but is not limited thereto. For example, the encapsulation layer 340 may have a structure in which at least one organic encapsulating layer is disposed between two inorganic encapsulating layers. The uppermost layer of the encapsulation layer 340 may be the inorganic encapsulating layer. For example, an upper surface and a side surface of the organic encapsulating layer may be covered by the inorganic encapsulating layer.

[145] The inorganic encapsulating layers may include an inorganic insulating material. For example, the inorganic encapsulating layers may include an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON) and aluminum oxide (AI2O3).

[146] The organic encapsulating layer may include an organic insulating material, such as acrylic resin, epoxy resin, polyimide, polyethylene and silicon oxycarbide (SiOC).

[147] Hereinafter, the stack-up configuration of the display panel 110 according to aspects of the present disclosure will be described in more detail with reference to FIG. 3.

[148] Referring to FIG. 3, the first buffer layer 311 may be disposed on the substrate 111. The first buffer layer 311 may be in the form of a single layer or a multilayer. In an example where the first buffer layer 311 is in the form of a multilayer, the first buffer layer 311 may include a multibuffer layer 311a and an active buffer layer 311b disposed on the multi-buffer layer 311a.

[149] Several types of transistors, at least one storage capacitor, and several electrodes or signal lines may be disposed on the first buffer layer 311. For example, the transistors disposed on the first buffer layer 311 may include a same material, and be located in one or more same layers. However, aspects of the present disclosure are not limited thereto. For example, the transistors disposed on the first buffer layer 311 may include different materials, and be located in one or more different layers.

[150] The first active layer ACT1 of the first transistor TFT1 may be disposed on the first buffer layer 311. The first active layer ACT1 may include a channel region where a channel is formed, a source connection region on a first side of the channel region, and a drain connection region on a second opposing side of the channel region. The first active layer ACT1 may refer to an active layer of a transistor, or may refer to a semiconductor layer including the same material as the active layer. For example, the first active layer ACT1 may be used as the active layer of the transistor, or used as one or more other circuit elements and / or one or more other signal lines.

[151] A first gate insulating layer 312 may be disposed on the first active layer ACT1 of the first transistor TFT1. The first gate insulating layer 312 may be in the form of, for example, a single layer including silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including silicon nitride (SiNx) and / or silicon oxide (SiOx). However, aspects of the present disclosure are not limited thereto.

[152] The first gate electrode Ela of the first transistor TFT1 may be disposed on the first gate insulating lay er 312. The first gate electrode Ela may refer to a gate electrode of the first transistor TFT1, or may refer to a metal layer including the same material as the gate electrode. For example, the first gate electrode Ela may be used as the gate electrode of the transistor, or used as one or more other circuit elements and / or one or more other signal lines. The first gate electrode Ela may include a conductive material. For example, the first gate electrode Ela of the first transistor TFT1 may include, but is not limited to, a single layer of one, or an alloy of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W), or a multilayer of two or more, or two or more alloys of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W). However, aspects of the present disclosure are not limited thereto. For example, the first gate electrode Ela may include a double layer of Mo and Ti.

[153] A first interlayer insulating layer 313 may be disposed on the first gate electrode Ela of the first transistor TFT1. The first interlayer insulating layer 313 may be in the form of, for example, a single layer including silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including silicon nitride (SiNx) and / or silicon oxide (SiOx). However, aspects of the present disclosure are not limited thereto.

[154] The second buffer layer 321 may be disposed on the first interlayer insulating layer 313. The second buffer layer 321 may be in the form of, for example, a single layer including silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including silicon nitride (SiNx) and / or silicon oxide (SiOx). However, aspects of the present disclosure are not limited thereto.

[155] The second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 321. The second active layer ACT2 may include a channel region where a channel is formed, a source connection region on a first side of the channel region, and a drain connection region on a second opposing side of the channel region. The second active layer ACT2 may refer to an active layer of a transistor, or may refer to a semiconductor layer including the same material as the active layer. For example, the second active layer ACT2 may be used as the active layer of the transistor, or used as one or more other circuit elements and / or one or more other signal lines.

[156] A second gate insulating layer 322 may be disposed on the second active layer ACT2 of the second transistor TFT2. The second gate insulating layer 322 may be in the form of, for example, a single layer including silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including silicon nitride (SiNx) and / or silicon oxide (SiOx). However, aspects of the present disclosure are not limited thereto.

[157] The second gate electrode E2a of the second transistor TFT2 may be disposed on the second gate insulating layer 322. The second gate electrode E2a may refer to a gate electrode of the second transistor TFT2, or may refer to a metal layer including the same material as the gate electrode. For example, the second gate electrode E2a may be used as the gate electrode of the transistor, or used as one or more other circuit elements and / or one or more other signal lines. The second gate electrode E2a may include a conductive material. For example, the second gate electrode E2a of the second transistor TFT2 may include, but is not limited to, a single layer of one, or an alloy of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W), or a multilayer of two or more, or two or more alloys of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W). However, aspects of the present disclosure are not limited thereto. For example, the second gate electrode E2a may include a double layer of Mo and Ti.

[158] A second interlayer insulating layer 323 may be disposed on the second gate electrode E2a of the second transistor TFT2. The second interlayer insulating layer 323 may be in the form of, for example, a single layer including silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including silicon nitride (SiNx) and / or silicon oxide (SiOx). However, aspects of the present disclosure are not limited thereto.

[159] The first source electrode Elb and the first drain electrode Ele of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may be disposed on same layer.

[160] The first source electrode Elb and the first drain electrode Ele of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may be disposed on the second interlayer insulating layer 323.

[161] The first source electrode Elb and the first drain electrode Ele of the first transistor TFT1 may be electrically connected to a source connection region and a drain connection region of the first active layer ACT1, respectively, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may be electrically connected to the source connection region and drain connection region of the second active layer ACT2, respectively.

[162] The first source electrode Elb and the first drain electrode Ele of the first transistor TFT1 may be electrically connected to a source connection region and a drain connection region of the first active layer ACT1, respectively, through holes of the second interlayer insulating layer 323, the second gate insulating layer 322, the second buffer layer 321, the first interlayer insulating layer 313, and the first gate insulating layer 312, but is not limited thereto.

[163] The second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may be electrically connected to the source connection region and drain connection region of the second active layer ACT2 respectively through holes in the second interlayer insulating layer 323 and the second gate insulating layer 322, but is not limited thereto.

[164] The first source electrode Elb and the first drain electrode Ele of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may include a first metal and may be disposed in a first metal layer. For example, the first metal and the first metal layer may be referred to as a first source-drain metal and a first source-drain metal layer, respectively, and the first metal layer may refer to a metal layer including the same material as the first source-drain metal. Therefore, the first source and drain electrodes (Elb and Ele) may be used as the portions of the transistor, or used as one or more other circuit elements and / or one or more other signal lines. The first source and drain electrodes (Elb and Ele) may include a conductive material. For example, the first source and drain electrodes (Elb and Ele) may include, but is not limited to, a single layer of one, or an alloy of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W), or a multilayer of two or more, or two or more alloys of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W). However, aspects of the present disclosure are not limited thereto. For example, the first source and drain electrodes (Elb and Ele) may include a triple layer of Ti, Al, and Ti.

[165] Referring to FIG. 3, in one or more aspects, the storage capacitor Cst may include the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2. In one or more aspects, the storage capacitor Cst may include three or more capacitor electrodes, or two or more capacitors connected in parallel. For example, the first interlayer insulating layer 313 may be disposed between the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2.

[166] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may be disposed in several metal layers in the display panel 110.

[167] In one or more aspects, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode Ela of the first transistor TFT1 on the first gate insulating layer 312, and be disposed in a first gate metal layer.

[168] In one or more aspects, the second capacitor electrode CAPE2 may be disposed on the first interlayer insulating layer 313.

[169] The second source electrode E2b of the second transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 through holes of the second interlayer insulating layer 323, the second gate insulating layer 322, and the second buffer layer 321.

[170] For example, the first transistor TFT1 may be the scan transistor ST of FIG. 1, and the second transistor TFT2 may be the driving transistor DT of FIG. 1.

[171] The transistor part may further include several metal layers (MP1 and MP2). For example, a first metal layer MP1 may be disposed between the multi-buffer layer 311a and the active buffer layer 311b included in the first buffer layer 311. A second metal layer MP2 may include the same first gate metal as the first gate electrode Ela of the first transistor TFT1, and may be disposed in the first gate metal layer. The second metal layer MP2 and the first gate electrode Ela of the first transistor TFT1 may be disposed on the same layer, but is not limited thereto. The first metal layer MP1 may be a first metal pattern, and the second metal layer MP2 may be a second metal pattern MP2, but aspects of the present disclosure are not limited thereto.

[172] Each of the first metal layer MP1 and the second metal layer MP2 may be disposed in the display area DA or the second non-display area NDA2.

[173] Referring to FIG. 3, the transistor part may further include a first shield metal BSM1 disposed on the substrate 111, overlapped with the first active layer ACT1 of the first transistor TFT1, and disposed under the first active layer ACT1 of the first transistor TFT1. For example, the first shield metal BSM1 may be disposed between the substrate 111 and the first buffer layer 311, or may be disposed between the multi-buffer layer 311a and the active buffer layer 311b.

[174] The transistor part may further include a second shield metal BSM2 disposed on the substrate 111, overlapped with the second active layer ACT2 of the second transistor TFT2, and disposed under the second active layer ACT2 of the second transistor TFT2.

[175] For example, the second shield metal BSM2 may be disposed in a metal layer between the first interlayer insulating layer 313 and the second buffer layer 321. The second shield metal BSM2 may be disposed in the same metal layer as the second capacitor electrode CAPE2. The first gate electrode Ela of the first transistor TFT1 may be disposed in the same metal layer as the first capacitor electrode CAPE1, but is not limited thereto.

[176] In another example, the second shield metal BSM2 may be disposed in the same first gate metal layer as the first gate electrode Ela of the first transistor TFT1.

[177] At least one planarization layer may be disposed on the first transistor TFT1 and the second transistor TFT2. FIG. 3 illustrates, for example, two planarization layers (first and second planarization layers (331 and 332)) may be disposed on the first transistor TFT1 and the second transistor TFT2. In one or more aspects, three or more planarization layers may be disposed on the first transistor TFT1 and the second transistor TFT2, but aspects of the present disclosure are not limited thereto.

[178] The two planarization layers (first and second planarization layers (331 and 332)) may be formed of one or more materials of acrylic resin, epoxy resin, phenolic resin, polyamides resin, unsaturated polyesters resin, polyphenylene resin, polyphenylene sulfides resin, and benzocyclobutene, but embodiments are not limited thereto.

[179] Referring to FIG. 3, the first planarization layer 331 may be disposed on the first source electrode Elb and the first drain electrode Ele of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2. For example, the first planarization layer 331 may be disposed such that it covers both the first transistor TFT1 and the second transistor TFT2. For example, the first planarization layer 331 may be configured to protect both the first transistor TFT1 and the second transistor TFT2 and to planarize a step caused due to the first transistor TFT1 and the second transistor TFT2.

[180] Referring to FIG. 3, a relay electrode RE may be disposed on the first planarization layer 331. The relay electrode RE may be electrically connected to the second transistor TFT2, and the second transistor TFT2 may be electrically connected to the storage capacitor Cst. For example, the relay electrode RE may be electrically connected to the second source electrode E2b of the second transistor TFT2 through a hole of the first planarization layer 331. The second source electrode E2b of the second transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst. However, aspects of the present disclosure are not limited thereto.

[181] The relay electrode RE may be disposed in a second metal layer on the first planarization layer 331, and include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer, respectively. The second source or drain electrode (E2b or E2c) may also refer to an electrode for electrically connecting the first source or drain electrodes (Elb or Ele) to a light emitting element ED, and may refer to a metal layer including the same material as the first source and drain electrodes (Elb and Elc). Therefore, the second source or drain electrode (E2b or E2c) may be the electrode for electrically connecting the first transistor TFT1 and the light emitting element ED to each other, or be used as one or more other circuit elements and / or one or more other signal lines. The second source and drain electrodes (E2b and E2c) may include a conductive material. For example, the second source and drain electrodes (E2b and E2c) may include, but is not limited to, a single layer of one, or an alloy of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W), or a multilayer of two or more, or two or more alloys of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W). However, aspects of the present disclosure are not limited thereto. For example, the second source and drain electrodes (E2b and E2c) may include a triple layer of Ti, Al, and Ti.

[182] The second planarization layer 332 may be disposed on the relay electrode RE. For example, second planarization layer 332 may be disposed such that it covers the relay electrode RE.

[183] Referring to FIG. 3, the light emitting element part may be disposed on the second planarization layer 332. The light emitting element ED may be formed on the second planarization layer 332. The light emitting element ED may include the pixel electrode PE, the intermediate layer EL, and the common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE. A light emitting area of the light emitting element ED may be formed by an area where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[184] The pixel electrode PE may be disposed on the second planarization layer 332, and a bank 333 may be disposed on the pixel electrode PE. An opening of the bank 333 may expose a portion of the pixel electrode PE to form a light emitting area. For example, the opening of the bank 333 may overlap with the portion of the pixel electrode PE. For example, a spacer (e.g., 334 in FIG. 5) may be further disposed on the bank 333.

[185] The bank 333 serves to define a sub-pixel. Thus, the bank 333 may be made of an insulating material containing a black material. The bank 333 may be made of, for example, a transparent carbon-based mixture. Specifically, the bank 333 may contain carbon black, but is not limited thereto. The bank 333 may also be made of a transparent insulating material.

[186] The intermediate layer EL of the light emitting element ED may be disposed on a portion of the pixel electrode PE and the bank 333. The common electrode CE may be disposed on the intermediate layer EL.

[187] Referring to FIG. 3, the encapsulation part may be disposed on the light emitting element part, and be disposed on the common electrode CE. The encapsulation part may include an encapsulation layer 340 disposed on the common electrode CE.

[188] The encapsulation layer 340 can prevent moisture or oxygen from penetrating into the light emitting element ED. For example, the encapsulation layer 340 can prevent moisture or oxygen from penetrating into an organic material included in the intermediate layer EL of the light emitting element ED. For example, the encapsulation layer 340 may be in the form of a single layer or multilayer, but aspects of the present disclosure are not limited thereto.

[189] Referring to FIG. 3, for example, the encapsulation layer 340 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343. The first encapsulation layer 341 and the third encapsulation layer 343 may include, for example, an inorganic layer, and the second encapsulation layer 342 may include, for example, an organic layer. For example, the second encapsulation layer 342 may be disposed between the first encapsulation layer 341 and the third encapsulation layer 343.

[190] The first encapsulation layer 341 and the third encapsulation layer 343 may include, for example, an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON) and aluminum oxide (AI2O3). The second encapsulation layer 342 may include, for example, an organic insulating material, such as acrylic resin, epoxy resin, polyimide, polyethylene and silicon oxycarbide (SiOC).

[191] In one or more aspects, a touch sensor may be embedded in the display panel 110. In this configuration, the display panel 110 may include a touch sensor layer 350 disposed on the encapsulation layer 340. The touch sensor may be implemented in the form of a touch panel outside of the display panel 110 or be integrated inside of the display panel 110.

[192] Referring to FIG. 3, the touch sensor layer 350 may include a plurality of touch electrodes TE, and include touch sensor metals TSM and bridge metals BRG to form the plurality of touch electrodes TE. Herein, a layer where the sensor metals TSM are disposed may also be referred to as a sensor metal layer TSM, and a layer where the bridge metals BRG are disposed may also be referred to as a bridge metal layer BRG.

[193] The touch sensor layer 350 may further include one or more insulating layers such as a sensor buffer layer 351 on the encapsulation layer 340, a sensor interlayer insulating layer 352 on the sensor buffer layer 351, and / or a sensor protection layer 353 on the sensor interlayer insulating layer 352. In one or more aspects, the sensor buffer layer 351 may be omitted.

[194] The bridge metals BRG may be disposed between the sensor buffer layer 351 and the sensor interlayer insulation layer 352, and the sensor metals TSM may be disposed between the sensor interlayer insulation layer 352 and the sensor protection layer 353.

[195] Each of the plurality of touch electrodes TE may be configured with one or more touch sensor metals TSM. Each of a plurality of touch electrodes TE may be a mesh-type electrode configured to have a mesh and having a plurality of openings.

[196] For example, the plurality of touch electrodes TE may include at least one first touch electrode TEI and at least one second touch electrode TE2. Two or more touch sensor metals TSM, or two or more parts of one touch sensor metal TSM, included in each first touch electrode TEI or each second touch electrode TE2 may be electrically connected through one or more bridge metals BRG. For example, sensor metals TSM spaced apart from each other may be electrically connected by one or more bridge metals BRG, and thereby, one first touch electrode TEI or one second touch electrode TE2 can be formed. For example, the first touch electrode TEI may include two touch sensor metals TSM and bridge metal BRG, and the sensor metals TSM spaced apart from each other may be electrically connected by the bridge metal BRG. The sensor metals TSM may be disposed on the sensor interlayer insulating layer 352.

[197] The bridge metals BRG may be disposed on the sensor buffer layer 351, and the sensor interlayer insulating layer 352 may be disposed on the bridge metals BRG. Specifically, the sensor interlayer insulating layer 352 may be disposed on the bridge metals BRG and the sensor buffer layer 351. The sensor metals TSM may be disposed on the sensor interlayer insulating layer 352. A part of the sensor metal TSM may be electrically connected to the corresponding bridge metal BRG through a hole in the sensor interlayer insulation layer 352.

[198] Referring to FIG. 3, the sensor metals TSM and the bridge metals BRG may be disposed not to overlap with the light emitting element ED. The sensor metals TSM and the bridge metals BRG may overlap with the bank 333.

[199] A plurality of sensor metals TSM may form one touch electrode TE, and be disposed in a mesh form and electrically connected to each other. One or more of the sensor metals TSM or a portion of each of the sensor metals TSM may be electrically connected to the remaining one or more sensor metals TSM or the remaining portion of each of the sensor metals TSM through one or more bridge metals BRG, and thereby, one touch electrode TE can be formed.

[200] The sensor protection layer 353 may be disposed such that it covers the sensor metals TSM and the bridge metals BRG. For example, the sensor protection layer 353 may be disposed on the sensor metals TSM and the bridge metals BRG and a portion of the sensor interlayer insulation layer 352.

[201] Referring to FIG. 3, a touch line TL may electrically connect a touch electrode TE and a touch pad TP. The touch line TL may be formed by using at least one of a touch sensor metal TSM and a bridge metal BRG.

[202] In an example where the touch sensor is embedded into the display panel 110, the touch line TL may extend along an outer inclined surface SLPENCAP of the encapsulation layer 340, extend beyond an upper portion of a dam structure (e.g., an outer dam structure DM0), and reach the touch pad TP in the non-display area ND A.

[203] FIG. 4 is an example enlarged view of area SA of FIG. 2 in the display device 100 according to aspects of the present disclosure. FIG. 5 is an example cross-sectional view taken along line C-D of FIG. 4 in the display device 100 according to aspects of the present disclosure. In discussions that follow for the configuration of FIGS. 4 and 5, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 3 are omitted or briefly described for convenience of description.

[204] Referring to FIGS. 4 and 5, in one or more example embodiments, the display device 100 may include at least one power line and at least one first moisture preventing structure MPS1. Area SA is an area located between the display area DA and the bending area BA, and may be referred to as a link area of a power supplying part.

[205] The display device 100 may include a plurality of insulating layers (311, 312, 313, 321, 322, and 323) on the substrate 111. Each of the plurality of insulating layers (311, 312, 313, 321, 322, and 323) may be an inorganic insulating layer including an inorganic insulating material.

[206] The at least one power line may include a first power line 210 and a second power line 220. For example, the first power line 210 may include the second common driving voltage line VSSL or the first common driving voltage line VDDL, and the second power line 220 may include the first common driving voltage line VDDL or the second common driving voltage line VSSL.

[207] For example, each of the power line 210 and the second power line 220 may comprise the first moisture preventing structure MPS 1 the first moisture preventing structure disposed in the first power line 210 and the first moisture preventing structure MPS1 disposed in the second power line220 are spaced apart from each other and face each other.

[208] For convenience of description, discussions are provided based on the example where the first power line 210 includes the second common driving voltage line VS SL, and the second power line 220 includes the first common driving voltage line VDDL.

[209] The first power line 210 can deliver a low voltage to the common electrode CE. For example, a portion of the first power line 210 may be disposed in the second non-display area NDA2 adjacent to an lower edge of the display area DA. The first power line 210 may include a first sourcedrain metal layer and a second source-drain metal layer. For example, the first power line 210 may include first to fourth parts (211, 212, 213, and 214). In this configuration, the first part 211 and the third part 213 may be formed by using the first source-drain metal layer and the second source-drain metal layer, and the second part 212 and the fourth part 214 may be formed by using the second source-drain metal layer.

[210] The second power line 220 can deliver a high voltage higher than a low voltage. For example, a portion of the second power line 220 may be disposed in parallel with the first power line 210 in the second non-display area NDA2. For example, the first power line 210 and the second power line 220 may be disposed such that the first power line 210 and the second power line 220 are spaced apart from each other and face each other. The second power line 220 may include the first sourcedrain metal layer and the second source-drain metal layer. For example, the second power line 220 may include first to fourth parts (221, 222, 223, and 224). In this configuration, the first part 221 and the third part 223 may be formed by using the first source-drain metal layer and the second sourcedrain metal layer, and the second part 222 and the fourth part 224 may be formed by using the second source-drain metal layer.

[211] For example, the second part 212 of the first power line 210 and the second part 222 of the second power line 220 may have a single structure of the second source-drain metal layer according to an increase in voltage between the low voltage and the high voltage, and be disposed such that the second part 212 of the first power line 210 and the second part 222 of the second power line 220 are spaced apart from each other and face each other.

[212] Although not shown in FIG. 4, the second part 212 of the first power line 210 and the second part 222 of the second power line 220 may be disposed to overlap with at least a portion of a dam structure (DM0, see FIG. 5).

[213] The second non-display area NDA2 may be an area located in an outer edge of the display device 100, and be an area located in, or in close proximity to, an end (or an outer edge) of the display device 100. Accordingly, the second non-display area NDA2 may be an area where external moisture can directly penetrate the inside of the display device 100.

[214] At least one first moisture preventing structure MPS1 may be used to cause a moisture flowing path through which external moisture penetrates to lengthen, and be disposed in the second non-display area ND A2. For example, the at least one first moisture preventing structure MPS 1 may be formed to lengthen a flowing path of moisture that may flow in along the power lines (210 and 220) that may be disposed to extend from the pad area PA to the display area DA. For example, the at least one first moisture preventing structure MPS 1 may be disposed in the second non-display area NDA2 between the display area DA and the bending area BA. For example, each of the power line 210 and the second power line 220 may comprise a plurality of first moisture preventing structures MPS1, and the plurality of first moisture preventing structures MPS1 disposed in the first power line 210 and the second power line 220 are spaced apart from each other and face each other. FIG. 4 illustrates that six first moisture preventing structures MPS 1 are formed in each of the power lines (210 and 220), but aspects of the present disclosure are not limited thereto. More or less first moisture preventing structures MPS1 can be included. As the number of first moisture preventing structures MPS1 increases, the moisture flowing paths of the power lines (210 and 220) may become longer.

[215] The at least one first moisture preventing structure MPS1 may include a first metal layer MTL1. For example, the at least one first moisture preventing structure MPS 1 including the first metal layer MTL1 may be disposed in disposed in each of the power lines (210 and 220). The first metal layer MTL1 may include the same material as the second parts (212 and 222) of the power lines (210 and 220). For example, the first metal layer MTL1 may be formed integrally with the second parts (212 and 222) of the power lines (210 and 220) and be formed in a pattern shape on one side of each of the power lines (210 and 220). The first metal layer MTL1 may include the same material as the second source-drain metal layer. For example, the first metal layer MTL1 may include the same material as the relay electrode RE. The first metal layer MTL1 may be disposed in the same layer as the relay electrode RE, but is not limited thereto. The first metal layer MTL1 may be formed from the same material as the relay electrode RE in the same process, but is not limited thereto.

[216] For example, the first metal layer MTL1 may include, but is not limited to, a single layer of one, or an alloy of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W), or a multilayer of two or more, or two or more alloys of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W). However, aspects of the present disclosure are not limited thereto. For example, the first metal layer MTL1 may include a triple layer of Ti, Al, and Ti.

[217] The at least one first moisture preventing structure MPS1 may be disposed such that a plurality of first moisture preventing structures MPS1 having a protruding shape and spaced apart from each other are disposed on one side of each of the power lines (210 and 220). According to this configuration, since the at least one first moisture preventing structure MPS 1 including the first metal layer MTL1 is disposed in each of the power lines (210 and 220), a moisture flowing path of each of the power line (210 and 220) can lengthen, and thereby, the display device 100 can provide an advantage of improving moisture resistance.

[218] The at least one first moisture preventing structure MPS 1 may be disposed in each of the first power line 210 and the second power line 220. For example, the at least one first moisture preventing structure MPS1 disposed in the first power line 210 and the at least one first moisture preventing structure MPS1 disposed in the second power line 220 may be spaced apart, face each other, and be disposed in parallel to each other. The at least one first moisture preventing structure MPS1 disposed in the first power line 210 may be disposed to protrude toward the second power line 220, and the at least one first moisture preventing structure MPS1 disposed in the second power line 220 may be disposed to protrude toward the first power line 210.

[219] The at least one first moisture preventing structure MPS1 may include an extension part and a head part. For example, the first metal layer MTL1 included in the at least one first moisture preventing structure MPS1 may include an extension part and a head part. The extension part may extend from a portion of each of the power line (210 and 220). For example, a plurality of extension parts may be disposed to be spaced apart from each other. The head part may be located at an end of the extension part and have a width greater than the extension part. According to these configurations, since the width of the head part is formed to be greater than that of the extension part, the at least one first moisture preventing structure MPS1 may have a hammer-shaped pattern and can cause a flowing path of moisture to lengthen.

[220] The dam structure DM0 may be disposed in the link area of the power supplying part where the at least one first moisture preventing structure MPS1 is disposed. The dam structure DM0 may be disposed outside of the display area DA and be referred to as an outer dam structure DM0. The am structure DM0 may be disposed in the non-display area.

[221] The at least one first moisture preventing structure MPS1 may include a first inner moisture preventing structure disposed between the display area DA and the dam structure DM0 and a first outer moisture preventing structure disposed between the outer dam structure DM0 and the pad area PA.

[222] FIG. 6 is an example enlarged view of area OA of FIG. 2 in the display device 100 according to aspects of the present disclosure. FIG. 7 is an example cross-sectional view taken along line E-F of FIG. 6 in the display device 100 according to aspects of the present disclosure. In discussions that follow for the configuration of FIGS. 6 and 7, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 5 are omitted or briefly described for convenience of description.

[223] Referring to FIGS. 6 and 7, in one or more example embodiments, an optical area OA may be disposed in the display area DA. Subpixels SP may be disposed around the optical area OA.

[224] Referring to FIGS. 6 and 7, the optical area OA may include a camera hole CH and a first non-display area NDA1 around the camera hole CH. The camera hole CH may be referred to as an open area. A first non-display area NDA1 located between the camera hole CH and the display area DA may be referred to as an inner bezel area. The inner bezel area may be referred to as a HiAA bezel area (HBA).

[225] The camera hole CH may be formed by removing a substrate along a trimming line. The camera hole CH may have a circular shape as shown in FIG. 6, but may have various shapes such as an oval, a square, a hexagon, or an octagon.

[226] At least one dam structure DMI may be located in the HiAA bezel area HBA, which is the first non-display area NDA1. The dam structure DMI may be located in the display area DA and be referred to as an inner dam structure DMI. The dam structure DMI may be a structure for controlling the flow of one of a plurality of insulating layers included in the display device 100. For example, the dam structure DMI may be a structure for controlling the flow of an organic insulating layer disposed on one or more light emitting elements. For example, the insulating layer may be an organic layer that may be a part of an encapsulating layer for encapsulating the light emitting elements. Although FIG. 6 illustrates that one dam structure DMI is disposed in the first non-display area NDA1, but aspects of the present disclosure are not limited thereto. For example, two or more dam structures may be disposed in the first non-display area NDA1 according to design requirements.

[227] The at least one second moisture preventing structure MPS2 may include a second inner moisture preventing structure IMPS2 disposed between the display area DA and the inner dam structure DMI and a second outer moisture preventing structure OMPS2 disposed between the inner dam structure DMI and the pad area PA.

[228] The dam structure DMI may be a structure in which a plurality of insulating layers are stacked. For example, the dam structure DMI may be in the form of a stack of the second planarization layer 332 and the bank 333.

[229] The shape of the dam structure DMI may correspond to the shape of the camera hole CH. For example, the dam structure DMI may have a closed curve shape surrounding the camera hole CH. For example, the dam structure DMI and the camera hole CH may have different closed curve shapes. For example, the dam structure DMI and the camera hole CH may have the same shape, but have different closed curve sizes, but is not limited thereto. For example, the dam structure DMI and the camera hole CH may have the different shape and different closed curve sizes. For example, the dam structure DMI and the camera hole CH may have concentric shapes and be spaced apart from each other by a predefined distance.

[230] Referring to FIG. 6, at least one second moisture preventing structure MPS2 may be disposed in the first non-display area NDA1. The at least one second moisture preventing structure MPS2 may mean an area where a plurality of second moisture preventing structures MPS2 are disposed. The at least one second moisture preventing structure MPS2 may be a structure for blocking the penetration of external moisture from the camera hole CH into the display area DA, and may refer to a structure for blocking a flowing path of moisture by cutting off an intermediate layer and / or a cathode electrode of at least one light emitting element.

[231] The at least one second moisture preventing structure MPS2 may include a second metal layer MTL2. The second metal layer MTL2 may include the same material as the second sourcedrain metal layer. For example, the second metal layer MTL2 may include the same material as the relay electrode RE. The second metal layer MTL2 may be disposed in the same layer as the relay electrode RE. The second metal layer MTL2 may be formed from the same material as the relay electrode RE in the same process.

[232] For example, the second metal layer MTL2 may include, but is not limited to, a single layer of one, or an alloy of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W), or a multilayer of two or more, or two or more alloys of two or more, of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and / or tungsten (W). However, aspects of the present disclosure are not limited thereto. For example, the second metal layer MTL2 may include a triple layer of Ti, Al, and Ti.

[233] The at least one second moisture preventing structure MPS2 may include a second inner moisture preventing structure IMPS2 and a second outer moisture preventing structure OMPS2. The second inner moisture preventing structure IMPS2 may be located between the display area DA and the dam structure DMI. The second outer moisture preventing structure 0MPS2 may be located between the dam structure DMI and the camera hole CH. At least one disconnecting structure may be disposed in the optical area OA. For example, the at least one disconnecting structure may include an inner disconnecting structure located in an inner disconnection area ISTA and an outer disconnecting structure located in an outer disconnection area OSTA.

[234] The at least one second moisture preventing structure MPS2 may have a closed loop shape to surround the camera hole CH in the plan view. For example, the at least one second moisture preventing structure MPS2 may be spaced apart from the camera hole CH by a predefined distance and have a closed loop shape.

[235] The shape of at least one second moisture preventing structure MPS2 may correspond to the shape of the camera hole CH. For example, the second moisture preventing structure MPS2 and the camera hole CH may have different closed curve shapes. For example, the second moisture preventing structure MPS2 and the camera hole CH may have the same shape, but have different closed curve sizes, but is not limited thereto. For example, the second moisture preventing structure MPS2 and the camera hole CH may have the different shape and different closed curve sizes.

[236] Referring to FIGS. 6 and 7, at least one subpixel SP disposed in the display area DA may include a corresponding light emitting element. An intermediate layer EL included in the light emitting element and including an emission layer may be disposed in the display area DA. When the light emitting element is an organic light emitting element such as an organic light emitting diode or the like, the intermediate layer EL may include at least one organic layer containing an organic material. The intermediate layer EL may be disposed to extend to at least a portion of the optical area OA. For example, the intermediate layer EL may be disposed to extend to a boundary between the first non-display area NDA1 and the camera hole CH.

[237] In one or more aspects, when moisture penetrates into the intermediate layer EL, display artifacts, such as a dark point presented by defecting of one or more subpixels and the like may occur. There is a possibility that moisture may penetrate into the area where the camera hole CH is located and reach the display area through the intermediate layer EL disposed in the first non-display area NDA1. In this situation, the intermediate layer EL may be disposed to be spaced apart, and thereby, a path through which moisture penetrates can be cut off. Further, as the at least one second moisture preventing structure MPS2 is disposed, a spaced distance of an intermediate layer (EL) pattern can be increased, and thereby, the penetration of external moisture into the display area DA can be blocked or reduced.

[238] Referring to FIG. 7, a crack preventing structure CSP may be disposed at an outermost portion of the second outer moisture prevention structure 0MPS2 adjacent to the camera hole CH. The crack preventing structure CSP can prevent cracks that may occur in the cut surface of the camera hole CH from extending to the display area DA. The crack preventing structure CSP may be formed by metal layers (CSP1 and CSP2) disposed on the substrate 111 of the display panel 110. An organic insulating layer may be disposed on the metal layers (CSP1 and CSP2).

[239] For example, the metal layers (CSP1 and CSP2) may include a first layer CSP1 and a second layer CSP2 disposed on the first layer CSP1. For example, the second layer CSP2 may be disposed to cover the upper surface of the first layer CSP1 and the side surfaces of the first buffer layer 311, the first gate insulating layer 312, the first interlayer insulating layer 313, the second buffer layer 321, the second gate insulating layer 322, and the second interlayer insulating layer 323, but is not limited thereto.

[240] For example, the crack preventing structure CSP may be formed such that a first layer CSP1 including the same material as the first shield metal BSM1 is disposed on the substrate 111, and a second layer CSP2 including the same material as the first source-drain metal is disposed in an area where the first buffer layer 311, the first gate insulating layer 312, the first interlayer insulating layer 313, the second buffer layer 321, the second gate insulating layer 322, and the second interlayer insulating layer 323 among a plurality of inorganic insulating layers are removed. In this configuration, the first layer CSP1 and the second layer CSP2 may be disposed to overlaps with each other. For example, an organic insulating layer including a first layer 331 formed with the first planarization layer 331 and / or a second layer 332 formed with the second planarization layer 332 may be disposed to cover at least one portion of the second layer CSP2 and an area around the at least one portion thereof.

[241] The plurality of inorganic insulating layers may be removed to expose a portion of the substrate 111. Thereafter, the crack preventing structure CSP formed with the metal layers and the organic insulating layer may cover the area from which the inorganic layers are removed. Thereby, cracks that may occur in an open area OA can be absorbed by the crack preventing structure CSP.

[242] The crack preventing structure CSP may have a closed loop shape to surround the open area OA in the plan view. For example, the crack preventing structure CSP may form a closed loop in a ring shape spaced apart from the open area OA by a certain distance.

[243] FIG. 8 illustrates a phenomenon in which a seam occurs in metal layers (MTL1 and / or MTL2) of a moisture preventing structure. In discussions that follow for the configuration of FIG. 8, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 7 are omitted or briefly described for convenience of description.

[244] Referring to FIG 8, after forming the metal layers (MTL1 and MTL2), a planarization layer and a bank (including a spacer) may be formed in a subsequent process, and thereafter, the metal layers (MTL1 and MTL2) may be exposed to a developer and etched in a developing process to form a bank undercut. When the metal layers (MTL1 and MTL2) are in the form of a triple layer of Ti, Al, and Ti, a difference in etching rates of metals included in the metal layers (MTL1 and MTL2) with respect to the developer solution may cause aluminum (Al) located in the middle of the triple layer to be etched more than titanium (Ti). Thereby, there may occur a phenomenon in which aluminum pores are formed. These pores may be formed by titanium (Ti) tips located on and underneath aluminum (Al).

[245] In this configuration, an encapsulation layer (for example, a first encapsulation layer 341) may be formed on the metal layers (MTL1 and MTL2), the first encapsulation layer 341 may not completely cover respective side surfaces of the metal layers (MTL1 and MTL2) due to the aluminum (Al) pores. Thus, a seam SE with a groove or recess shape may be formed in the first encapsulation layer 341. In this situation, the seam SE may easily cause a defect such as a crack and the like, and thereby, a path through which undesired substances such as moisture can penetrate may be formed. The penetrated moisture may cause corrosion of the metal layers (MTL1 and MTL2) or cause malfunction of the display device.

[246] FIG. 9 is example cross-sectional views of a first moisture preventing structure MPS 1 and a second moisture preventing structure MPS2 included in the display device 100 according to aspects of the present disclosure. In discussions that follow for the configuration of FIG. 9, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 8 are omitted or briefly described for convenience of description.

[247] Referring to FIG. 9, in one or more example embodiments, the first moisture preventing structure MPS1 and the second moisture preventing structure MPS2 may include a first metal layer MTL1 and a second metal layer MTL2 disposed on a plurality of insulating layers, respectively.

[248] Referring to FIG. 9, the first moisture preventing structure MPS1 may include the first metal layer MTL1 disposed on a second interlayer insulating layer 323. A first encapsulating layer 341 and a third encapsulating layer 343 may be disposed on the first metal layer MTL1.

[249] The first encapsulating layer 341 and the third encapsulating layer 343 may be disposed to cover the upper and side surfaces of the first metal layer MTL1 and the upper surface of the second interlayer insulating layer 323. The third encapsulating layer 343 may be disposed on the first encapsulating layer 341.

[250] The first encapsulating layer 341 and the third encapsulating layer 343 may be disposed to cover a side surface and an upper surface of the first metal layer MTL1 of the first moisture preventing structure MPS 1. In addition, the first encapsulating layer 341 and the third encapsulating layer 343 may be disposed to cover a partial side surface and a partial upper surface of the second interlayer insulating layer 323.

[251] The first metal layer MTL1 may have a lower surface, an upper surface, and an inclined surface extending from the lower surface to the upper surface. The inclined surface of the first metal layer MTL1 may be formed continuously from the lower surface to the upper surface at an equal taper angle. For example, a width of the upper surface of the first metal layer MTL1 may be less than that of the lower surface.

[252] The first metal layer MTL1 may have a tapered shape in a vertical direction in the cross-sectional view. For example, the first metal layer MTL1 in the vertical direction in the cross sectional view may have a trapezoidal shape in which a length of the upper side is less than a length of the lower side.

[253] The first metal layer MTL1 may be in the form of a triple layer. In the example where the first metal layer MTL1 is in the form of a triple layer, the first metal layer MTL1 may include a first layer ML1, a second layer ML2 disposed on the first layer ML1, and a third layer ML3 disposed on the second layer ML2.

[254] Each of the first layer ML1, the second layer ML2, and the third layer ML3 may have a tapered shape in the vertical direction in the cross-sectional view. For example, each of the first layer ML1, the second layer ML2, and the third layer ML3 may have a trapezoidal shape in which a length of the respective upper side is less than a length of the respective lower side. For example, the second layer ML2 may be thicker than the first layer ML1 and the third layer ML3, but is not limited thereto.

[255] A width of an upper surface of the first layer ML1 may be less than that of a lower surface of the first layer ML1. The width of the upper surface of the first layer ML1 may be substantially the same as that of a lower surface of the second layer ML2. A width of an upper surface of the second layer ML2 may be less than that of the lower surface of the second layer ML2. The width of the upper surface of the second layer ML2 may be substantially the same as that of a lower surface of the third layer ML3. A width of an upper surface of the third layer ML3 may be less than that of the lower surface of the third layer ML3. In this structure, the inclined surface of the first metal layer MTL1 including the first layer ML1, the second layer ML2, and the third layer ML3 may be continuously formed from the lower surface to the upper surface at an equal taper angle.

[256] The first metal layer MTL1 may be, for example, a second source-drain electrode.

[257] The first layer ML1 and the third layer ML3 may be metal layers including a same material, and the second layer ML2 may be a metal layer including a different material from the first layer ML1 and the third layer ML3. For example, the first layer ML1 and the third layer ML3 may include titanium (Ti), and the second layer ML2 may include aluminum (Al). For example, the first metal layer MTL1 including the first layer ML1, the second layer ML2, and the third layer ML3 may be in the form of a multilayer of Ti, Al, and Ti. As the first to third layers (ML1, ML2, and ML3) include these materials, the second layer ML2 can be configured with a material having better conductivity, and the first layer ML1 and the third layer ML3 can be configured with a material capable of protecting the second layer ML2 during the manufacturing process.

[258] The first metal layer MTL1 included in the first moisture preventing structure MPS1 may have a continuously tapered inclined surface. Since the first metal layer MTL1 has this structure, a pore that may be caused by a titanium (Ti) tip may not be formed. For example, in FIG. 8, there may occur a phenomenon in which aluminum pores are formed. These pores may be formed by titanium (Ti) tips located on and underneath aluminum (Al). The example embodiment of FIG. 9 can prevent the formation of pore that may be caused by a titanium (Ti) tip in the first metal layer MTL1.

[259] Referring to FIG. 9, the second moisture preventing structure MPS2 may include the second metal layer MTL2 disposed on the second interlayer insulating layer 323. The first encapsulating layer 341 and the third encapsulating layer 343 may be disposed on the second metal layer MTL2. For example, the first encapsulating layer 341 and the third encapsulating layer 343 may be disposed to cover the upper and side surfaces of the second metal layer MTL2. The third encapsulating layer 343 may be disposed on the first encapsulating layer 341.

[260] Referring to FIG. 9, the second moisture preventing structure MPS2 may include an undercut area UCA. The undercut area UCA may include a side pattern PS disposed on a substrate and located under a light emitting element. For example, the side pattern PS may be formed by patterning an organic insulating layer. The side pattern PS of the undercut area UCA may be formed in such a manner that at least one organic insulating layer is etched to form the undercut area UCA. The organic insulating layer in which the undercut area UCA is formed may be, for example, at least one of a first planarization layer PLN1 and a second planarization layer PLN2. Although FIG. 9 illustrates that the second moisture preventing structure MPS2 includes the side pattern PS in the form of a single layer, however, aspects of the present disclosure are not limited thereto. For example, the second moisture preventing structure MPL2 may include at least one of the first planarization layer PLN1 and the second planarization layer PLN2, and at least one undercut area UCA may be formed in at least one of the first planarization layer PLN1 and the second planarization layer PLN2.

[261] The second moisture preventing structure MPS2 may include at least one depression in at least one insulating layer among a plurality of insulating layers. For example, the depression may be disposed on the substrate 111 and located in an inorganic insulating layer located under a light emitting element. The depression located in the inorganic insulating layer may be formed in such a manner that at least one of the inorganic insulating layers is etched to form the depression. The inorganic insulating layer may be an inorganic insulating layer disposed on the substrate 111 and located under the light emitting element. For example, the inorganic insulating layer may be at least one of the second interlayer insulating layer 323, a second buffer layer 321, and one or more insulating layers located between the second interlayer insulating layer 323 and the second buffer layer 321. Although FIG. 9 illustrates in which the depression is included in a portion of the second interlayer insulating layer 323, however, aspects of the present disclosure are not limited thereto.

[262] The undercut area UCA and the side pattern PS formed by an organic insulating layer may be located in the depression. A portion of an inorganic insulating layer may be exposed by the undercut area UCA of the organic insulating layer. For example, the second interlayer insulating layer 323 may be exposed by the undercut area UCA of the organic insulating layer, and an intermediate layer EL may be located on the exposed second interlayer insulating layer 323. The intermediate layer EL may be disconnected (or separated) at the undercut area UCA. For example, a portion of the intermediate layer EL may be located on the exposed second interlayer insulating layer 323and a portion of the side surface of the second interlayer insulating layer 323 may not be covered by the intermediate layer EL.

[263] The second moisture preventing structure MPS2 may include the second metal layer MTL2 located on the undercut area UCA. The second metal layer MTL2 may be disposed to protrude from the side pattern PS. The intermediate layer EL may be disconnected (or separated) at an area under the second metal layer MTL2.

[264] The second metal layer MTL2 may have a lower surface, an upper surface, and an inclined surface extending from the lower surface to the upper surface. The inclined surface of the second metal layer MTL2 may be formed continuously from the lower surface to the upper surface at an equal taper angle. For example, a width of the upper surface of the second metal layer MTL2 may be less than that of the lower surface.

[265] The second metal layer MTL2 may have a tapered shape in a vertical direction in the cross-sectional view. For example, the second metal layer MTL2 in the vertical direction in the crosssectional view may have a trapezoidal shape in which a length of the upper side is less than a length of the lower side. The second metal layer MTL2 may have the same shape as the first metal layer MTL1.

[266] The second metal layer MTL2 may be in the form of a triple layer. In the example where the second metal layer MTL2 is in the form of a triple layer, the second metal layer MTL2 may include a fourth layer ML4, a fifth layer ML5 disposed on the fourth layer ML4, and a sixth layer ML6 disposed on the fifth layer ML5.

[267] Each of the fourth layer ML4, the fifth layer ML5, and the sixth layer ML6 may have a tapered shape in the vertical direction in the cross-sectional view. For example, each of the fourth layer ML4, the fifth layer ML5, and the sixth layer ML6 may have a trapezoidal shape in which a length of the respective upper side is less than a length of the respective lower side. For example, the fifth layer ML5 may be thicker than the sixth layer ML6 and the fourth layer ML4, but is not limited thereto.

[268] A width of an upper surface of the fourth layer ML4 may be less than that of a lower surface of the fourth layer ML4. The width of the upper surface of the fourth layer ML4 may be substantially the same as that of a lower surface of the fifth layer ML5. A width of an upper surface of the fifth layer ML5 may be less than that of the lower surface of the fifth layer ML5. The width of the upper surface of the fifth layer ML5 may be substantially the same as that of a lower surface of the sixth layer ML6. A width of an upper surface of the sixth layer ML6 may be less than that of the lower surface of the sixth layer ML6. In this structure, the inclined surface of the second metal layer MTL2 including the fourth layer ML4, the fifth layer ML5, and the sixth layer ML6 may be continuously formed from the lower surface to the upper surface at an equal taper angle.

[269] The second metal layer MTL2 may be, for example, the second source-drain electrode.

[270] The fourth layer ML4 and the sixth layer ML6 may be metal layers including a same material, and the fifth layer ML5 may be a metal layer including a different material from the fourth layer ML4 and the sixth layer ML6. For example, the fourth layer ML4 and the sixth layer ML6 may include titanium (Ti), and the fifth layer ML5 may include aluminum (Al). For example, the second metal layer MTL2 including the fourth layer ML4, the fifth layer ML5, and the sixth layer ML6 may be in the form of a multilayer of Ti, Al, and Ti. As the fourth to sixth layers (ML4, ML5, and ML6) include these materials, the fifth layer ML5 can be configured with a material having better conductivity, and the fourth layer ML4 and the sixth layer ML6 can be configured with a material capable of protecting the fifth layer ML5 during the manufacturing process.

[271] The second metal layer MTL2 included in the second moisture preventing structure MPS2 may have a continuously tapered inclined surface. Since the second metal layer MTL2 has this structure, a pore that may be caused by a titanium (Ti) tip may not be formed. For example, in FIG. 8, there may occur a phenomenon in which aluminum pores are formed. These pores may be formed by titanium (Ti) tips located on and underneath aluminum (Al). The example embodiment of FIG. 9 can prevent the formation of pore that may be caused by a titanium (Ti) tip in the second metal layer MTL2.

[272] The first encapsulation layer 341 and the third encapsulation layer 343 may be formed on the intermediate layer EL and a common electrode CE.

[273] Referring to FIG. 9, in one or more aspects, in an area where the second moisture preventing structure MPS2 is disposed, the intermediate layer EL may have several portions. The intermediate layer EL may include a first portion ELI, a second portion EL2, and a third portion EL3. As illustrated in FIG. 9, the first portion ELI, the second portion EL2, and the third portion EL3 of the intermediate layer EL may be spaced apart from each other. The first portion ELI, the second portion EL2, and the third portion EL3 of the intermediate layer EL may be expressed to be separated from each other.

[274] For example, the first portion ELI of the intermediate layer EL may be located on the sixth layer ML6 of the second metal layer MTL2. The second portion EL2 of the intermediate layer EL may be located on the inclined surface (e.g., a side surface) of the second metal layer MTL2. The fourth layer ML4, the fifth layer ML5, and the sixth layer ML6 of the second metal layer MTL2 may extend further in a first direction (e.g., a side surface direction) than some of insulating layers to form the undercut area UCA. For example, the fourth layer ML4, the fifth layer ML5, and the sixth layer ML6 of the second metal layer MTL2 may extend further than a portion of an insulating layer, such as the second interlayer insulating layer 323, to form the undercut area UCA.

[275] The third portion EL3 of the intermediate layer EL may be located adjacent to the undercut area UCA. For example, the third portion EL3 of the intermediate layer EL may be located in the depression. For example, the third portion EL3 of the intermediate layer EL may be disposed on the second interlayer insulating layer 323 in the depression. The third portion EL3 of the intermediate layer EL may be spaced apart from the second portion EL2 of the intermediate layer EL, and the third portion EL3 of the intermediate layer EL and the second portion EL2 of the intermediate layer EL may overlap with each other in a plan view.

[276] In one or more aspects, the common electrode CE may have several portions. The common electrode CE may include a first portion CE1, a second portion CE2, and a third portion CE3. As illustrated in FIG. 9, the first portion CE1, the second portion CE2, and the third portion CE3 of the common electrode CE may be spaced apart from each other. For example, the first portion CE1, the second portion CE2, and the third portion CE3 of the common electrode CE may be disposed to be separated from each other.

[277] The first portion CE1 of the common electrode CE may be located over the sixth layer ML6 of the second metal layer MTL2. The second portion CE2 of the common electrode CE may be located on the second portion EL2 of the intermediate layer EL. The second portion CE2 of the common electrode CE may also be located over the inclined surface (e.g., the side surface) of the second metal layer MTL2.

[278] The third portion CE3 of the common electrode CE may be located adjacent to the undercut area UCA. For example, the third portion CE3 of the common electrode CE may be located in the depression. For example, the third portion CE3 of the common electrode CE may be located on the third portion EL3 of the intermediate layer EL. The third portion CE3 of the common electrode CE may be spaced apart from the second portion CE2 of the common electrode CE, and the third portion CE3 of the common electrode CE and the second portion CE2 of the common electrode CE may overlap with each other in the plan view.

[279] FIGS. 10 to 12 are example views illustrating a process of manufacturing the first moisture preventing structure MPS 1 and the second moisture preventing structure MPS2 in the display device 100 according to aspects of the present disclosure. In discussions that follow for the configurations of FIGS. 10, 11 and 12, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 9 are omitted or briefly described for convenience of description.

[280] In one or more example embodiments, first, referring to FIG. 10, a depression may be formed in a portion where a second moisture preventing structure MPS2 is to be formed among portions of a second interlayer insulating layer 323 of the optical area OA, and thereafter, a first planarization layer (331a) material may be formed to fill the depression.

[281] After the first planarization layer (33 la) material is formed, a first metal layer MTL1 may be formed in a portion where a first moisture preventing structure MPS 1 is to be formed using a second source-drain electrode material, and a second metal layer MTL2 may be formed on the portion where the second moisture preventing structure MPS2 is to be formed.

[282] For example, the first metal layer MTL1 and the second metal layer MTL2 may be in the form of a multilayer of Ti, Al, and Ti.

[283] Next, as illustrated in FIG. 11, a second planarization layer (332a) material may be formed using a mask to cover at least one side surface and a portion of an upper surface of each of the first metal layer MTL1 and the second metal layer MTL2.

[284] Next, at least one pixel electrode PE and a bank 333 defining at least one light emitting element DE may be sequentially formed in the display area DA where at least one subpixel SP is formed.

[285] In this situation, a pixel electrode material may be etched using an anode etchant for forming the pixel electrode PE, but the first metal layer MTL1 and the second metal layer MTL2 may not be exposed to the anode etchant due to the second planarization layer (332a) material formed on the at least one side surface and the portion of the upper surface of each of the first metal layer MTL1 and the second metal layer MTL2. Accordingly, etching of metals included in the first metal layer MTL1 and the second metal layer MTL2, particularly aluminum Al, can be prevented, and thereby, the formation of aluminum pores can be prevented.

[286] For example, the second planarization layer (332a) material may be formed to cover at least one side surface and a portion of an upper surface of each of the first metal layer MTL1 and the second metal layer MTL2 to protect the first metal layer MTL1 and the second metal layer MTL2, thereby preventing the formation of aluminum pores.

[287] Next, as illustrated in FIG. 12, the second planarization layer (332a) material and the first planarization layer (331a) material may be etched to form respective structures of the first metal layer MTL1 and the second metal layer MLT2.

[288] FIG. 13 is example cross-sectional views of another first moisture preventing structure MPS1 and another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configuration of FIG. 13, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 10 are omitted or briefly described for convenience of description.

[289] The first moisture preventing structure MPS1 illustrated in FIG. 13 may be substantially the same as the first moisture preventing structure MPS1 illustrated in FIG. 9, and therefore, detailed discussions for this structure in the illustration of FIG. 13 are omitted.

[290] The second moisture preventing structure MPS2 illustrated in FIG. 13 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 9, except that a second gate insulating layer 322 is exposed in a depression. For example, in FIG. 9, the second moisture preventing structure MPS2 is not exposed, and in FIG. 13, the second moisture preventing structure MPS2 may be exposed.

[291] Referring to FIG. 13, in one or more example embodiments, the second moisture preventing structure MPS2 may include at least one depression in at least one insulating layer among a plurality of insulating layers. For example, the depression may be formed by the exposure of a portion of the second gate insulating layer 322 as a second interlayer insulating layer 323 is etched. A side pattern PS and a third portion EL3 of an intermediate layer EL may be disposed on the second gate insulating layer 322. A third portion CE3 of a common electrode CE may be located adjacent to an undercut area UCA. For example, the third portion CE3 of the common electrode CE may be located on the third portion EL3 of the intermediate layer EL, and the third portion EL3 of the intermediate layer EL may be located on the second gate insulating layer 322.

[292] FIG. 14 is an example cross-sectional view of another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configuration of FIG. 14, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 13 are omitted or briefly described for convenience of description.

[293] The second moisture preventing structure MPS2 illustrated in FIG. 14 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 13, except that an auxiliary metal layer MLA is disposed between inorganic insulating layers located in an undercut area UCA.

[294] Referring to FIG. 14, in one or more example embodiments, the second moisture preventing structure MPS2 may include the auxiliary metal layer MLA located in, or under, the undercut area UCA. Referring to FIG. 14, the auxiliary metal layer MLA may be disposed between a plurality of insulating layers located under a second metal layer MTL2. The auxiliary metal layer MLA may be located in a depression. For example, the auxiliary metal layer MLA may be disposed such that the auxiliary metal layer MLA extends from a portion disposed between a second gate insulating layer 322 and a second interlayer insulating layer 323 located under the second metal layer MTL2 to the depression so that the auxiliary metal layer MLA can be located inside thereof. A side pattern PS may be disposed on a portion of the auxiliary metal layer MLA disposed in the depression. For example, the auxiliary metal layer MLA may be disposed on the second gate insulating layer 322. For example, the auxiliary metal layer MLA may be exposed by the undercut area UCA of an organic insulating layer, and an intermediate layer EL may be located on the exposed auxiliary metal layer MLA. For example, the common electrode CE may be disposed on the intermediate layer EL.

[295] The auxiliary metal layer MLA may include a metal material. For example, the auxiliary metal layer MLA may include a single layer of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), or an alloy of two or more thereof, or a multiple layer of one or more of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and / or one or more alloys of two or more thereof. However, aspects of the present disclosure are not limited thereto. The auxiliary metal layer MLA may include the same material as a gate electrode material or a shield metal. For example, the auxiliary metal layer MLA may be in the form of a double layer of Mo and Ti or a single layer of Mo.

[296] During an etching process of forming the depression by patterning a metal material such as a pixel electrode PE or one or more metal layers (MTL1 and / or MTL2) during the process of forming the second moisture preventing structure MPS2 or patterning a plurality of insulating layers, the auxiliary metal layer MLA can prevent some of the etched insulating layers or insulating layers disposed thereunder from being over-etched. For example, referring to FIG. 14, a portion of a second interlayer insulating layer 323 disposed on the auxiliary metal layer MLA may be etched, while the undercut area UCA may be formed with a structure in which the auxiliary metal layer MLA is not etched.

[297] Referring to FIG. 14, a third portion EL3 of an intermediate layer EL may be located adjacent to the undercut area UCA. For example, the third portion EL3 of the intermediate layer EL may be located under a second portion EL2 of the intermediate layer EL. For example, the third portion EL3 of the intermediate layer EL may be located in the depression. The third portion EL3 of the intermediate layer EL may be disposed on the auxiliary metal layer MLA disposed in the depression. The third portion EL3 of the intermediate layer EL may be spaced apart from the second portion EL2 of the intermediate layer EL, and the third portion EL3 of the intermediate layer EL and the second portion EL2 of the intermediate layer EL may overlap with each other in a plan view.

[298] Referring to FIG. 14, a third portion CE3 of a common electrode CE may be located adjacent to the undercut area UCA. For example, the third portion CE3 of the common electrode CE may be located in the depression. For example, the third portion CE3 of the common electrode CE may be located on the third portion EL3 of the intermediate layer EL. The third portion CE3 of the common electrode CE may be spaced apart from a second portion CE2 of the common electrode CE, and the third portion CE3 of the common electrode CE and the second portion CE2 of the common electrode CE may overlap with each other in the plan view.

[299] In one or more aspects, the second moisture preventing structure MPS2 illustrated in FIG. 14 is different from the second moisture preventing structure MPS2 illustrated in FIG. 13, but a first moisture preventing structure MPS1 may be substantially the same as the first moisture preventing structure MPS1 illustrated in FIG. 13.

[300] FIG. 15 is an example cross-sectional view of another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configurations of FIG. 15, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 14 are omitted or briefly described for convenience of description.

[301] The second moisture preventing structure MPS2 illustrated in FIG. 15 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 13, except that an auxiliary metal layer MLA is disposed between inorganic insulating layers located in an undercut area UCA.

[302] Referring to FIG. 15, in one or more example embodiments, the auxiliary metal layer MLA may be disposed between a plurality of insulating layers located under a second metal layer MTL2. For example, a portion of the auxiliary metal layer MLA may be disposed between a second interlayer insulating layer 323 and a second gate insulating layer 322 located under the second metal layer MTL2. Unlike the auxiliary metal layer MLA illustrated in FIG. 14, the auxiliary metal layer MLA may not be located in a depression, and be disposed between the insulating layers. For example, in an etching process, the auxiliary metal layer MLA may be over-etched, and a portion of the auxiliary metal layer MLA may be etched and removed. For example, the portion of the auxiliary metal layer MLA in the depression may be etched and removed, and the remaining portion of the auxiliary metal layer MLA outside the depression may be not etched and removed. For example, the auxiliary metal layer MLA may not be disposed in the depression. A side pattern PS may be disposed on a portion of the second gate insulating layer 322 disposed in the depression. For example, the second gate insulating layer 322 may be exposed by the undercut area UCA of an organic insulating layer, and an intermediate layer EL may be located on the exposed second gate insulating layer 322.

[303] Referring to FIG. 15, a third portion EL3 of the intermediate layer EL may be located adjacent to the undercut area UCA. For example, the third portion EL3 of the intermediate layer EL may be located under a second portion EL2 of the intermediate layer EL. For example, the third portion EL3 of the intermediate layer EL may be located in the depression. The third part EL3 of the intermediate layer EL may be located on the second gate insulating layer 322 located in the depression. The third portion EL3 of the intermediate layer EL may be spaced apart from the second portion EL2 of the intermediate layer EL, and the third portion EL3 of the intermediate layer EL and the second portion EL2 of the intermediate layer EL may overlap with each other in a plan view.

[304] A third portion CE3 of a common electrode CE may be located adjacent to an undercut area UCA. For example, the third portion CE3 of the common electrode CE may be located on the third portion EL3 of the intermediate layer EL. The third portion CE3 of the common electrode CE may be spaced apart from the second portion CE2 of the common electrode CE, and the third portion CE3 of the common electrode CE and the second portion CE2 of the common electrode CE may overlap with each other in the plan view.

[305] In one or more aspects, the second moisture preventing structure MPS2 illustrated in FIG. 15 is different from the second moisture preventing structure MPS2 illustrated in FIG. 13, but a first moisture preventing structure MPS1 may be substantially the same as the first moisture preventing structure MPS1 illustrated in FIG. 13.

[306] FIG. 16 is example cross-sectional views of another first moisture preventing structure MPS1 and another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configurations of FIG. 16, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 15 are omitted or briefly described for convenience of description.

[307] The first moisture preventing structure MPS1 illustrated in FIG. 16 may have the same configuration as the first moisture preventing structure MPS1 illustrated in FIG. 9, except that a protection layer PAS is disposed to cover a side surface of a first metal layer MTL1. For example, the protection layer PAS may be disposed between the first metal layer MTL1 and the first encapsulation layer 341. Specifically, the protection layer PAS is disposed to cover a portion of the upper surface and the side surface of a first metal layer MTL1.

[308] The second moisture preventing structure MPS2 illustrated in FIG. 16 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 9, except that the protection layer PAS is disposed to cover a side surface of a second metal layer MTL2.

[309] The protection layer PAS may be disposed on the first metal layer MTL1 and the second metal layer MTL2. Although not illustrated in FIG. 3, the protection layer PAS may cover the relay electrode RE and may be disposed between the first planarization layer 331 and the second planarization layer 332. For example, the protection layer PAS may cover a second source-drain metal layer and may be disposed between the first planarization layer 331 and the second planarization layer 332. The protection layer PAS may be in the form of, for example, a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) and / or silicon oxide (SiOx). However, aspects of the present disclosure are not limited thereto.

[310] Referring to FIG. 16, the first moisture preventing structure MPS1 may include the first metal layer MTL1 disposed on a second interlayer insulating layer 323. The protection layer PAS may be disposed to cover a side surface of the first metal layer MTL1.

[311] The protection layer PAS may be disposed to cover the side surface and a portion of an upper surface of the first metal layer MTL1. The protection layer PAS may be disposed to extend from the side surface of the first metal layer MTL1 and cover a portion of a side surface and a portion of an upper surface of the second interlayer insulating layer 323.

[312] As the protection layer PAS is disposed to cover the side surface of the first metal layer MTL1, at least one layer (e.g., aluminum (Al)) included in the first metal layer MTL1 may be prevented from being etched during the etching process.

[313] Referring to FIG. 16, the second moisture preventing structure MPS2 may include the second metal layer MTL2 disposed on the second interlayer insulating layer 323. The protection layer PAS may be disposed to cover a side surface of the second metal layer MTL2.

[314] The protection layer PAS may be disposed to cover the side surface and a portion of the upper surface of the second metal layer MTL2. An intermediate layer EL and a common electrode CE may be disposed on the protection layer PAS. For example, the intermediate layer EL and the common electrode CE may be disposed on the protection layer PAS and the portion of the second metal layer MTL2 exposed by the protection layer PAS.

[315] As the protection layer PAS is disposed to cover the side surface of the second metal layer MTL2, at least one layer (e.g., aluminum (Al)) included in the second metal layer MTL2 may be prevented from being etched during the etching process.

[316] Referring to FIG. 16, a third portion EL3 of the intermediate layer EL may be located adjacent to an undercut area UCA. For example, the third portion EL3 of the intermediate layer EL may be located in a depression. The third portion EL3 of the intermediate layer EL may be spaced apart from a second portion EL2 of the intermediate layer EL, and the third portion EL3 of the intermediate layer EL and the second portion EL2 of the intermediate layer EL may overlap with each other in a plan view.

[317] A third portion CE3 of the common electrode CE may be located adjacent to the undercut area UCA. For example, the third portion CE3 of the common electrode CE may be located on the third portion EL3 of the intermediate layer EL. For example, the third portion EL3 of the intermediate layer EL may be located on the second interlayer insulating layer 323. The third portion CE3 of the common electrode CE may be spaced apart from the second portion CE2 of the common electrode CE, and the third portion CE3 of the common electrode CE and the second portion CE2 of the common electrode CE may overlap with each other in the plan view.

[318] Referring to FIG. 16, the protection layer PAS may overlap with the second portion EL2 of the intermediate layer EL and the second portion CE2 of the common electrode CE in a plan view. The protection layer PAS may be spaced apart from the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE, and may overlap with the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE in the plan view.

[319] FIGS. 17 to 22 are example views illustrating a process of manufacturing the first moisture preventing structure MPS 1 and the second moisture preventing structure MPS2 in the display device 100 according to aspects of the present disclosure. In discussions that follow for the configuration of FIGS. 17 to 22, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 16 are omitted or briefly described for convenience of description.

[320] In one or more example embodiments, first, referring to FIG. 17, a depression may be formed in a portion where a second moisture preventing structure MPS2 is to be formed among portions of a second interlayer insulating layer 323 of the optical area OA, and thereafter, a first planarization layer (331a) material may be formed to fill the depression.

[321] After the first planarization layer (33 la) material is formed, a first metal layer MTL1 may be formed in a portion where a first moisture preventing structure MPS 1 is to be formed using a second source-drain electrode material, and a second metal layer MTL2 may be formed on the portion where the second moisture preventing structure MPS2 is to be formed.

[322] For example, the first metal layer MTL1 and the second metal layer MTL2 may be in the form of a multilayer of Ti, Al, and Ti.

[323] Next, as illustrated in FIG. 18, a protection layer (PASa) material may be deposited to cover all of the first metal layer MTL1 and the second metal layer MTL2. For example, the protection layer (PASa) material may be deposited to cover the upper and side surfaces of the first metal layer MTL1 and the second metal layer MTL2, but is not limited thereto.

[324] Next, as illustrated in FIG. 19, a second planarization layer (332a) material may be formed on the protection layer (PASa) material using a mask to overlap with a side surface and a portion of an upper surface of each of the first metal layer MTL1 and the second metal layer MTL2. For example, the second planarization layer (332a) material may be disposed on a portion of the upper surface and the side surface of the protection layer (PASa) material.

[325] Next, at least one pixel electrode PE and a bank 333 defining at least one light emitting element DE may be sequentially formed in the display area DA where at least one subpixel SP is formed.

[326] In this situation, a pixel electrode material may be etched using an anode etchant for forming the pixel electrode PE, but the first metal layer MTL1 and the second metal layer MTL2 may not be exposed to the anode etchant due to the protection layer (PASa) material formed on the side surface and the portion of the upper surface of each of the first metal layer MTL1 and the second metal layer MTL2 and the second planarization layer (332a) material. Accordingly, etching of metals included in the first metal layer MTL1 and the second metal layer MTL2, particularly aluminum Al, can be prevented, and thereby, the formation of aluminum pores can be prevented.

[327] Next, as illustrated in FIG. 20, the protection layer (PASa) material may be etched using the second planarization layer (332a) material as a mask, and thereby, the protection layer PASa can be patterned.

[328] Next, as illustrated in FIG. 21, the second planarization layer (332a) material and the first planarization layer (331a) material may be etched to form a structure in which a protection layer PAS is disposed on the side surface and the portion of the upper surface of each of the first metal layer MTL1 and the second metal layer MLT2.

[329] Next, as illustrated in FIG. 22, an intermediate layer EL, a common electrode CE, and an encapsulation layer 340 may be sequentially formed to form the first moisture preventing structure MPS1 and the second moisture preventing structure MPS2 according to aspects of the present disclosure.

[330] In this situation, the first moisture preventing structure MPS1 may be located in the second non-display area NDA2 located outside of the display area DA, and thereby, the intermediate layer EL, the common electrode CE, and a second encapsulation layer 342 may not be disposed on the first metal layer MTL1. In addition, the second moisture preventing structure MPS2 may be located in the optical area OA inside of the display area DA, and thereby, the second encapsulation layer 342 may not be disposed on the second metal layer MTL2.

[331] FIG. 23 is an example cross-sectional view of another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configurations of FIG. 23, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 22 are omitted or briefly described for convenience of description.

[332] The second moisture preventing structure MPS2 illustrated in FIG. 23 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 16 except that a second gate insulating layer 322 is exposed in a depression.

[333] Referring to FIG. 23, in one or more example embodiments, the second moisture preventing structure MPS2 may include at least one depression in least one insulating layer among a plurality of insulating layers. For example, the depression may be formed by the exposure of a portion of the second gate insulating layer 322 as a second interlayer insulating layer 323 is etched. A side pattern PS and a third portion EL3 of an intermediate layer EL may be disposed on the second gate insulating layer 322.

[334] The protection layer PAS may be disposed to cover at least one side surface of the second metal layer MTL2. The protection layer PAS may be disposed to cover the at least one side surface and a portion of an upper surface of the second metal layer MTL2. The intermediate layer EL and a common electrode CE may be disposed on the protection layer PAS. The intermediate layer EL and a common electrode CE may be disposed on the portion of the upper surface of the second metal layer MTL2 and the upper and side surfaces of the protection layer PAS.

[335] Referring to FIG. 23, the protection layer PAS may overlap with a second portion EL2 of the intermediate layer EL and a second portion CE2 of the common electrode CE in a plan view. The protection layer PAS may be spaced apart from the third portion EL3 of the intermediate layer EL and a third portion CE3 of the common electrode CE, and may overlap with the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE in the plan view.

[336] In one or more aspects, the second moisture preventing structure MPS2 illustrated in FIG. 23 is different from the second moisture preventing structure MPS2 illustrated in FIG. 16, but a first moisture preventing structure MPS1 may be substantially the same as the first moisture preventing structure MPS1 illustrated in FIG. 16.

[337] FIG. 24 is an example cross-sectional view of another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configuration of FIG. 24, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 23 are omitted or briefly described for convenience of description.

[338] The second moisture preventing structure MPS2 illustrated in FIG. 24 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 23 except that an auxiliary metal layer MLA is disposed between inorganic insulating layers located in an undercut area UCA. For example, the auxiliary metal layer MLA may be disposed on the second gate insulating layer 322.

[339] Referring to FIG. 24, in one or more example embodiments, the second moisture preventing structure MPS2 may include the auxiliary metal layer MLA located in, or under, the undercut area UCA. Referring to FIG. 24, the auxiliary metal layer MLA may be disposed between a plurality of insulating layers located under a second metal layer MTL2. The auxiliary metal layer MLA may be located in a depression. For example, the auxiliary metal layer MLA may be disposed such that the auxiliary metal layer MLA extends from a portion disposed between a second gate insulating layer 322 and a second interlayer insulating layer 323 located under the second metal layer MTL2 to the depression so that the auxiliary metal layer MLA can be located inside thereof. A side pattern PS may be disposed on a portion of the auxiliary metal layer MLA disposed in the depression. For example, the auxiliary metal layer MLA may be exposed by the undercut area UCA of an organic insulating layer, and an intermediate layer EL may be located on the exposed auxiliary metal layer MLA, and the common electrode CE may be located on the intermediate layer EL.

[340] The auxiliary metal layer MLA may include the same metallic material as the auxiliary metal layer MLA illustrated in FIG. 14.

[341] During an etching process of forming the depression by patterning a metal material such as a pixel electrode PE or one or more metal layers (MTL1 and / or MTL2) during the process of forming the second moisture preventing structure MPS2 or patterning a plurality of insulating layers, the auxiliary metal layer MLA can prevent some of the etched insulating layers or insulating layers disposed thereunder from being over-etched. For example, referring to FIG. 24, a portion of a second interlayer insulating layer 323 disposed on the auxiliary metal layer MLA may be etched, while the undercut area UCA may be formed with a structure in which the auxiliary metal layer MLA is not etched.

[342] Referring to FIG. 24, the intermediate layer EL and a common electrode CE may have the same arrangement relationship and configuration as those of the intermediate layer EL and the common electrode CE illustrated in FIG. 14.

[343] Referring to FIG. 24, the protection layer PAS may overlap with a second portion EL2 of the intermediate layer EL and a second portion CE2 of the common electrode CE in a plan view. For example, the first portion ELI of the intermediate layer EL and the first portion CE1 of the common electrode CE may be disposed on the upper surface of the protection layer PAS, the second portion EL2 of the intermediate layer EL and the second portion CE2 of the common electrode CE may be disposed on the side surface of the protection layer PAS, and the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE may be disposed on the auxiliary metal layer MLA. The protection layer PAS may be spaced apart from a third portion EL3 of the intermediate layer EL and a third portion CE3 of the common electrode CE, and may overlap with the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE in the plan view.

[344] In one or more aspects, the second moisture preventing structure MPS2 illustrated in FIG. 24 is different from the second moisture preventing structure MPS2 illustrated in FIG. 16, but a first moisture preventing structure MPS1 may be substantially the same as the first moisture preventing structure MPS1 illustrated in FIG. 16.

[345] FIG. 25 is an example cross-sectional view of another second moisture preventing structure MPS2 according to aspects of the disclosure. In discussions that follow for the configurations of FIG. 25, discussions for features and configurations equal, substantially equal, or similar to the features and configurations described with reference to FIGS. 1 to 24 are omitted or briefly described for convenience of description.

[346] The second moisture preventing structure MPS2 illustrated in FIG. 25 may have the same configuration as the second moisture preventing structure MPS2 illustrated in FIG. 23 except that an auxiliary metal layer MLA is disposed between inorganic insulating layers located in an undercut area UCA.

[347] Referring to FIG. 25, in one or more example embodiments, the auxiliary metal layer MLA may be disposed between a plurality of insulating layers located under a second metal layer MTL2. For example, a portion of the auxiliary metal layer MLA may be disposed between a second interlayer insulating layer 323 and a second gate insulating layer 322 located under the second metal layer MTL2. Unlike the auxiliary metal layer MLA illustrated in FIG. 24, the auxiliary metal layer MLA may not be located in a depression, and be disposed between the insulating layers. For example, in an etching process, the auxiliary metal layer MLA may be over-etched, and a portion of the auxiliary metal layer MLA may be etched and removed. For example, the portion of the auxiliary metal layer MLA in the depression may be etched and removed, and the remaining portion of the auxiliary metal layer MLA outside the depression may be not etched and removed. For example, the auxiliary metal layer MLA may not be disposed in the depression. A side pattern PS may be disposed on a portion of the second gate insulating layer 322 disposed in the depression. For example, the second gate insulating layer 322 may be exposed by the undercut area UCA of an organic insulating layer, and an intermediate layer EL may be located on the exposed second gate insulating layer 322.

[348] Referring to FIG. 25, the intermediate layer EL and a common electrode CE may have the same arrangement relationship and configuration as those of the intermediate layer EL and the common electrode CE illustrated in FIG. 15.

[349] Referring to FIG. 25, the protection layer PAS may overlap with a second portion EL2 of the intermediate layer EL and a second portion CE2 of the common electrode CE in a plan view. For example, the first portion ELI of the intermediate layer EL and the first portion CE1 of the common electrode CE may be disposed on the upper surface of the protection layer PAS, the second portion EL2 of the intermediate layer EL and the second portion CE2 of the common electrode CE may be disposed on the side surface of the protection layer PAS, and the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE may be disposed on the second gate insulating layer 322. The protection layer PAS may be spaced apart from a third portion EL3 of the intermediate layer EL and a third portion CE3 of the common electrode CE, and may overlap with the third portion EL3 of the intermediate layer EL and the third portion CE3 of the common electrode CE in the plan view.

[350] In one or more aspects, the second moisture preventing structure MPS2 illustrated in FIG. 25 is different from the second moisture preventing structure MPS2 illustrated in FIG. 16, but a first moisture preventing structure MPS1 may be substantially the same as the first moisture preventing structure MPS1 illustrated in FIG. 16.

[351] The examples, aspects, and embodiments for the display device 100 and the display panel 110 described herein may be described as follows.

[352] According to the one or more example embodiments described herein, a display device can be provided that includes a substrate including a display area including at least one light emitting element, a non-display area including at least one power line extending from a pad area and surrounding the display area, and an optical area located in the display area and including an open area from which a portion of the substrate is removed, a first moisture preventing structure extending from a portion of the power line and including a first metal layer, and a second moisture preventing structure disposed between the display area and the open area in the optical area and including a second metal layer.

[353] In one or more aspects, in the display device, the first metal layer and the second metal layer may include a same material and have a tapered shape.

[354] In one or more aspects, the display device may further include a thin film transistor, and a relay electrode electrically connecting the light emitting element and the thin film transistor to each other. In one or more aspects, the first metal layer and the second metal layer may include the same material as the relay electrode.

[355] In one or more aspects, the display device may further include an outer dam structure disposed in the non-display area. In one or more aspects, the first moisture preventing structure may include a first inner moisture preventing structure disposed between the display area and the outer dam structure, and a first outer moisture preventing structure disposed between the outer dam structure and the pad area.

[356] In one or more aspects, the display device may further include an inner dam structure disposed in the optical area. In one or more aspects, the second moisture preventing structure may include a second inner moisture preventing structure disposed between the display area and the inner dam structure, and a second outer moisture preventing structure disposed between the inner dam structure and the open area in the optical area.

[357] In one or more aspects, the display device may further include an encapsulation layer disposed on the light emitting element. In one or more aspects, the encapsulation layer may be disposed to cover the first metal layer and the second metal layer.

[358] In one or more aspects, the display device may further include a protection layer disposed to cover respective side surfaces of the first metal layer and the second metal layer.

[359] In one or more aspects, in the display device, the non-display area may include a bending area located between the pad area and the display area, and the first moisture preventing structure may be located between the display area and the bending area.

[360] In one or more aspects, in the display device, the first moisture preventing structure may include an extension part and a head part. In one or more aspects, the extension part extends from a portion of the power line, and when a plurality of first moisture preventing structures are disposed, a plurality of extension parts may be disposed to be spaced apart from each other. In one or more aspects, the head part may be located at an end of the extension part and have a width greater than the extension part.

[361] In one or more aspects, in the display device, the power line may include a first power line and a second power line. In one or more aspects, each of the first power line and the second power line may include the first moisture preventing structure. In one or more aspects, the first moisture preventing structure disposed in the first power line and the first moisture preventing structure disposed in the second power line may be spaced apart from each other and face each other.

[362] In one or more aspects, in the display device, the first power line may include one of a low voltage line, a high voltage line, and an initialization voltage line. In one or more aspects, the second power line may include a voltage line different from the first power line among the low voltage line, the high voltage line, and the initialization voltage line.

[363] In one or more aspects, at least one first moisture preventing structure disposed in the first power line may be disposed to protrude toward the second power line, and the at least one first moisture preventing structure disposed in the second power line may be disposed to protrude toward the first power line.

[364] In one or more aspects, in the display device, the first metal layer may include a first layer disposed on an insulating layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. In one or more aspects, the second metal layer may include a fourth layer disposed on the insulating layer, a fifth layer disposed on the fourth layer, and a sixth layer disposed on the fifth layer.

[365] In one or more aspects, the first layer and the third layer may be configured with a material capable of protecting the second layer during a manufacturing process, and the first metal layer included in the first moisture preventing structure and the second metal layer included in the second moisture preventing structure may have a continuously tapered inclined surface.

[366] In one or more aspects, in the display device, the second moisture preventing structure may include a side pattern disposed in a depression of the insulating layer. In one or more aspects, the side pattern may overlap with the second metal layer in a plan view.

[367] In one or more aspects, in the display device, the light emitting element may include an intermediate layer extending from the display area to the optical area. In one or more aspects, the intermediate layer may be disposed on the second metal layer and be disconnected in the depression.

[368] In one or more aspects, the intermediate layer may comprise a first portion and a second portion located on the second metal layer and a third portion located in the depression, and the second portion may be spaced apart from and overlaps with the third portion.

[369] In one or more aspects, in the display device, the second metal layer may protrude more than the side pattern.

[370] In one or more aspects, the display device may further include an auxiliary metal layer spaced apart from the second metal layer and disposed under the second metal layer.

[371] In one or more aspects, in the display device, the auxiliary metal layer may be disposed to extend inside of the depression, and the side pattern may be disposed on the auxiliary metal layer.

[372] In one or more aspects, in the display device, the auxiliary metal layer may be disposed outside of the depression.

[373] In one or more aspects, the intermediate layer may be located on exposed second gate insulating layer or the auxiliary metal layer in the depression.

[374] In one or more aspects, the display device may further include a thin film transistor electrically connected to the light emitting element and comprising a gate electrode. In one or more aspects, the auxiliary metal layer and the gate electrode may include a same material.

[375] In one or more aspects, the display device may further include a crack preventing structure formed as a closed loop in a ring shape spaced apart from the open area in the optical area by a certain distance, and the crack preventing structure may comprise a first layer and a second layer overlapping each other.

[376] According to the one or more example embodiments described herein, a display device can be provided that includes a substrate including a display area comprising at least one light emitting element, a non-display area surrounding the display area and including a power line area that is disposed between a pad area and the display area and that includes at least one power line extending from the pad area, and an optical area located in the display area and including an open area from which a portion of the substrate is removed; at least one moisture preventing structure disposed in at least one of the power line area or the optical area, and the light emitting element may comprise an intermediate layer extending from the display area to the optical area, and a plurality of portions of the intermediate layer may be disposed to be spaced apart.

[377] According to the one or more example embodiments described herein, a display device can be provided that includes a substrate including a display area comprising at least one light emitting element, a non-display area disposed outside the display area and comprising at least one power line extending from a pad area, and an open area located in the display area and from which a portion of the substrate is removed, wherein an opto-electronic component is arranged to overlap the opening in a plan view; at least one protrusion disposed in the non-display area, between the pad area and the display area, with each of the at least one protrusion protruding from a side of the power line and including a first metal layer; and at least one undercut area disposed in the optical area, between an edge of the display area and the open area, with each of the at least one undercut area including a second metal layer.

[378] According to the one or more aspects described herein, a display device may be provided with improved reliability.

[379] According to the one or more aspects described herein, a display device may be provided including at least one moisture preventing structure disposed in a power line area and an optical area.

[380] According to the one or more aspects described herein, a display device may be provided that is capable of causing a moisture flowing path to lengthen by including at least one moisture preventing structure disposed in a power line area and an optical area.

[381] According to the one or more aspects described herein, a display device may be provided that is capable of reducing or preventing moisture from entering a display area from an area outside of the display area by including a moisture preventing structure.

[382] According to the one or more aspects described herein, a display device may be provided that is capable of reducing or preventing moisture from entering a display area from an area outside of the display area, which may cause the lifetime of light emitting elements to be reduced or cause defects in the light emitting elements, and thereby, enabling the display device to be driven with low power.

[383] The above description has been presented to enable any person skilled in the art to make, use and practice the technical features of the present disclosure, and has been provided in the context of a particular application and its requirements as examples. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and the accompanying drawings provide an example of the technical idea of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.

Claims

1. A display device comprising:a substrate comprising a display area comprising at least one light emitting element, a nondisplay area comprising at least one power line extending from a pad area and surrounding the display area, and an optical area comprising an open area and located in the display area;a first moisture preventing structure extending from a portion of the power line and including a first metal layer; anda second moisture preventing structure disposed in the optical area, between an edge of the display area and the open area and including a second metal layer.

2. The display device of claim 1, wherein the first metal layer and the second metal layer comprise a same material and have a tapered shape.

3. The display device of claim 1 or 2, further comprising:a thin film transistor; anda relay electrode electrically connecting the light emitting element and the thin film transistor to each other,wherein the first metal layer and the second metal layer comprise the same material as the relay electrode.

4. The display device of any preceding claim, further comprising an outer dam structure disposed in the non-display area between the pad area and the display area,wherein the first moisture preventing structure comprises:a first inner moisture preventing structure disposed between the display area and the outer dam structure; anda first outer moisture preventing structure disposed between the outer dam structure and thepad area.

5. The display device of any preceding claim, further comprising an inner dam structure disposed in the optical area between the display area and the open area,wherein the second moisture preventing structure comprises:a second inner moisture preventing structure disposed between the display area and the inner dam structure; anda second outer moisture preventing structure disposed between the inner dam structure and the open area.

6. The display device of any preceding claim, further comprising an encapsulation layer disposed on the light emitting element,wherein the encapsulation layer is disposed to cover the first metal layer and the second metal layer.

7. The display device of claim 6, further comprising a protection layer disposed to cover respective side surfaces of the first metal layer and the second metal layer.

8. The display device of any preceding claim, wherein the non-display area comprises a bending area located between the pad area and the display area, and the first moisture preventing structure is located between the display area and the bending area.

9. The display device of any preceding claim, wherein the first moisture preventing structure comprises an extension part and a head part,wherein the extension part protrudes from a portion of the power line, and when a plurality of first moisture preventing structures are disposed, a plurality of extension parts are disposed to be spaced apart from each other, andwherein the head part is located at an end of the extension part and has a width greater than the extension part.

10. The display device of any preceding claim, wherein the power line comprises a first power line and a second power line, and each of the first power line and the second power line comprises the first moisture preventing structure, andwherein the first moisture preventing structure disposed in the first power line and the first moisture preventing structure disposed in the second power line are spaced apart from each other and face each other.

11. The display device of claim 10, wherein the first power line comprises one of a low voltage line, a high voltage line, and an initialization voltage line, and the second power line comprises a voltage line different from the first power line among the low voltage line, the high voltage line, and the initialization voltage line.

12. The display device of claim 10 or 11, wherein at least one first moisture preventing structure disposed in the first power line is disposed to protrude toward the second power line, and the at least one first moisture preventing structure disposed in the second power line is disposed to protrude toward the first power line.

13. The display device of any preceding claim, wherein the first metal layer comprises:a first layer disposed on an insulating layer;a second layer disposed on the first layer; anda third layer disposed on the second layer, andwherein the second metal layer comprises:a fourth layer disposed on the insulating layer;a fifth layer disposed on the fourth layer; anda sixth layer disposed on the fifth layer.

14. The display device of claim 13, wherein the second moisture preventing structure comprises a side pattern disposed in a depression of the insulating layer, and the side pattern overlaps with the second metal layer in a plan view.

15. The display device of claim 14, wherein the light emitting element comprises an intermediate layer extending from the display area to the optical area, and the intermediate layer is disposed on the second metal layer and is disconnected in the depression.

16. The display device of claim 15, wherein the intermediate layer comprises a first portion and a second portion located on the second metal layer and a third portion located in the depression, andthe second portion is spaced apart from and overlaps with the third portion.

17. The display device of any of claims 14 to 16, wherein the second metal layer protrudes more than the side pattern.

18. The display device of any of claims 15 to 17, further comprising an auxiliary metal layer spaced apart from the second metal layer and disposed under the second metal layer.

19. The display device of claim 18, wherein the auxiliary metal layer is disposed to extend inside of the depression, and the side pattern is disposed on the auxiliary metal layer.

20. The display device of claim 18, wherein the auxiliary metal layer is disposed outside of the depression.

21. The display device of claim 18 or 19, wherein the intermediate layer is located on exposed second gate insulating layer or the auxiliary metal layer in the depression.

22. The display device of any of claims 18 to 21, further comprising a thin film transistor electrically connected to the light emitting element and comprising a gate electrode,wherein the auxiliary metal layer and the gate electrode comprise a same material.

23. The display device of any preceding claim, further comprising a crack preventing structure formed as a closed loop in a ring shape spaced apart from the optical area by a certain distance, andwherein the crack preventing structure comprises a first layer and a second layer overlapping each other.

24. A display device comprising:a substrate comprising a display area comprising at least one light emitting element, a nondisplay area disposed around the display area and comprising a power line area that is disposed between a pad area and the display area and extending from the pad area, and an optical area located in the display area and including an open area from which a portion of the substrate is removed;at least one moisture preventing structure disposed in at least one of the power line area or the optical area, andwherein the light emitting element comprises an intermediate layer extending from the display area to the optical area, and a plurality of portions of the intermediate layer are disposed to be spaced apart.

25. A display device comprising:a substrate comprising (i) a display area comprising at least one light emitting element, (ii) a non-display area disposed outside the display area and comprising at least one power line extending from a pad area, and (iii) an open area located in the display area and from which a portion of the substrate is removed, wherein an opto-electronic component is arranged to overlap the open area in a plan view;at least one protrusion disposed in the non-display area, between the pad area and the display area, with each of the at least one protrusion protruding from a side of the power line and including a first metal layer; andat least one undercut area disposed in an optical area, between an edge of the display areaand the open area, with each of the at least one undercut area including a second metal layer.A

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