Integrated passive device and manufacturing method thereof

Abstract

The present application discloses an integrated passive device and a method for manufacturing the same. It relates to the field of semiconductor technology. The integrated passive device includes a substrate; and a first type of passive element and a second type of passive element located on one side of the substrate and arranged along a first direction; wherein the first type of passive element and the second type of passive element are connected, and the first direction is a direction parallel to the surface of the substrate. By changing the passive elements deposited on the substrate in the integrated passive device from a vertical stack to a horizontal arrangement (arranged along a first direction parallel to the surface of the substrate), the use of at least one dielectric layer is reduced, the interlayer parasitic capacitance and the loss of the dielectric material are reduced, thereby improving the inductor Q value and the self-resonant frequency, and ultimately improving the device performance. This solves the technical problem in the prior art that the integrated passive device adopts a vertical stacking architecture to arrange various passive elements, and the multi-layer dielectric layer introduces interlayer parasitic capacitance and high-frequency loss, resulting in poor device performance stability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated passive device and a manufacturing method thereof. Background Art

[0002] In recent years, the integrated passive device (IPD) market has experienced significant growth due to the growing demand for miniaturization of electronic devices and advances in the semiconductor industry. IPDs significantly improve circuit density and system reliability by integrating discrete passive components (resistors, capacitors, and inductors) into a single chip-scale package.

[0003] Existing integrated passive devices generally utilize a vertical stacking technique for passive components on a single side of a substrate. For a typical structure consisting of a capacitor and a double-layer inductor, the manufacturing process is as follows: First, a MIM (metal-insulator-metal) capacitor structure (composed of a first electrode, a first dielectric layer, and a second electrode) is constructed on the substrate surface. Subsequently, a second dielectric layer, a first inductor layer (connected to the capacitor via vias), a third dielectric layer, and a second inductor layer (connected to the first inductor layer via vias) are sequentially deposited, ultimately forming a vertically stacked capacitor-dual inductor layout.

[0004] However, this vertical stacking architecture has the following technical bottlenecks: (1) The introduction of multiple dielectric layers inevitably generates interlayer parasitic capacitance, whose value is proportional to the dielectric constant of the dielectric layer and the electrode overlap area, causing the inductor self-resonance frequency to shift significantly downward and reducing the quality factor (Q value), affecting the device performance stability; (2) In high-frequency scenarios such as millimeter waves, the polarization loss (caused by dipole steering hysteresis) and leakage loss (caused by material conductivity) of the dielectric material increase sharply, causing the device temperature to rise, which may trigger the risk of inductor metal migration and capacitor dielectric breakdown, further affecting the device performance stability.

[0005] Therefore, there is an urgent need for an innovative integrated passive device architecture that can fundamentally reduce parasitic effects and high-frequency losses and improve device performance by reducing the use of dielectric layers. Summary of the Invention

[0006] The embodiments of the present disclosure provide an integrated passive device and a method for manufacturing the same, aiming to at least address the problem in the prior art of using a vertically stacked architecture to arrange various passive components, resulting in poor device performance stability due to parasitic capacitance and high-frequency loss introduced by multiple dielectric layers.

[0007] According to one aspect of an embodiment of the present disclosure, an integrated passive device is provided, comprising: a substrate; and a first type of passive components and a second type of passive components located on one side of the substrate and arranged along a first direction; wherein the first type of passive components and the second type of passive components are connected, and the first direction is a direction parallel to the surface of the substrate.

[0008] Optionally, the first type of passive element includes: a first electrode located in a first region on one side of the substrate; a first dielectric layer located on a side of the first electrode away from the substrate; and a second electrode located on a side of the first dielectric layer away from the substrate.

[0009] Optionally, the second type of passive component includes: a first inductor layer located in a second area on one side of the substrate; wherein the first inductor layer includes at least two inductor areas spaced apart along the first direction, and at least one inductor area is connected to the first type of passive component; a first metal support structure, the first metal support structure including a plurality of support units spaced apart along the first direction; wherein at least one support unit is located between adjacent inductor areas in a non-contact manner and covers a portion of the surface of the substrate, and at least some of the support units are respectively located on a side of each inductor area away from the substrate; a second dielectric layer located on a side of the first metal support structure away from the substrate, the second dielectric layer exposing a portion of the surface of at least some of the support units; and a second inductor layer located on a side of the second dielectric layer away from the substrate, the second inductor layer covering the exposed surfaces of the plurality of support units.

[0010] Optionally, the first inductor layer includes a first inductor region and a second inductor region spaced apart along the first direction, and the first inductor region is connected to the first type of passive element; the first metal support structure includes a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein, the first support unit is located on a side of the first inductor region away from the substrate, the second support unit is located between the first inductor region and the second inductor region in a non-contact manner and covers a portion of the surface of the substrate, the third support unit is located on a side of the second inductor region away from the substrate; and the second dielectric layer exposes a portion of the surface of the first support unit and a portion of the surface of the third support unit.

[0011] Optionally, the integrated passive device further includes: a second metal support structure located on one side of the substrate, the second metal support structure being connected to the first type of passive components and the second type of passive components; and a conductive connection structure located on a side of the second metal support structure away from the substrate.

[0012] Optionally, the second metal support structure includes: a fourth support unit located in a third area on one side of the substrate, the fourth support unit being connected to the first type of passive component; and a fifth support unit located in a fourth area on one side of the substrate, the fifth support unit being connected to the second type of passive component.

[0013] Optionally, the first type of passive element includes: a first electrode located in a first area on one side of the substrate; a first dielectric layer located on a side of the first electrode away from the substrate; and a second electrode located on a side of the first dielectric layer away from the substrate; and in the first direction, the fourth support unit is isolated from the first type of passive element by an air dielectric; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode.

[0014] Optionally, the second type of passive component includes at least two layers of inductors, and the fifth supporting unit is only connected to the inductors of the second type of passive component that are arranged on the surface of the substrate.

[0015] Optionally, the conductive connection structure includes: a first conductive connection member located on a side of the fourth support unit away from the substrate; and a second conductive connection member located on a side of the fifth support unit away from the substrate.

[0016] Optionally, the second type of passive component further includes: a third dielectric layer, the third dielectric layer being located on a side of the second inductor layer away from the substrate and exposing a portion of the surface of the second inductor layer; and a third inductor layer, the third inductor layer being located on a side of the third dielectric layer away from the substrate and covering the exposed surface of the second inductor layer.

[0017] According to another aspect of an embodiment of the present disclosure, a method for manufacturing an integrated passive device is also provided, comprising: manufacturing a substrate; and manufacturing a first type of passive component and a second type of passive component located on one side of the substrate and arranged along a first direction; wherein the first type of passive component and the second type of passive component are connected, and the first direction is a direction parallel to the surface of the substrate.

[0018] Optionally, the process of manufacturing the first type of passive component includes: manufacturing a first electrode, a first dielectric layer, and a second electrode; wherein the first electrode is located in a first region on one side of the substrate, the first dielectric layer is located on a side of the first electrode away from the substrate, and the second electrode is located on a side of the first dielectric layer away from the substrate; and the process of manufacturing the second type of passive component includes: manufacturing a first inductor layer, a first metal support structure, a second dielectric layer, and a second inductor layer; wherein the first inductor layer is located in a second region on one side of the substrate, the first inductor layer includes at least two inductor regions spaced apart along the first direction, and at least one inductor region is connected to the first type of passive component; the first metal support structure includes a plurality of support units spaced apart along the first direction; wherein at least one support unit is located between adjacent inductor regions in a non-contact manner and covers a portion of the surface of the substrate, and at least some of the support units are located on a side of each inductor region away from the substrate; the second dielectric layer is located on a side of the first metal support structure away from the substrate, exposing at least some of the surfaces of the support units; and the second inductor layer is located on a side of the second dielectric layer away from the substrate, and the second inductor layer covers the exposed surfaces of the plurality of support units.

[0019] Optionally, the process of making the first inductor layer includes: making a first inductor region and a second inductor region spaced apart along the first direction, and the first inductor region is connected to the first type of passive element; the process of making the first metal support structure includes: making a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein, the first support unit is located on a side of the first inductor region away from the substrate, the second support unit is located between the first inductor region and the second inductor region in a non-contact manner and covers a portion of the surface of the substrate, the third support unit is located on a side of the second inductor region away from the substrate; and the second dielectric layer exposes a portion of the surface of the first support unit and a portion of the surface of the third support unit.

[0020] Optionally, the manufacturing method also includes: manufacturing a second metal support structure located on one side of the substrate, the second metal support structure being connected to the first type of passive components and the second type of passive components; and manufacturing a conductive connection structure located on a side of the second metal support structure away from the substrate; the process of manufacturing the second metal support structure includes: manufacturing a fourth support unit located in a third area on one side of the substrate, the fourth support unit being connected to the first type of passive components; and manufacturing a fifth support unit located in a fourth area on one side of the substrate, the fifth support unit being connected to the second type of passive components.

[0021] Optionally, the process of making the first type of passive component includes: making a first electrode located in a first area on one side of the substrate; making a first dielectric layer located on a side of the first electrode away from the substrate; and making a second electrode located on a side of the first dielectric layer away from the substrate; and in the first direction, the fourth support unit and the first type of passive component are isolated by an air dielectric; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode; the second type of passive component includes at least two layers of inductance, and the fifth support unit is only connected to the inductance of the second type of passive component arranged on the surface of the substrate; the process of making the conductive connection structure includes: making a first conductive connector, the first conductive connector is located on a side of the fourth support unit away from the substrate; and making a second conductive connector, the second conductive connector is located on a side of the fifth support unit away from the substrate.

[0022] Optionally, the process of manufacturing the second type of passive component further includes: manufacturing a third dielectric layer, wherein the third dielectric layer is located on a side of the second inductor layer away from the substrate and exposes a portion of the surface of the second inductor layer; and manufacturing a third inductor layer, wherein the third inductor layer is located on a side of the third dielectric layer away from the substrate and covers the exposed surface of the second inductor layer.

[0023] In the integrated passive device and its manufacturing method proposed in this application, by changing the passive components deposited on the substrate in the integrated passive device from a vertical stack to a horizontal arrangement layout (arranged along a first direction parallel to the substrate surface), an innovation at the architectural level is achieved. Specifically, by arranging various passive components horizontally on the substrate surface, the use of at least one dielectric layer is reduced (that is, the dielectric layer between the passive components is reduced). By reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of dielectric materials are reduced, thereby improving the inductor Q value and self-resonant frequency, and ultimately improving the device performance. This solves the technical problem in the prior art that integrated passive devices use a vertical stacking architecture to arrange various passive components, and the multi-layer dielectric layers introduce interlayer parasitic capacitance and high-frequency losses, resulting in poor device performance stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of this application. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0025] Figure 1 A structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0026] Figure 2This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0027] Figure 3 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0028] Figure 4 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0029] Figure 5 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0030] Figure 6 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0031] Figure 7 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0032] Figure 8 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0033] Figure 9 This is another structural diagram of the manufacturing process of the integrated passive device provided in Example 1 of the present application;

[0034] Figure 10 This is a schematic structural diagram of the integrated passive device provided in Example 2 of the present application;

[0035] Figure 11 This is a schematic structural diagram of the integrated passive device provided in Example 3 of the present application;

[0036] Figure 12 This is a structural diagram of the integrated passive device provided in Example 4 of the present application. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0040] As mentioned in the background technology section, existing integrated passive devices generally adopt the technical path of vertically stacking passive components on a single surface of the substrate. However, this vertical stacking architecture has the following technical bottlenecks: (1) The introduction of multiple dielectric layers inevitably generates interlayer parasitic capacitance, whose value is proportional to the dielectric constant of the dielectric layer and the electrode overlap area, causing the inductor self-resonance frequency to shift significantly downward and reducing the quality factor (Q value), affecting the device performance stability; (2) In high-frequency scenarios such as millimeter waves, the polarization loss (caused by dipole steering hysteresis) and leakage loss (caused by material conductivity) of the dielectric material increase sharply, causing the device temperature to rise, which may trigger the risk of inductor metal migration and capacitor dielectric breakdown, further affecting the device performance stability.

[0041] In view of this, the embodiments of the present application provide an integrated passive device and a method for manufacturing the same, which achieves innovation at the architectural level by changing the passive components deposited on the substrate in the integrated passive device from a vertical stack to a horizontal arrangement (arranged along a first direction parallel to the substrate surface). Specifically, by arranging various passive components horizontally on the substrate surface, the use of at least one dielectric layer is reduced (that is, the dielectric layer between the passive components is reduced). By reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of dielectric materials are reduced, thereby improving the inductor Q value and self-resonant frequency, and ultimately improving the device performance. This solves the technical problem in the prior art that the integrated passive device adopts a vertical stacking architecture to arrange various passive components, and the multi-layer dielectric layer introduces interlayer parasitic capacitance and high-frequency loss, resulting in poor device performance stability.

[0042] The integrated passive device and its manufacturing method provided in the embodiments of the present application are described below in conjunction with specific embodiments.

[0043] Example 1

[0044] For ease of understanding, this application first describes the manufacturing method of the integrated passive device. The manufacturing method of the integrated passive device provided in the embodiment of the present application includes:

[0045] like Figure 1 As shown, a sacrificial layer 110 is formed on one side of a substrate 100 serving as a carrier, the sacrificial layer exposing the surface of multiple regions of the substrate 100. Optionally, the material of the sacrificial layer 110 may be SiO2, PSG, USG, a-Si, or photoresist; and the formation process of the sacrificial layer 110 may be PVD, CVD, or spin coating.

[0046] Alternatively, using photoresist as the material for sacrificial layer 110, the process for fabricating sacrificial layer 110 is as follows: Photoresist is coated on one side of substrate 100, i.e., the photoresist is applied to one surface of substrate 100 to form a photosensitive film. The photoresist is then exposed to light, specifically by selectively irradiating the photoresist with ultraviolet light or another light source to induce a photochemical reaction. Subsequently, a chemical solvent (e.g., a developer) is used to dissolve the exposed portion of the photoresist to form the desired physical pattern, thereby obtaining sacrificial layer 110.

[0047] Optionally, in one embodiment of the present application, the substrate 100 is a silicon substrate, a silicon-on-insulator substrate, a glass substrate, a silicon carbide substrate, or a gallium arsenide (GaAs) substrate.

[0048] like Figure 2 As shown, a first metal layer 120 is deposited on the surface of the substrate 100 where no photoresist is applied, and chemical mechanical planarization is performed on the surface of the first metal layer 120. The first metal layer 120 is used to subsequently fabricate the first electrode of the capacitor structure, the first inductor layer of the double-layer inductor structure, and a portion of the support structure.

[0049] Optionally, in one embodiment of the present application, the first metal layer 120 may be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and may be formed by a physical vapor deposition (PVD) process.

[0050] like Figure 3As shown, the first region of the first metal layer 120 is fabricated into the first electrode 122, and the second region of the first metal layer 120 is fabricated into the first inductor layer. The first inductor layer includes at least two inductor regions (e.g., a first inductor region 123 and a second inductor region 125) spaced apart along a first direction, and at least one inductor region (e.g., the first inductor region 123) is connected to the first electrode 122. The first direction is parallel to the surface of the substrate 100. The remaining region of the first metal layer 120 serves as part of the metal support structure (i.e., a portion of a plurality of support units spaced apart along the first direction), for example, including a portion of a fourth support unit (a first support portion 121, located in the third region on one side of the substrate 100), a portion of a second support unit (a second support portion 124), and a portion of a fifth support unit (a third support portion 126, located in the fourth region on one side of the substrate 100). At least one support unit (e.g., the second support unit) is non-contactly positioned between adjacent inductor regions (i.e., the first inductor region 123 and the second inductor region 125) and covers a portion of the surface of the substrate 100.

[0051] Optionally, the process of forming the first region of the first metal layer 120 into the first electrode 122 includes the following steps:

[0052] A layer of photoresist is evenly coated on the first area of ​​the first metal layer 120. Then, ultraviolet light or another suitable light source is used to selectively illuminate the photoresist through a prefabricated mask. The mask defines the pattern of the first electrode 122. During the exposure process, the pattern on the mask is precisely projected onto the photoresist, triggering a photochemical reaction.

[0053] After exposure, the exposed photoresist is treated with a chemical solvent (such as a developer). The developer dissolves the exposed photoresist while leaving the unexposed photoresist, thereby forming a photoresist pattern corresponding to the mask pattern, i.e., the pattern of the first electrode 122.

[0054] After development, the first region of the first metal layer 120 is etched using a chemical etchant or a physical etching method (such as plasma etching). During the etching process, the portion of the metal layer not protected by the photoresist is removed, while the portion protected by the photoresist remains, forming a pattern of the first electrode 122.

[0055] After the etching is completed, a specific solvent or method is used to remove the remaining photoresist, exposing the patterned first electrode 122 .

[0056] Through the above steps, the first region of the first metal layer 120 is accurately fabricated into the first electrode 122 , laying a foundation for subsequent semiconductor device manufacturing.

[0057] Optionally, the process of manufacturing the second region of the first metal layer 120 into the first inductor layer is substantially the same as that of manufacturing the first electrode 122 , except that the pattern of the first inductor layer is defined on the mask.

[0058] like Figure 4 As shown, a first dielectric layer 130 is formed on the side of the first electrode 122 away from the substrate 100. Optionally, the formation process of the first dielectric layer 130 is a deposition process, specifically PVD or CVD, etc. The material of the first dielectric layer 130 can be SiO2, SiNx or AlN, etc. This application does not limit this, and it depends on the specific situation.

[0059] It should be noted that, in the embodiment of the present application, the first dielectric layer 130 is a protective layer for the first electrode 122 to prevent the first electrode 122 from being oxidized. Optionally, the first dielectric layer 130 also serves as a dielectric layer for a capacitor formed subsequently.

[0060] Continue as Figure 4 As shown, a second electrode 140 is formed on the surface of the first dielectric layer 130 away from the substrate 100. The first electrode 122, the first dielectric layer 130, and the second electrode 140 constitute a capacitor (i.e., a first-class passive component). Optionally, the material of the second electrode 140 may be Al, Cu, Mo, Au, or Pt, etc., which is not limited in this application and is determined based on specific circumstances.

[0061] like Figure 5 As shown, a second metal layer 150 is deposited on the first metal layer 120 and the second electrode 140. The second metal layer 150 serves as a metal support structure. Specifically, metal is deposited on the first support portion 121, the second electrode 140, the first inductor region 123, the second support portion 124, the second inductor region 125, and the third support portion 126, thereby forming the second metal layer 150. The area of ​​the second metal layer 150 located on the first inductor region 123 constitutes a first support unit, the area of ​​the second metal layer 150 located on the second support portion 124 and the second support portion 124 constitute a second support unit, and the area of ​​the second metal layer 150 located on the second inductor region 125 constitutes a third support unit. These first, second, and third support units constitute the first metal support structure.

[0062] Optionally, the second metal layer 150 may be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and may be formed by a physical vapor deposition (PVD) process.

[0063] Optionally, a gap exists in the first direction between the area of ​​the second metal layer 150 located on the second inductor region 125 and the area located on the third support portion 126. This lays the foundation for the subsequent fifth support unit to be connected only to the inductor disposed on the surface of the substrate 100 in the second type of passive component. That is, the fifth support unit is connected only to the second inductor region 125 in the second type of passive component, and not to the second inductor layer 170 in the second type of passive component. Compared to an arrangement in which the fifth support unit is connected not only to the second inductor region 125 but also to the second inductor layer 170, this connection only to the second inductor region 125 allows for a longer inductor trace, thereby increasing the inductance value of the second type of passive component.

[0064] Continue as Figure 5 As shown, sacrificial material is continuously deposited on the basis of the sacrificial layer 110 , so that the sacrificial layer 110 fills the gaps between the various structures.

[0065] like Figure 6 As shown, a second dielectric layer 160 is formed on the side of the first supporting unit, the second supporting unit, and the third supporting unit away from the substrate 100 , and the second dielectric layer 160 exposes a portion of the surface of the first supporting unit and the third supporting unit.

[0066] Optionally, the second dielectric layer 160 is formed by a deposition process, specifically PVD or CVD, and the material of the second dielectric layer 160 may be SiO2, SiNx or AlN, etc. This application does not limit this, and it depends on the specific situation.

[0067] Optionally, the material of the second dielectric layer 160 is different from the material of the first dielectric layer 130. For example, when the material of the first dielectric layer 130 is SiO2, the material of the second dielectric layer 160 may be SiNx.

[0068] It should be noted that, in the embodiment of the present application, the second dielectric layer 160 serves as the dielectric layer of a double-layer inductor structure (ie, a second type of passive component) formed subsequently.

[0069] like Figure 7 As shown, a second inductive layer 170 is deposited on a side of the second dielectric layer 160 away from the substrate 100 , and the second inductive layer 170 covers exposed surfaces of the first supporting unit and the third supporting unit.

[0070] Continue as Figure 7As shown, metal material is continuously deposited in the region of the second metal layer 150 located on the first supporting portion 121, and metal material is continuously deposited in the region of the second metal layer 150 located on the third supporting portion 126, thereby forming a third metal layer 180. The region of the third metal layer 180 that overlaps with the first supporting portion 121 in a direction perpendicular to the surface of the substrate 100 (corresponding to the second direction) covers the support structure located on the second electrode 140 (i.e., the region of the second metal layer 150 located on the second electrode 140).

[0071] The area of ​​the third metal layer 180 that overlaps with the first support portion 121 in a direction perpendicular to the substrate surface, the area of ​​the second metal layer 150 located on the first support portion 121, the first support portion 121, and the support structure located on the second electrode 140 constitute a fourth support unit. The area of ​​the third metal layer 180 that overlaps with the third support portion 126 in a direction perpendicular to the substrate surface, the area of ​​the second metal layer 150 located on the third support portion 126, and the third support portion 126 constitute a fifth support unit. The fourth and fifth support units constitute a second metal support structure.

[0072] Optionally, the third metal layer 180 may be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and may be formed by a physical vapor deposition (PVD) process.

[0073] Continue as Figure 7 As shown, sacrificial material is continuously deposited on the basis of the currently formed sacrificial layer 110 , so that the sacrificial layer 110 fills the gaps between the various structures.

[0074] like Figure 8 As shown, a first conductive connector 191 is formed on a side of the fourth support unit away from the substrate 100, and a second conductive connector 192 is formed on a side of the fifth support unit away from the substrate 100. The first conductive connector 191 and the second conductive connector 192 constitute a conductive connection structure. Optionally, the first conductive connector 191 and the second conductive connector 192 are solder or pad pins.

[0075] like Figure 9As shown, the sacrificial layer 110 is released to form a first air cavity, a second air cavity, and a third air cavity. The first air cavity is the area defined by the third support unit, the substrate 100, the first electrode 122, the first dielectric layer 130, the second electrode 140, and the support structure located on the second electrode 140. The second air cavity is the area defined by the substrate 100, the first inductor region 123, the first support unit, the second dielectric layer 160, and the second support unit. The third air cavity is the area defined by the substrate 100, the second support unit, the second dielectric layer 160, the third support unit, and the second inductor region 125.

[0076] Optionally, the sacrificial layer 110 is released by using a liquid phase etching method or a gas phase etching method, including: etching the sacrificial layer 110 using a liquid phase etching solution such as a hydrofluoric acid solution (HF) or a buffered oxide etchant (BOE); or etching the sacrificial layer 110 using a gas such as gaseous hydrogen fluoride (HF) or xenon difluoride (XeF2).

[0077] In addition, an embodiment of the present application also provides an integrated passive device manufactured using the manufacturing method provided by any of the above embodiments.

[0078] like Figure 9 As shown, the integrated passive device provided in an embodiment of the present application includes: a substrate 100; and a first type of passive components and a second type of passive components located on one side of the substrate 100 and arranged along a first direction; wherein the first type of passive components and the second type of passive components are connected, and the first direction is a direction parallel to the surface of the substrate 100.

[0079] Optionally, the first type of passive element includes: a first electrode 122 located in a first region on one side of the substrate 100; a first dielectric layer 130 located on a side of the first electrode 122 away from the substrate; and a second electrode 140 located on a side of the first dielectric layer 130 away from the substrate 100.

[0080] Optionally, the second type of passive component includes: a first inductor layer located in a second region on one side of the substrate 100; wherein the first inductor layer includes at least two inductor regions spaced apart along the first direction, and at least one inductor region is connected to the first electrode 122; a first metal support structure, the first metal support structure including a plurality of support units spaced apart along the first direction; wherein at least one support unit is located between adjacent inductor regions in a non-contact manner and covers a portion of the surface of the substrate, and at least some of the support units are located on a side of each inductor region away from the substrate; a second dielectric layer 160 located on a side of the first metal support structure away from the substrate 100, the second dielectric layer 160 exposing a portion of the surface of at least some of the support units; and a second inductor layer 170 located on a side of the second dielectric layer 160 away from the substrate 100, the second inductor layer 170 covering the exposed surfaces of the plurality of support units.

[0081] Optionally, the first inductor layer includes a first inductor region 123 and a second inductor region 125 spaced apart along the first direction, and the first inductor region 123 is connected to the first electrode 122; the first metal support structure includes a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein the first support unit is located on a side of the first inductor region 123 away from the substrate 100, the second support unit is located between the first inductor region 123 and the second inductor region 125 in a non-contact manner and covers a portion of the surface of the substrate 100, the third support unit is located on a side of the second inductor region 125 away from the substrate 100; and the second dielectric layer 160 exposes a portion of the surface of the first support unit and a portion of the surface of the third support unit.

[0082] Optionally, the integrated passive device further includes: a second metal support structure located on one side of the substrate 100, the second metal support structure being connected to the first type of passive components and the second type of passive components; and a conductive connection structure located on a side of the second metal support structure away from the substrate.

[0083] Optionally, the second metal support structure includes: a fourth support unit located in a third area on one side of the substrate 100, the fourth support unit being connected to the first type of passive component; and a fifth support unit located in a fourth area on one side of the substrate 100, the fifth support unit being connected to the second type of passive component.

[0084] Optionally, the first type of passive component includes: a first electrode 122 located in a first area on one side of the substrate 100; a first dielectric layer 130 located on a side of the first electrode 122 away from the substrate 100; and a second electrode 140 located on a side of the first dielectric layer 130 away from the substrate 100; and in the first direction, the fourth support unit is isolated from the first type of passive component by an air medium; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode 140.

[0085] Optionally, the second type of passive component includes at least two layers of inductors, and the fifth supporting unit is only connected to the inductors of the second type of passive component that are arranged on the surface of the substrate 100 .

[0086] Optionally, the conductive connection structure includes: a first conductive connection member 191, which is located on a side of the fourth support unit away from the substrate 100; and a second conductive connection member 192, which is located on a side of the fifth support unit away from the substrate 100.

[0087] It should be noted that, since the detailed structure of the integrated passive device has been described in detail in the manufacturing method of the integrated passive device, it will not be repeated here.

[0088] In summary, in the integrated passive device and its manufacturing method proposed in this application, by changing the passive components deposited on the substrate in the integrated passive device from a vertical stack to a horizontal arrangement layout (arranged along a first direction parallel to the substrate surface), innovation at the architectural level is achieved. Specifically, by arranging various passive components horizontally on the substrate surface, the use of at least one dielectric layer is reduced (that is, the dielectric layer between the passive components is reduced). By reducing the number of dielectric layers, the interlayer parasitic capacitance and the loss of dielectric materials are reduced, thereby improving the inductor Q value and self-resonant frequency, and ultimately improving the device performance. This solves the technical problem in the prior art that the integrated passive device adopts a vertical stacking architecture to arrange various passive components, and the multi-layer dielectric layer introduces interlayer parasitic capacitance and high-frequency loss, resulting in poor device performance stability.

[0089] Example 2

[0090] The invention scheme in this embodiment is basically the same as that in the first embodiment, except that in the invention scheme, Figure 10 As shown, the first conductive connection member 191 and the second conductive connection member 192 are bonding wires.

[0091] Example 3

[0092] The invention scheme in this embodiment is basically the same as that in the first embodiment, except that in the invention scheme, Figure 11 As shown, the second type of passive component further includes: a third dielectric layer 200, which is located on a side of the second inductor layer 170 away from the substrate 100 and exposes a portion of the surface of the second inductor layer 170; and a third inductor layer 210, which is located on a side of the third dielectric layer 200 away from the substrate 100 and covers the exposed surface of the second inductor layer 170. The integrated passive device further includes a fourth metal layer 220, which includes three parts: a first part is located between the fourth support unit and the first conductive connector 191, a second part is the third inductor layer 210, and a third part is located between the fifth support unit and the second conductive connector 192.

[0093] Specifically, in the first embodiment Figure 7 On this basis, a third dielectric layer 200 is formed on the side of the second inductor layer 170 away from the substrate 100. Optionally, the third dielectric layer 200 can be formed by a deposition process, specifically PVD or CVD. The material of the third dielectric layer 200 can be SiO2, SiNx, or AlN, etc. This application does not impose any restrictions on this, and the specific process depends on the specific situation.

[0094] Optionally, the material of the third dielectric layer 200 is different from that of the first dielectric layer 130, and the material of the third dielectric layer 200 can be the same as that of the second dielectric layer 160. For example, when the material of the first dielectric layer 130 is SiO2, the materials of the second dielectric layer 160 and the third dielectric layer 200 are SiNx.

[0095] Then, metal material is deposited on the fourth support unit, the third dielectric layer 200, and the fifth support unit to form the fourth metal layer 220. The fourth metal layer 220 comprises three parts. The first part covers the fourth support unit and serves as a support structure. The second part is located on the side of the third dielectric layer 200 away from the substrate 100 and covers the exposed surface of the second inductor layer 170. This second part becomes the third inductor layer 210. The third part covers the fifth support unit and serves as a support structure.

[0096] Optionally, the fourth metal layer 220 may be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and may be formed by a physical vapor deposition (PVD) process.

[0097] Next, sacrificial material is continuously deposited on the basis of the currently formed sacrificial layer 110 , so that the sacrificial layer 110 fills the gaps between the various structures.

[0098] Next, a first conductive connection 191 is fabricated on a side of the first portion of the fourth metal layer 220 away from the substrate 100 , and a second conductive connection 192 is fabricated on a side of the third portion of the fourth metal layer 220 away from the substrate 100 .

[0099] Finally, the sacrificial layer 110 is released, thereby obtaining Figure 11 The integrated passive device.

[0100] Example 4

[0101] The invention scheme in this embodiment is basically the same as that in the third embodiment, except that in the invention scheme, Figure 12 As shown, the first conductive connection member 191 and the second conductive connection member 192 are bonding wires.

[0102] In summary, the integrated passive device and its manufacturing method proposed in this application include a substrate; and a first type of passive components and a second type of passive components located on one side of the substrate and arranged along a first direction; wherein the first type of passive components and the second type of passive components are connected, and the first direction is a direction parallel to the substrate surface. By changing the passive components deposited on the substrate in the integrated passive device from a vertical stack to a horizontal arrangement (arranged along a first direction parallel to the substrate surface), architectural innovation is achieved. Specifically, by arranging the various passive components horizontally on the substrate surface, the use of at least one dielectric layer is reduced (i.e., the number of dielectric layers between passive components is reduced). By reducing the number of dielectric layers, interlayer parasitic capacitance and dielectric material losses are reduced, thereby improving the inductor Q value and self-resonant frequency, and ultimately improving device performance. This solves the technical problem in the prior art that integrated passive devices use a vertical stacking architecture to arrange various passive components, which introduces interlayer parasitic capacitance and high-frequency losses due to multiple dielectric layers, resulting in poor device performance stability.

[0103] The various parts in this manual are described in a progressive manner, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0104] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated passive device, characterized in that: include: substrate; and a first type of passive component and a second type of passive component located on one side of the substrate and arranged along a first direction; wherein the first type of passive component and the second type of passive component are connected, and the first direction is a direction parallel to the surface of the substrate; wherein the second type of passive component includes a first inductor layer, a first metal support structure, a second dielectric layer, and a second inductor layer sequentially deposited in a direction perpendicular to the surface of the substrate; The first inductive layer includes at least two inductive regions spaced apart and distributed along the first direction; The first metal support structure includes two types of support units spaced apart along the first direction; wherein the first type of support units are located between adjacent inductor regions in a non-contact manner and cover a portion of the surface of the substrate, and the second type of support units are located on a side of each inductor region away from the substrate; The second dielectric layer covers the entire surface of the first type support unit and exposes a portion of the surface of each second type support unit; and The second inductive layer covers the second dielectric layer and the exposed surface of each second-type supporting unit.

2. The integrated passive device according to claim 1, characterized in that The first type of passive element includes: a first electrode located in a first region on one side of the substrate; a first dielectric layer located on a side of the first electrode away from the substrate; and a second electrode located on a side of the first dielectric layer away from the substrate.

3. The integrated passive device according to claim 1, characterized in that The first inductor layer is located in a second region on one side of the substrate, and at least one inductor region is connected to the first type of passive components.

4. The integrated passive device according to claim 3, characterized in that The first inductive layer includes a first inductive region and a second inductive region spaced apart along the first direction, and the first inductive region is connected to the first type of passive components; The first metal support structure includes a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein the first support unit is located on a side of the first inductor region away from the substrate, the second support unit is located between the first inductor region and the second inductor region in a non-contact manner and covers a portion of the surface of the substrate, and the third support unit is located on a side of the second inductor region away from the substrate; and The second dielectric layer covers the entire surface of the second supporting unit and exposes a portion of the surface of the first supporting unit and a portion of the surface of the third supporting unit.

5. The integrated passive device according to claim 1, characterized in that Also includes: a second metal support structure located on one side of the substrate, the second metal support structure being connected to the first type of passive components and the second type of passive components respectively; as well as A conductive connection structure is located on a side of the second metal support structure away from the substrate.

6. The integrated passive device according to claim 5, characterized in that: The second metal support structure comprises: a fourth supporting unit located in a third region on one side of the substrate, the fourth supporting unit being connected to the first type of passive component; and A fifth supporting unit is located in a fourth area on one side of the substrate, and the fifth supporting unit is connected to the second-type passive component.

7. The integrated passive device according to claim 6, characterized in that: The first type of passive element includes: a first electrode located in a first region on one side of the substrate; a first dielectric layer located on a side of the first electrode away from the substrate; and a second electrode located on a side of the first dielectric layer away from the substrate; and In the first direction, the fourth supporting unit is isolated from the first type of passive components by air; in a second direction perpendicular to the first direction, the fourth supporting unit is connected to the second electrode.

8. The integrated passive device according to claim 6, characterized in that: The second type of passive component includes at least two layers of inductors, and the fifth supporting unit is only connected to the inductors of the second type of passive component that are arranged on the surface of the substrate.

9. The integrated passive device according to claim 6, characterized in that: The conductive connection structure includes: a first conductive connection member, the first conductive connection member being located on a side of the fourth support unit away from the substrate; and A second conductive connecting member is located on a side of the fifth supporting unit away from the substrate.

10. The integrated passive device according to claim 3, characterized in that: The second category of passive components also includes: a third dielectric layer, the third dielectric layer being located on a side of the second inductor layer away from the substrate and exposing a portion of a surface of the second inductor layer; and a third inductive layer, located on a side of the third dielectric layer away from the substrate and covering an exposed surface of the second inductive layer.

11. A method for manufacturing an integrated passive device, characterized in that: include: Manufacturing a substrate; and manufacturing a first type of passive component and a second type of passive component located on one side of the substrate and arranged along a first direction; wherein the first type of passive component and the second type of passive component are connected, and the first direction is a direction parallel to the surface of the substrate; The process of manufacturing the second-type passive components includes: sequentially depositing a first inductor layer, a first metal support structure, a second dielectric layer, and a second inductor layer in a direction perpendicular to the substrate surface; wherein the first inductor layer includes at least two inductor regions spaced apart along the first direction; the first metal support structure includes two types of support units spaced apart along the first direction; wherein the first type of support units are located between adjacent inductor regions in a non-contact manner and cover a portion of the substrate surface, and the second type of support units are located on a side of each inductor region away from the substrate; the second dielectric layer covers the entire surface of the first type of support units and exposes a portion of the surface of each second type of support unit; and the second inductor layer covers the second dielectric layer and the exposed surface of each second type of support unit.

12. The manufacturing method according to claim 11, characterized in that: The process of manufacturing the first type of passive component includes: manufacturing a first electrode, a first dielectric layer, and a second electrode; wherein the first electrode is located in a first area on one side of the substrate, the first dielectric layer is located on a side of the first electrode away from the substrate, and the second electrode is located on a side of the first dielectric layer away from the substrate; and The first inductor layer is located in a second region on one side of the substrate, and at least one inductor region is connected to the first type of passive components.

13. The manufacturing method according to claim 12, characterized in that: The process of manufacturing the first inductor layer includes: manufacturing a first inductor region and a second inductor region spaced apart along the first direction, wherein the first inductor region is connected to the first type of passive components; The process of manufacturing the first metal support structure includes: manufacturing a first support unit, a second support unit, and a third support unit spaced apart along the first direction; wherein the first support unit is located on a side of the first inductor region away from the substrate, the second support unit is located between the first inductor region and the second inductor region in a non-contact manner and covers a portion of the surface of the substrate, and the third support unit is located on a side of the second inductor region away from the substrate; and the second dielectric layer covers the entire surface of the second support unit and exposes a portion of the surface of the first support unit and a portion of the surface of the third support unit.

14. The manufacturing method according to claim 11, characterized in that: The manufacturing method further includes: manufacturing a second metal support structure located on one side of the substrate, the second metal support structure being connected to the first type of passive components and the second type of passive components respectively; and manufacturing a conductive connection structure located on a side of the second metal support structure away from the substrate; The process of making the second metal support structure includes: making a fourth support unit located in the third area on one side of the substrate, and the fourth support unit is connected to the first type of passive component; and making a fifth support unit located in the fourth area on one side of the substrate, and the fifth support unit is connected to the second type of passive component.

15. The manufacturing method according to claim 14, characterized in that: The process of manufacturing the first type of passive element includes: manufacturing a first electrode located in a first region on one side of the substrate; manufacturing a first dielectric layer located on a side of the first electrode away from the substrate; and manufacturing a second electrode located on a side of the first dielectric layer away from the substrate; and In the first direction, the fourth support unit is isolated from the first type of passive components by an air medium; in a second direction perpendicular to the first direction, the fourth support unit is connected to the second electrode; The second type of passive component includes at least two layers of inductors, and the fifth supporting unit is connected only to the inductors of the second type of passive component that are arranged on the surface of the substrate; The process of making the conductive connection structure includes: making a first conductive connection member, which is located on a side of the fourth support unit away from the substrate; and making a second conductive connection member, which is located on a side of the fifth support unit away from the substrate.

16. The manufacturing method according to claim 13, characterized in that: The process of manufacturing the second type of passive component further includes: manufacturing a third dielectric layer, the third dielectric layer being located on a side of the second inductor layer away from the substrate and exposing a portion of the surface of the second inductor layer; and manufacturing a third inductor layer, the third inductor layer being located on a side of the third dielectric layer away from the substrate and covering the exposed surface of the second inductor layer.

Images