INTEGRATED DEVICE WITH TRENCH ISOLATION STRUCTURE AND RELATED MANUFACTURING PROCESS.

Description

Patent application for an industrial invention entitled: "Device integrated with trench insulation structure and related manufacturing process" on behalf of: STMicroelectronics Srl with headquarters in: Agrate Brianza (MI) * * ★ * * DESCRIPTION Scope of application The present invention relates to a device integrated with insulation structure. More specifically, the invention relates to an integrated device of the type comprising a substrate, on which a buried layer and an epitaxial region have been formed, as well as an isolation structure suitable for defining a plurality of pockets of isolation for the integration of the embedded device components. The invention also refers to a process for manufacturing such a device integrated with an isolation structure. Known art As is known, in most integrated semiconductor devices, the electrical isolation of the integrated components is achieved using the so-called junction isolation technique. Figure 1 shows a schematic vertical section of an integrated IC device with known type of insulation structures. In particular, this integrated IC device comprises wells A, of a first type of dopant, in the illustrated case of N-type, designed to contain various types of components. Such components are, for example, bipolar and / or MOS types. The pockets A are delimited by an insulation region B of a second type of dopant, of opposite sign to the first type of dopant, in the illustrated case of type P. These pockets A are therefore electrically isolated by reverse biasing of the PN junctions defined by the pockets A and the insulation region B: this is called "junction insulation". The effectiveness of such junction isolation depends on the type of components integrated inside the A-pockets as well as the type of circuitry included in the IC integrated device. It should be noted, however, that during the various operating conditions of the integrated IC device, the reverse bias state of the PN junctions defined by the wells A and the isolation region B cannot always be maintained. Furthermore, capacitive and / or inductive effects due to the presence of various layers or the type of bias to which they are subjected make the electrical insulation of the components integrated into the wells A using the junction insulation technique precarious. This technique ultimately requires the use of a large amount of silicon. Indeed, the area occupied by an active component integrated within a pocket A, regardless of its type, is significantly smaller than the area occupied by the isolation region B, which comprises deep and therefore very extensive layers. There are essentially two different types of technologies process note for making an integrated device with junction isolation structure according to the prior art. According to a so-called low power technology, as schematically illustrated in Figure 2, starting from a P-type semiconductor material (substrate 1) a masking, implantation and diffusion step of N-type dopant is carried out, necessary for the creation of a buried layer 2 of the N+ type. In particular, this buried layer 2 represents the collector or drain region for NPN or VDMOS bipolar components respectively. An N-type epitaxial region 3 is then grown, followed by a masking, implantation and diffusion step of P-type dopant to form isolation regions 4 that ensure lateral isolation of the isolation pockets IS defined by the epitaxial region 3 and the buried layer 2. A subsequent masking, implantation and diffusion step with N-type dopant creates sinker regions 5 at the end of the buried layer 2. These sinker regions 5 allow contact from the surface of the integrated IC device to the buried layer 2. Inside the N-type IS isolation wells, delimited by P-type dopant regions, in particular substrate 1 and isolation region 4, other layers will be integrated as necessary to complete the various types of components, such as P-well and N-well regions, active areas, etc. The definition of regions of surface enrichment, of areas •contact and the related metallization and passivation phase, conclude the processing of the entire integrated IC device. In the case of VIPower technology, as illustrated in Figure 3, vertical current flow power components, such as VIPower devices, comprise an N-type substrate. In this case, the process sequence that leads to the definition of an integrated IC device with IS junction insulation wells starts from an N+ type semiconductor material la and initially includes a phase for the creation of a first N- type epitaxial region lb, followed by a phase of masking, implantation and diffusion of P-type dopant necessary for the creation of a buried layer le of the insulation well. In particular, the buried layer le, in addition to creating part of the buried insulation of the driving circuitry or LV region, allows in this case also to create part of the base region of the NPN power component or HV region. A subsequent masking, implantation and diffusion phase with N-type dopant to be carried out in correspondence with the buried layer le, provides for the bulk delimitation of the N-type regions 2 intended to contain various circuitry components, as illustrated in relation to the known embodiment of Figure 1. This buried layer, in addition to forming the emitter of the NPN power component in the HV region, also acts as a buried collector or buried drain, respectively, for the NPN and VDMOS signal components in the LV region. An additional epitaxial region 3 is necessary to allow the creation of the insulated N-type IS pockets whose complete delimitation will be obtained with the further P-type masking, implantation and diffusion phase to create the insulation regions 4, on the epitaxial region 3 and such as to allow electrical continuity with the buried region. The isolation regions 4 also form part of the basis of the bipolar NPN power component. Once the isolation regions 4 have been defined, a subsequent masking, implantation and diffusion phase with N-type dopant creates the sinker regions 5 at and at the end of the buried layer 2, to allow contact from the surface of the integrated IC device to the buried layer 2. Once these steps are completed, the other layers will be integrated inside the N-type IS isolation pockets comprising the buried layer 2 and the epitaxial region 3 to complete the construction of the various types of components, such as P-well and N-well regions, active areas, etc. The definition of surface enrichment regions, contact areas and the related metallization and passivation phase conclude the processing of the integrated IC device. It is worth noting that both of the previously described IS-type isolation pocket structures are virtually identical. The only differences are the substrate type, P-type or N-type, and the integration of the le region using VIPower technology. The purpose of the present invention is to provide a integrated device with a dielectric-type insulation structure with reduced overall dimensions that improves the electrical insulation of the components integrated in the insulation pockets, while reducing the overall dimensions of the insulation structure itself, said structure also being usable in all semiconductor devices (low and high voltage) in which there is an insulation pocket created using the junction insulation technique. Summary of the invention The idea behind the present invention is to provide an integrated device with an isolation structure comprising a dielectric trench region to ensure lateral isolation. : of the components, internally filled with conductive material, so that they can contact the buried regions starting from the surface. On the basis of this solution idea, the technical problem is solved by an integrated device with an insulation structure of the type previously indicated and defined in the characterising part of claim 1. The problem is also solved by a process for manufacturing an integrated device with an insulation structure of the type previously indicated and defined by the characterizing part of claim 9. The characteristics and advantages of the device integrated with an insulating structure according to the invention will be apparent from the description given below of its embodiment examples given at indicative and non-limiting title with reference to the attached drawings. Brief description of the drawings In these drawings: Figure 1 shows a schematic cross-section of an integrated device with a junction isolation structure made according to the prior art; Figure 2 shows a schematic cross-section of an integrated device with a junction isolation structure made with the well-known low power technology; Figure 3 shows a schematic cross-section of an integrated device with an isolation structure made with the well-known VIPower technology; Figure 4 shows a schematic cross-section of an integrated device with a trench insulation structure according to the invention; Figures 5 to 5e show successive process steps for the realization of the integrated device with trench insulation structure according to the invention; Figures 6 to 10 show variants of construction and application of the integrated device with trench insulation structure according to the invention. Detailed description With reference to these figures, and in particular to Figure 4, an integrated device with trench insulation structure according to the invention is globally and schematically indicated as ICnew. As seen in relation to devices integrated according to known techniques, the ICnew integrated device comprises a substrate 1, on which a buried layer 2 and an epitaxial region 3 have been created. The integrated device ICnew also comprises an isolation structure 10 suitable for defining a plurality of isolation pockets IS in which the components of the integrated device ICnew are integrated. Advantageously according to the invention, said insulation structure 10 comprises a plurality of dielectrically insulated trench regions of dielectric 4*, internally filled with suitably doped polysilicon or with other conductive material to form a plurality of contact regions 5*, capable of putting the buried regions 1 and 2 in contact with the surface of the integrated device ICnew. In particular, advantageously according to the invention, the dielectric trench regions 4* ensure lateral insulation of the components, while the contact regions 5* internal to the regions 4* ensure contact from the surface of the integrated device ICnew of the buried regions 1 and 2. These regions 4* and 5* are formed at the edges of the insulation pockets IS in contact with the buried layer 2 and in the areas between said pockets IS in contact with the substrate I. It should also be noted that a trench insulation structure according to the invention can be made from all semiconductor structures and devices that include junction insulation structures. Such a trench 10 insulation structure is advantageous in several respects. First of all, the lateral insulation of the components is dielectric rather than junction, thus eliminating all the parasitic effects described previously in relation to known solutions. The use of the trench isolation structure 10 according to the invention also allows for a significant reduction in the overall dimensions of the entire ICnew integrated device (by at least a factor of 2), since, as is known for junction-based isolated devices, most of the overall area of ​​each elementary component depends mainly on the isolation region 4 as well as on the sinker region 5, which have been replaced in the solution according to the invention by a plurality of filled trenches 4* which are certainly less bulky. In addition to considerably reducing the silicon footprint, the presence of the dielectric trenches still ensures greater voltage holding capacity of the IS insulation pockets since the dielectric has a much larger critical field than silicon. The 4* dielectric trenches also act as interface regions between multiple neighboring pockets or as edge regions, thus allowing the device to perform multiple electrical functions without resorting to special technological or circuit solutions. Last but not least, as we will see below, the presence of the dielectric trenches does not bring additional costs compared to the insulation bag made according to standard integration processes since both phases of masking, implantation and diffusion of the insulation regions 4 and sinker 5 respectively are eliminated and replaced according to the invention, with a masking step, silicon etching (creation of the trenches), oxidation and filling with conductive material. Let us now look in more detail at the process sequence for manufacturing an integrated device with a trench-filled insulation structure according to the invention. In particular, this process sequence involves the integration of dielectric trenches filled with conductive material, for example suitably doped polysilicon, and such as to guarantee, in addition to the electrical insulation between the 'pockets', also the contacting of the buried regions. As seen in relation to the known solutions, starting from a P-type semiconductor material, substrate 1, a masking, implantation and diffusion step of N-type dopant is carried out, necessary for the creation of a buried N+ type layer 2 and then an N-type epitaxial region 3 is grown, as schematically illustrated in Figure 5. Advantageously, according to the invention, upon completion of the epitaxial region 3, an oxidation and a deposition phase follow. In particular, an oxidation 6 of a few hundred Angstroms is carried out and a layer of pyrolytic silicon nitride 7 with a thickness of approximately 1000 Angstroms is deposited. This is followed by a phase of construction of the 4* trench coats. In a preferred embodiment of the invention, such trenches 4* are made by a phototechnique comprising a deposition of photoresist, exposure and development, sequential etching of nitride and thermal oxide on the photoresist-free regions and removal of the photoresist, as schematically illustrated in Figure 5a. c The realization of the trenches therefore involves a dry etching of the underlying silicon up to the buried regions 1 and 2, as illustrated schematically in Figure 5b. Surface silicon attack is masked by the previously grown nitride and the photoresist deposited during the trench phototechnical stage. Once the trenches are formed, their walls are oxidized using an oxidation stage. It is worth noting that the oxide grows only on the trench walls and not on the surface of the integrated device due to the presence of nitride. The oxidized trench bottom is then perforated using a dry etch, as schematically illustrated in Figure 5c. Advantageously according to the invention, at this point the trenches are filled with conductive material or polysilicon, through a deposition step over the entire surface, as schematically illustrated in Figure 5d, so as to ensure contact from the surface of the buried regions 1 and 2. In the case of polysilicon filling, it is also necessary to provide a doping phase of the same capable of lowering its resistivity and thus forming ohmic contacts on the buried regions 1 and 2. Contacts can be further improved by performing a channeling implantation phase immediately after drilling the trench bottom. It is worth noting that the doping of the polysilicon (as well as any contact enrichment) must be performed with a dopant having the same sign as the buried region to be contacted (P-type for region 1 and N-type for region 2). The doping phase therefore requires a selective masking and implantation phase (one for each type of dopant), immediately after the polysilicon deposition phase. Since the diffusivity of dopants in polysilicon is higher than in silicon, the dopant concentration in the 5* regions inside the trenches is uniform. Advantageously according to the invention, it is possible to eliminate an enrichment masking step by implanting a P-type dopant (not at very high concentration) over the entire surface immediately after the polysilicon deposition and to compensate the P-type dopant with an N-type dopant by masking and implanting at very high concentration in correspondence with the buried N-type regions. Alternatively, a boron deposition or a ' in situ doping. Once the electrical contact of the buried regions has been ensured, a planarization phase of the surface is carried out by chemical etching, in order to eliminate the polysilicon, nitride and oxide layers previously grown to define the trenches, as schematically illustrated in Figure 5e. At this stage of the processing, the dielectric trenches 4* and the associated contact regions 5* for the buried regions are defined. The manufacturing process of the integrated device then proceeds according to the standard integration criteria of the components (P-well, N-well, active area, active regions, enrichments, contacts, etc.). Starting from the process sequence described and depending on the type of application required, structural variants can be created for the ICnew integrated device according to the invention, some of which are illustrated in Figures 6 to 10. In particular, as schematically illustrated in Figure 6, it is possible to realize a plurality of trenches respectively on the P-type region 1 (bulk insulation) or on the N-type region 2 (buried N+). The contact region between regions 1 and 2 and the respective regions 4* and 5* therefore extends over a larger surface and thus decreases the contact resistance. Advantageously according to the invention, it is also possible to realize a larger dielectric region around the conductive material inside the trench, as illustrated schematically in Figure 7. In a preferred embodiment of this variant, two trenches can be constructed close together but with different openings and such a distance that during the lateral oxidation phase of the walls the oxidized regions are joined. In this case, the outer trench must have a smaller opening than the inner trench so that it closes completely. during the lateral oxidation phase of the walls and avoid filling with conductive material. Furthermore, as schematically illustrated in Figure 8, the residual silicon region between two different trenches can be conveniently used to integrate active or passive components, such as resistors or capacitors. Advantageously, according to the invention, in addition to improving the insulation between adjacent pockets and compacting the integration area, the trench-filled insulation structure according to the invention can also be used to contact buried regions, for example of high or low voltage active components, as schematically illustrated in Figure 9. As can be seen in Figure 9, in this case the inventive filled trench insulation structure allows for contact between the base and emitter regions of a bipolar component integrated using VIPower technology. In this case, in fact, the conductive regions within the trench, in addition to polarizing the regions below, are also subjected to current. The area and number of trenches must therefore be chosen appropriately to allow the integrated device that includes them to function correctly. Finally, the trench-filled insulation structure according to the invention allows the integration of quite complex structures while still having a significant saving in area compared to known structures, as schematically illustrated in Figure 10, which represents a section. • vertical of an emitter switching device (MOS + bipolar in the case illustrated), in which the disturbances due to the lateral parasitics of the structure have been eliminated thanks to the dielectric regions. Note also how trivially the region between base and 5 emitter of Figure 10 constitutes a buried diode and contacted to the surface through contact regions surrounded by dielectric. In conclusion, the ICnew integrated device according to the invention comprises a filled trench insulation structure capable of ensuring correct insulation of the pockets in which the device components are integrated and at the same time guaranteeing the contacting of the deep regions of the device itself, reducing the overall dimensions of this insulation structure and of the device integrated in the his complex. The presence of these filled trenches also appears 15 advantageous for making simple modifications to the integrated device and increasing its performance and reliability in different types of applications.

Claims

CLAIMS 1. Integrated device of the type comprising a substrate (1), on which a buried layer (2) and an epitaxial region (3) have been made, as well as an insulating structure (10) able to define a plurality of insulating pockets (IS) for integrating the components of the integrated device, characterized in that said insulating structure (10) comprises a plurality of dielectrically isolated regions or dielectric trenches (4*), internally filled with conductive material to form a plurality of contact regions (5*) towards buried regions of the device itself, said buried regions comprising in particular the substrate (1) and the buried layer (2). >• • 2. Integrated device according to claim 1, characterized in that said dielectric trenches (4*) are formed at the edges of the insulation pockets (IS) in contact with said buried layer (2).

3. Integrated device according to claim 1, characterized in that said dielectric trenches (4*) are formed in correspondence with areas included between adjacent insulation pockets (IS) in contact with said substrate (1).

4. Integrated device according to claim 2, characterized in that each insulation pocket (IS) comprises, at each of its edges, a plurality of trenches in contact with said buried layer (2).

5. Integrated device according to claim 3, characterized in that each area comprised between adjacent insulation pockets (IS) comprises a plurality of trenches in contact with said substrate (1).

6. Integrated device according to claim 1, characterized in that said plurality of trenches (4*) comprises thick dielectric regions around the contacting regions (5*).

7. Integrated device according to claim 1, characterized in that it comprises active or parasitic components integrated in regions present between two different trenches of said plurality of trenches.

8. Integrated device according to claim 1, characterized in that said trench insulation structure (10) contacts buried regions of high or low voltage active components of the integrated device itself.

9. Process for making an integrated device comprising an insulating structure according to any one of the preceding claims from 1 to 8, of the type comprising, starting from a substrate (1) of a first type of dopant (P), the steps of : masking, implantation and diffusion of dopant of a second type (N) to form a buried layer (2); and growth of an epitaxial region (3) of said second type of dopant (N) characterized in that it comprises the steps of: making a plurality of trench coats (4*); and filling these trenches (4*) with a material conductive to form a plurality of contact regions (5*) of the buried layers (1,2) of the integrated device itself.

10. Process for making an integrated device with an insulating structure according to claim 9, characterized in that said step for making a plurality of trenches (4*) comprises the steps of: oxidation of the epitaxial region (3) and deposition of a silicon nitride layer; photoresist deposition, exposure and development, sequential nitride and thermal oxide etching on photoresist-free regions and photoresist removal, dry etching of the underlying silicon up to said buried regions (1,2); and oxidation of trench walls (4*).

11. Process for making an integrated device with an insulating structure according to claim 10, characterized in that said step for making a plurality of trenches (4*) further comprises the step of: dry attack [dry] to pierce the bottom of oxidized trenches (4*).

12. Process for making an integrated device with an insulating structure according to claim 11, characterized in that it also provides, after the dry etching step, a channeling implant step.

13. Process of making a device integrated with insulation structure according to claim 9, characterized in that said trench filling step (4*) with a conductive material comprises the steps of: deposition on the entire surface of said conductive material, so as to ensure contact from the surface of said buried regions (1,2).

14. Process for making an integrated device with an insulating structure according to claim 13, characterized in that said conductive material comprises polysilicon and the deposition step is followed by a doping step of the polysilicon to lower its resistivity and thus form contacts ohmy.

15. Process for manufacturing an integrated device with an insulating structure according to claim 14, characterized in that said doping step comprises a selective masking and implantation step, immediately after the polysilicon deposition step.

16. Process for making an integrated device with an insulating structure according to claim 14, characterized in that it provides the steps of: implantation of said first type of dopant (P) over the whole surface immediately after the polysilicon deposition step; and masking and very high concentration implantation at the buried regions of said second type of dopant