Auto-increment write count for nonvolatile memory

Abstract

To provide a method of tracking metadata for a nonvolatile memory device.SOLUTION: In a system 100, a memory device 110 has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array storing a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The description relates generally to non-volatile memory devices, and more specifically to tracking metadata for non-volatile memory devices. [Background technology]

[0002] Non-volatile (NV) memory devices have limited write endurance. NV memory refers to memory whose state is uncertain when power to the device is removed. Write endurance refers to the number of times the media can be written before it becomes unreliable. In addition, the media is subject to write disturb, where repeated accesses to a target memory address result in unintended changes to values ​​at adjacent victim addresses. situation It is.

[0003] Because of the potential problems associated with the number of writes, the system uses the number of writes to determine how often to refresh and move data to manage cell endurance and write disturb. Track The traditional approach to write tracking is to track writes on a block-by-block basis. Each time data is written to a block, the system accesses the write count and increments it. In systems where the write count is stored in the non-volatile media itself, accesses include the write count being accessed before the block is written. the It is necessary to read the data. Conventionally, a media controller but , the Read data the law of nature , Increment that data, then Write back to media along with user data death attitude R This operation reduces the effective write bandwidth of the system. [Brief description of the drawings]

[0004] The following description includes discussion of figures with illustrations given as examples of implementations. The drawings should be understood as examples and not as limitations. As used herein, reference to one or more examples should be understood as a description of specific features, structures or characteristics included in at least one implementation of the present invention. Phrases such as "in one example" or "in alternative examples" appearing in this specification provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0005] [Figure 1] FIG. 1 is a block diagram of an example system having selected memory arrays that store write counts and perform auto-increment on the write counts.

[0006] [Diagram 2] FIG. 1 is a block diagram of an example system having selected memory arrays that perform auto-increment on write count metadata.

[0007] [Diagram 3] FIG. 13 is a block diagram of an implementation that performs auto-increment on write count metadata.

[0008] [Figure 4] FIG. 11 is a flow diagram of an example process for write count auto-increment.

[0009] [Diagram 5] FIG. 1 is a block diagram of an example memory subsystem in which write count auto-increment can be implemented.

[0010] [Figure 6] FIG. 1 is a block diagram of an example computing system in which write count auto-increment may be implemented.

[0011] [Figure 7]FIG. 1 is a block diagram of an example mobile device in which write count auto-increment may be implemented.

[0012] Specific details and implementation descriptions are provided below, including non-limiting descriptions of figures that may show some or all of the examples and other potential implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] As described herein, a system tracks the number of writes to a non-volatile (NV) memory by storing metadata in one of a number of NV memory arrays. in In one example, the NV memory is a memory device having a three-dimensional cross-point (3DXP) storage medium. Multiple NV memory arrays store data blocks together. Each array stores one Department of Store and select array However, Data block For Store the write count. The system may use the write count to determine how often to refresh or move data to manage cell endurance and write disturb.

[0014] The write procedure for certain NV memory technologies takes a relatively long time and uses a lot of power. To manage energy usage and write latency, in one example, the NV memory is configured to For The NV memory responds to a write command by writing only the bits that are changed. Target It can be issued. this internal Like The reading is, Pre-read "or" Pre-write read " Internal Like By reading, the memory device Own Reads the contents of the memory cells, compares the existing data with the input data, and modifies It has beenIt becomes possible to write only the bits.

[0015] The selected NV memory array that stores the write count has its contents internally including the write count. Like The selected NV memory array is Ko To Controller calligraphy Write count To increment The write count is internally auto-incremented without transmission. The selected NV memory array can write back the incremented write count to its bit cells. In one example, the selected NV memory array can write back to other NV memory arrays. Should Write back the write count along with the user data. Auto-increment can eliminate the need for the controller to read and increment the write count. Controller Involvement is gone ,With automatic increment, For each write cycle of the NV media, controller By For NV media Departure line At least this will save a read cycle. .

[0016] In one example, the selected NV memory array that stores the write count may include an internal write count threshold. this NV Memory Array but , increment the write count Time , This NV memory array is Compare the write count to a threshold and determine if the write count threshold has been reached. case can also send or pass an alert to the controller.

[0017] In one example, the selected NV memory array is of mode of choice To In response, it performs an auto-increment. Mode generally refers to the operation that is performed based on the configuration setting, and different operations are performed in response to the same situation based on different configurations. Thus, for example, a selected NV memory array may: Pre-read operation Along with It may be configured to perform auto-increment, and other Multiple The NV memory array is auto-incremented. Without simply Pre-read In one example, this mode enables auto-increment hardware available in each NV memory array.

[0018] 1 is a block diagram of an example system having a selected memory array that stores a write count and performs an auto-increment on the write count. System 100 represents a memory system or device. System 100 includes multiple memory devices 110, identified as devices [0:10]. It will be understood that having eleven devices is an example and other systems may have more or fewer devices. Each device shown may include one or more memory devices.

[0019] In one example, Multiple The device 110 is of Separate Multiple Device 110 represents an NV memory array. In one example, the memory array may include 3DXP media. In one example, the memory array may include other NV storage media. In one example, each device 110 includes multiple arrays. In one example, each device 110 represents a separate NV memory array. In one example, each device 110 represents a separate NV memory chip or die. The number of devices 110 in system 100 depends on the storage capacity, internal architecture, and other factors of system 100. In one example, each device 110 represents a separate media die. In one example, each device 110 represents a separate media device.

[0020] In one example, system 100 represents a NV storage device, such as a storage module, such as a NV dual in-line memory module (DIMM). In one example, system 100 is or is part of a device, such as a solid-state drive (SSD). In one example, controller 120 represents a media controller for system 100. The media controller represents a control device for controlling access to the storage media of system 100. From the perspective of a host system into which system 100 is integrated, When I look , Multiple The device 110 only sees available storage. The controller 120, as a media controller, 、 Data Address Access to , internal command and An operation for executing a host command. 、 Adherence to timing and Manage other controls over access to the device 110. In one example, the following:

[0021] System 100 shows device[0:7] as storing data 130. Data 130 represents user data or data created by an associated host and stored in system 100. In one example, device[8:9] stores ECC 132, which represents error checking and correction (ECC) data for data 130. In one example, device 10 stores ECC 132 and metadata (MD) 134. Thus, device 10 may not only store ECC data for use with ECC 132, but may also have additional metadata for managing access to device 110. In one example, additional metadata 134 includes a write count for tracking the number of writes to block 112. Block 112 may include data 130, ECC 132, and MD 134. From block 112, a plurality of Device 110 but Data blocks can be stored together Reason Let it be understood.

[0022] Channel 140 represents a communication channel between controller 120 and device 110. In one example, channel 140 may be referred to as a 3DXP channel. Channel 140 allows controller 120 to communicate with device 110. Channel 140 may include control signal lines or command signal lines and data signal lines.

[0023] In one example, when the system 100 receives a write operation or command from a host, the controller 120: D Execute the write command to device 110. In some cases, commands or controls may be generated within the system 100 to The command includes an address and the data to be written. The controller 120 decodes the command and uses the block 112 as the address of the data to be written. knowledge In one example, controller 120 generates ECC data to write along with data received from a host. In one example, device[0:7] receives bytes of data to be written to device 10, and controller 120 provides ECC 132 to device[8:10]. In one example, controller 120 does not provide a write count to device 10. If metadata 134 includes information other than the write count, controller 120 does not provide such metadata to device 10. It would have been .

[0024] In one example, block 112 includes: Multiple written across multiple devices 110 , represented by data 130 In one example, the device 10 may be considered to have a codeword. M Tracking write counts in metadata Specializing in The selected device. In one example, the controller 120 identifies the location of each device 110 and selects one device for tracking the metadata. The system 100 represents the device 110 as a selected array for storing the metadata 134. In one example, the controller 120 identifies the location of each device 110 and selects one device for tracking the metadata. To Provides configuration settings And in this configuration:Device 110 but , are enabled as selected arrays for performing auto-increment of write count. Thus, by configuration settings, auto-increment can be selectively enabled or disabled for selected memory arrays.

[0025] In one example, for every code write or codeword write: Multiple The device 110 first device Read the data content of each of the Pre-write read of part of In one example, device 10 reads the write count and, for writebacks to device 10, The Increment the write count. In one example, device 10 places the incremented write count on the data bus along with the other data being written. Ku .

[0026] Conventionally, logic for tracking the write count would be included in controller 120. In one example, device 10 includes logic for tracking the write count. In one example, the logic is enabled when device 10 is in auto-increment mode. In one example, controller 120: D Vice 10 Switch to auto increment mode In connection with the configuration, a write count threshold (eg, a value in a register) is set.

[0027] In one example, the block size of block 112 may be 64 bytes, 128 bytes, 256 bytes, or some other number of bytes for 3DXP media. NAND (not AND) flash typically has a block size of 4K bytes or 2K bytes, etc. twist Having a large block size, managing the write count of a block can have a more positive performance impact than a system having a smaller block size.

[0028] 2 is a block diagram of a system having a selected memory array that performs auto-increment on write count metadata. System 200 provides an example of a system related to system 100 of FIG. 1. Storage 250 may represent an example of system 100. Controller 252 is an example of controller 120 of system 100.

[0029] System 200 includes a host 210 having a memory controller 220 coupled to storage 250. Host 210 represents a computing platform to which storage 250 is coupled. For example, host 210 may be or include a computer or other computing device. Memory controller 220 represents a controller for managing access to memory device 230. In one example, memory controller 220 is part of a host processor (not specifically shown) of host 210. Memory controller 220 may alternatively be considered a storage controller depending on the connection of storage 250.

[0030] In one example, the non-volatile memory of memory device 230 may be coupled to a storage bus, such as a Peripheral Component Interconnect Express (PCIe) bus. In one example, the non-volatile memory of memory device 230 is non-volatile, but also byte addressable and randomly accessible, and may be coupled to a system memory bus, such as a double data rate (DDR) memory bus. Host 210 includes an I / O (input / output) interface 212. I / O 212 represents hardware for interfacing with storage 250. I / O 212 may include an interface to a command bus or a command and address bus, and a data bus. In one example, the interface includes other signal lines, such as signal lines for memory device 230 to send alerts to host 210.

[0031] The memory device 230 is shown having an I / O 240 that represents the I / O for the memory device. To include Although not shown, it will be understood that controller 252 includes I / O hardware and I / O firmware for receiving commands and exchanging data with host 210, and interfacing memory device 230. I / O 240 includes command (CMD) 242, which represents an interface to a command bus or CA bus. Data 244 represents an interface to a data bus or DQ bus. In one example, I / O 240 includes alert 246, which represents an interface to one or more signal lines via which memory device 230 sends alerts to host 210. For example, if memory device 230: A group of Memory device For If it is the selected device for managing the write count, alert 246 enables the selected device to send an alert in response to the write count reaching a threshold.

[0032] Memory controller 220 includes a scheduler 222 for managing the scheduling and transmission of a series of commands to storage 250. Scheduler 222 includes logic for determining the order of commands and their timing requirements. Memory controller 220 makes decisions about which commands to transmit and in what order. Scheduler 222 determines the order of commands to ensure compliance with timing requirements.

[0033] In one example, the host 210 Certain Data Blocks About Receive an alert from memory device 230 indicating that a write threshold has been reached. In one example, in response to the alert flag, memory controller 220 may read one or more registers of memory device 230 to identify the alert. In response to the alert, in one example, memory controller 220 may Or moving data to a different location (e.g., a different address in storage), etc. Command to trigger the operation of send vinegar If memory controller 220 determines to perform an operation in response to the alert, scheduler 222 may schedule the command to be sent to storage 250.

[0034] The memory controller 220 includes command logic 224 for generating commands to send to the memory device 230. The commands may include write commands or read commands. The memory controller 220 sends a read command on a command bus, which may also be referred to as a command and address bus, and after a delay period, the memory device 230 drives the data on a data bus. In one example, the command logic 224 may send a refresh command or a command to move data to a different location.

[0035] Storage 250 includes multiple memory devices 230. Memory devices 230 include memory arrays 232 that represent an array of non-volatile memory cells or storage cells. A memory cell stores one bit of data or multiple bits for multi-level cells. In one example, arrays 232 are partitioned as banks of memory or other subsets of memory. In one example, memory devices 230 are part of a group of memory devices where one or more memory devices are organized as a rank of memory. A rank of memory is a group of memory resources that are accessed in parallel because they share chip select or enable signals.

[0036] In one example, array 232 includes non-volatile memory cells. Non-volatile (NV) memory maintains its state even when power is removed from the memory. Volatile memory is in an indeterminate state when power is removed from the memory. In one example, the NV media of array 232 is a 3DXP media.

[0037] The system 200 includes a controller 252, which represents a media controller for the storage 250, which represents a memory or storage module. In one example, the controller 252 receives commands and data from the host 210. death , M Determines the internal command to send to the memory device. The memory device will respond to internal commands. The controller 252 can also direct certain portions of data to specific memory devices 230. The system 200 also shows a controller 234 for the memory devices 230. The controller 234 represents logic in the memory device for receiving and decoding commands and can drive circuitry that needs to respond to the commands.

[0038] The memory device 230 includes: Related to the operation of the memory device 230 Configuration information or value In one example, registers 236 include one or more mode registers. In one example, registers 236 include configuration information for controlling a write count auto-increment mode of memory device 230.

[0039] In one example, memory device 230 includes a scratchpad 262 that represents a temporary storage location for use by memory device 230 for internal operations. In one example, memory device 230 responds to a write command by: Pre-write read Perform the operation. Pre-write read The operation is performed by Certain The contents of the address can be read and written Should A buffered copy of the data and A write buffer, not specifically shown, may include storing data to be exchanged with the array 232. For Provide a temporary buffer. In one example, the buffer but A data path for exchanging data between the array 232 and the data bus. contact The fact that it continues In , The buffer in question is Data Bus to It can be considered inline.

[0040] In one example, the comparison produces a result that can be stored in a scratchpad 262. The scratchpad 262 represents storage for internal operations that are not sent to the controller 252. An auto-increment circuit 264 increments a value and The incremented value Write back to the memory array Should be User data and ECC data Conclusion Combined fix 2 represents hardware for enabling auto-increment, such as logic circuitry for performing the following: In one example, the auto-increment circuit 264 may be dynamically enabled and disabled based on the configuration of the memory device 230. That is, when the memory device 230 is configured as a selected write count array, the auto-increment circuit 264 may be enabled to perform an auto-increment operation on the write counts.

[0041] 3 is a block diagram of an implementation of performing auto-increment on write count metadata. Diagram 300 depicts a flow that may be implemented by a system in accordance with the described non-volatile memory system.

[0042] In one example, controller represents a media controller and 3DXP represents a NV memory device. The center column represents operations performed by all 3DXPs or all memory arrays or memory devices. The right column represents operations performed by a selected 3DXP device.

[0043] The controller issues write commands and The Write command ForAn address (ADDR) is generated (block 310). In one example, in response to a write command, all 3DXP devices decode the address of the command (block 320). After sending the command, the controller generates the DQ bus after an appropriate delay. On top The data is sent (block 312), the delay being the write delay defined for the 3DXP media.

[0044] In one example, the command of Decoding did In response, all 3DXP devices Self The current data content of Pre-read (block 322). These 3DXP devices are Pre-read The data, D Q Bus Received on The data is compared (block 324).

[0045] One of the 3DXP devices is selected as the selected 3DXP device for managing the write count. attitude In one example, the selected 3DXP device is configured to enter into an auto-increment mode. Such a mode may be configured, in one example, by setting a register or configuration bit. For example, the configuration field or bit may be auto-increment=0 for unselected 3DXP devices and auto-increment=1 for the selected device.

[0046] In one example, the selected 3DXP device increments a write count (block 330). In one example, the selected 3DXP device compares the current write count (WR_CNT) to the incremented write count (WR_CNT+1) (block 332). In one example, the selected 3DXP device stores ECC data or user data in addition to the write count. Thus, the selected 3DXP device: Pre-read Data and DQ Bus AboveComparisons with the data may be performed.

[0047] In one example, for a selected 3DXP device, an auto-increment write count mode is enabled, which means that the system can ignore a certain N bytes (e.g., 2 bytes or 3 bytes) of the DQ bus for a write command. Thus, for example, in one example Multiple The 3DXP device may perform a joint comparison of PRE_RD[15:3] and DQ_BUS[15:3]. PRE_RD[15:3] is Multiple DQ_BUS[15:3] represents the 14 bytes of data read from the memory array of the 3DXP device (which may include data from the selected 3DXP device), and DQ_BUS[15:3] represents the 14 bytes of data received from the host. last The next three bytes may be ignored. The selected 3DXP device may perform a comparison between PRE_RD[2:0] and (PRE_RD[2:0]+1), where PRE_RD[2:0] represents the write count metadata and (PRE_RD[2:0]+1) represents the incremented write count.

[0048] In one example, the 3DXP device writes only data that is changed in response to a write command. In one example, a comparison of user data, ECC data, or write count metadata Regarding either ,3DXP devices are D Data on the bus Back For example, 3DXP The device is D The result of the comparison of data is inverted. Is Bit Follow comparison In order to In one example, the 3DXP device may place an inverted Is Only the bits are written (block 326).

[0049] In one example, the selected 3DXP device compares the incremented write count (WR_CNT+1) to a threshold count (WR_CNT_MAX) (block 334). In one example, if the threshold has been reached, the 3DXP device alerts the host (block 336). In one example, the media controller sets the threshold or write count limit through a configuration register (such as a mode register). Thus, if the count has reached the threshold, the selected 3DXP device can set a flag or other alert. In response to the alert, the media controller can take appropriate action to respond to the write count reaching the threshold (block 338).

[0050] 4 is a flow diagram of an example process for auto-incrementing a write count. The process 400 for auto-incrementing a write count may be performed by an example system according to system 100 of FIG. 1 or system 200 of FIG.

[0051] In one example, a non-volatile memory device, such as a 3DXP device, receives a configuration command from a host controller at 402. If the NV memory device is the one selected to store a write count, the configuration command can set the NV memory device to perform auto-increment.

[0052] If the configuration command in the YES branch of 404 enables auto-increment, in one example, in 406: composition The command configures the selected device to manage a write count. If the configuration command does not enable auto-increment at the NO branch of 404, then the device is not selected to manage a write count. If the device does not manage write count metadata, then in one example, at 408: The The configuration disables the auto-increment circuitry on the device. In other words All devices may include an auto-increment circuit. 、 One selected device but, have the functionality enabled, and other devices have the functionality disabled.

[0053] Regardless of which configuration is set for the memory device, the memory device is ready to receive an access command. In response to receiving a write command at 410, or in response to receiving the command, in one example, the memory device accesses the address associated with the write command at 412. Memory Devices of data already stored Pre-read Execute.

[0054] In the case of multiple memory devices, there is one device selected to manage the write count. Thus, mark Standard operation A typical example is , one device will have other operations to manage the write count. In one example, Auto-increment is not enabled, In case of NO branch of 414, 416 In , the memory device is The pre-read data, Write Command For Compare with the received data.

[0055] In one example, the memory device stores the current data content ( Pre-read Perform a comparison between the data that was written and the data that was 。 because, Memory The device is flipped due to a write command. It will be This is because it only writes deltas or bits. So, in one example, Multiple Each memory device is written Should For each bit of data, B Determine whether the bit is inverted. B If the bit is not inverted, in one example, at 420, the device Unchanged Do not write any bits.

[0056] At the YES branch of 418 BIf the bits are inverted, in one example, at 422, Memory The device inverts the bits on the data bus so that it can place the result of the comparison on the data bus for writing to the memory array. Pre-read The data is placed on the data bus. figure , used for comparison purposes only, In this case, it should be written result but , D Once on the data bus, To Once the data is set, 424 Memory The device is The Write data to the array.

[0057] For devices that store a write count, auto-increment is enabled at 414, YES branch. In one example, at 426, the selected device increments the write count and compares the incremented write count to a threshold value, which may be a threshold value for indicating a risk of write disturb, Life Cycle or some other threshold value. The The device compares the incremented value to a number of different thresholds.

[0058] If one or more thresholds have been reached at YES branch of 428, in one example, the device sends an alert to the host at 430. In one example, if multiple thresholds are compared, the device can send different alerts for different thresholds. In one example, the device sends a single alert and the host sends multiple alerts. Source decision In order to Querying the device: Whether or not the threshold has been reached, in one example, after incrementing the write count, the device can load the incremented write count for write-back to the array, at 432. For selected devices, the write is done for comparison on the inverted bit. The write count is Pre-read can be considered as data 、 The incremented write count is read from the DQ bus. This is a replacement for the written dataProcessing returns to 416.

[0059] 5 is a block diagram of an example of a memory subsystem in which write count auto-increment can be implemented. System 500 includes a processor and elements of a memory subsystem in a computing device. System 500 provides an example of a system according to system 100 of FIG. 1 or system 200 of FIG. 2.

[0060] In one example, the system 500 includes auto-increment logic 590 in the memory device 540. In one example, the memory device 540 is a memory block according to any example herein. About A memory device 540 may be selected from among multiple memory devices of memory module 570 for managing the block write count. In one example, memory device 540 stores write count metadata in memory array 560. In one example, register 544 includes a field that is written to to determine whether memory device 540 is the selected memory device for managing the write count. In one example, auto-increment logic 590 includes hardware for performing auto-incrementing of the write count.

[0061] Processor 510 represents a processing unit of a computing platform that may run an operating system (OS) and applications, which may collectively be referred to as hosts or users of memory. The OS and applications perform operations that result in memory access. Processor 510 may include one or more separate processors. Each of the separate processors may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing units may be a primary processor, such as a CPU (Central Processing Unit), a peripheral processor, such as a GPU (Graphics Processing Unit), or a combination thereof. Memory access may also be initiated by devices such as a network controller or a hard disk controller. Such devices may be integrated with or attached to the processor in some systems, via a bus (e.g., PCI Express), or a combination thereof. System 500 may be implemented as a SoC (System on a Chip) or with stand-alone components.

[0062] In one example, reference to a memory device may refer to a non-volatile memory device whose state is deterministic even when power is interrupted to the device. In one example, the non-volatile memory device is a block addressable memory device, such as NAND or NOR technology. Thus, the memory device may also include future generation non-volatile devices, such as three-dimensional cross-point memory devices, other byte-addressable non-volatile memory devices. The memory device may include a non-volatile byte-addressable medium that stores data based on the resistance state of a memory cell or the phase of a memory cell. In one example, the memory device may use a chalcogenide phase change material (e.g., chalcogenide glass). In one example, the memory device may be or include a multi-threshold level NAND flash memory, a NOR flash memory, a single or multi-level phase change memory (PCM) or a switched phase change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), a magnetoresistive random access memory (MRAM) incorporating memristor technology, or a rotational transfer torque (STT) MRAM, or any combination of the above or other memories.

[0063] The memory controller 520 represents one or more memory controller circuits or devices for the system 500. The memory controller 520 represents control logic that generates memory access commands in response to execution of operations by the processor 510. The memory controller 520 accesses one or more memory devices 540. The memory devices 540 can be DRAM devices according to any of those mentioned above. In one example, the memory devices 540 are organized and managed as different channels. Each channel couples to buses and signal lines that couple multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and timing, data transfer, command and address exchange, and other operations are separate for each channel. Coupling may refer to electrical coupling, communicative coupling, physical coupling, or combinations thereof. Physical coupling may include direct contact. Electrical coupling includes interfaces or interconnects that allow electricity to flow between components or allow signaling between components, or both. A communicative coupling includes any connection, including wired or wireless, that allows the components to exchange data.

[0064] In one example, the settings for each channel are controlled by a separate mode register or other register settings. In one example, each memory controller 520 manages a separate memory channel, although system 500 can be configured to have multiple channels managed by a single controller or multiple controllers on a single channel. In one example, memory controller 520 is part of a host processor or host processor device 510, such as logic implemented on the same die or in the same package space as the processor.

[0065] The memory controller 520 includes I / O interface logic 522 that couples to a memory bus, such as the memory channel mentioned above. The I / O interface logic 522 (and the I / O interface logic 542 of the memory device 540) may include pins, pads, connectors, signal lines, traces or wires, or other hardware that connects to the device, or a combination thereof. The I / O interface logic 522 may include a hardware interface. As shown, the I / O interface logic 522 includes at least a driver / transceiver for the signal lines. Typically, wires in an integrated circuit interface couple with pads, pins or connectors to interface with signal lines or traces or other wires between devices. The I / O interface logic 522 may include drivers, receivers, transceivers or terminations or other circuits or combinations of circuits for exchanging signals on the signal lines between the devices. The exchange of signals includes at least one of transmission or reception. Although shown coupling I / O 522 from memory controller 520 to I / O 542 of memory device 540, it will be understood that in implementations of system 500 where groups of memory devices 540 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of memory controller 520. An implementation of system 500 includes one or more memory modules 570. I / O 542 may include interface hardware of the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 520 include separate interfaces to other memory devices 540.

[0066] The bus between the memory controller 520 and the memory devices 540 may be implemented as multiple signal lines coupling the memory controller 520 to the memory devices 540. The bus may typically include at least a clock (CLK) 532, a command / address (CMD) 534, and write data (DQ) and read data (DQ) 536, as well as zero or more other signal lines 538. In one example, the bus or connection between the memory controller 520 and the memory may be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line for CMD may be referred to as a "C / A bus" (or ADD / CMD bus, or some other designation indicating transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for write and read DQ may be referred to as a "data bus." In one example, the independent channels have different clock signals, C / A bus, data bus, and other signal lines. Thus, the system 500 may be considered to have multiple "buses" in the sense that independent interface paths may be considered separate buses. In addition to the lines explicitly shown, it will be understood that the buses may include at least one of strobe signaling lines, alert lines, auxiliary lines, or other signal lines, or combinations thereof. It will also be understood that serial bus technology may be used for the connection between the memory controller 520 and the memory devices 540. An example of a serial bus technology is the transmission of high speed data with 8B10B encoding and an embedded clock over a single differential pair of signals in each direction. In one example, CMD 534 represents a signal line shared with multiple memory devices in parallel. In one example, multiple memory devices share the encoded command signal line of CMD 534, each with a separate chip select (CS_n) signal line for selecting an individual memory device.

[0067] It will be appreciated that in the example of the system 500, the bus between the memory controller 520 and the memory devices 540 includes an auxiliary command bus CMD 534 and an auxiliary bus DQ 536 for carrying write data and read data. In one example, the data bus may include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ 536 may include a unidirectional write signal line for writes and data from the host to the memory, and a unidirectional line for read data from the memory to the host. Depending on the memory technology and system design chosen, other signals 538 may accompany the bus or sub-buses, such as strobe lines DQ. Depending on the design of the system 500, or implementation if a design supports multiple implementations, the data bus may have more or less bandwidth per memory device 540. For example, the data bus may support memory devices having either a x4 interface, a x8 interface, a x16 interface, or other interfaces. The W in the definition "xW" is an integer that refers to the interface size or width of the memory device 540, representing the number of signal lines for exchanging data with the memory controller 520. The interface size of a memory device is the controlling factor as to how many memory devices can be used simultaneously per channel in the system 500 or coupled in parallel to the same signal lines. In one example, high bandwidth memory devices, wide interface devices or stacked memory configurations or combinations thereof can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface or other data bus interface width.

[0068] In one example, the memory device 540 and the memory controller 520 exchange data over the data bus in bursts or a series of consecutive data transfers. A burst corresponds to a number of transfer cycles related to the bus frequency. In one example, a transfer cycle can be a full clock cycle of transfers occurring on the same clock or strobe signal edge (e.g., rising edge). In one example, a full clock cycle, referring to a cycle of the system clock, is divided into a number of unit intervals (UIs). Each UI is a transfer cycle. For example, a double data rate transfer triggers on both edges (e.g., rising and falling) of the clock signal. A burst can last for a configured number of UIs. This can be a configuration stored in a register or triggered on the fly. For example, a series of eight consecutive transfer periods can be considered a burst length of 8 (BL8), and each memory device 540 can transfer data in each UI. Thus, a x8 memory device operating at BL8 can transfer 54 bits of data (8 data signal lines x 8 data bits transferred per line via the burst). It will be understood that this simple example is illustrative only and is not limiting.

[0069] The memory devices 540 represent memory resources for the system 500. In one example, each memory device 540 is a separate memory die. In one example, each memory device 540 can be an interface with multiple (e.g., two) channels per device or die. Each memory device 540 includes an I / O interface logic 542 with a bandwidth (e.g., x16 or x8 or some other interface bandwidth) determined by the implementation of the device. The I / O interface logic 542 allows the memory device to interface with the memory controller 520. The I / O interface logic 542 can include a hardware interface and can respond to the I / O 522 of the memory controller, but at the memory device end. In one example, multiple memory devices 540 are connected in parallel to the same command and data bus. In another example, multiple memory devices 540 are connected in parallel to the same command bus and connected to different data buses. For example, the system 500 can be configured with multiple memory devices 540 coupled in parallel. Each memory device responds to commands and accesses its internal memory resources 560. For a write operation, each memory device 540 can write a portion of the entire data word, and for a read operation, each memory device 540 can fetch a portion of the entire data word, with the remaining bits of the word being provided or received in parallel by the other memory device.

[0070] In one example, the memory device 540 is disposed directly on a motherboard of a computing device or a host system platform (e.g., a PCB (printed circuit board) on which the processor 510 is disposed). In one example, the memory device 540 may be organized into a memory module 570. In one example, the memory module 570 represents a dual in-line memory module (DIMM). In one example, the memory module 570 represents another organization of multiple memory devices for sharing at least a portion of the access or control circuitry. The circuitry may be a separate circuit, separate device, or separate board from the host system platform. The memory module 570 may include multiple memory devices 540 and may include support for multiple separate channels to the included memory devices disposed therein. In another example, the memory device 540 may be incorporated into the same package as the memory controller 520, for example, by a technology such as a multi-chip module (MCM), package-on-package, through silicon via (TSV) or other technology or combination thereof. Similarly, in one example, multiple memory devices 540 may be incorporated into the memory module 570. They may themselves be incorporated into the same package as the memory controller 520. It will be appreciated that in these and other implementations, the memory controller 520 may be part of the host processor 510.

[0071] Each of the memory devices 540 includes one or more memory arrays 560. The memory arrays 560 represent addressable memory locations or storage locations of data. Typically, the memory arrays 560 are managed as rows of data and accessed via control of wordlines (rows) and bitlines (individual bits within a row). The memory arrays 560 may be organized as separate channels, ranks, banks, and partitions of memory. A channel may refer to an independent control path to storage locations in the memory device 540. A rank may refer to a common location across multiple memory devices in parallel (e.g., the same row address in different devices). A bank may refer to a sub-array of memory locations in the memory device 540. In one example, a bank of memory is divided into sub-banks with at least a portion of the shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks. This allows for separate addressing and access. It will be understood that the channels, ranks, banks, sub-banks, bank groups, or other organization of memory locations, and combinations of such organization may overlap in their application to physical resources. For example, the same physical memory location may be accessed through a particular channel as a particular bank that may also belong to a rank. Thus, the organization of memory resources may be understood inclusively, not exclusively.

[0072] In one example, the memory device 540 includes one or more registers 544. The registers 544 represent one or more storage devices or memory locations that provide configuration or settings for operation of the memory device. In one example, the registers 544 can provide memory locations in the memory device 540 for storing data accessed by the memory controller 520 as part of a control or management operation. In one example, the registers 544 include one or more mode registers. In one example, the registers 544 include one or more general purpose registers. Configuration of the locations in the registers 544 can configure the memory device 540 to operate in different "modes." Command information can trigger different operations in the memory device 540 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines depending on the mode. Settings in the registers 544 can indicate configuration of I / O settings (e.g., timing, termination or ODT (on-die termination) 546, driver configurations or other I / O settings).

[0073] In one example, the memory device 540 includes an ODT 546 as part of the interface hardware associated with the I / O 542. The ODT 546 may be configured as described above and may provide an impedance setting that is applied to the interface to designated signal lines. In one example, the ODT 546 is applied to the DQ signal lines. In one example, the ODT 546 is applied to the command signal lines. In one example, the ODT 546 is applied to the address signal lines. In one example, the ODT 546 may be applied to any combination of the above. The ODT setting may be changed based on whether the memory device is a selected target or non-target device of an access operation. The ODT 546 setting may affect the timing and reflection of the signaling on the termination lines. Careful control over the ODT 546 may allow for faster operation with better matching of the applied impedance and load. The ODT 546 may be applied to certain signal lines of the I / O interface 542, 522 (e.g., ODT for the DQ lines or ODT for the CA lines), but not necessarily to all signal lines.

[0074] The memory device 540 includes a controller 550 that represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 550 decodes commands sent by the memory controller 520 and generates internal operations to execute or satisfy the commands. The controller 550 may be referred to as an internal controller and is separate from the host's memory controller 520. The controller 550 may determine which mode is selected based on the register 544 and may configure operations for accessing the memory resource 560 or other operations internally based on the selected mode. The controller 550 generates control signals to control the routing of bits within the memory device 540 to provide an appropriate interface for the selected mode and send the command to the appropriate memory location or address. The controller 550 includes a command logic 552 that can decode command encodings received on the command and address signal lines. Thus, the command logic 552 may be or include a command decoder. Using the command logic 552, the memory device can identify the command and generate internal operations to execute the requested command.

[0075] Referring back to memory controller 520, memory controller 520 includes command (CMD) logic 524, which represents logic or circuitry for generating commands to be sent to memory device 540. Generating a command may refer to preparing a pre-scheduled command or a queued command for transmission. Generally, signaling within a memory subsystem includes address information within or associated with a command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling a transaction for memory device 540, memory controller 520 can issue a command via I / O 522 to cause memory device 540 to execute the command. In one example, controller 550 of memory device 540 receives and decodes command and address information received from memory controller 520 via I / O 542. Based on the received command and address information, controller 550 can execute the command by controlling the timing of operations of logic and circuits within memory device 540. The controller 550 is responsible for compliance with standards or specifications, such as timing and signaling requirements, within the memory device 540. The memory controller 520 can implement compliance with standards or specifications through scheduling and control of accesses.

[0076] Memory controller 520 includes a scheduler 530, which represents logic or circuitry for generating and ordering transactions to be sent to memory device 540. From one perspective, the primary function of memory controller 520 is to schedule memory accesses and other transactions to memory device 540. thing Such scheduling can be said to be the process of data transfer by the processor 510. ofThis may include generating the transactions themselves to implement the requests and to maintain data integrity (e.g., using refresh related commands). A transaction may include one or more commands and may result in the transfer of commands or data or both in one or more timing cycles, such as a clock cycle or unit interval. A transaction may be for an access, such as a read or write or related command or combination thereof. Other transactions may include configuration, settings, memory management commands for data integrity, or other commands or combinations thereof.

[0077] The memory controller 520 typically includes logic, such as a scheduler 530, to enable transaction selection and ordering to improve performance of the system 500. Thus, the memory controller 520 can select which of the outstanding transactions should be sent to the memory device 540 and in what order. This is typically accomplished using logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 520 manages the transmission of transactions to the memory device 540 and manages the timing associated with the transactions. In one example, transactions have deterministic timing. The timing can be managed by the memory controller 520 and used in determining how to schedule transactions with the scheduler 530.

[0078] In one example, the memory controller 520 includes refresh (REF) logic 526. The refresh logic 526 may be used to refresh memory resources to maintain a deterministic state. Volatile memory resources need to be refreshed regularly to maintain state, while non-volatile memory resources may need to be refreshed to avoid read / write disturb. In one example, the refresh logic 526 indicates the location of the refresh and the type of refresh to perform. The refresh logic 526 may trigger a self-refresh in the memory device 540 or may perform an external refresh (which may be referred to as an auto-refresh command) by sending a refresh command, or a combination thereof. In one example, the controller 550 in the memory device 540 includes refresh logic 554 for applying refreshes in the memory device 540. The refresh logic 554 generates internal operations to perform the refreshes either internally or according to an external refresh received from the memory controller 520.

[0079] 6 is a block diagram of an example of a computing system in which write count auto-increment can be implemented. System 600 represents a computing device according to any of the examples herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device. System 600 provides an example of a system according to system 100 of FIG. 1 or system 200 of FIG. 2.

[0080] In one example, system 600 includes auto-increment logic 692 in memory subsystem 620 or auto-increment logic 694 in storage subsystem 680, or both. In one example, one NV memory device or NV memory array of memory 630 or one NV memory device of storage 684 Selected from multiple devices Manage block write counts for memory blocks according to any example herein death In one example, the selected NV memory device or NV memory array stores the write count metadata. In one example, the selected device is selected based on a configuration mode configured to manage the write count. R In one example, the auto-increment logic 692 or the auto-increment logic 694 includes hardware for performing auto-incrementing of the write count.

[0081] System 600 includes a processor 610. Processor 610 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core or other processing hardware, or combination thereof, to provide processing or execution of instructions for system 600. Processor 610 controls the overall operation of system 600 and may be or include one or more programmable general-purpose or application-specific microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0082] In one example, the system 600 includes an interface 612 coupled to the processor 610. The interface 612 may represent a higher speed or high throughput interface for a system component that requires a higher bandwidth connection, such as the memory subsystem 620 or the graphics interface component 640. The interface 612 represents an interface circuit that may be a standalone component or may be integrated into the processor die. The interface 612 may be integrated on the processor die as a circuit or integrated into a system-on-chip as a component. If present, the graphics interface 640 interfaces to a graphics component for providing a visual display to a user of the system 600. The graphics interface 640 may be a standalone component or may be integrated into the processor die or system-on-chip. In one example, the graphics interface 640 can drive a high definition (HD) or ultra high definition (UHD) display that provides output to a user. In one example, the display may include a touch screen display. In one example, graphics interface 640 generates a display based on data stored in memory 630, or based on operations performed by processor 610, or both.

[0083] Memory subsystem 620 represents the main memory of system 600 and provides storage for data values ​​used in the execution of codes or routines executed by processor 610. Memory subsystem 620 may include one or more memory devices 630, such as one or more types of random access memory (RAM), such as read-only memory (ROM), flash memory, DRAM, 3DXP (three-dimensional crosspoint) or other memory devices or combinations of such devices. Memory 630 stores and hosts, among other things, an operating system (OS) 632 for providing a software platform for the execution of instructions within system 600. Additionally, applications 634 may be executed on the software platform of OS 632 from memory 630. Applications 634 represent programs. The programs have their own operating logic for the execution of one or more functions. Processes 636 represent agents or routines that provide auxiliary functions to OS 632 or one or more applications 634 or a combination thereof. OS 632, applications 634 and processes 636 provide the software logic for providing the functionality for system 600. In one example, memory subsystem 620 includes memory controller 622, which is a memory controller that generates and issues commands to memory 630. It will be appreciated that memory controller 622 may be a physical part of processor 610 or a physical part of interface 612. For example, memory controller 622 may be an integrated memory controller that is integrated into a circuit with processor 610, such as integrated into a processor die or a system on a chip.

[0084] Although not specifically shown, it will be understood that system 600 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or others. A bus or other signal lines may communicatively or electrically couple components to each other, or may communicatively and electrically couple components. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport Architecture bus or an Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other buses, or combinations thereof.

[0085] In one example, the system 600 includes an interface 614 that may be coupled to the interface 612. The interface 614 may be a slower interface than the interface 612. In one example, the interface 614 represents an interface circuit that may include standalone components and integrated circuits. In one example, multiple user interface and / or peripheral components are coupled to the interface 614. The network interface 650 provides the system 600 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. The network interface 650 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB) or other wired or wireless standards-based or proprietary interface. The network interface 650 may exchange data with remote devices. Such exchanges may include transmitting data stored in memory or receiving data stored in memory.

[0086] In one example, system 600 includes one or more input / output (I / O) interfaces 660. I / O interface 660 may include one or more interface components through which a user interacts with system 600 (e.g., voice, alphanumeric, haptic / touch or other interfaces). Peripheral interface 670 may include any hardware interface not specifically mentioned above. Peripheral generally refers to devices that connect dependently to system 600. A dependent connection is one in which system 600 provides a software or hardware platform or where operations are performed on the platform with which a user interacts.

[0087] In one example, the system 600 includes a storage subsystem 680 for storing data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of the storage 680 may overlap with components of the memory subsystem 620. The storage subsystem 680 includes a storage device 684. The storage device 684 may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic disks, solid state disks, 3DXP disks, or optical-based disks, or combinations thereof. The storage 684 holds code or instructions and data 686 in a persistent state (i.e., the value is retained even if power to the system 600 is interrupted). While the storage 684 may be generally considered to be a "memory," the memory 630 is typically an execution or operating memory for providing instructions to the processor 610. While the storage 684 is non-volatile, the memory 630 may include a volatile memory (i.e., the value or state of the data is indeterminate if power to the system 600 is interrupted). In one example, storage subsystem 680 includes a controller 682 for interfacing with storage 684. In one example, controller 682 may be a physical part of interface 614 or processor 610, or may include circuitry or logic in both processor 610 and interface 614.

[0088] The power source 602 provides power to the components of the system 600. More specifically, the power source 602 typically interfaces with one or more power sources 604 in the system 600 to provide power to the components of the system 600. In one example, the power source 604 includes an AC-DC (alternating current-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy (e.g., solar power) power source 602. In one example, the power source 602 includes a DC power source, such as an external AC-DC converter. In one example, the power source 602 or the power source 604 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 602 can include an internal battery or fuel cell power source.

[0089] 7 is a block diagram of an example of a mobile device in which write count auto-increment may be implemented. System 700 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device or other mobile or embedded computing device. It will be understood that not all components of such a device are shown in system 700, although certain of these components are generally shown. System 700 provides an example of a system according to system 100 of FIG. 1 or system 200 of FIG. 2.

[0090] In one example, the system 700 includes auto-increment logic 790 in the memory subsystem 760. In one example, one NV memory device or NV memory array of the memory 762 may be selected from among a plurality of devices for managing block write counts of memory blocks according to any example herein. In one example, the selected NV memory device or NV memory array stores the write count metadata. In one example, the selected device is selected based on a configuration mode configured to manage the write counts. In one example, the auto-increment logic 790 includes hardware for performing auto-increment of the write counts.

[0091] The system 700 includes a processor 710 that performs the primary processing operations of the system 700. The processor 710 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. The processing operations performed by the processor 710 include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting the system 700 to another device, or combinations thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or combinations thereof. The processor 710 may execute data stored in memory. The processor 710 may write or edit data stored in memory.

[0092] In one example, the system 700 includes one or more sensors 712. The sensors 712 represent embedded sensors or interfaces to external sensors, or a combination thereof. The sensors 712 enable the system 700 to monitor or detect one or more conditions of the environment or device in which the system 700 is implemented. The sensors 712 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors, or combinations thereof. The sensors 712 may also include sensors for biometric authentication systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize features of a user. The sensors 712 should be understood broadly and not as a limitation on the many different types of sensors that may be implemented with the system 700. In one example, the one or more sensors 712 couple to the processor 710 via a front-end circuit integrated into the processor 710. In one example, the one or more sensors 712 couple to the processor 710 via another component of the system 700.

[0093] In one example, system 700 includes an audio subsystem 720 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. The audio functionality may include a speaker or headphone output and a microphone input. Devices for such functionality may be integrated into or connected to system 700. In one example, a user interacts with system 700 by providing voice commands that are received and processed by processor 710.

[0094] The display subsystem 730 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide a visual display for display to a user. In one example, the display includes a haptic component or touch screen element for a user to interact with the computing device. The display subsystem 730 includes a display interface 732 that includes a particular screen or hardware device used to provide a display to a user. In one example, the display interface 732 includes logic separate from the processor 710 (such as a graphics processor) for performing at least some processing related to the display. In one example, the display subsystem 730 includes a touch screen device that provides both output and input to a user. In one example, the display subsystem 730 includes a high definition (HD) display or an ultra high definition (UHD) display that provides output to a user. In one example, the display subsystem includes or drives a touch screen display. In one example, the display subsystem 730 generates display information based on data stored in memory, or based on operations performed by the processor 710, or both.

[0095] The I / O controller 740 represents hardware devices and software components related to interaction with a user. The I / O controller 740 may operate to manage hardware that is part of the audio subsystem 720 or the display subsystem 730, or both. In addition, the I / O controller 740 represents connection points for additional devices to connect to the system 700 through which a user may interact with the system. For example, devices that may be attached to the system 700 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, buttons / switches, or other I / O devices for use with a particular application, such as a card reader, or other devices.

[0096] As mentioned above, I / O controller 740 can interact with audio subsystem 720 or display subsystem 730, or both. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of system 700. Additionally, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem includes a touch screen, the display device also functions as an input device that may be managed, at least in part, by I / O controller 740. Additional buttons or switches may also be present on system 700 to provide I / O functions managed by I / O controller 740.

[0097] In one example, I / O controller 740 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, global positioning systems (GPS) or other hardware or sensors 712 that may be included in system 700. Inputs may be part of direct user interaction, but also may provide environmental input to the system that affects its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash for a camera or other features).

[0098] In one example, the system 700 includes a power management 750 that manages battery power usage and functions related to battery charging and power saving operations. The power management 750 manages power from a power source 752 that provides power to the components of the system 700. In one example, the power source 752 includes an AC-DC (alternating current-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy source (e.g., solar power, motion-based power). In one example, the power source 752 includes only DC power, which can be provided by a DC power source such as an external AC-DC converter. In one example, the power source 752 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 752 can include an internal battery or a fuel cell power source.

[0099] The memory subsystem 760 includes a memory device 762 for storing information in the system 700. The memory subsystem 760 may include non-volatile (state does not change when power to the memory device is removed) or volatile (state is indeterminate when power to the memory device is removed) memory devices or a combination thereof. The memory 760 may store application data, user data, music, photos, documents or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the system 700. In one example, the memory subsystem 760 includes a memory controller 764 (which may also be considered part of the control of the system 700 and potentially part of the processor 710). The memory controller 764 includes a scheduler that generates and issues commands to control access to the memory device 762.

[0100] The connections 770 include hardware devices (e.g., wireless or wired connectors and communication hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable the system 700 to communicate with external devices. The external devices can be other computing devices, separate devices such as wireless access points or base stations, and peripherals such as headsets, printers or other devices. In one example, the system 700 exchanges data with the external devices for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory for reading, writing or editing data.

[0101] The connection 770 may include multiple different types of connections. For generalization, the system 700 is shown with a cellular connection 772 and a wireless connection 774. The cellular connection 772 generally refers to a cellular network connection provided by a wireless carrier, such as provided via GSM (Global System for Mobile Communications) or a variant or derivative thereof, or CDMA (Code Division Multiple Access) or a variant or derivative thereof, TDM (Time Division Multiplexing) or a variant or derivative thereof, LTE (Long Term Evolution, also referred to as "4G", "5G"), or other cellular service standards. The wireless connection 774 refers to a wireless connection that is not cellular and may include a personal area network (such as Bluetooth), a local area network (such as WiFi), or a wide area network (such as WiMAX), or other wireless communication, or a combination thereof. Wireless communication refers to the transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication occurs by a solid communication medium.

[0102] Peripheral connections 780 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be appreciated that system 700 can be both a peripheral device connected to other computing devices ("out" 782) and to system 700 ("from" 784). System 700 will typically have a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, synchronizing) content on system 700. In addition, docking connectors may enable system 700 to connect to certain peripherals that allow system 700 to control content output to, for example, an audiovisual system or other system.

[0103] In addition to proprietary docking connectors or other proprietary connection hardware, system 700 may make peripheral connections 780 through common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), MiniDisplayPort (MDP), DisplayPort including High-Definition Multimedia Interface (HDMI®), or other types.

[0104] Generally with respect to the description herein, in one example, a non-volatile memory device comprises a plurality of non-volatile (NV) memory arrays for collectively storing a data block, each array storing a portion of the data block, one of the NV memory arrays storing a write count of the data block, and a command bus interface for receiving a write command to write the data block to the NV memory array, wherein in response to receiving the write command, the NV memory arrays perform an internal read / write of the data block to the NV memory array, one NV memory array performs a read / write of the write count, increments the internal write count of the one NV memory array, and writes the incremented write count to the one NV memory array.

[0105] In one example, the NV memory array includes separate NV memory chips. In one example, one NV memory array further stores error checking and correction (ECC) data. In one example, the NV memory array further includes a register for storing a write count configuration, where one NV memory array stores a register configuration for a write count mode and the other NV memory array stores a register configuration for not enabling the write count mode. In one example, the NV memory array further includes auto-increment hardware, where the write count mode selectively enables or disables the auto-increment hardware. In one example, the NV memory array performs read-ahead and write of data to the NV memory array, compares the data in the NV memory array with the data to be written, and writes only bits that have different values ​​due to the write command. In one example, one NV memory array stores a write threshold and passes an alert to an associated controller in response to the write count reaching the write threshold.

[0106] Generally with respect to the description herein, in one example, a system includes a controller and a non-volatile memory device, the non-volatile memory device having a plurality of non-volatile (NV) memory arrays for collectively storing a data block, each array storing a portion of the data block, one of the NV memory arrays storing a write count of the data block, and a command bus interface for receiving a write command to write the data block to the NV memory array, wherein in response to receiving the write command, the NV memory arrays perform an internal read / write of the data block to the NV memory arrays, one NV memory array performs a read / write of the write count, increments the internal write count of the one NV memory array, and writes the incremented write count to the one NV memory array.

[0107] In one example, the NV memory array has separate NV memory chips. In one example, one NV memory array further stores error checking and correction (ECC) data. In one example, the NV memory array further has a register for storing a write count configuration, where one NV memory array stores a register configuration for a write count mode and the other NV memory array stores a register configuration for not enabling the write count mode. In one example, the NV memory array further has auto-increment hardware, where the write count mode selectively enables or disables the auto-increment hardware. In one example, one NV memory array stores a write threshold and passes an alert to the controller in response to the write count reaching the write threshold. In one example, the system further includes one or more of a host processor device coupled to the non-volatile memory device, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that provides power to the system.

[0108] Generally, with respect to the description herein, in one example, a method includes collectively storing a data block in a plurality of non-volatile (NV) memory arrays, each array storing a portion of the data block, and one of the NV memory arrays storing a write count for the data block; receiving a write command to write a block of data to the NV memory array; Equipped with In response to receiving a write command, the NV memory arrays perform an internal read and write of the data block to the NV memory arrays, the one NV memory array performs an internal read and write of a write count, increments the one NV memory array's internal write count, and writes the incremented write count to the one NV memory array.

[0109] In one example, the NV memory arrays include separate NV memory chips. In one example, one NV memory array further stores error checking and correction (ECC) data. In one example, the NV memory arrays further include a register that stores a write count configuration, where one NV memory array stores a register configuration for a write count mode and the other NV memory array stores a register configuration for not enabling the write count mode. In one example, the NV memory arrays further include auto-increment hardware, where the write count mode selectively enables or disables the auto-increment hardware. In one example, one NV memory array further stores a write threshold, where one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold.

[0110] The flow diagrams shown herein provide examples of sequences of various processing operations. The flow diagrams may depict physical operations as well as operations performed by software or firmware routines. The flow diagrams may depict examples of implementations of states of a finite state machine (FSM) that may be implemented in hardware and / or software. The order of operations, although shown in a particular sequence or order, may be modified unless otherwise specified. Thus, the illustrated diagrams should be understood as examples only, and the processes may be performed in different orders and some operations may be performed in parallel. Additionally, one or more operations may be omitted. Thus, not all implementations perform all operations.

[0111] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations and / or data. The content may be directly executable ("object" or "executable"), source code or difference code ("delta" or "patch" code). The software content of what is described herein may be provided via an article of manufacture in which the content is stored, or via a method of operating a communications interface to transmit data through the communications interface. A machine-readable storage medium may cause a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface may include any mechanism for interfacing to either a hardwired, wireless, optical, etc. medium for communicating with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured by providing configuration parameters and / or sending signals to prepare the communications interface to provide data signals describing the software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0112] Various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component may be implemented as a software module, a hardware module, special purpose hardware (e.g., special purpose hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0113] In addition to what is described herein, various modifications may be made to the disclosure and implementation of the present invention without departing from the scope thereof. Thus, the illustrations and examples herein should be construed in an illustrative sense and not in a limiting sense. The scope of the present invention should be determined solely by reference to the claims that follow. [Other possible items] [Item 1] a plurality of non-volatile (NV) memory arrays for collectively storing a data block, each array storing a portion of the data block, one of the NV memory arrays storing a write count of the data block; a command bus interface for receiving a write command to write the data block to the NV memory array, in response to receiving the write command, the NV memory array internally writing the data block to the NV memory array; Pre-write read and one of the NV memory arrays is Pre-write read a command bus interface for executing the command, incrementing the write count within the one NV memory array, and writing the incremented write count to the one NV memory array; 1. A non-volatile memory device comprising: [Item 2] 2. The non-volatile memory device of item 1, wherein the NV memory array has separate NV memory chips. [Item 3] 2. The non-volatile memory device of item 1, wherein the one NV memory array further stores error checking and correction (ECC) data. [Item 4] The nonvolatile memory device of item 1, wherein the NV memory arrays further have registers for storing a write count configuration, and one of the NV memory arrays stores a register configuration for a write count mode and the other of the NV memory arrays stores a register configuration for not enabling the write count mode. [Item 5] 5. The non-volatile memory device of item 4, wherein the NV memory array further comprises auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. [Item 6] The NV memory array is In The above data block Pre-write read 2. The non-volatile memory device of claim 1, further comprising: a) executing a write command to compare the data in the NV memory array with the data to be written; and b) writing only those bits that have different values ​​due to the write command. [Item 7] 2. The non-volatile memory device of item 1, wherein the one NV memory array stores a write threshold and passes an alert to an associated controller in response to the write count reaching the write threshold. [Item 8] A controller; Non-volatile memory devices and A system comprising: The non-volatile memory device is Store data blocks together Multiple a plurality of non-volatile (NV) memory arrays, each storing a portion of the data block, one of the NV memory arrays storing a write count of the data block; a command bus interface for receiving a write command to write the data block to the NV memory array, in response to receiving the write command, the NV memory array internally writing the data block to the NV memory array; Pre-write readand one of the NV memory arrays is Pre-write read a command bus interface for executing the command, incrementing the write count inside the one NV memory array, and writing the incremented write count to the one NV memory array; having system. [Item 9] 9. The system of claim 8, wherein the NV memory array includes separate NV memory chips. [Item 10] 9. The system of claim 8, wherein the one NV memory array further stores error checking and correction (ECC) data. [Item 11] The system of item 8, wherein the NV memory arrays further have registers for storing a write count configuration, and one of the NV memory arrays stores a register configuration for a write count mode and the other of the NV memory arrays stores a register configuration for not enabling the write count mode. [Item 12] 12. The system of claim 11, wherein the NV memory array further comprises auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. [Item 13] 9. The system of claim 8, wherein the one NV memory array stores a write threshold and passes an alert to the controller in response to the write count reaching the write threshold. [Item 14] a host processor device coupled to the non-volatile memory device; a display communicatively coupled to the host processor; a network interface communicatively coupled to the host processor; or A battery to power the above system 9. The system of claim 8, further comprising one or more of the following: [Item 15] collectively storing a data block in a plurality of non-volatile (NV) memory arrays, each array storing a portion of the data block, and one of the NV memory arrays storing a write count for the data block; receiving a write command to write the data block to the NV memory array; Equipped with In response to receiving the write command, the NV memory array writes the internal data of the data block to the NV memory array. Pre-write read and one of the NV memory arrays is Pre-write read Execute the above and the inside of one NV memory array in incrementing the write count and writing the incremented write count to the one NV memory array; method. [Item 16] Item 16. The method of item 15, wherein the NV memory array includes separate NV memory chips. [Item 17] Item 16. The method of item 15, wherein the one NV memory array further stores error checking and correction (ECC) data. [Item 18] Item 16. The method of item 15, wherein the NV memory arrays further have registers for storing a write count configuration, and one of the NV memory arrays stores a register configuration for a write count mode and the other of the NV memory arrays stores a register configuration for not enabling the write count mode. [Item 19] 20. The method of claim 18, wherein the NV memory array further comprises auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. [Item 20] Item 16. The method of item 15, wherein the one NV memory array further stores a write threshold, and the one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold.

Claims

1. a plurality of non-volatile (NV) memory arrays collectively storing a data block, each of the plurality of NV memory arrays storing a portion of the data block, and one NV memory array of the plurality of NV memory arrays further storing a write count of the data block; a command bus interface that receives a write command for writing the data block to the plurality of NV memory arrays, wherein in response to receiving the write command, the plurality of NV memory arrays perform an internal pre-write read of the data block in the plurality of NV memory arrays, and the one NV memory array performs the internal pre-write read of the write count, increments the write count within the one NV memory array, and writes the incremented write count to the one NV memory array; 1. A non-volatile memory device comprising:

2. The non-volatile memory device of claim 1 , wherein the plurality of NV memory arrays comprise separate NV memory chips.

3. The non-volatile memory device of claim 1 or 2, wherein the one NV memory array further stores error checking and correction (ECC) data.

4. 4. The non-volatile memory device of claim 1, wherein the plurality of NV memory arrays further have registers for storing a write count configuration, and one of the NV memory arrays stores a register configuration for a write count mode, and the other of the plurality of NV memory arrays stores a register configuration for not enabling the write count mode.

5. The non-volatile memory device of claim 4 , wherein the plurality of NV memory arrays further comprise auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware.

6. 6. The non-volatile memory device of claim 1, wherein after performing the pre-write read of the data blocks in the multiple NV memory arrays, the multiple NV memory arrays compare the data read by the pre-write read of the multiple NV memory arrays with the data to be written, and write only bits that have different values ​​due to the write command.

7. 7. The non-volatile memory device of claim 1, wherein the one NV memory array stores a write threshold and passes an alert to an associated controller in response to the write count reaching the write threshold.

8. 1. A system having a non-volatile memory, comprising: A controller; Non-volatile memory devices and Equipped with The non-volatile memory device comprises: a plurality of non-volatile (NV) memory arrays collectively storing a data block, each of the plurality of NV memory arrays storing a portion of the data block, and one NV memory array of the plurality of NV memory arrays further storing a write count of the data block; a command bus interface that receives a write command for writing the data block to the plurality of NV memory arrays, wherein in response to receiving the write command, the plurality of NV memory arrays perform an internal pre-write read of the data block in the plurality of NV memory arrays, and the one NV memory array performs the internal pre-write read of the write count, increments the write count within the one NV memory array, and writes the incremented write count to the one NV memory array; having system.

9. The system of claim 8 , wherein the multiple NV memory arrays comprise separate NV memory chips.

10. The system of claim 8 or 9, wherein the one NV memory array further stores error checking and correction (ECC) data.

11. 11. The system of claim 8, wherein the plurality of NV memory arrays further include a register for storing a write count configuration, and wherein one of the NV memory arrays stores a register configuration for a write count mode and another of the plurality of NV memory arrays stores a register configuration for not enabling the write count mode.

12. 12. The system of claim 11, wherein the plurality of NV memory arrays further include auto-increment hardware, and wherein the write count mode selectively enables or disables the auto-increment hardware.

13. 13. The system of claim 8, wherein the one NV memory array stores a write threshold and passes an alert to the controller in response to the write count reaching the write threshold.

14. a host processor device coupled to the non-volatile memory device; a display communicatively coupled to the host processor; a network interface communicatively coupled to the host processor; or A battery that powers the system The system of claim 8 , further comprising one or more of:

15. 1. A method for storing data, comprising: collectively storing a data block in a plurality of non-volatile (NV) memory arrays, each of the plurality of NV memory arrays storing a portion of the data block, and an NV memory array of the plurality of NV memory arrays further storing a write count of the data block; receiving a write command to write the data block to the plurality of NV memory arrays; Equipped with in response to receiving the write command, the one NV memory array performs the internal pre-write read of the write count, increments the write count within the one NV memory array, and writes the incremented write count to the one NV memory array, as the multiple NV memory arrays perform internal pre-write reads of the data block in the multiple NV memory arrays. method.

16. The method of claim 15 , wherein the multiple NV memory arrays comprise separate NV memory chips.

17. The method of claim 15 or 16, wherein the one NV memory array further stores error checking and correction (ECC) data.

18. 18. The method of claim 15, wherein the plurality of NV memory arrays further include a register for storing a write count configuration, the one NV memory array storing a register configuration for a write count mode and the other of the plurality of NV memory arrays storing a register configuration for not enabling the write count mode.

19. 20. The method of claim 18, wherein the plurality of NV memory arrays further include auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware.

20. 20. The method of claim 15, wherein the one NV memory array further stores a write threshold, and the one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold.

21. 1. An apparatus for storing data, comprising: means for collectively storing a data block in a plurality of non-volatile (NV) memory arrays, each of the plurality of NV memory arrays storing a portion of the data block, and an NV memory array of the plurality of NV memory arrays further storing a write count for the data block; means for receiving a write command to write the data block to the plurality of NV memory arrays; means for performing the internal pre-write read of the write count in the one NV memory array in response to receiving the write command, in conjunction with performing an internal pre-write read of the data block in the plurality of NV memory arrays, incrementing the write count within the one NV memory array, and writing the incremented write count to the one NV memory array; An apparatus comprising:

22. The apparatus of claim 21 , wherein the multiple NV memory arrays comprise separate NV memory chips.

23. 23. The apparatus of claim 21 or 22, wherein the one NV memory array further comprises means for storing error checking and correction (ECC) data.

24. 24. The apparatus of claim 21, wherein the plurality of NV memory arrays further include registers for storing a write count configuration, the one NV memory array storing a register configuration for a write count mode and the other of the plurality of NV memory arrays storing a register configuration for not enabling the write count mode.

25. 25. The apparatus of claim 24, wherein the plurality of NV memory arrays further include auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware.

26. 24. The apparatus of claim 21, wherein the one NV memory array further stores a write threshold, and the one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold.

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