Configurable time sequence control system

Abstract

The invention discloses a configurable time sequence control system, which relates to the technical field of electronic components, can replace the requirements of most scenes on a time sequence controller, can be directly reused in a development process, can greatly reduce the development workload and can improve the development efficiency. And the time sequence can be flexibly adjusted by adjusting configuration parameters, so that the working difficulty of debugging and maintenance is reduced. The system is constructed by single-channel basic modules, and the maturity and reliability of the system are easy to guarantee. Pure Veri log / VHDL design is adopted, an IP core can be independently packaged and added into an IP library of a programmable logic device integrated development environment, the IP core can be directly called during design and use, and due to the fact that pure logic codes are adopted for implementation, limitation of device models and development platforms is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of electronic components, and in particular to a configurable timing control system. Background Art

[0002] Timing controllers are mainly used to generate a series of electrical signals with timing requirements in electronic devices. Electronic devices or circuits often need to act or respond in a prescribed order, which requires the control part of the device to not only correctly send out various control signals, but also require these control signals to have a certain sequence in time to achieve coordinated actions of the various circuits in the device. The commonly used method is to use a timing controller to generate these control signals.

[0003] The timing controller generates a signal group (usually a standard digital signal) that meets the timing requirements according to the specific application requirements, and then passes through various drive conversion circuits to realize signal conversion or the action of the actuator. The timing controller can be simply divided into open-loop and trigger control. Once the open-loop controller is started, it will continuously output according to the planned time sequence until the end, without interruption or stop during the period; the trigger controller has multiple feedback inputs, and the output value of the timing signal is logically related to the feedback signal.

[0004] The digital timing signal generation technologies in the prior art mainly include the following:

[0005] 1. Use digital logic circuit to build.

[0006] Use triggers, shift memory, counters, decoders and other sequential logic devices, connect the output end with the input or trigger end of the logic device, and realize the ever-changing control timing. Generally, it is only used for simple sequential logic implementation. When the timing requirements are complex, the circuit complexity will increase exponentially, which is not conducive to the long-term reliable operation of the circuit and increases the maintenance cost.

[0007] 2. Implemented using dedicated ASIC chip.

[0008] The circuit with special timing function requirements is realized as an ASIC chip, and the chip generally also includes a clock oscillation circuit, a clock frequency division circuit, etc., so as to achieve the effect of simple application circuit, fast response, stable and reliable operation. Such as fuze control, engine fuel controller, etc.

[0009] 3. Use microprocessor GPIO function and implement it with embedded software programming.

[0010] Use the timer, interrupt and other functions integrated in the microprocessor, configure the GPIO as input or output mode, and complete the timing, signal triggering, delayed output and other functions by running a specific program. This method is flexible in programming and convenient for output adjustment. However, because it is controlled by software, the time control accuracy is not high, and the real-time performance of the processor in processing other transactions will be reduced when using interrupt control.

[0011] 4. Implemented using programmable logic devices (CPLD / FPGA).

[0012] By using advanced editable logic device technology and combining programmable logic language Veri log / VHDL, the traditional use of logic chips to build timing signal control circuits is changed to programmable CPLD / FPGA chips. It can be implemented by a small-scale programmable device (GAL / CPLD), or it can be implemented as a functional module and embedded in a large-scale FPGA device. This method is generally programmed according to the requirements of the specific circuit. Once the design status is determined, the function and implementation logic of the timing controller are fixed.

[0013] The common implementation method using programmable logic devices, thanks to the flexibility of programming languages, can quickly realize functions and timing, especially for relatively simple timing control, which can be perfectly realized by using synchronous state machines and counter functions. Generally, after the debugging of this embedded timing control module is completed, its design status is determined, and it is solidified in the chip along with other logic circuits in the device and will not be changed.

[0014] The above methods mainly have the following disadvantages:

[0015] 1. The debugging process requires professional knowledge and has high requirements on personnel.

[0016] In addition to the development of digital logic circuits during the design process, this method also requires the full participation of FPGA / CPLD designers during the debugging process. Designers are required to have relevant knowledge of logic circuits, digital circuits, etc., and have high requirements on the skills and quality of developers.

[0017] 2. Poor versatility.

[0018] For different applications, the module needs to be redesigned, taking into account the number of signals, trigger relationships, relative timing, etc., and rewriting the timing state machine, trigger logic, and counting signals. Only a small part of the code (such as the counter) can be reused, resulting in poor versatility of the timing controller and low development efficiency.

[0019] 3. Design changes will cause a large workload.

[0020] When timing logic is implemented together with other logic in an FPGA / CPLD chip, if the logic circuit in the chip is changed, since the synthesis and implementation process is global, the entire design layout and timing performance will change after synthesis and implementation, which may affect other functional modules. Therefore, the design needs to be reconfirmed and tested, resulting in a lot of testing and verification work. Summary of the invention

[0021] In view of the above problems, the present invention provides a configurable timing control system for overcoming the above problems or at least partially solving the above problems.

[0022] The present invention provides the following scheme:

[0023] A configurable timing control system, comprising:

[0024] A programmable logic device, wherein the programmable logic device is used to carry at least one timing signal generator and at least one parameter register, and is used to provide pin resources for an output terminal, a feedback trigger terminal, and a configuration bus; at least one of the timing signal generators is communicatively connected to at least one of the parameter registers in a one-to-one correspondence;

[0025] A circuit clock module, wherein the circuit clock module is connected to the programmable logic device;

[0026] The parameter register is used to store the timing control parameters input by the external device through the configuration bus, so that the timing signal generator connected to the parameter register outputs the timing signal to the electronic device through the output end according to the timing control parameters.

[0027] Preferably, the external device comprises a UC processor, and the UC processor is used to write the timing control parameter into the parameter register through the configuration bus.

[0028] Preferably: the external device includes a powered erasable programmable memory, the programmable logic device further includes a parameter loading module, the parameter loading module is connected to the parameter register; the parameter loading module is connected to the powered erasable programmable memory through the configuration bus;

[0029] The parameter loading module is used to read the timing control parameters in the electrically erasable programmable memory and write them into the parameter register.

[0030] Preferably: each of the timing signal generators has two trigger source options, which are respectively used for a valid trigger source and an invalid trigger source of the timing signal;

[0031] The first 16 sources of the parameter register are external inputs, and the last 16 sources correspond to internal feedback of the channel output.

[0032] Preferably: one or more sources are selected as trigger sources from 32 sources through a configured trigger source selection register.

[0033] Preferably: the signal generation logic of the timing signal generator includes:

[0034] After the circuit is reset, the output signal is set to the default value; when the selected valid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is effectively triggered, and after a period of delay, the signal of the corresponding polarity is output and maintained; until the selected invalid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is invalidly triggered, and after a time delay, the output signal is flipped.

[0035] Preferably: the output signal is effectively triggered and started again after the invalid triggering process is executed.

[0036] Preferably, the programmable logic device includes an FPGA device or a CPLD device.

[0037] Preferably, the configuration bus includes any one of I2C, SPI, 1-Wire, UART, and LocalBus.

[0038] Preferably: the circuit clock module includes an active crystal oscillator.

[0039] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0040] A configurable timing control system provided by an embodiment of the present application can replace the demand for a timing controller in most scenarios, can be directly reused during the development process, can greatly reduce the development workload, and improve development efficiency. The timing can be flexibly adjusted by adjusting the configuration parameters, reducing the difficulty of debugging and maintenance. It is built from a single-channel basic module, and its maturity and reliability are easy to guarantee. It adopts pure Veri log / VHDL design, can be independently packaged into an IP core, added to the IP library of the integrated development environment of a programmable logic device, and directly called when designed and used. Since it is implemented using pure logic code, it is not limited by device models and development platforms.

[0041] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 It is a connection block diagram of a configurable timing control system provided by an embodiment of the present invention;

[0044] Figure 2 This is a timing signal output diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0046] See also Figure 1 , is a configurable timing control system provided by an embodiment of the present invention, such as Figure 1 As shown, the system may include:

[0047] A programmable logic device, wherein the programmable logic device is used to carry at least one timing signal generator and at least one parameter register, and is used to provide pin resources for an output terminal, a feedback trigger terminal, and a configuration bus; at least one of the timing signal generators is communicatively connected to at least one of the parameter registers in a one-to-one correspondence;

[0048] A circuit clock module, wherein the circuit clock module is connected to the programmable logic device;

[0049] The parameter register is used to store the timing control parameters input by the external device through the configuration bus, so that the timing signal generator connected to the parameter register outputs the timing signal to the electronic device through the output end according to the timing control parameters.

[0050] The configurable timing control system provided in the embodiment of the present application realizes multi-channel output by instantiating the logic circuit in a programmable logic controller chip. Then, only the parameters of the control register need to be configured through the external interface to realize online reconfiguration of the timing signal phase, polarity, pulse width, and period to meet the timing control requirements of various application scenarios. The redevelopment of the timing control logic is avoided, and the debugging process is also easy and simple, which improves development efficiency, reduces the workload of secondary testing, and shortens the R&D verification cycle.

[0051] The external device provided in the embodiment of the present application is used for the user to modify the timing control parameters. In specific implementation, a variety of different devices can be used for implementation. For example, in one implementation method, the embodiment of the present application can provide that the external device includes a UC processor, and the UC processor is used to write the timing control parameters into the parameter register through the configuration bus.

[0052] In another implementation, the embodiment of the present application may further provide that the external device includes a powered erasable programmable memory, the programmable logic device further includes a parameter loading module, the parameter loading module is connected to the parameter register; the parameter loading module is connected to the powered erasable programmable memory through the configuration bus;

[0053] The parameter loading module is used to read the timing control parameters in the electrically erasable programmable memory and write them into the parameter register.

[0054] Furthermore, the embodiment of the present application can provide that each of the timing signal generators has two trigger source options, which are respectively used for a valid trigger source and an invalid trigger source of the timing signal;

[0055] The first 16 sources of the parameter register are external inputs, and the last 16 sources correspond to the internal feedback of the channel output. Through the configured trigger source selection register, one or more sources are selected from 32 sources as trigger sources.

[0056] The signal generation logic of the timing signal generator includes:

[0057] After the circuit is reset, the output signal is set to the default value; when the selected valid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is effectively triggered, and after a period of delay, the signal of the corresponding polarity is output and maintained; until the selected invalid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is invalidly triggered, and after a time delay, the output signal is flipped. Furthermore, the output signal is effectively triggered and started again after the invalid trigger process is executed.

[0058] The system provided in the embodiment of the present application is constructed by building a logic circuit architecture for obtaining multi-channel timing control signals. The architecture is based on multiple single-channel timing output modules that can be reused and implemented in conjunction with a trigger signal selection matrix. When the hardware structure is specifically selected, the embodiment of the present application can provide that the programmable logic device includes an FPGA device or a CPLD device. The configuration bus includes any one of I2C, SPI, 1-Wire, UART, and LocalBus. The circuit clock module includes an active crystal oscillator.

[0059] It can be seen that the system provided by the embodiment of the present application uses modular and universal ideas to design a timing controller, and can realize the rapid construction of a multi-channel timing controller through simple instantiation operations. By adopting parameterized design, by configuring registers to meet various timing change requirements, trigger source selection, trigger delay, output polarity, etc. can be realized, thereby combining a myriad of timing signal combinations. The changing edge of the timing signal is controlled by the trigger source, which simplifies the control logic circuit. At the same time, the function of the number of activations is increased, which improves the application scope of the timing controller.

[0060] The system provided by this application is introduced in detail below.

[0061] The system provided in this application is based on Figure 1 The circuit realizes the construction of the timing controller platform; the circuit has the following elements:

[0062] ①UC or EEPROM memory that can load configuration parameters. UC can be an embedded SoC or a single-chip microcomputer. The bus interface is implemented as I2C by default, and can also be SPI, 1-Wire, UART or LocalBus, etc. EEPROM directly uses an I2C interface chip, and a capacity of 2Kbit can meet the needs.

[0063] ② The circuit clock source is generated by an active crystal oscillator, which can be selected according to the accuracy required by the timing, generally 25-50MHz;

[0064] ③ The programmable logic device (FPGA / CPLD) loaded with timing controller logic, in addition to ensuring certain logic block resources, also needs to provide pin resources for output Out, feedback trigger TrigIn, and configuration bus (such as I2C, etc.);

[0065] 2. Use hardware description language to implement the timing controller.

[0066] The timing controller is implemented by a parameter loading module RegLoad and a plurality of single-channel timing signal generators CH0 to CHX.

[0067] ①Parameter loading module RegLoad and parameter register group.

[0068] This part completes the loading of configuration information, mainly including a bus interface logic and a set of parameter registers. When connected to the UC processor, the UC processor writes the parameters into the parameter registers through the bus interface, which can configure the timing controller more flexibly; when using the electrically erasable programmable memory (EEPORM Flash) for configuration, the FPGA loading module reads the data in the Flash and writes it into the parameter registers.

[0069] The timing output signal of each timing signal generator is controlled by two 64-bit parameter registers. When there are multiple outputs, a register group is formed and arranged in sequence. The definition and function of each register bit are shown in Table 1:

[0070] Table 1 Registers

[0071]

[0072]

[0073] ② Input selection matrix.

[0074] Each timing signal channel of the timing signal generator has two trigger source selections, which are used for the valid (Assert) trigger source and invalid (Dessert) trigger source of the timing signal respectively.

[0075] The first 16 parameters in the parameter register are external inputs, and the last 16 parameters correspond to the internal feedback of the channel output. By configuring the trigger source selection register, one or more of the 32 sources can be selected as the trigger source. When multiple sources are selected at the same time, the multiple source signals are used as trigger signals in phase or in the future. When the value of this channel is selected as the valid trigger source, the channel will be automatically executed after the FPGA logic is reset.

[0076] ③Signal generation logic.

[0077] This part of logic is an important part of the timing generator.

[0078] After the circuit is reset, the output signal is set to the default value. When the selected valid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is effectively triggered, and after a delay, the signal of the corresponding polarity is output and maintained; until the selected invalid trigger (Dessert) signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is invalidly triggered, and after a delay, the output signal is flipped;

[0079] The output signal can be effectively triggered and started again after the invalid trigger process is executed. The timing signal output is as follows Figure 2 shown.

[0080] 3. How to configure the controller registers.

[0081] When UC is used for configuration, the processor accesses the parameter register through the bus and writes the configuration parameters. When the Enable bit of the channel in the written configuration parameters is 1, the channel is turned on and works. Therefore, it is recommended to place the configuration on / off register (EnableReg) at the end.

[0082] If EEPROM is used to configure the parameters, the configuration values ​​are stored in the EEPROM Flash in order. After power-on, the RegLoad module automatically reads the contents in order and loads them into the parameter register group of the timing control. When all parameter registers are loaded, the timing signal generator starts working. The EEPROM parameter storage correspondence table is shown in Table 2.

[0083] Table 2 EEPROM parameter storage correspondence table

[0084]

[0085] In short, the configurable timing control system provided by this application can replace the demand for timing controllers in most scenarios, can be directly reused during the development process, can greatly reduce the development workload, and improve development efficiency. The timing can be flexibly adjusted by adjusting the configuration parameters to reduce the difficulty of debugging and maintenance. It is built from single-channel basic modules, and its maturity and reliability are easy to guarantee. It adopts pure Veri log / VHDL design, can be independently packaged into IP cores, added to the IP library of the integrated development environment of programmable logic devices, and directly called when designing and using. Since it is implemented using pure logic code, it is not limited by device models and development platforms.

[0086] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0087] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0088] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0089] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A configurable timing control system, characterized in that: include: A programmable logic device, wherein the programmable logic device is used to carry at least one timing signal generator and at least one parameter register, and is used to provide pin resources for an output terminal, a feedback trigger terminal, and a configuration bus; at least one of the timing signal generators is communicatively connected to at least one of the parameter registers in a one-to-one correspondence; A circuit clock module, wherein the circuit clock module is connected to the programmable logic device; The parameter register is used to store the timing control parameters input by the external device through the configuration bus, so that the timing signal generator connected to the parameter register outputs the timing signal to the electronic device through the output end according to the timing control parameters.

2. The configurable timing control system according to claim 1, characterized in that: The external device includes a UC processor, and the UC processor is used to write the timing control parameter into the parameter register through the configuration bus.

3. The configurable timing control system according to claim 1, characterized in that: The external device includes a powered erasable programmable memory, and the programmable logic device also includes a parameter loading module, and the parameter loading module is connected to the parameter register; the parameter loading module is connected to the powered erasable programmable memory through the configuration bus; The parameter loading module is used to read the timing control parameters in the electrically erasable programmable memory and write them into the parameter register.

4. The configurable timing control system according to claim 1, characterized in that: Each of the timing signal generators has two trigger source options, which are respectively used for a valid trigger source and an invalid trigger source of the timing signal; The first 16 sources of the parameter register are external inputs, and the last 16 sources correspond to internal feedback of the channel output.

5. The configurable timing control system according to claim 4, characterized in that: By configuring the trigger source selection register, select one or more of the 32 sources as the trigger source.

6. The configurable timing control system according to claim 1, characterized in that: The signal generation logic of the timing signal generator includes: After the circuit is reset, the output signal is set to the default value; when the selected valid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is effectively triggered, and after a period of delay, the signal of the corresponding polarity is output and maintained; until the selected invalid trigger signal changes, the signal edge detection logic finds the trigger edge that meets the requirements, the timing channel is invalidly triggered, and after a time delay, the output signal is flipped.

7. The configurable timing control system according to claim 6, characterized in that: The output signal is activated again after being effectively triggered after executing the invalid trigger process.

8. The configurable timing control system according to claim 1, characterized in that: The programmable logic device includes an FPGA device or a CPLD device.

9. The configurable timing control system according to claim 1, characterized in that: The configuration bus includes any one of I2C, SPI, 1-Wire, UART, and LocalBus.

10. The configurable timing control system according to claim 1, characterized in that: The circuit clock module includes an active crystal oscillator.

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