Image sensing device and operation method of the same

Abstract

To provide an image sensing device capable of reducing noise generation by setting an offset voltage for A / D (analog-to-digital) conversion on the basis of a readout pixel signal, and to provide an operation method of the same.SOLUTION: An image sensing device is provided with: a pixel array that includes unit pixels each transmitting and storing electric charges in response to a transmission signal and reading out a pixel signal corresponding to the stored electric charges in response to a selection signal; a signal converter that compares the pixel signal and a ramp signal on the basis of a switch signal to generate a distance information signal; and a signal controller that generates the switch signal in a section where the pixel signal is read out to initialize the signal converter.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to semiconductor design technology, and more particularly, to an image sensing device and an operation method thereof.

Background Art

[0002] An image sensing device is an element that captures an image by utilizing the property of a semiconductor that reacts to light. Image sensing devices can be broadly classified into image sensing devices using a CCD (Charge Coupled Device) and image sensing devices using a CMOS (Complementary Metal Oxide Semiconductor). In recent years, due to the advantage that analog and digital control circuits can be directly realized on a single integrated circuit (IC), image sensing devices using CMOS are widely used.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide an image sensing device and an operation method thereof that can set an offset voltage for A / D (analog to digital) conversion based on a read pixel signal and reduce noise generation.

Means for Solving the Problems

[0004] An image sensing device according to an embodiment of the present invention includes a pixel array including unit pixels that transfer and accumulate charges in response to a transfer signal and read pixel signals corresponding to the accumulated charges in response to a selection signal, a signal converter that compares the pixel signal and a ramp signal based on a switch signal and generates a distance information signal, and a signal controller that generates the switch signal in a section where the pixel signal is read to initialize the signal converter.

[0005] An operating method for an image sensing device according to yet another embodiment of the present invention may include the steps of: reading out first and second pixel signals corresponding to first and second charges accumulated in a unit pixel, respectively, in response to a selection signal; setting an offset voltage between the read-out first and second pixel signals and a ramp signal in response to a switch signal; resetting the first and second pixel signals in response to a transmission signal; and generating a distance information signal corresponding to the voltage change difference of the reset first and second pixel signals in response to the ramp signal. [Effects of the Invention]

[0006] An image sensing device according to an embodiment of the present invention can set an offset voltage for A / D (analog to digital) conversion based on the readout pixel signal and perform A / D conversion with the pixel signal reset. While the offset voltage is set and A / D conversion is performed, the transistors included in the unit pixel, i.e., the driving transistors, can maintain the same state. Therefore, noise caused by threshold voltage changes of the unit pixel transistors, such as fixed pattern noise, can be removed, and the signal-to-noise ratio of the distance information signal generated from the image sensing device can be improved. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram showing an image sensing device according to an embodiment of the present invention. [Figure 2] Figure 1 is a circuit diagram showing the unit pixel included in the pixel array. [Figure 3] This is a block diagram of the signal converter shown in Figure 1. [Figure 4] Figure 1 is a timing diagram illustrating the operation of the image sensing device. [Figure 5]This is a sequence diagram showing the operation of an image sensing device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to explain in detail to the extent that a person with ordinary skill in the art to which the present invention pertains can easily implement the technical idea of ​​the present invention.

[0009] Furthermore, throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "electrically connected" with other elements in between. Also, when a part is described as "including" or "equipping" a certain component, this means, unless otherwise stated, that it may include or equip with other components, rather than excluding them. Moreover, even if a component is described singly throughout the specification, it will be clear that the present invention is not limited to that singular component, and that such component may consist of multiple units.

[0010] Figure 1 shows a block diagram of an image sensing device according to an embodiment of the present invention.

[0011] As shown in Figure 1, the image sensing device 100 can generate a distance information signal DOUT representing the distance (depth) to the subject 200 using the TOF (time of flight) method. For example, the image sensing device 100 can generate the distance information signal DOUT by detecting the phase difference between a first optical signal MS output to the subject 200 and a second optical signal RS reflected from the subject 200. The image sensing device 100 may include an optical transmitter 110, an optical receiver 120, a signal controller 130, a pixel array 140, and a signal converter 150.

[0012] The optical transmitter 110 can output a first optical signal MS to the subject 200. In this case, the first optical signal MS can be a periodic signal that toggles periodically.

[0013] The optical receiver 120 can receive a second optical signal RS reflected from the subject 200. The optical receiver 120 can remove noise such as ambient light from the second optical signal RS and provide a third optical signal RS' corresponding to the first optical signal MS to the pixel array 140.

[0014] The signal controller 130 can generate control signals MIXA / B, ROWs, SW, and VRAMP for controlling the pixel array 140 and the signal converter 150. As shown in Figure 1, the signal controller 130 may include a phase signal generation unit 132, a control signal generation unit 134, and a ramp signal generation unit 136.

[0015] The phase signal generation unit 132 can generate first and second phase signals MIXA and MIXB having different phases from each other. For example, the first and second phase signals MIXA and MIXB may have a phase difference of 180 degrees, or other phase differences may be used. The first and second phase signals MIXA and MIXB have the same period as the first optical signal MS, and one of the first and second phase signals MIXA and MIXB may have the same phase as the first optical signal MS, while the other may have a phase difference of 180 degrees.

[0016] The control signal generation unit 134 can generate multiple row signals ROWs for controlling the pixel array 140 row by row. For example, the control signal generation unit 134 can generate a first row signal for controlling the pixels arranged in the first row of the pixel array 140, and can generate an nth row signal for controlling the pixels arranged in the nth row of the pixel array 140 (where "n" is a natural number greater than 2). The control signal generation unit 134 can also generate a switch signal SW for initializing the signal converter 150.

[0017] The ramp signal generation unit 136 can generate a ramp signal VRAMP and transmit it to the signal converter 150. The ramp signal VRAMP may include a signal in which the voltage level rises from low voltage to high voltage with a predetermined slope.

[0018] The pixel array 140 can generate multiple pixel signals VPXs based on a third optical signal RS', first and second phase signals MIXA and MIXB, and multiple low signals ROWs. The pixel array 140 can include at least one unit pixel 142 for measuring the distance to the subject 200. For example, the unit pixel can be selected based on multiple low signals ROWs and can generate first and second pixel signals VPX_A and VPX_B based on the first and second phase signals MIXA and MIXB and the third optical signal RS'. Such a unit pixel configuration will be explained in more detail with reference to Figure 2.

[0019] The signal converter 150 can generate a distance information signal DOUT representing the distance to the subject 200 based on multiple pixel signals VPXs. For example, the signal converter 150 can perform A / D (analog to digital) conversion on the first and second pixel signals VPX_A and VPX_B, respectively, and then calculate the distance information signal DOUT from the A / D converted signals.

[0020] Figure 2 shows the schematic of a unit pixel included in the pixel array 140 shown in Figure 1. As shown in Figure 2, one unit pixel may include a first pixel TAPA and a second pixel TAPB pair.

[0021] The first pixel TAPA can generate a first pixel signal VPX_A based on a reset signal RX, a transmission signal TX, a selection signal SX, and a first phase signal MIXA. At this time, the reset signal RX, the transmission signal TX, and the selection signal SX can be signals included in the plurality of low signals ROWs described above. As shown in FIG. 2, the first pixel TAPA can include a first sensing circuit P1, a first reset circuit RT1, a first transmission circuit TT1, a first charge storage circuit C1, a first drive circuit DT1, and a first selection circuit ST1.

[0022] The first sensing circuit P1 can be connected between a first node N1 and a low voltage terminal. The first sensing circuit P1 can generate a first charge corresponding to a third optical signal RS’ in response to the first phase signal MIXA. For example, the first sensing circuit P1 can include a photodiode. The photodiode can receive the third optical signal RS’, convert it into a first digital signal related to the first charge, and provide the converted first digital signal to the first node N1.

[0023] The first reset circuit RT1 can be connected between a high voltage terminal and the first node N1. The first reset circuit RT1 can reset the first sensing circuit P1 and the first charge storage circuit C1 in response to the reset signal RX. For example, the first reset circuit RT1 can include an NMOS transistor.

[0024] The first transfer circuit TT1 can be connected between the first node N1 and the first floating diffusion node FD1. The first transfer circuit TT1 can reset the first charge storage circuit C1 in response to a transfer signal TX and transfer the first charge generated from the first sensing circuit P1 to the first charge storage circuit C1. According to an embodiment of the present invention, the first transfer circuit TT1 can reset the first charge storage circuit C1 in response to a transfer signal TX during the readout interval of the first pixel TAPA. For example, the first transfer circuit TT1 may comprise an NMOS transistor.

[0025] The first charge storage circuit C1 can be connected between the first floating diffusion node FD1 and the low-voltage terminal. As described above, the first charge storage circuit C1 can be reset by the first transfer circuit TT1 during the readout interval of the first pixel TAPA. For example, the first charge storage circuit C1 may include a parasitic capacitor and / or a capacitor added between the low-voltage terminal and the first floating diffusion node FD1.

[0026] The first drive circuit DT1 can be connected between the high-voltage terminal and the first selection circuit ST1. The first drive circuit DT1 can drive the first column line COL1 with a high voltage supplied through the high-voltage terminal based on the voltage applied to the first floating diffusion node FD1. For example, the first drive circuit DT1 may comprise an NMOS transistor.

[0027] The first selection circuit ST1 can be connected between the first drive circuit DT1 and the first column line COL1. The first selection circuit ST1 can selectively connect the first drive circuit DT1 and the first column line COL1 in response to a selection signal SX. For example, the first selection circuit ST1 may include an NMOS transistor.

[0028] The second pixel TAPB can generate a second pixel signal VPX_B based on a reset signal RX, a transfer signal TX, a selection signal SX, and a second phase signal MIXB. As shown in Figure 2, the second pixel TAPB may include a second sensing circuit P2, a second reset circuit RT2, a second transfer circuit TT2, a second charge storage circuit C2, a second drive circuit DT2, and a second selection circuit ST2.

[0029] A second sensing circuit P2 can be connected between the second node N2 and the low-voltage terminal. The second sensing circuit P2 can generate a second charge corresponding to the third optical signal RS' in response to the second phase signal MIXB. For example, the second sensing circuit P2 may include a photodiode. The photodiode can receive the third optical signal RS', convert it into a second digital signal associated with the second charge, and provide the converted second digital signal to the second node N2.

[0030] A second reset circuit RT2 can be connected between the high-voltage terminal and the second node N2. The second reset circuit RT2 can reset the second sensing circuit P2 and the second charge storage circuit C2 in response to a reset signal RX. For example, the second reset circuit RT2 may comprise an NMOS transistor.

[0031] A second transfer circuit TT2 can be connected between a second node N2 and a second floating diffusion node FD2. The second transfer circuit TT2 can reset a second charge storage circuit C2 in response to a transfer signal TX and transfer the second charge generated from the second sensing circuit P2 to the second charge storage circuit C2. According to an embodiment of the present invention, during the readout interval of the second pixel TAPB, the second transfer circuit TT1 can reset the second charge storage circuit C2 in response to a transfer signal TX. For example, the second transfer circuit TT2 may comprise an NMOS transistor.

[0032] A second charge storage circuit C2 can be connected between the second floating diffusion node FD2 and the low-voltage terminal. As previously mentioned, the second charge storage circuit C2 can be reset by the second transfer circuit TT2 during the readout interval of the second pixel TAPB. For example, the second charge storage circuit C2 may include a parasitic capacitor.

[0033] A second drive circuit DT2 can be connected between the high-voltage terminal and the second selection circuit ST2. The second drive circuit DT2 can drive the second column line COL2 with a high voltage supplied via the high-voltage terminal, based on the voltage applied to the second floating diffusion node FD2. For example, the second drive circuit DT2 may comprise an NMOS transistor.

[0034] A second selection circuit ST2 can be connected between the second drive circuit DT2 and the second column line COL2. The second selection circuit ST2 can selectively connect the first drive circuit DT2 and the second column line COL2 in response to a selection signal SX. For example, the second selection circuit ST2 may include an NMOS transistor.

[0035] Figure 3 shows a block diagram of an example of the signal converter 150 shown in Figure 1.

[0036] The signal converter 150 can generate a first count signal CNT1 and a second count signal CNT2 corresponding to the voltage level difference between the first pixel signal VPX_A and the second pixel signal VPX_B and the ramp signal VRAMP. The signal converter 150 may include the same configuration for processing the first pixel signal VPX_A and the second pixel signal VPX_B, and Figure 3 illustrates only a configuration that processes one of the first pixel signal VPX_A and the second pixel signal VPX_B as a representative example.

[0037] As shown in Figure 3, the signal converter 150 may include first and second input units C3 and C4, first and second switching units SW1 and SW2, a comparison unit 310, and a counting unit 320. For example, although not shown in Figure 3, the signal converter 150 may further include a logic unit that calculates the difference between a first count signal CNT1 and a second count signal CNT2 and outputs the difference in count values ​​as a distance information signal DOUT.

[0038] The first input unit C3 can receive a first pixel signal VPX_A (or a second pixel signal VPX_B) and generate an input signal VIN_A or VIN_B. For example, the first input unit C3 may include a capacitor that samples the first pixel signal VPX_A (or VPX_B) to generate an input signal VIN_A or VIN_B.

[0039] The second input section C4 can receive the ramp signal VRAMP and generate a reference signal VREF. For example, the second input section C4 may include a capacitor that samples the ramp signal VRAMP to generate the reference signal VREF.

[0040] The comparison unit 310 compares the input signal VIN_A or VIN_B with the reference signal VREF and can output the comparison signal VOUTP_A or VOUTP_B. The comparison unit 310 can maintain the comparison signal VOUTP_A or VOUTP_B at a logic high or low level until the voltage level of the reference signal VREF becomes the same as that of the input signal VIN_A or VIN_B.

[0041] The first and second switching units SW1 and SW2 can be connected between the input and output nodes of the comparison unit 310. In response to a switch signal SW, the first and second switching units SW1 and SW2 can selectively connect between the input and output nodes of the comparison unit 310. When the switch signal SW changes, the first and second switching units SW1 and SW2 are turned on, and the input and output nodes of the comparison unit 310 can be connected.

[0042] The counting unit 320 can count the clock signal CLK in response to the comparison signal VOUTP_A or VOUTP_B and output a count signal CNT1 or CNT2. The counting unit 320 can output a count signal CNT1 or CNT2 having a count value corresponding to the interval in which the logic level of the comparison signal VOUTP_A or VOUTP_B is maintained.

[0043] Figure 4 shows a timing diagram illustrating the operation of the image sensing device 100 shown in Figure 1.

[0044] As shown in Figure 4, the first and second pixels TAPA and TAPB can perform a reset operation during the RESET interval in response to the reset signal RX and the transmission signal TX. That is, when the reset signal RX is activated, the first sensing circuit P1 of the first pixel TAPA and the second sensing circuit P2 of the second pixel TAPB can be reset. Also, in response to the activation of the reset signal RX and the transmission signal TX, the first charge storage circuit C1 of the first pixel TAPA and the second charge storage circuit C2 of the second pixel TAPB can be reset.

[0045] Next, during the exposure period, the first and second pixels TAPA and TAPB can generate, transmit, and store first and second charges based on the third optical signal RS', the transmission signal TX, and the first and second phase signals MIXA and MIXB. For example, the first sensing circuit P1 can generate a first charge based on the third optical signal RS' and the first phase signal MIXA. If the first transmission circuit TT1 of the first pixel TAPA transmits the first charge in response to the transmission signal TX, the first charge storage circuit C1 can store the first charge. Similarly, the second sensing circuit P2 can generate a second charge based on the third optical signal RS' and the second phase signal MIXB. If the second transmission circuit TT2 of the second pixel TAPB transmits the second charge in response to the transmission signal TX, the second charge storage circuit C2 can store the second charge. In this case, the first phase signal MIXA and the second phase signal MIXB can have a phase difference of 180 degrees.

[0046] During the READOUT section of the first and second pixel TAPA and TATB, the reset signal RX and the selection signal SX may be activated to a logic high level. In response to the selection signal SX, the first and second pixel TAPA and TATB can read out the first and second pixel signals VPX_A and VPX_B, which correspond to the first and second charges stored in the first and second charge storage circuits C1 and C2.

[0047] For example, in the first pixel TAPA, the first selection circuit ST1 can electrically connect the first drive circuit DT1 and the first column line COL1 in response to the activation of the selection signal SX. The first drive circuit DT1 can read out the first pixel signal VPX_A by driving the first column line COL1 with a high voltage based on the voltage applied to the first floating spread node FD1.

[0048] Similarly, in the second pixel TAPB, the second selection circuit ST2 can electrically connect the second drive circuit DT2 and the second column line COL2 in response to the activation of the selection signal SX. The second drive circuit DT2 can read out the second pixel signal VPX_B by driving the second column line COL2 with a high voltage due to the voltage applied to the second floating spread node FD2.

[0049] In an embodiment of the present invention, the switch signal SW can transition between a logic low level and a logic high level at the beginning of the readout section READOUT. The control signal generation unit 134 of the signal controller 130 activates the selection signal SX in the readout section READOUT, and once the selection signal SX is activated, the switch signal SW can transition between a logic low level and a logic high level.

[0050] The signal converter 150 can be initialized in response to a transition of the switch signal SW. That is, the first and second switching units SW1 and SW2 are turned on in response to a transition of the switch signal SW, and the input and output nodes of the comparison unit 310 can be linked. As a result, the offset voltage between the read-out first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP can be stored in the first and second input units C3 and C4. Therefore, the initialization operation of the signal converter 150 can include an auto-zeroing operation that cancels out the input offset voltage of the comparison unit 310.

[0051] After the switch signal SW is transitioned, the control signal generation unit 134 of the signal controller 130 can activate the transmission signal TX. If the transmission signal TX is activated while the reset signal RX is at a logic high level in the readout section READOUT, the first and second pixel signals VPX_A and VPX_B can be reset. That is, the first and second reset circuits RT1 and RT2 and the first and second transmission circuits TT1 and TT2 can initialize the first and second charge storage circuits C1 and C2 in response to the activated reset signal RX and transmission signal TX. Therefore, the first and second pixel signals VPX_A and VPX_B, i.e., the input signals VIN_A and VIN_B, can rise by the amount of the reset voltage change ΔVPX_A and ΔVPX_B.

[0052] After the transmission signal TX is activated, the ramp signal generation unit 136 of the signal controller 130 can generate a ramp signal VRAMP that gradually increases from low voltage to high voltage. The voltage level of the reference signal VREF can also increase in proportion to the ramp signal VRAMP. Therefore, the comparison unit 310 can compare the input signals VIN_A, VIN_B and the reference signal VREF and maintain the comparison signals VOUTP_A and VOUTP_B at a logic high or logic low level until the voltage level of the reference signal VREF becomes the same as that of the input signals VIN_A and VIN_B.

[0053] In other words, the counting unit 320 counts the clock signal CLK from the point when the reference signal VREF ramps until the point when the logic levels of the comparison signals VOUTP_A and VOUTP_B change, and can generate first and second count signals CNT1 and CNT2 corresponding to the voltage changes △VPX_A and △VPX_B, respectively. The signal converter 150 calculates the first and second count signals CNT1 and CNT2 and can output a distance information signal DOUT corresponding to the difference between the first and second charges generated by the first and second pixels TAPA and TATB.

[0054] Figure 5 is a sequence diagram showing the operation of an image sensing device according to an embodiment of the present invention.

[0055] In step S510, the unit pixels of the pixel array 140 can read out the first and second pixel signals VPX_A and VPX_B in response to the selection signal SX. In the readout section READOUT, the control signal generation unit 134 of the signal controller 130 can activate the selection signal SX to a logic high level. Once the selection signal SX is activated, the first and second pixels TAPA and TATB can read out the first and second pixel signals VPX_A and VPX_B corresponding to the first and second charges stored in the first and second charge storage circuits C1 and C2.

[0056] In step S520, the signal converter 150 can set the offset voltage between the read-out first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP. After the selection signal SX is activated to a logic high level in the readout section READOUT, the control signal generation unit 134 can transition the switch signal SW between a logic low level and a logic high level. In response to the transition of the switch signal SW, the switching units SW1 and SW2 of the signal converter 150 are turned on, and the offset voltage between the read-out first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP can be stored in the first and second input units C3 and C4.

[0057] In step S530, the unit pixels of the pixel array 140 can reset the first and second pixel signals VPX_A and VPX_B in response to the selection signal TX. After the switch signal SW is switched, the control signal generation unit 134 can activate the transmission signal TX to a logic high level. When the transmission signal TX is activated, the first and second pixels TAPA and TATB initialize the first and second charge storage circuits C1 and C2, and the first and second pixel signals VPX_A and VPX_B can be reset.

[0058] In step S540, the signal converter 150 can generate a distance information signal DOUT corresponding to the voltage change ΔVPX_A, ΔVPX_B difference of the first and second pixel signals VPX_A, VPX_B, which have been reset in response to the ramp signal VRAMP. When the transmission signal TX is activated, the ramp signal generation unit 136 of the signal controller 130 can gradually increase the ramp signal VRAMP from a low voltage to a high voltage.

[0059] The signal converter 150 can compare the rising ramp signal VRAMP with the reset first pixel signal VPX_A and generate a first count signal CNT1 corresponding to the voltage change ΔVPX_A. The signal converter 150 can also compare the rising ramp signal VRAMP with the reset second pixel signal VPX_B and generate a second count signal CNT2 corresponding to the voltage change ΔVPX_B. The signal converter 150 can calculate the first count signal CNT1 and the second count signal CNT2 and generate a distance information signal DOUT corresponding to the difference between the voltage changes ΔVPX_A and ΔVPX_B.

[0060] While the technical concept of the present invention has been specifically described by the preferred embodiments described above, it should be noted that the embodiments described above are for illustrative purposes only and not to limit them. Furthermore, a person of ordinary skill in the art of the present invention will understand that various embodiments are possible through various substitutions, modifications, and changes without departing from the technical concept of the present invention. [Explanation of Symbols]

[0061] 100 Image Sensing Devices 200 subjects 110 Optical Transmitter 120 Optical Receiver 130 Signal controller 132 Phase signal generation section 134 Control signal generation unit 136 Lamp signal generation unit 140 pixel array 150 Signal Converters 310 Comparison Section 320 Counting Section

Claims

1. a pixel array including unit pixels that transfer and accumulate charges in response to a transfer signal, and that read out pixel signals including a first pixel signal and a second pixel signal corresponding to the accumulated charges in response to a selection signal provided to the unit pixels; a signal converter for comparing the pixel signal and the ramp signal based on a switch signal to generate a distance information signal; a signal controller for generating the switch signal during a temporary period for reading out the pixel signal to initialize the signal converter; Equipped with An image sensing device, wherein the distance information signal is generated by comparing the first pixel signal and the second pixel signal with the ramp signal.

2. 2. The image sensing device of claim 1, wherein the signal controller generates the selection signal that is activated during the temporary period for reading out the pixel signal, and when the selection signal is activated, transitions the switch signal between a first logic level and a second logic level.

3. The signal converter includes: a first input section for receiving the pixel signal and generating an input signal; a second input for receiving the ramp signal and generating a reference signal; a comparison unit that compares the input signal with the reference signal and outputs a comparison signal; a switching unit for selectively connecting an input node and an output node of the comparison unit in response to the switch signal; a counting unit that counts clock signals in response to the comparison signal; The image sensing device of claim 2 .

4. 4. The image sensing device of claim 3, wherein the switching unit is turned on in response to a transition of the switch signal to connect the input node and the output node of the comparison unit.

5. 3. The image sensing device of claim 2, wherein the signal controller generates the transfer signal that is activated when the switch signal transitions, and the unit pixel resets the pixel signal in response to the activated transfer signal.

6. The unit pixel is a charge storage circuit for storing the charge; a reset circuit for resetting the charge storage circuit in response to a reset signal; a transfer circuit that transfers the charge to the charge storage circuit in response to the transfer signal; a selection circuit that generates the pixel signal corresponding to the charge stored in the charge storage circuit in response to the selection signal; The image sensing device according to claim 5 .

7. The image sensing device of claim 6 , wherein the signal controller generates the reset signal that is activated simultaneously with the selection signal during a period in which the pixel signal is read out.

8. 8. The image sensing device of claim 7, wherein the reset circuit and the transfer circuit initialize the charge storage circuit in response to the activated reset signal and the activated transfer signal, respectively.

9. The image sensing device of claim 5 , wherein the signal controller generates the ramp signal that gradually rises from a low voltage to a high voltage when the transfer signal is activated.

10. The unit pixel is a first pixel that generates a first charge in response to a light signal and a first phase signal, and generates a first pixel signal corresponding to the first charge in response to the selection signal; a second pixel generating a second charge in response to the optical signal and a second phase signal, and generating a second pixel signal corresponding to the second charge in response to the selection signal; 2. The image sensing device of claim 1, comprising:

11. The signal converter includes: a first signal conversion unit that generates a first count signal corresponding to a voltage level difference between the first pixel signal and the ramp signal; a second comparator that generates a second count signal corresponding to a voltage level difference between the second pixel signal and the ramp signal; a logic operation unit that performs an operation on the first count signal and the second count signal and outputs a difference between the count values ​​as the distance information signal; The image sensing device of claim 10 .

12. The image sensing device of claim 10 , wherein the first and second phase signals have a phase difference of 180 degrees.

13. reading out first and second pixel signals corresponding to the first and second charges stored in the unit pixel in response to a selection signal; setting an offset voltage between the read out first and second pixel signals and a ramp signal in response to a switch signal; resetting the first and second pixel signals in response to a transfer signal; generating a distance information signal corresponding to a voltage change difference between the reset first and second pixel signals in response to the ramp signal; A method of operating an image sensing device comprising:

14. 14. The method of claim 13, wherein the selection signal is activated during a period in which the first and second pixel signals are read out, and when the selection signal is activated, a switch signal transitions between a first logic level and a second logic level.

15. The method of claim 14 , wherein the transfer signal is activated when the switch signal transitions.

16. 16. The method of claim 15, wherein the ramp signal gradually rises from a low voltage to a high voltage when the transfer signal is activated.

17. The step of generating the distance information signal in response to the ramp signal includes: comparing the ramp signal with the reset first pixel signal to generate a first count signal corresponding to a voltage change of the reset first pixel signal; comparing the ramp signal with the reset second pixel signal to generate a second count signal corresponding to a voltage change of the reset second pixel signal; calculating the first count signal and the second count signal to generate the distance information signal; 14. A method of operating an image sensing device according to claim 13, comprising:

18. A method for operating an image sensing device including a pixel array having a unit pixel including a first pixel and a second pixel, comprising: accumulating a first charge at the first pixel based on a first photodiode output; accumulating a second charge at the second pixel based on a second photodiode output; reading out a first pixel signal from the first pixel corresponding to the first charge; reading out a second pixel signal from the second pixel corresponding to the second charge; comparing the first pixel signal and the second pixel signal with a ramp signal to generate a distance information signal corresponding to a voltage change; Including, A method of operating an image sensing device, wherein the first charge is accumulated a) based on a reflected signal returning from a subject to the image sensing device and b) in response to a first phase signal that is the same phase as an optical signal output from the image sensing device, and the second charge is accumulated a) based on the reflected signal and b) in response to a second phase signal that is different phase from the optical signal output from the image sensing device.

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