Image sensor

Abstract

To provide an image sensor that increases the size of a gate electrode and simultaneously minimizes cross-talk between pixels.SOLUTION: An image sensor 500 comprises: a substrate 1 having a first surface 1a and a second surface 1b opposite to the first surface, the substrate comprising a first pixel and a second pixel adjacent to the first pixel: a deep device isolation portion DTI disposed in the substrate and isolating the first pixel and the second pixel from each other: a transfer gate disposed on the first surface; a ground region disposed selectively in one of the first pixel and the second pixel; and a first color filter CF1 and a micro lens array layer ML sequentially stacked on the second surface. The deep device isolation portion includes a first isolation portion 20 and a second isolation portion 30 which vertically overlap with each other and are separated from each other. The first isolation portion includes a conductive pattern 24 extending from the first surface toward the second surface; a high-concentration doped pattern 26 on the conductive pattern; and a liner insulating pattern 25 between the conductive pattern and the high-concentration doped pattern.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Recently, with the development of the computer and communication industries, there is an increasing demand for image sensors with improved performance in various fields such as digital cameras, video cameras, personal communication systems (PCS), game machines, security cameras, and medical micro cameras. Image sensors can be classified into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CMOS type image sensors are abbreviated as CMOS image sensors (CIS). The CIS has a plurality of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal. The pixels are defined by deep isolation patterns arranged between them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,868,070B2 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENT One technical problem to be solved by the present invention is to provide an image sensor structure and manufacturing method that can increase the size of gate electrodes while minimizing cross talk between pixels.

[0005] Another technical problem to be solved by the present invention is to provide an image sensor that can be easily highly integrated and a method for manufacturing the same. [Means for solving the problem]

[0006] According to an embodiment of the present invention, there is provided an image sensor comprising: a substrate having a first surface and an opposite second surface, the substrate including a first pixel and a second pixel adjacent to the first pixel; a deep device isolation portion disposed within the substrate and isolating the first pixel and the second pixel; a transfer gate disposed on the first surface of each of the first pixel and the second pixel; a ground region selectively disposed in one of the first pixel and the second pixel; and a first color filter and a microlens array layer sequentially stacked on the second surface, the deep device isolation portion including a first isolation portion and a second isolation portion vertically overlapping each other and spaced apart from each other, the first isolation portion including a first conductive pattern extending from the first surface to the second surface, a heavily doped pattern provided in the substrate on the first conductive pattern, and an insulating pattern between the first conductive pattern and the heavily doped pattern, the ground region and the heavily doped pattern being doped with impurities having the same conductivity type.

[0007] According to some embodiments, an image sensor includes a substrate having a first surface and an opposite second surface, the substrate including a first pixel group, a second pixel group, and a pair of third pixel groups, the first pixel group, and the second pixel group being two-dimensionally arranged along a first direction parallel to the first surface of the substrate and a second direction parallel to the first surface and intersecting the first direction, a first color filter being disposed on the first pixel group, a second color filter being disposed on the second pixel group, and a third color filter being disposed on each of the pair of third pixel groups, the first pixel group, the second pixel group, and the third pixel group being arranged in an NxN array along the first and second directions. 2 pixels, 2 a deep device isolation portion is provided in the substrate between the pixels and between the first, second, and third pixel groups, the deep device isolation portion including a first isolation portion extending from the first surface toward the second surface and a second isolation portion extending from the second surface toward the first surface, the first isolation portion being disposed between the N 2 a first separation pattern provided between the N pixel groups and a second separation pattern provided between the first, second and third pixel groups, 2 pixels and a fourth isolation pattern provided between the first, second, and third pixel groups, the first isolation pattern and the third isolation pattern being aligned in a vertical direction and spaced apart from each other, the second isolation pattern and the fourth isolation pattern being aligned in a vertical direction, any one of the first, second, and fourth pixels selectively including a ground region, the first isolation portion including a first conductive pattern extending from the first surface to the second surface, a heavily doped pattern on the first conductive pattern, and an insulating pattern between the first conductive pattern and the heavily doped pattern, and N may be a natural number of 2 or more.

[0008] According to some embodiments, an image sensor includes a substrate having a first surface and an opposite second surface, the substrate including a first pixel and a second pixel adjacent to the first pixel; a deep device isolation portion disposed within the substrate and isolating the first pixel and the second pixel; a transmission gate disposed on the first surface of each of the first pixel and the second pixel; a ground region selectively disposed in one of the first pixel and the second pixel; and a color filter and a microlens array layer sequentially stacked on the second surface, the deep device isolation portion including a first isolation portion and a second isolation portion vertically overlapping each other and spaced apart from each other, the first isolation portion including a first conductive pattern extending from the first surface to the second surface, a heavily doped pattern on the first conductive pattern, and an insulating pattern between the first conductive pattern and the heavily doped pattern, the heavily doped pattern being continuous between the first pixel and the second pixel. Effect of the Invention

[0009] According to the concept of the present invention, each pixel group can share a ground region. When four pixels form one pixel group, the ground region can be selectively provided to one pixel among the four pixels. The deep device isolation portion isolating the pixels can include first and second isolation patterns vertically overlapping and spaced apart from each other. Even in the pixel not provided with the ground region, positive charges can be transferred through the high concentration doping pattern of the first isolation pattern. As a result, even if three pixels do not have a ground region, positive charges can be discharged through the ground region through the first isolation pattern. Also, since the remaining three pixels do not require a ground region, the area of ​​the gate electrode constituting the image sensor can be increased instead. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention; [Diagram 2]1 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a plan view of an image sensor according to an embodiment of the present invention. [Figure 4] FIG. 4 is a plan view of the image sensor corresponding to FIG. 3. [Figure 5A] FIG. 5 is a cross-sectional view taken along line AA' of FIG. 4 in accordance with an embodiment of the present invention. [Figure 5B] FIG. 5 is a cross-sectional view taken along line BB' of FIG. 4 in accordance with an embodiment of the present invention. [Figure 5C] FIG. 5 is a cross-sectional view taken along line BB' of FIG. 4 in accordance with an embodiment of the present invention. [Figure 6] FIG. 5B is an enlarged view of U' in FIG. 5A. [Figure 7] FIG. 2 is a plan view of an image sensor according to some embodiments of the invention. [Figure 8A] FIG. 8 is a cross-sectional view taken along line AA' of FIG. 7 in accordance with an embodiment of the present invention. [Figure 8B] FIG. 8 is a cross-sectional view taken along line BB' of FIG. 7 in accordance with an embodiment of the present invention. [Figure 9] FIG. 2 is a plan view of an image sensor according to some embodiments. [Figure 10A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 10B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 11A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 11B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 12A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 12B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 13A]5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 13B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 14A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 14B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 15A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 15B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 16A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 16B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 17A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 17B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 18A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 18B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 19A] 5B is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5A. [Figure 19B] 5C is a cross-sectional view sequentially illustrating a process for manufacturing the image sensor of FIG. 5B. [Figure 20] FIG. 2 is a plan view of an image sensor according to some embodiments of the invention. [Figure 21] 21 is a cross-sectional view taken along line II' in FIG. 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically explain the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0012] FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention.

[0013] Referring to FIG. 1, the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog to digital converter (ADC) 1007, and an input / output buffer 1008.

[0014] The active pixel sensor array 1001 includes a plurality of unit pixels arranged two-dimensionally, and can convert an optical signal into an electrical signal. The active pixel sensor array 1001 can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 1003. The converted electrical signal can be provided to a correlated double sampler 1006.

[0015] The row driver 1003 can provide a number of driving signals to the active pixel sensor array 1001 for driving a number of unit pixels according to the result decoded by the row decoder 1002. When the unit pixels are arranged in a matrix, a driving signal can be provided for each row.

[0016] A timing generator 1005 may provide timing and control signals to the row decoder 1002 and the column decoder 1004 .

[0017] The correlated double sampler (CDS) 1006 may receive, hold, and sample an electrical signal generated by the active pixel sensor array 1001. The correlated double sampler 1006 may double sample a specific noise level and a signal level according to an electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

[0018] An analog-to-digital converter (ADC) 1007 can convert an analog signal corresponding to the difference level output from the correlated double sampler 1006 into a digital signal and output the digital signal.

[0019] The input / output buffer 1008 latches digital signals, and the latched signals can be sequentially output to a video signal processor (not shown) according to the results of decoding by the column decoder 1004 .

[0020] 2 is a circuit diagram of an image sensor according to an embodiment of the present invention. Specifically, it is a circuit diagram of the active pixel sensor array 1001 of FIG. 1. Referring to FIG. 2, each of a plurality of pixel groups (for example, GRP1: first pixel group) may include first to fourth photoelectric conversion units PD1, PD2, PD3, PD4, first to fourth transfer transistors TX1, TX2, TX3, TX4, and logic transistors RX, SX, DX. Here, the logic transistor may include a reset transistor RX, a selection transistor SX, and a drive transistor DX. Gate electrodes of the first to fourth transfer transistors TX1, TX2, TX3, TX4, the reset transistor RX, and the selection transistor SX may be connected to drive signal lines TG1, TG2, TG3, TG4, RG, and SG, respectively.

[0021] The first to fourth transfer transistors TX1, TX2, TX3, and TX4 may include first to fourth gate electrodes TG1, TG2, TG3, and TG4 and first to fourth photoelectric conversion units PD1, PD2, PD3, and PD4, respectively. According to an embodiment, the first to fourth transfer transistors TX1, TX2, TX3, and TX4 may each be connected to a floating diffusion region FD.

[0022] A plurality of floating diffusion regions FD each connected to the transfer transistors TX1, TX2, TX3, and TX4 may be provided in a pixel group (e.g., GRP1). According to another example, one floating diffusion region FD may be formed in one pixel group (e.g., GRP1). The transfer transistors TX1, TX2, TX3, and TX4 in one pixel group (e.g., GRP1) may share one floating diffusion region FD.

[0023] The first to fourth photoelectric conversion units PD1, PD2, PD3, and PD4 may generate and accumulate photocharges in proportion to the amount of light incident from the outside. The first to fourth photoelectric conversion units PD1, PD2, PD3, and PD4 may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0024] The floating diffusion region FD may transmit and cumulatively store charges generated in the first to fourth photoelectric conversion units PD1, PD2, PD3, and PD4, and may control the drive transistor DX according to the amount of photocharges stored in the floating diffusion region FD.

[0025] The reset transistor RX can periodically reset the charge stored in the floating diffusion region FD. In particular, the drain electrode of the reset transistor RX can be connected to the floating diffusion region FD, and the source electrode can be connected to a power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX can be transferred to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge stored in the floating diffusion region FD can be discharged, and the floating diffusion region FD can be reset.

[0026] The drive transistor DX amplifies a potential change in the floating diffusion region FD and outputs an amplified pixel signal to an output line VOUT through the selection transistor SX. The drive transistor DX may be a source follower buffer amplifier that generates a source-drain current in proportion to the amount of photocharge input to the gate electrode. The gate electrode of the drive transistor DX may be connected to the floating diffusion region FD, the drain of the drive transistor DX may be connected to a power supply voltage VDD, and the source of the drive transistor DX may be connected to the drain of the selection transistor SX.

[0027] The selection transistor SX can select a pixel to be read out on a row-by-row basis. When the selection transistor SX is turned on, a power supply voltage VDD connected to a drain electrode of the drive transistor DX can be transferred to the drain electrode of the selection transistor SX.

[0028] FIG. 3 shows a plan view of an image sensor according to an embodiment of the present invention.

[0029] Referring to FIG. 3, the image sensor 500 according to the present embodiment may include first to third pixel groups GRP1, GRP2, and GRP3 arranged two-dimensionally along a first direction D1 and a second direction D2. A first color filter CF1 may be arranged on the first pixel group GRP1. A second color filter may be arranged on the second pixel group GRP2. A third color filter may be arranged on the third pixel group GRP3. The first to third color filters may have different colors. For example, the second color filter may be green. One of the first color filter and the third color filter may be red and the other may be blue. The arrangement of the first to third pixel groups GRP1, GRP2, and GRP3 in FIG. 3 forms one group unit, and may be provided in a plurality of group units and arranged two-dimensionally along the first direction D1 and the second direction D2.

[0030] The first, second and third pixel groups GRP1, GRP2 and GRP3 each have N rows and N columns in the second direction D2 and the first direction D1, respectively. 2 pixels, where N can be a natural number equal to or greater than 2.

[0031] As an example, as shown in FIG. 3, the first to third pixel groups GRP1, GRP2, and GRP3 may each include first to fourth pixels PX1 to PX4 arranged in a 2x2 array, which are arranged in two rows along the second direction D2 and two columns along the first direction D1. In the first to third pixel groups GRP1, GRP2, and GRP3, the first and second pixels PX1 and PX2 may be sequentially arranged along the second direction D2 to form a first column. The third and fourth pixels PX3 and PX4 may be sequentially arranged along the second direction D2 to form a second column. The first and third pixels PX1 and PX3 may be sequentially arranged along the first direction D1 to form a first row. The second and fourth pixels PX2 and PX4 may be sequentially arranged along the first direction D1 to form a second row. A photoelectric conversion unit PD may be disposed in each of the first to fourth pixels PX1 to PX4. The photoelectric conversion units PD of the first to fourth pixels PX1 to PX4 may correspond to the photoelectric conversion units PD in FIGS. 5A to 5C, respectively.

[0032] A microlens array layer ML may be disposed on each of the first to fourth pixels PX1 to PX4. Deep isolation parts DTI may be interposed in the substrate 1 between the first to fourth pixels PX1 to PX4 and between the first to third pixel groups GRP1, GRP2, and GRP3.

[0033] Figure 4 shows a plan view of an image sensor corresponding to Figure 3. Figure 5A is a cross-sectional view taken along line A-A' of Figure 4 in accordance with an embodiment of the present invention. Figure 5B is a cross-sectional view taken along line B-B' of Figure 4 in accordance with an embodiment of the present invention. Figure 5C is a cross-sectional view taken along line C-C' of Figure 4 in accordance with an embodiment of the present invention. Figure 6 is an enlarged view of U' of Figure 5A.

[0034] 4, 5A, 5B, and 5C, an image sensor 500 according to an embodiment of the present invention includes a substrate 1. The substrate 1 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. The substrate 1 may be doped with impurities of a first conductivity type. For example, the first conductivity type may be P-type. The substrate 1 includes a first surface 1a and a second surface 1b that are opposite to each other. The substrate 1 includes an active pixel sensor array 1001 as shown in FIG. 1, and the first to fourth pixels PX1 to PX4 of FIG. 3 may each correspond to a unit pixel UP.

[0035] In the pixel, a deep device isolation part DTI is disposed on the substrate 1 to isolate / define the unit pixel UP. The deep device isolation part DTI may have a net shape in a plane.

[0036] In the unit pixel UP, a photoelectric conversion unit PD may be disposed in the substrate 1. The photoelectric conversion unit PD may be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, N type. The N type impurities doped in the photoelectric conversion unit PD may form a PN junction with P type impurities doped in the surrounding substrate 1 to provide a photodiode.

[0037] A shallow isolation portion STI adjacent to the first surface 1a may be disposed in the substrate 1. The shallow isolation portion STI may be penetrated by the deep isolation portion DTI. The shallow isolation portion STI may define an active area ACT adjacent to the first surface 1a in each unit pixel UP. The active area ACT may be provided for the transistors TX, RX, DX, and SX of FIG. 2.

[0038] A transfer gate TG may be disposed on the first surface 1a of the substrate 1 in each unit pixel UP. A portion of the transfer gate TG may extend into the substrate 1. The transfer gate TG may be a vertical type. Alternatively, the transfer gate TG may not extend into the substrate 1 and may be a planar type having a flat shape. A gate insulating film Gox may be interposed between the transfer gate TG and the substrate 1. A floating diffusion region FD may be disposed in the substrate 1 on one side of the transfer gate TG. The floating diffusion region FD may be doped with impurities of, for example, the second conductive type (for example, N-type).

[0039] The image sensor 500 may be a rear light receiving image sensor. Light may be incident into the substrate 1 through the second surface 1b of the substrate 1. Electron-hole pairs may be generated at the PN junction by the incident light. The generated electrons may be transferred to the photoelectric conversion unit PD. When a voltage is applied to the transmission gate TG, the electrons may be transferred to the floating diffusion region FD.

[0040] In one unit pixel (first unit pixel) UP, a ground region GND may be provided adjacent to the transmission gate TG on the first surface 1a. The ground region GND may have the same conductivity type as the substrate 1. The ground region GND may be a region doped with impurities of the first conductivity type. In another unit pixel (second unit pixel) UP, a reset gate RG may be provided adjacent to the transmission gate TG. In another unit pixel (third unit pixel) UP, a source follower gate SF may be provided adjacent to the transmission gate TG on the first surface 1a. In another unit pixel (fourth unit pixel) UP, a selection gate SEL may be provided adjacent to the transmission gate TG. The gates TG, RG, SF, and SEL may correspond to the gates of the transistors TX, RX, DX, and SX of FIG. 2, respectively. A source / drain region SD may be provided based on each gate of the reset gate RG, the source follower gate SF, and the selection gate SEL. The ground region GND and the gates TG, RG, SF, and SEL may overlap with the active region ACT. The first to fourth unit pixels UP may form a pixel group (eg, GRP1, GRP2, GRP3).

[0041] The first surface 1a may be covered with a first interlayer insulating film IL. The first interlayer insulating film IL may be formed of a multi-layer film of at least one film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous low dielectric film. Wirings 15 may be disposed between or within the first interlayer insulating film IL. The ground region GND may be electrically connected to a corresponding wiring 15 among the contact plugs 17 and the wirings 15. The contact plugs 17 may pass through the first interlayer insulating film IL that is the closest (lowest layer) to the first surface 1a among the first interlayer insulating films IL. A ground voltage may be applied to the substrate 1 through the corresponding wiring 15 and the ground region GND. The ground region GND may be disposed adjacent to the deep device isolation part DTI. The layout shape of the ground region GND may be various. For example, (outside 1) TIFF2023044647000002.tif7170. The floating diffusion region FD may be electrically connected to a corresponding one of the contact plugs 17 and the wiring 15.

[0042] The deep device isolation portion DTI may include a first isolation portion 20 and a second isolation portion 30. The first isolation portion 20 may include a first isolation pattern 201 and a second isolation pattern 202. The second isolation portion 30 may include a third isolation pattern 301 and a fourth isolation pattern 302. The first isolation portion 20 may extend from the first surface 1a toward the second surface 1b. The second isolation portion 30 may extend from the second surface 1b toward the first surface 1a.

[0043] The first separation part 20 may include a first separation pattern 201 and a second separation pattern 202. The first separation pattern 201 may be provided between two adjacent unit pixels UP in each of the pixel groups GRP1, GRP2, and GRP3. The second separation pattern 202 may be provided between the pixel groups GRP1, GRP2, and GRP3.

[0044] A width 201d of the first separation pattern 201 in the first direction D1 may be smaller than a width 202d of the second separation pattern 202 in the first direction D1. The first separation pattern 201 may extend less from the first surface 1a toward the second surface 1b than the second separation pattern 202. The length of the first separation pattern 201 may be shorter than the length of the second separation pattern 202. The lengths of the first separation pattern 201 and the second separation pattern 202 refer to the length from the first surface 1a of the substrate 1 in a third direction D3 perpendicular to the first surface 1a.

[0045] The second separation unit 30 may include a third separation pattern 301 and a fourth separation pattern 302. The third separation pattern 301 may be provided between two adjacent unit pixels UP in each of the pixel groups GRP1, GRP2, and GRP3. The fourth separation pattern 302 may be provided between the pixel groups GRP1, GRP2, and GRP3.

[0046] The first and third separated patterns 201 and 301 may be vertically overlapped (or aligned) and spaced apart from each other. A distance ΔD between the first and third separated patterns 201 and 301 may be 100 nm to 300 nm (see FIG. 6 ). The second and fourth separated patterns 202 and 302 may be vertically overlapped (or aligned) and contact each other.

[0047] The first isolation portion 20 may include a buried insulating pattern 22, a conductive pattern 24, a liner insulating pattern 25, and a highly doped pattern 26. The buried insulating pattern 22 may be disposed on the interlayer insulating layer IL. The conductive pattern 24 may be provided on the buried insulating pattern 22 and may be separated from the interlayer insulating layer IL via the buried insulating pattern 22. A liner insulating pattern 25 may be interposed between the conductive pattern 24 and the substrate 1, and between the buried insulating pattern 22 and the device isolation portion STI.

[0048] The buried insulating pattern 22 and / or the liner insulating pattern 25 may include, for example, silicon oxide. The conductive pattern 24 may be separated from the substrate 1. The conductive pattern 24 may include a polysilicon film or a silicon germanium film doped with impurities. The impurities doped into the polysilicon or silicon germanium film may be, for example, one of boron, phosphorus, and arsenic.

[0049] The buried insulating pattern 22, the conductive pattern 24, and the liner insulating pattern 25 may fill the first deep trench 9 and the second trench 10. The heavily doped pattern 26 may be formed on the inner wall regions of the first deep trench 9 and the second trench 10. The heavily doped pattern 26 may be a region of the substrate 1 doped with impurities of a first conductivity type. The heavily doped pattern 26 has an impurity concentration higher than the impurity concentration of the substrate 1, for example, 1×10 17 / cm 3 ~1x10 19 / cm 3 The concentration of

[0050] The second separator 30 may include a first fixed charge layer 34 and an insulating pattern 36. The first fixed charge layer 34 may be a single layer or a multi-layer of a metal oxide layer or a metal fluoride layer containing oxygen or fluorine in an amount less than the stoichiometric ratio. Therefore, the first fixed charge layer may have a negative fixed charge. The first fixed charge layer 34 may be a single layer or a multi-layer of a metal oxide or a metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. As a specific example, the first fixed charge layer 34 may include a hafnium oxide layer and / or an aluminum oxide layer. The first fixed charge layer 34 may improve dark current and white spots. An insulating pattern 36 may be provided on the first fixed charge layer 34. The insulating pattern may include a silicon oxide layer.

[0051] The first fixed charge layer 34 may contact the surface of the substrate 1. The first fixed charge layer 34 may cover a trench formed in the second surface 1b of the substrate 1. The first fixed charge layer 34 may contact the liner insulating pattern 25 and / or the conductive pattern 24 of the second isolated pattern 202. The heavily doped patterns 26 of the second isolated pattern 202 may not be connected by the first fixed charge layer 34. On the contrary, the heavily doped patterns 26 of the first isolated pattern 201 may be continuous between adjacent unit pixels UP.

[0052] 5B, a first distance between two adjacent unit pixels UP in a pixel group (e.g., GRP1) and an upper surface of the first separation pattern 201 from the second surface 1b may be greater than a second distance between four adjacent unit pixels UP in a pixel group (e.g., GRP1, GRP2, GRP3) and an upper surface of the first separation pattern in a location CN1 where four adjacent unit pixels UP are adjacent to each other. Also, a bottom level of the second surface 1b in a location CN2 where four adjacent unit pixels UP in adjacent pixel groups (e.g., GRP1, GRP2) are adjacent to each other may be lower than the level of the upper surface of the second separation pattern 202.

[0053] According to the concept of the present invention, each of the pixel groups (e.g., GRP1, GRP2, GRP3) can share the ground region GND. For example, when four pixels form one pixel group as shown in FIG. 3 and FIG. 4, the ground region GND can be selectively provided to one pixel (e.g., PX2) among the four pixels. Since the first isolation pattern 201 and the third isolation pattern 301 do not contact each other, even if there are pixels (e.g., PX1, PX3, PX4) to which the ground region GND is not provided, positive charges can be transferred to the pixel (e.g., PX2) to which the ground region GND is provided through the continuous high concentration doping pattern 26 of the first isolation pattern 201 (see FIG. 6). As a result, even if the three pixels do not have the ground region GND, the positive charges can be discharged through the ground region GND through the first isolation pattern 201. Also, since the remaining three pixels do not need the ground region GND, the areas of the gate electrodes TG, RG, SEL, and SF can be increased. As an example, the area on the plane occupied by the transmission gate TG may be 10% or more of the unit pixel area.

[0054] According to another concept of the present invention, the second separation pattern 202 and the fourth separation pattern 302 contact each other between pixel groups, so that the received light cannot move to other pixel groups (see FIG. 6), thereby preventing crosstalk between adjacent pixels sharing color filters of different colors.

[0055] A first protective layer 44 may be provided on the second surface 1b. According to some embodiments, a second fixed charge layer may be interposed between the first protective layer 44 and the insulating pattern 36. The second fixed charge layer may include a single layer or multiple layers of a metal oxide layer or a metal fluoride layer. The second fixed charge layer may include, for example, a hafnium oxide layer and / or an aluminum oxide layer. The second fixed charge layer may reinforce the first fixed charge layer 34 or function as an adhesive layer. The first protective layer 44 may be made of a material such as PETEOS, SiOC, SiO 2, SiN. The first protective film 44 can function as an anti-reflection film and / or a planarization film.

[0056] A light-shielding pattern 48a and a low refraction pattern 50a may be sequentially stacked on the first protective layer 44. The light-shielding pattern 48a and the low refraction pattern 50a may have a net shape in a plan view and may overlap the deep device isolation portion DTI. The light-shielding pattern 48a may include, for example, titanium. The low refraction pattern 50a may include an organic material. The low refraction pattern 50a may have a refractive index smaller than that of the color filters CF1, CF2, and CF3. For example, the low refraction pattern 50a may have a refractive index of about 1.3 or less. A sidewall of the low refraction pattern 50a may be aligned with a sidewall of the light-shielding pattern 48a. The light-shielding pattern 48a and the low refraction pattern 50a may prevent crosstalk between adjacent pixels.

[0057] A second protective layer 56 is stacked on the first protective layer 44. The second protective layer 45 may conformally cover the low refraction pattern 50a, the light blocking pattern 48a, and the connecting contact BCA. Color filters CF1, CF2, and CF3 may be disposed between the low refraction patterns 50a. A microlens array layer ML may be disposed on the color filters CF1, CF2, and CF3. The microlens array layer ML may include convex lens portions overlapping the unit pixels UP, respectively.

[0058] Fig. 7 is a plan view of an image sensor according to some embodiments of the present invention. Fig. 8A is a cross-sectional view taken along line A-A' in Fig. 7 according to an embodiment of the present invention. Fig. 8B is a cross-sectional view taken along line B-B' in Fig. 7 according to an embodiment of the present invention. Except as otherwise described below, the same description has been given with reference to Figs. 4 to 6, and therefore will not be repeated.

[0059] 7, 8A, and 8B, a width 202d of the second separated pattern 202 in the first direction D1 may be substantially equal to a width 201d of the first separated pattern 201 in the first direction D1. The second separated pattern 202 may extend from the first surface 1a toward the second surface 1b to substantially the same depth as the first separated pattern 201. That is, the length of the second separated pattern 202 may be substantially equal to the length of the first separated pattern 201.

[0060] The first and third isolated patterns 201 and 301 may be vertically overlapped (or aligned) and spaced apart from each other. The second and fourth isolated patterns 202 and 302 may be vertically overlapped (or aligned) and spaced apart from each other.

[0061] 8B, the bottom level of the second surface 1b at CN2 where four adjacent unit pixels UP between adjacent pixel groups (e.g., GRP1 and GRP2) are adjacent at the same time may be located above the level of the top surface of the second isolated pattern 202. Therefore, the heavily doped pattern 26 of the first isolated pattern 201 and the heavily doped pattern 26 of the second isolated pattern 202 may be connected to each other.

[0062] That is, according to one aspect of the present invention, even if a pixel in the first pixel group GRP1 is not provided with the ground region GND, positive charges can be transferred to the ground region GND of the second pixel group GRP2 through the heavily doped pattern 26 of the first isolation pattern 201 and the continuous heavily doped pattern 26 of the second isolation pattern 202. As described above, as the number of pixels sharing the ground region GND increases, the areas of the gate electrodes TG, RG, SEL, and SF of the sharing pixels can increase.

[0063] FIG. 9 illustrates a top view of an image sensor according to some embodiments.

[0064] Referring to FIG. 9, the first to third pixel groups GRP1, GRP2, and GRP3 may each include first to ninth pixels PX1 to PX9 arranged in a 3x3 array having three rows along the second direction D2 and three columns along the first direction D1.

[0065] The image sensor 510 according to some embodiments may also include structural features of sharing a ground region GND within the same pixel group and a deep device isolation layer DTI, as described with reference to FIGS.

[0066] According to some embodiments, the first to third pixel groups GRP1, GRP2, GRP3 may each include 1st to 16th pixels in a 4x4 array having four rows along the second direction D2 and four columns along the first direction D1.

[0067] Figures 10A to 19A are cross-sectional views sequentially showing a process of manufacturing the image sensor of Figure 4A, and correspond to A-A' of Figure 4A. Figures 10B to 19B are cross-sectional views sequentially showing a process of manufacturing the image sensor of Figure 4B, and correspond to B-B' of Figure 4B.

[0068] 10A and 10B, a substrate 1 is prepared. A first trench 5 is formed on the substrate 1 by performing an etching process using a first etching mask 3.

[0069] 11A and 11B, a first insulating film 8 is formed to cover the second surface 1b of the substrate 1. The first insulating film 8 may fill the first trench 5. The first insulating film 8 may include, for example, a silicon oxide film. Then, a first deep trench 9 and a second deep trench 10 may be formed penetrating the first trench 5. The first deep trench 9 and the second deep trench 10 may include forming a second mask pattern and etching the first insulating film 8 and the substrate 1 using the second mask pattern. The first deep trench 9 and the second deep trench 10 may be formed in a net shape with intersecting grooves. A width 9D in a first direction D1 may be smaller than a width 10D of the second deep trench 10 in the first direction D1. A depth 9H of the first deep trench 9 may be smaller than a depth 10H of the second deep trench 10 (loading effect).

[0070] At this time, the amount of etching of the substrate 1 between four adjacent pixels UP may be greater than the amount of etching of the substrate 1 between two adjacent pixels UP. That is, the amount of etching of the substrate 1 may be greater at a point 9a where a pair of first deep trenches 9 intersect and a point 10a where a second deep trench 10 intersects with the first deep trench 9 or the second deep trench 10. The amount of etching H2 of the substrate 1 at a point 10a where a second deep trench 10 intersects with the first deep trench 9 or the second deep trench 10 may be greater than the amount of etching H1 at a point 9a where a pair of first deep trenches 9 intersect (loading effect).

[0071] 12A and 12B, a first conductive type (e.g., p-type) impurity may be implanted into a portion of the semiconductor substrate 1 through a plasma doping (PLAD) process P1 toward a second surface 1b of the substrate 1. For example, the first conductive type impurity may be boron. As a result of the plasma doping process P1, a doping pattern 26 may be formed on the inner walls of the first deep trench 9 and the second deep trench 10.

[0072] 13A and 13B, a liner insulating film 25a and a conductive film 24a may be formed to fill the first deep trench 9 and the second deep trench 10. As an example, the liner insulating film 25a may include a silicon oxide film, and the conductive film 24a may include polysilicon doped with impurities of a first conductivity type (e.g., p-type).

[0073] 14A and 14B, a portion of the conductive layer 24a may be removed. The process of removing the conductive layer 24a may include an etch-back process. The conductive pattern 24 may be formed by the etch-back process. Then, a second insulating layer 22a may be formed on the liner insulating layer 25a. The second insulating layer 22a may include a silicon oxide layer.

[0074] 15A and 15B, a planarization process may be performed on the second surface 1b of the substrate 1. A portion of the second insulating film 22a may be removed to form a shallow device isolation portion STI and a buried insulating pattern 22. A portion of the liner insulating film 25a may be removed to form a liner insulating pattern 25. An active region may be defined by the shallow device isolation portion STI.

[0075] 16A and 16B, a photoelectric conversion unit PD is formed on a substrate 1 by performing an ion implantation process, etc., and thus a unit pixel UP can be separated. Then, a gate insulating film Gox, a transfer gate TG, a floating diffusion region FD, a contact plug 17, a wiring 15, and an interlayer insulating film IL can be formed on a first surface 1a of the substrate 1 by performing a general process.

[0076] 17A and 17B, the substrate 1 is turned over so that the second surface 1b faces upward. A grinding or chemical mechanical polishing (CMP) process may be performed to reduce the thickness of the substrate 1. The grinding or CMP process may be performed so that the highly doped pattern 26 is not exposed. According to some embodiments, this process may be omitted.

[0077] 18A and 18B, a third etching mask pattern may be formed on the second surface 1b of the substrate 1. The third etching mask pattern may be formed to have an opening overlapping the first isolation pattern 201 and the second isolation pattern 202. The substrate 1 may be etched using the third etching mask pattern as an etching mask to form a third trench 11 and a fourth trench 12. The third trench 11 may be formed such that a bottom surface of the third trench 11 is separated from a top surface of the first isolation pattern 201. The fourth trench 12 may be formed such that a bottom surface of the fourth trench 12 exposes a top surface of the second isolation pattern 202. The level of the bottom surface of the fourth trench 12 may be lower than the level of the bottom surface of the third trench 11. According to some embodiments, the bottom surface of the fourth trench 12 may not expose a top surface of the second isolation pattern 202 (see FIG. 8A).

[0078] At this time, the amount of etching of the substrate 1 between four adjacent pixels UP may be greater than the amount of etching of the substrate 1 between two adjacent pixels UP. That is, the amount of etching of the substrate 1 may be greater at a point where a pair of third trenches 11 intersect and at a point where the fourth trench 12 intersects with the third trench 11 or the fourth trench 12.

[0079] Then, the third etching mask pattern may be removed. Then, a first fixed charge film 34 may be conformally stacked on the second surface 1b. The first fixed charge film 34 may conformally cover the inner wall and bottom of the third trench 11 and the inner wall and bottom of the fourth trench 12. An insulating pattern 36 may be formed on the first fixed charge film 34 to fill the third trench 11 and the fourth trench 12.

[0080] 19A and 19B, a second fixed charge layer (not shown) and a first protective layer 44 are sequentially stacked. A diffusion barrier layer and a first metal layer are sequentially stacked on the first protective layer 44. The first metal layer is etched to form a low refraction pattern 50a. Then, the diffusion barrier layer is etched to form a light-shielding pattern 48a.

[0081] 5A and 5B, a second protective layer 56 may be conformally formed on the first protective layer 44. Then, color filters CF1, CF2, and CF3 may be formed between the low refraction patterns 50a on the second protective layer 56. A microlens array layer ML is formed on the color filters CF1, CF2, and CF3. Thus, the image sensor 500 of FIGS. 5A and 5B may be manufactured.

[0082] FIG. 20 is a plan view of an image sensor according to some embodiments of the present invention, and FIG. 21 is a cross-sectional view taken along line II' of FIG.

[0083] 20 and 21, the image sensor 700 may include a substrate 1 including a pixel array region AR, an optical black region OB, and a pad region PR, a wiring layer 200 on a first surface 100a of the substrate 1, a base substrate 400 on the wiring layer 200, and a light-transmitting layer 300 on a second surface 1b of the substrate 1. The wiring layer 200 may be disposed between the first surface 1a of the substrate 1 and the base substrate 400. The wiring layer 200 may include an upper wiring layer 210 adjacent to the first surface 1a of the substrate 1, and a lower wiring layer 230 between the upper wiring layer 210 and the base substrate 400. The pixel array region AR may include a plurality of pixels PX and deep isolation parts DTI disposed therebetween. The deep isolation parts DTI may be configured substantially similarly to the image sensors 500 and 600 described above.

[0084] A first connection structure 50, a first contact 81, and a bulk color filter 90 may be disposed on the optical black area OB of the substrate 1. The first connection structure 50 may include a first light-shielding pattern 51, a first low-refractive residual film 53, and a first capping pattern 55. The first light-shielding pattern 51 may be disposed on the second surface 1b of the substrate 1. The first light-shielding pattern 51 may cover the first passivation film 44 and conformally cover the inner walls of the first trench TRA and the second trench TRB. The first light-shielding pattern 51 may penetrate the substrate 1 and the upper wiring layer 210. The first light-shielding pattern 51 may be connected to the first isolation portion 20 of the deep device isolation portion DTI of the substrate 1, and may be connected to wiring in the upper wiring layer 210 and the lower wiring layer 230. Therefore, the first connection structure 50 may electrically connect the substrate 1 and the wiring layer 200. The first light-blocking pattern 51 may include a metal material (for example, tungsten) and may block light incident into the optical black area OB.

[0085] The first contact 81 may fill the remainder of the first trench TRA. The first contact 81 may include a metal material (for example, aluminum). The first contact 81 may be connected to the first isolation portion 20 of the deep device isolation portion DTI. A bias may be applied to the first isolation portion 20 through the first contact 81. The first low refraction residual film 53 may fill the remainder of the second trench TRB. The first low refraction residual film 53 may penetrate the substrate 1 and may penetrate a portion of the wiring layer 200. The first low refraction residual film 53 may include an insulating material. The first capping pattern 55 may be disposed on the first low refraction residual film 53. The first capping pattern 55 may include the same material as the buried insulating pattern 22 of the deep device isolation portion DTI.

[0086] The bulk color filter 90 may be disposed on the first connecting structure 50 and the first contact 81. The bulk color filter 90 may cover the first connecting structure 50 and the first contact 81. A first passivation layer 71 may be provided on the bulk color filter 90 to cover the bulk color filter 90.

[0087] An additional photoelectric conversion unit PD' and a dummy region 111 may be provided in a corresponding pixel PX of the optical black region OB. The additional photoelectric conversion unit PD' may be a region doped with impurities of a second conductivity type (e.g., N-type impurities) different from the first conductivity type of the substrate 100. The additional photoelectric conversion unit PD' may have a similar structure to the photoelectric conversion unit PD in the plurality of pixels PX of the pixel array region AR, but may not perform the same operation as the photoelectric conversion unit PD (i.e., an operation of receiving light and generating an electrical signal). The dummy region 111 may not be doped with impurities.

[0088] A second connecting structure 60, a second contact 83, and a second passivation film 73 may be disposed on the pad region PR of the substrate 100. The second connecting structure 60 may include a second light blocking pattern 61, a second low refractive residual film 63, and a second capping pattern 65.

[0089] The second light-shielding pattern 61 may be disposed on the second surface 1b of the substrate 1. The second light-shielding pattern 61 may cover the first passivation film 44 and conformally cover the inner walls of the third trench TRC and the fourth trench TRD. The second light-shielding pattern 61 may penetrate the substrate 1 and the upper wiring layer 210. The second light-shielding pattern 61 may be connected to a wiring in the lower wiring layer 230. Therefore, the second connection structure 60 may electrically connect the substrate 1 and the wiring layer 200. The second light-shielding pattern 61 may include a metal material, tungsten (W). The second light-shielding pattern 61 may block light incident into the pad region PR.

[0090] The second contact 83 may fill the remainder of the third trench TRC. The second contact 83 may include a metal material (for example, aluminum). The second pad terminal 83 may serve as an electrical connection path between the image sensor and an external device. The second low refraction residual film 63 may fill the remainder of the fourth trench TRD. The second low refraction residual film 63 may penetrate the substrate 1 and may penetrate a portion of the wiring layer 200. The second low refraction residual film 63 may include an insulating material. The second capping pattern 65 may be disposed on the second low refraction residual film 63. The second capping pattern 65 may include the same material as the buried insulating pattern 22 of the deep device isolation part DTI. The second passivation film 73 may cover the second connection structure 60.

[0091] A current applied through the second contact 83 may flow to the first isolation portion 20 of the deep device isolation portion DTI through the second light-shielding pattern 61, the wiring in the wiring layer 200, and the first light-shielding pattern 51. An electrical signal generated from the photoelectric conversion unit PD in the plurality of pixels PX of the pixel array region AR may be transmitted to the outside through the wiring in the wiring layer 200, the second light-shielding pattern 61, and the second contact 83.

[0092] Although the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0093] 15 Wiring 17 Contact plug 20 1st separation section 30 Second separation section 500 Image Sensor ACT active region CF1, CF2, CF3 color filters DTI Deep Isolation FD Floating diffusion region GND ground area IL Interlayer insulating film ML Microlens Array Layer PD Photoelectric conversion unit PX1~PX4 pixels STI Shallow isolation TG Transmission Gate UP unit pixel

Claims

1. a substrate having a first surface and a second surface opposite the first surface; a first pixel group including first four photoelectric conversion units (PDs) arranged in a 2×2 matrix; a second pixel group including a second four PDs arranged in a 2x2 matrix; a first color filter on the first pixel group; a second color filter on the second pixel group; a first ground region provided on the first surface and shared by the first pixel group; a second ground region provided on the first surface and shared by the second pixel group; a first isolated pattern extending from the second surface toward the first surface and disposed between the first four PDs; a second isolation pattern extending from the first surface toward the second surface and disposed between the second four PDs; a third separation pattern extending from the second surface toward the first surface and disposed between the first pixel group and the second pixel group; a fourth separation pattern extending from the first surface toward the second surface and disposed between the first pixel group and the second pixel group; a microlens array laminated on the second surface, the first separated pattern vertically overlaps the second separated pattern and is spaced apart from the second separated pattern in a first direction perpendicular to the first surface; the first color filter is different from the second color filter; the first pixel group is directly adjacent to the second pixel group in the second direction; The image sensor, wherein the second isolation pattern includes a filled insulating pattern extending in the first direction from the level of the first surface of the substrate.

2. An image sensor as described in claim 1, wherein the first separation pattern has a first length in the first direction, and the second separation pattern has a second length longer than the first length.

3. further comprising a light-shielding pattern between the first pixel group and the second pixel group; The image sensor of claim 2 , wherein each of the first pixel group and the second pixel group does not include a light blocking pattern.

4. The first grounding region is selectively disposed under one of the first four PDs; The image sensor of claim 2 , wherein the second ground region is selectively disposed under one of the second four PDs.

5. further comprising a contact plug connected to the first ground region; The image sensor of claim 2 , wherein the contact plug vertically overlaps the first ground region in the first direction.

6. An image sensor as described in claim 5, further comprising a shallow element isolation portion between the first ground region and the second isolation pattern.

7. a substrate having a first surface and a second surface opposite the first surface; a first pixel group and a second pixel group, each of which includes N 2 pixels arranged in an N×N matrix in a plan view, and which are formed along a first direction and a second direction perpendicular to the first direction, where "N" is a natural number equal to or greater than 2; a first color filter on the first pixel group; a second color filter on the second pixel group; a first ground region provided on the first surface and shared by the N 2 pixels in the first pixel group; a second ground region provided on the first surface and shared by the N 2 pixels in the second pixel group; a first separation pattern extending from the second surface toward the first surface and disposed between the N 2 pixels in the first pixel group; a second separation pattern extending from the first surface toward the second surface and disposed between the N 2 pixels in the first pixel group; a third separation pattern extending from the second surface toward the first surface and disposed between the first pixel group and the second pixel group; a fourth separation pattern extending from the first surface toward the second surface and disposed between the first pixel group and the second pixel group; a microlens array laminated on the second surface, the first separated pattern overlaps the second separated pattern perpendicularly and is spaced apart from the second separated pattern in a third direction perpendicular to the first surface; the first color filter is different from the second color filter; the first pixel group is directly adjacent to the second pixel group in the first direction in a plan view, The image sensor, wherein the second isolation pattern includes a filled insulating pattern extending in the first direction from the level of the first surface of the substrate.

8. The first separation pattern has a first length in the third direction, and the second separation pattern has a second length in the third direction; The image sensor of claim 7 , wherein the second length is greater than the first length.

9. The image sensor of claim 8, wherein the first ground region is selectively positioned at one pixel among the N 2 pixels in the first pixel group.

10. The image sensor of claim 8, wherein each of the first and second pixel groups includes N 2 microlenses.

Images