Integrated radar signal processing circuit

Abstract

To provide radar system signal processing that can react quickly.SOLUTION: An integrated radar signal processing circuit includes: a signal processing unit to generate a radar map represented by a field with a first index and a second index; a peak detection unit to identify potential targets in the radar map; and a hardware accelerator. The peak detection unit includes first and second peak detection units that respectively scan the radar map along the first and second indices and store, in a radar data memory, first and second detection bitmaps that identify peaks as functions of the first and second indices. The first and second detection bitmaps identify each peak using a single bit. The hardware accelerator is connected to the radar data memory, and processes individual bits of the first and second detection bitmaps.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] Embodiments generally relate to integrated radar signal processing circuits. [Background technology]

[0002] The results of radar detection can be represented in the form of a bitmap. Each entry in such a bitmap is referenced by two index values ​​(e.g., a distance index value and a Doppler index (or velocity index) value) and indicates whether a target has been detected in the direction, by the distance, or using the velocity value corresponding to the two indexes. For example, the first index is a distance index, the second index is a velocity index, and the bitmap value indicates, for each combination of the distance index and velocity index values, whether a target has been detected at a distance corresponding to the distance index value and at a velocity corresponding to the velocity index value. Another possible combination is distance and direction, and velocity and direction. Processing such a bitmap bit by bit is generally required for subsequent processing (e.g., direction determination, grouping detected targets into objects, etc.). An efficient approach for such processing is desirable to calculate rapid results of radar processing, for example, to enable rapid reaction when using radar systems in autonomous vehicles to avoid accidents. Summary of the Invention [Means for solving the problem]

[0003] According to one embodiment, an integrated radar signal processing circuit is provided, the integrated radar signal processing circuit including: a signal processing unit configured to generate a radar map represented by a field having a first index and a second index; and a peak detection unit configured to identify potential targets in the radar map, the peak detection unit including a first peak detection unit configured to scan the radar map along the first index and store in a radar data memory a first detection bitmap that identifies peaks as a function of the first index; and a second peak detection subunit configured to scan the radar map along the second index and output to the radar data memory a second detection bitmap that identifies peaks as a function of the second index, the first detection bitmap and the second detection bitmap using individual bits to identify their respective peaks, and the integrated radar signal processing circuit further includes a hardware accelerator connected to the radar data memory, the hardware accelerator being a bit-wise hardware accelerator configured to process individual bits of the first detection bitmap and the second detection bitmap.

[0004] The drawings are not drawn to scale and are used to illustrate the basic concepts of the various embodiments. The various embodiments are described below with reference to the following drawings: [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a diagram illustrating a radar device. [Figure 2] FIG. 1 is a diagram illustrating an FMCW (Frequency Modulated Continuous Wave) radar system. [Figure 3] FIG. 1 illustrates processing of a data cube. [Figure 4] FIG. 1 is a diagram illustrating an example of radar detection using three transmission channels. [Figure 5] FIG. 2 illustrates a hardware accelerator for processing bitmaps according to one embodiment. [Figure 6] FIG. 1 illustrates an integrated radar signal processing circuit according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] The following detailed description refers to the accompanying drawings, in which details and examples are shown. These examples are described in detail to enable those skilled in the art to practice the invention. Alternative embodiments are possible, and the examples can be modified in structural, logical, and electrical respects without departing from the subject matter of the invention. The various examples are not necessarily mutually exclusive, and the various examples can be combined with one another to yield new embodiments. Within the framework of this specification, the terms "coupled," "connected," and "coupled" are used to describe both direct and indirect coupling, direct or indirect connections, and direct or indirect couplings.

[0007] FIG. 1 shows a radar device 100.

[0008] The radar apparatus 100 has a radar system 101 that includes an antenna arrangement 102 and a radar device 103. The radar device 103 includes one or more (radar) transmitters 104, a duplexer 105 (i.e., circuitry for separating transmitted and received signals), a (radar) receiver 106, and a controller 107. The radar apparatus, shown as a key in this figure, may include multiple transmitting antennas in the form of a transmitting antenna array and multiple receiving antennas in the form of a receiving antenna array, and may be located, for example, on a vehicle.

[0009] To identify the object 108, the controller 107 controls one or more transmitters 104, duplexer 105, and receiver 106 as follows: 1. A transmitted signal 109 is received by one or more transmitters 104 via an antenna arrangement 102. 2. The transmitted signal 109 is reflected by a target. 3. The radar system 101 receives an echo 110 of the transmitted signal as a received signal.

[0010] From the received signals, information about the position and velocity of the object 108 is calculated by the radar device 103 (eg, integrated radar signal processing circuitry 111).

[0011] 1, the radar system 101 is shown as a (large) stationary device detecting large objects 108, such as the vehicle shown, but the radar system 101 may also be mobile, smaller, and used to detect smaller objects. For example, the radar device may be mounted on a vehicle to detect nearby objects, particularly for autonomous driving.

[0012] The transmitted signal 109 may include multiple pulses. Pulsed transmission involves transmitting short bursts at high power combined with time for the radar system 101 to wait for echoes 110. This is generally not optimal for highly dynamic situations such as those in vehicular scenarios.

[0013] Therefore, a continuous waveform can be used as the transmitted signal instead. Since a continuous waveform only allows velocity determination but does not provide distance information (due to the lack of a timestamp that would allow distance calculation), one approach is frequency modulated continuous wave radar (FWCM).

[0014] FIG. 2 shows an FMCW radar system 200.

[0015] In an FMCW radar system, the frequency of the transmit signal is not transmitted at a constant frequency, but is periodically increased and reset in response to a sawtooth waveform (or alternatively a triangular waveform) 201. The sawtooth waveform 201 modulates the frequency of an oscillator 202, and the resulting transmit signal is fed to a transmit antenna 203.

[0016] An echo of the transmitted signal (in addition to noise, etc.) is received as a received signal by a receiving antenna 204. The transmitted signal and the received signal are mixed by a mixer 205. The mixed result is filtered by a low-pass filter 206 and processed by a spectrum analyzer 207.

[0017] The transmitted signal has the shape of a train of chirps obtained by modulating a sinusoid with a sawtooth waveform 201. The individual chirps 208 correspond to the sinusoid of the oscillator signal that has been frequency modulated by the "teeth" of the sawtooth waveform 201 from a minimum frequency to a maximum frequency.

[0018] The spectrum analyzer 207 (e.g., implemented by the radar signal processing circuit 111) implements (at least) two FFT (Fast Fourier Transform) stages to extract distance information (through a first FFT stage) and velocity information (through a second FFT stage) from the received signal. The second FFT stage can also extract angle information, or a third FFT stage can be provided to extract angle information. In this embodiment, where a range-Doppler map is generated, velocity information is extracted by the second FFT stage. It should be noted that because the spectrum analyzer 207 operates on digital scan values, an analog-to-digital converter (A / D) is included in the path from the receive antenna 204 to the spectrum analyzer 207. For example, the filter 206 is an analog filter, and an analog-to-digital converter (ADC) is located between the filter 206 and the spectrum analyzer 207.

[0019] Furthermore, the antenna arrangement 102 may include multiple receive antennas, i.e., an array of receive antennas, to enable the determination of the direction of the object 108 relative to the radar system 101. In this case, the direction of the object 108 can be determined from the phase difference with which the echoes 110 from the object are received by these receive antennas. Correspondingly, the radar receiver may include a mixer 205, an analog filter 206, and an ADC for each receive antenna.

[0020] The digitized received signals for all receive antennas are generally collected in a so-called data cube.

[0021] FIG. 3 illustrates the processing of a data cube 300.

[0022] Data cube 300 contains digital scan values ​​of received signals from M antennas forming receive antenna array 303. The digital scan values ​​are generated by an analog-to-digital converter.

[0023] For example, for each chirp (eg, K=64 chirps), the received signal is scanned so that it has L scan values ​​(eg, L=512).

[0024] The L scan values ​​collected for each chirp are processed by a first FFT stage.

[0025] The processing of the first FFT stage is performed for each chirp and each antenna, so that the result of the processing of the data cube 300 becomes three-dimensional again by the first FFT stage and can have the size of the data cube 300, but now contains values ​​for L range bins (Bin) rather than values ​​for L scan time points. It should be noted that in the actual received signal of the first FFT stage, typically only range bins 0 to L / 2 are valid, because the spectrum of the first FFT reflects L / 2 and the latter part can be discarded.

[0026] The results of processing the data cube 300 by the first FFT stage are then processed along the chirp (for each antenna and for each range bin) by a second FFT stage.

[0027] The direction of the first stage FFT is called fast time, while the direction of the second stage FFT is called slow time (direction of chirp).

[0028] The result of the second stage FFT yields a range-Doppler map for each antenna, which, when collected across antennas (e.g., using NCI (non-coherent integration) or CI (coherent integration) to improve signal-to-noise ratio and have a high probability of discrimination), yields range-Doppler map 301. Range-Doppler map 301 contains the FFT output value for each combination of range bin and Doppler bin, i.e., a field with a range index and a Doppler index.

[0029] For a particular combination of range bin and Doppler bin (i.e., for a particular range bin / Doppler bin), the range-Doppler map 301 has an FFT peak 302 (i.e., a peak in the FFT output value (i.e., a peak value in terms of absolute value)).

[0030] Peak detection is applied to the range-Doppler map 301, generally in two dimensions (range and Doppler), to identify FFT peaks 302. That is, the range-Doppler map 301 (having row and column FFT output values ​​for range / Doppler bins) is searched for a maximum value in the column direction (here, range) and a maximum value in the row direction (here, velocity) (observing the absolute value of the FFT output values).

[0031] For each dimension, the result is a respective detection bitmap 304, 305, i.e. a field of bits, which contains a 1 if, for each range / Doppler bin (identified by the range index value and the Doppler index value), a maximum is found during detection in the direction of the respective dimension, and a 0 otherwise. Thus, a 1 indicates a potential target.

[0032] The two detection bitmaps 304, 305 are then logically combined (e.g., logically ANDed, i.e., combined; other logical combinations (OR, XOR, etc.) are also possible) into a ("final" or "combined") detection bitmap 306.

[0033] It should be noted that the data (i.e., range-Doppler maps) must be fully populated before detection in two dimensions (2D detection) can be performed. Furthermore, 2D detection (also called 2D filtering) is expensive in terms of area cost and energy consumption. Nevertheless, it is generally desirable to perform detection in two dimensions.

[0034] Further post-processing is typically required to extract additional data from the range-Doppler map (e.g., FFT points adjacent to a peak, e.g., a lower peak).

[0035] Subsequent processing of the bitmaps 304, 305, or even the final bitmap 306, requires different computationally expensive operations, especially bit-by-bit operations that are expensive to implement using a CPU or DSP (included in the radar device 103) and thus can significantly increase the delay of the radar processing.

[0036] For example, bitmaps 304 and 305 generally have different orientations, so one of bitmaps 304 and 305 must be transposed in order to be able to logically combine them into final bitmap 306.

[0037] Another example of costly bit-by-bit processing is the extraction of the index of the final bitmap 306, i.e., the determination of the range bin index value (i.e., the range index value) and the Doppler (or velocity) bin index value (i.e., the Doppler index value) for each peak represented (by each 1) by the final bitmap 306. This is necessary, in particular, for radar post-processing operations such as clustering peaks into objects, and calculating object velocity and distance.

[0038] Correspondingly, there is a cost involved in extracting the address (absolute system address) of the FFT output value belonging to the peak in physical memory, which is required, for example, to determine the orientation of the detected object.

[0039] Additional bit-wise processing is required in Doppler Division Multiplexing (DDM) MIMO (Multiple Input Multiple Output) radar systems. In such systems, each peak in the final bitmap 306 occurs multiple times, once per transmission channel at a fixed Doppler shift. Therefore, the final bitmap 306 must be rotated for each transmission channel (according to the respective Doppler shift), and the results must be logically combined (ANDed) bit-wise.

[0040] An example with three transmission channels is shown in FIG.

[0041] The transmission channel is realized by successive chirps of the transmission channel having different phase shifts (eg, according to Binary Phase Shift Keying (BPSK), Quadrature PSK (QPSK) or mPSK modulation).

[0042] In the example of Figure 4, consecutive chirps 401 (here indicated by the teeth of the frequency modulated signal) of the first transmit channel (TX1) have no phase shift from each other, consecutive chirps 402 of the second transmit channel (TX2) have a phase shift of 90° from each other, and consecutive chirps 403 of the third transmit channel (TX3) have a phase shift of 180° from each other.

[0043] The final bitmap 404 now contains information for all three transmission channels.

[0044] To combine this information, the final bitmap 404 and rotated versions 405, 406 of itself are logically combined.

[0045] In the example of FIG. 4, rotated versions 405, 406 are generated by row rotation (ie, each row belongs to the same Doppler bin in the diagram of FIG. 4).

[0046] The bitwise operations mentioned above (transposing bitmaps, combining bitmaps, and in particular combining rotated bitmaps for transmission modulation, index value extraction, and address extraction) can be performed by a CPU (or DSP) that retrieves the bitmaps from a memory stored by, for example, a signal processing unit (SPU) that generates the bitmaps described above. For this purpose, the CPU (or DSP) executes corresponding software.

[0047] However, performing the above bit-by-bit operations is quite expensive as explained above.

[0048] For example, if the bitmap has 256 rows (for Doppler bins) and 128 columns (for distance bins) and the CPU processes 8-bit words, each 8 bits is packed into one word (e.g., 128 columns into 16 columns of 8-bit words). Extracting the index in this case requires three For loops (one loop for the distance index, another loop for the bit position within the 8-bit word, and yet another loop for the Doppler index), and depending on the bit position, the 8-bit word must be shifted and / or masked accordingly.

[0049] To transpose, the CPU must take each bit from each 8-bit value (e.g., by logical AND for shifting and masking) and write it into a new 8-bit value (e.g., by logical OR for shifting and combining with the new 8-bit word).

[0050] To combine two bitmaps, the CPU must iterate over all (e.g., 256 x 16) 8-bit value locations, read two 8-bit values ​​at each location, perform a bitwise logical combination of these, and write the resulting 8-bit value back to memory.

[0051] According to various embodiments, a hardware accelerator is provided for bit-wise processing of (detection) bitmaps, i.e., for operations such as those described above. The hardware accelerator is configured to process bits of the bitmaps individually, i.e., the hardware accelerator can access individual bits (for processing) without accessing or needing to access adjacent bits in the respective bitmaps. For example, the hardware accelerator can process bits individually from a bitstream into which the bits of the bitmaps are transferred (e.g., from a memory) for processing. This allows the hardware accelerator, according to various embodiments, to efficiently perform bit-wise operations on the bitmaps, i.e., operations such as those described above.

[0052] The hardware accelerator may be tightly coupled to the SPU that generates the bitmap, but it can also operate as an independent unit ("standalone"), e.g., it can read data from memory and store results there by itself. For example, the hardware accelerator is located between the SPU and the CPU in the processing pipeline. The hardware accelerator and the SPU are implemented, for example, by the integrated radar signal processing circuit 111. The hardware accelerator can store the results of its processing in a (radar data) memory (e.g., the radar device 103), so that the CPU (radar device 103) can access the corresponding results for subsequent processing (post-processing). For example, the CPU can use the index of a peak to access the FFT output value of the peak and its neighboring values ​​(in another dimension).

[0053] It is also possible to provide DMA (Direct Memory Access) access to the results in memory.

[0054] FIG. 5 illustrates a hardware accelerator 500 according to one embodiment.

[0055] The hardware accelerator 500 has an input interface (read interface) 501 through which the hardware accelerator 500 reads the bitmap to be processed from the radar data memory 503, and an output interface (write interface) 502 through which the hardware accelerator 500 writes the processing results to the radar data memory 503 or another memory.

[0056] The input interface 501 may, for example, have a large bit width, which allows the hardware accelerator 500 to quickly load a bitmap into the internal bitmap memory 504. For example, the input interface 501 may be 256 bits wide, which allows a 128-bit by 256-bit bitmap to be loaded column by column. The bitmap memory 504 may, for example, be implemented by a static random access memory (SRAM) or a register. The hardware accelerator 500 further includes one or more configuration registers 505, which allow the processing performed by the hardware accelerator 500 to be controlled or configured (e.g., by a CPU).

[0057] The following describes the structure and operation of hardware accelerator 500 for extracting the peak indices, i.e., generating list 507. This list indicates, for each 1 in bitmap 506 stored in bitmap memory 504, the distance index value and Doppler index value of the 1 (and thus the location of the 1 in bitmap 506).

[0058] According to one embodiment, for this operation, hardware accelerator 500 includes hardware counter 512, comparison logic (ie, hardware comparison logic) 510, and list generation logic 511.

[0059] The bitmap is provided in a bitstream to the comparison logic 510. This is done column-by-column (i.e., Doppler bin-wise) in this embodiment, with one bit provided to the comparison logic 510 on each clock cycle of the hardware accelerator clock.

[0060] The hardware counter 512 counts from 0 to the number of Doppler bins (#Doppler) times the number of distance bins (#Distance). These are configurable via configuration registers 505, and the hardware counter 512 counts increments from 1, and the counter value is incremented on each clock cycle. The hardware counter 512 starts counting when the entire bitmap 506 is loaded. After #Doppler x #Distance, the hardware counter 512 jumps to 0 again.

[0061] At each clock cycle, comparison logic circuit 510 compares the bit value currently supplied to it with 1. If the bit value is equal to 1, comparison logic circuit 510 outputs a "true" event to list generation circuit 511. In response to the "true" event, list generation circuit 511 reads the latest count state of hardware counter 512 and writes the upper bit 508 (as a distance index) and the lower bit 509 (as a Doppler index) into list 507 as an index pair.

[0062] That is, the list generation circuit calculates the Doppler index from the lower counter value bits (for example, if #Doppler = 128, the lower 7 bits (bits 0 to 6)), and calculates the distance index from the upper counter value bits (for example, if #Distance = 256, the upper 8 bits (bits 7 to 14)).

[0063] If the length of the portion of the list generated by the list generation circuit 511 is equal to the width of the output interface 502, the list generation circuit 511 triggers the output of the portion of the list via the output interface (i.e., outputs the list in, for example, 256-bit portions).

[0064] This allows the hardware accelerator 500 to calculate the list 507 using a second For loop (implemented by the upper or lower bits of the hardware counter 512, respectively), operating directly on the internal memory 504. The bit width of the bitmap 506 is read in the range and Doppler directions.

[0065] This allows the hardware accelerator 500 to receive the entire list generation at once (i.e., triggered by one software instruction, i.e., one driving control by the CPU), so that from the CPU's perspective, only one instruction is required.

[0066] In a similar manner, other bitwise operations can be realized by a hardware accelerator, and a separate hardware accelerator can be provided for this purpose, or a hardware accelerator can be provided that supports multiple bitwise operations.

[0067] For the bitwise combination, an internal bitmap memory 504 for the two bitmaps is provided, and an AND combination between two bits of two bitmaps belonging to the same distance index value and the same Doppler index value replaces the comparator (AND combination with 1). Instead of list 507, a resulting bitmap is generated that contains the result of the AND combination (again, at a position given by the respective distance index value and the respective Doppler index value). It is also possible here to transpose one bitmap when combining, either by transposing the two bitmaps before combining them, or by reading one bitmap column by column and one bitmap row by row from memory 504 (in which case one bitmap is in memory 504, for example, as a 128x256 bit field).

[0068] Due to the transposition, the comparators are omitted and instead of list 507, a resulting bitmap is generated that contains each bit of bitmap 506, but with the positions swapped corresponding to the transposition (i.e., the Doppler index value of a bit in the resulting bitmap is the distance index value of the bit in the input bitmap, and vice versa).

[0069] In summary, various embodiments provide an integrated radar signal processing circuit as shown in FIG.

[0070] FIG. 6 illustrates an integrated radar signal processing circuit 600 according to one embodiment.

[0071] The integrated radar signal processing circuit 600 has a signal processing unit 601 configured to generate a radar map represented by a field (ie, an array) having a first index and a second index.

[0072] The integrated radar signal processing circuit 600 further includes a peak detection unit 602 configured to identify potential targets in the radar map.

[0073] The peak detection unit 602 has a first peak detection subunit 603 configured to scan the radar map along a first index and store in a radar data memory a first detection bitmap that identifies peaks as a function of the first index.

[0074] The peak detection unit 602 further includes a second peak detection subunit 604 configured to scan the radar map along the second index and output a second detection bitmap to the radar data memory that identifies peaks as a function of the second index.

[0075] The first detection bitmap and the second detection bitmap use separate bits to identify each peak.

[0076] The integrated radar signal processing circuit 600 further includes a hardware accelerator 605 coupled to the radar data memory 503, the hardware accelerator 605 being a bit-wise hardware accelerator configured to process individual bits of the first detection bitmap and the second detection bitmap.

[0077] The approach of FIG. 6 reduces energy consumption by reducing the number of memory accesses compared to software-based bitwise operations by a CPU or DSP (e.g., as described above), reduces latency through dedicated hardware acceleration, and reduces the load on the CPU or DSP, thereby freeing it up for other tasks.

[0078] This allows the radar to be used in particular in scenarios where radar processing results must be delivered reliably and quickly, for example in self-driving vehicles where being able to quickly detect objects is crucial for safety.

[0079] In the following, different examples are given.

[0080] The first embodiment is the integrated radar signal processing circuit described in relation to FIG.

[0081] Example 2 is the integrated radar signal processing circuit of Example 1, wherein the hardware accelerator is configured to transpose the first detection bitmap and / or the second detection bitmap.

[0082] Example 3 is the integrated radar signal processing circuit of Example 1 or 2, wherein the hardware accelerator is configured to combine the first detection bitmap and the second detection bitmap into a combined detection bitmap.

[0083] Example 4 is the integrated radar signal processing circuit of Example 3, wherein a combination of the first detection bitmap and the second detection bitmap has a logical product of each bit of the first detection bitmap and each bit of the second detection bitmap, whereby the combined detection bitmap identifies peaks that are identified by both the first detection bitmap and the second detection bitmap.

[0084] Example 5 is the integrated radar signal processing circuit of Example 3 or 4, wherein the hardware accelerator is configured to transpose the first detection bitmap for the combination, such that, during the combination, each bit of the first detection bitmap is combined with a bit of the second detection bitmap, and the bit of the second detection bitmap has the first index value of the bit of the first detection bitmap as the second index value and the second index value of the bit of the first detection bitmap as the first index value.

[0085] Example 6 is the integrated radar signal processing circuit of any one of Examples 3 to 5, wherein the hardware accelerator is configured to calculate a first index value and a second index value of a peak identified by the combined detection bitmap.

[0086] Example 7 is the integrated radar signal processing circuit of Example 6, wherein the hardware accelerator is configured to generate and output a list of first index values ​​and second index belonging values ​​of peaks identified by the combined detection bitmap.

[0087] In the eighth embodiment, the hardware accelerator a memory element for storing the combined bitmap; a hardware counter for counting bits; and a comparison logic unit for receiving the bits identified by the hardware counter and outputting a corresponding result if the bits identify a peak.

[0088] A ninth embodiment is the integrated radar signal processing circuit of the eighth embodiment, wherein the comparison logic unit is configured to output the result to a list generation circuit of a hardware accelerator, which is configured to output a first value provided by the upper bits of the hardware counter and a second value provided by the lower bits of the hardware counter as a peak index pair.

[0089] A tenth embodiment is the integrated radar signal processing circuit according to any one of the first to ninth embodiments, in which the radar data memory is an internal memory of the integrated radar signal processing circuit.

[0090] Example 11 is the integrated radar signal processing circuit of any one of Examples 1 to 10, wherein the hardware accelerator has an internal bitmap memory, the internal bitmap memory is configured to store the first detection bitmap, the second detection bitmap, and / or a combination of the first detection bitmap and the second detection bitmap, and is configured to output the stored bitmaps as a bitstream to the processing logic of the hardware accelerator, and the processing logic is configured to process bits of the bitstream individually.

[0091] Example 12 is the integrated radar signal processing circuit of Example 11, wherein the processing logic circuit is configured to compare each bit of the bit stream with a fixed value or combine each bit of the bit stream with another bitmap.

[0092] Example 13 is the integrated radar signal processing circuit of example 11 or 12, wherein the hardware accelerator is configured to fully load the first detection bitmap, the second detection bitmap, and / or a combination of the first detection bitmap and the second detection bitmap into an internal bitmap memory and then process them bit by bit.

[0093] Example 14 is an integrated radar signal processing circuit according to any one of Examples 11 to 13, wherein the hardware accelerator has a read interface, and the read interface is configured to read the first detection bitmap, the second detection bitmap, and / or a combination of the first detection bitmap and the second detection bitmap from the radar data memory into the internal bitmap memory, and the read interface is configured to read rows or columns of the first detection bitmap, the second detection bitmap, and / or a combination of the first detection bitmap and the second detection bitmap in parallel.

[0094] Example 15 is the integrated radar signal processing circuit according to any one of Examples 1 to 14, wherein the first index is a range index and the second index is a Doppler index, the first index is a range index and the second index is a direction index, or the first index is a velocity index and the second index is a direction index.

[0095] While the present invention has been particularly shown and described with reference to certain embodiments, those skilled in the art will recognize that numerous changes may be made in the embodiments and details thereof without departing from the spirit and scope of the invention as defined by the following claims. The scope of the present invention is therefore determined by the appended claims, and it is intended to embrace all changes that come within the meaning or range of equivalence of the claims. [Explanation of symbols]

[0096] 100 radar equipment 101 Radar System 102 Antenna device 103 Radar Device 104 Transmitter 105 Duplexer 106 Receiver 107 Control device 108 Object 109 Transmitted Signal 110 Echo 111 Radar signal processing circuit 200 FMCW radar equipment 201 Sawtooth Waveform 202 Oscillator 203 Transmitting Antenna 204 receiving antenna 205 Mixer 206 Low-pass filter 207 Spectrum Analyzer 208 Chirp 300 Data Cubes 301 Distance / Doppler Map 302 FFT Peaks 303 Receiving Antenna 304~306 Bitmap 401~403 Chirp 404 Bitmap 405,406 Rotated Bitmaps 500 Hardware Accelerators 501 Input Interface 502 output interface 503 Radar Data Memory 504 bitmap memory 505 Configuration Register 506 bitmaps 507 List 508 High-order bits of the hardware counter 509 Low-order bits of the hardware counter 510 Comparison Logic Circuit 511 List Generation Logic Circuit 512 hardware counters 600 Integrated radar signal processing circuit 601 Signal Processing Unit 602 Peak Detection Unit 603,604 Peak detection subunit 605 Hardware Accelerator

Claims

1. An integrated radar signal processing circuit, wherein the integrated radar signal processing circuit comprises: a signal processing unit configured to generate a radar map represented by a field having a first index and a second index; a peak detection unit configured to identify potential targets in the radar map; a hardware accelerator; and the peak detection unit comprises: a first peak detection unit configured to scan the radar map along the first index and store a first detection bitmap identifying peaks as a function of the first index in a radar data memory; a second peak detection subunit configured to scan the radar map along the second index and output a second detection bitmap identifying peaks as a function of the second index to the radar data memory; and the first detection bitmap and the second detection bitmap identify the respective peaks using individual bits; the hardware accelerator is connected to the radar data memory, and the hardware accelerator is a bit-level hardware accelerator configured to process the individual bits of the first detection bitmap and the second detection bitmap. Integrated radar signal processing circuit.

2. The hardware accelerator is configured to transpose the first detection bitmap and / or the second detection bitmap. The integrated radar signal processing circuit according to Claim 1.

3. The hardware accelerator is configured to combine the first detection bitmap and the second detection bitmap into a combined detection bitmap. The integrated radar signal processing circuit according to Claim 1.

4. The combination of the first detection bitmap and the second detection bitmap has a logical product of each bit of the first detection bitmap and each bit of the second detection bitmap, whereby the combined detection bitmap identifies peaks that are identified by both the first detection bitmap and the second detection bitmap. The integrated radar signal processing circuit according to claim 3.

5. The hardware accelerator is configured to transpose the first detection bitmap with respect to the combination, whereby, upon the combination, each bit of the first detection bitmap is combined with the bit of the second detection bitmap, and the bit of the second detection bitmap has the value of the first index of the bit of the first detection bitmap as the value of the second index and the value of the second index of the bit of the first detection bitmap as the value of the first index. The integrated radar signal processing circuit according to claim 3.

6. The hardware accelerator is configured to calculate the value of the first index and the value of the second index of the peak identified by the combined detection bitmap. The integrated radar signal processing circuit according to claim 3.

7. The hardware accelerator is configured to generate and output a list of the value of the first index of the peak identified by the combined detection bitmap and the value to which the second index belongs. The integrated radar signal processing circuit according to claim 6.

8. The hardware accelerator a memory element for storing the combined detection bitmap, a hardware counter for counting bits, a comparison logic unit that receives the bit identified by the hardware counter and outputs a corresponding result when a peak is identified by the bit, and has The integrated radar signal processing circuit according to claim 3.

9. The comparison logic unit is configured to output the result to the list generation circuit of the hardware accelerator that is configured to output, as a peak index pair, a first value given by the upper bits of the hardware counter and a second value given by the lower bits of the hardware counter. The integrated radar signal processing circuit according to claim 8.

10. The radar data memory is an internal memory of the integrated radar signal processing circuit. The integrated radar signal processing circuit according to claim 1.

11. The hardware accelerator has an internal bitmap memory, and the internal bitmap memory is configured to store the first detection bitmap, the second detection bitmap, and / or a combination of the first detection bitmap and the second detection bitmap, and is configured to output the stored detection bitmap as a bitstream to the processing logic circuit of the hardware accelerator. The processing logic circuit is configured to individually process the bits of the bitstream. The integrated radar signal processing circuit according to claim 1.

12. The processing logic circuit is configured to compare each bit of the bitstream with a fixed value or to combine each bit of the bitstream of another bitmap. The integrated radar signal processing circuit according to claim 11.

13. The hardware accelerator is configured to completely read the first detection bitmap, the second detection bitmap, and / or the combination of the first detection bitmap and the second detection bitmap into the internal bitmap memory and then process them bit by bit. The integrated radar signal processing circuit according to claim 11.

14. The hardware accelerator has a read interface, and the read interface is configured to read the first detection bitmap, the second detection bitmap, and / or the combination of the first detection bitmap and the second detection bitmap from the radar data memory into the internal bitmap memory. The read interface is configured to read rows or columns of the first detection bitmap, the second detection bitmap, and / or the combination of the first detection bitmap and the second detection bitmap in parallel. The integrated radar signal processing circuit according to claim 11.

15. The first index is a range index and the second index is a Doppler index. The first index is a range index and the second index is a Doppler index, or The first index is a speed index and the second index is a direction index. The integrated radar signal processing circuit according to claim 1.

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