RF peak detector circuit

Abstract

To provide a peak detector (PDET) that improves small signal voltage gain Aυ without increasing power loss.SOLUTION: A PDET circuit 200 includes a transistor pair including a first metal oxide semiconductor field effect transistor (MOSFET) 202 coupled to a second MOSFET 204. The first MOSFET includes a first gate terminal and a first drain terminal. The second MOSFET includes a second gate terminal and a second drain terminal. The first gate terminal receives a positive input voltage signal VINP. The second gate terminal receives a negative input voltage signal VINM that is shifted with respect to the positive input voltage signal. The first drain terminal and the second drain terminal are coupled to output an output voltage VOUTP proportional to the power of the positive and negative input voltage signals.SELECTED DRAWING: Figure 2A

Description

[Background technology]

[0001] Peak detectors, also known as signal level detectors, power detectors, or envelope detectors, are widely used in wireless transceivers. A peak detector (hereinafter referred to as "PDET") can be used to acquire the signal power level of a sinusoidal radio frequency (RF) signal received by the antenna of a wireless transceiver. PDETs are generally implemented using transistors. A transistor has a nonlinear voltage-current relationship. The small-signal voltage is an alternating current (AC) voltage signal (e.g., a voltage signal that changes over time), and the amplitude of this small signal is small (e.g., in millivolts or microvolts) compared to the direct current (DC) bias voltage (e.g., in volts) applied to bias the transistor in the PDET. The nonlinear voltage-current relationship during small-signal operation is the small-signal gate-source voltage (V gs It can be expressed as a function of the first and higher-order drain currents. For example, the small-signal drain current i d This is a linear current source gmV gs And a nonlinear current source, for example, gm2V gs 2 , gm3V gs 3 This is modeled as the sum of a higher-order nonlinear current source. The value gm is the first-order linear transconductance coefficient, gm2 is the second-order nonlinear transconductance coefficient, gm3 is the third-order nonlinear transconductance coefficient, and so on. Using the nonlinearity of the transistor, the PDET can detect the power of the received alternating current (AC) signal as a direct current (DC) voltage from the nonlinear current. The DC voltage is the power level of the received signal. [Overview of the project]

[0002] According to at least one example of the present disclosure, a system for detecting the power of a signal includes an antenna configured to transmit a first signal, an amplifier coupled to the antenna for receiving the first signal and configured to provide a second signal based on the first signal, a peak detector coupled to the amplifier, and an automatic gain control (AGC) circuit coupled to the peak detector and the amplifier. The peak detector includes a pair of transistors, a first input node, a second input node, and an output node. The peak detector includes a first metal oxide semiconductor field-effect transistor (MOSFET) having a first gate terminal, a first drain terminal, and a first source terminal, and a second MOSFET coupled to the first MOSFET having a second gate terminal, a second drain terminal, and a second source terminal. The second drain terminal is coupled to the first drain terminal, and the second source terminal is coupled to the first source terminal. A first input node is coupled to a first gate terminal and configured to receive a second signal; a second input node is coupled to a second gate terminal and configured to receive a third signal that is phase-shifted relative to the second signal; and a first output node is coupled to the first and second drain terminals and configured to output a fourth signal proportional to the power of the first and second signals. An AGC circuit is coupled to the first output node and an amplifier and configured to provide a gain control signal to the LNA based on the fourth signal.

[0003] According to another example of the present disclosure, the apparatus includes a pair of transistors comprising a first MOSFET and a second MOSFET. The first MOSFET includes a first gate terminal and a first drain terminal. The second MOSFET is coupled to the first MOSFET and includes a second gate terminal and a second drain terminal. A first input node is coupled to the first gate terminal and configured to receive a first signal. A second input node is coupled to the second gate terminal and configured to receive a second signal that is phase-shifted relative to the first signal. An output node is coupled to the first drain terminal and the second drain terminal and configured to output a first signal and a third signal proportional to the second signal.

[0004] A system includes an antenna configured to send a first signal, an amplifier coupled to the antenna to receive the first signal and configured to provide a second signal based on the first signal, a mixer coupled to the amplifier to receive the second signal and configured to provide a third signal based on the second signal, a filter coupled to the mixer to receive the third signal and configured to provide a fourth signal based on the third signal, an analog-to-digital converter (ADC) coupled to the filter and configured to provide a fifth signal based on the fourth signal, a peak detector coupled to the amplifier to receive the second signal and configured to provide a sixth signal based on the second signal, a comparator coupled to the peak detector to receive the sixth signal and configured to output a trigger signal based on a comparison between the threshold signal and the sixth signal, and an automatic gain control (AGC) circuit coupled to the comparator and the amplifier. The AGC circuit is configured to provide a gain control signal to the LNA based on the trigger signal.

Brief Description of the Drawings

[0005] Next, for a detailed description of various examples, reference is made to the accompanying drawings.

[0006] [Figure 1] It is a block diagram of a receiver circuit including a peak detector according to various examples.

[0007] [Figure 2A] It is a circuit diagram of a peak detector circuit according to various examples.

[0008] [Figure 2B] It is a circuit diagram of a peak detector circuit according to various examples.

[0009] [Figure 3] It is a circuit diagram of a peak detector circuit according to various examples.

[0010] [Figure 4]These waveform diagrams illustrate the operation of peak detector circuits according to various examples.

[0011] [Figure 5] These waveform diagrams illustrate the operation of peak detector circuits according to various examples.

[0012] [Figure 6] This is a block diagram of a computing device following various examples. [Modes for carrying out the invention]

[0013] Information in the form of an AC component (e.g., an RF signal) at a certain DC voltage, acquired by a PDET, can be used in an automatic gain control (AGC) circuit to adjust the gain of a low-noise amplifier (LNA) in a wireless transceiver. However, interference / blocker signals can also be received by the LNA. These interference signals are either in-band interference signals from other communication systems or out-of-band interference signals on neighboring channels within the same communication system. If these interference signals are not filtered at the LNA input, they can affect the linear operation of the LNA by saturating it (e.g., operating in the saturation region). When interference signals saturate the LNA, a control signal from the AGC can be used to adjust the gain of the LNA to move the LNA's operating point into the linear region of operation. However, during the time the LNA is saturated, the information received by the LNA may be corrupted and unrecoverable. PDETs can detect interference signals. However, during detection, these PDETs also attenuate the power of the desired RF signal when the desired RF signal is at a lower amplitude. Attenuating the desired RF signal affects the detection sensitivity of the PDET for detecting weaker interference signals compared to the desired RF signal (e.g., approximately 15 to 20 dB lower than the RF power of the desired RF signal). Interference signals can affect the linearity, signal-to-noise ratio (SNR), and other performance measurements of the LNA and mixer in the receiver chain of a wireless communication system. Therefore, weaker interference signals compared to the desired RF signal cannot be detected using the PDET, while stronger interference signals compared to the desired RF signal (e.g., within 5 dB of the RF power of the desired RF signal) can be detected. Some PDETs also employ a common drain topology, in which case the second-order nonlinear drain current is combined to exit the source terminal of the transistor in these PDETs. The impedance seen from the source node is 1 / gm, and the small-signal gain Aυ of the PDET is obtained at the source node and is (-gm² / gm) × Vgs 2 This small-signal gain Aυ makes it difficult to detect interference signals that are relatively weak compared to the desired RF signal.

[0014] Examples of PDETs arranged in a common source topology are disclosed in the present application. This PDET can detect the power of an interfering RF signal that is relatively weak compared to a desired RF signal (e.g., within 15 dB to 20 dB of the RF power of the desired RF signal) without degrading the performance measurements of the LNA and mixer in the receiver chain. In one example, the detected interference power is provided to an AGC circuit to adjust the gain of the LNA, thereby moving the LNA operating point from the saturation region to the linear region of operation. In one example, the PDET uses a differential interfering RF signal applied to a differential pair of transistors. In another example, the power of the interfering RF signal is detected using the second-order non-linear drain current of the transistor. In one example, the second-order non-linear drain current is obtained by combining the non-linear drain currents at the drain terminals of the transistors in the PDET. The second-order non-linear drain current provides a DC value (e.g., A 2 / 2) and an AC current value (A 2 / 2)sin(2ωt), where A is the amplitude. The DC value is proportional to the power of the interfering RF signal. In at least one example, the small-signal drain current that examines the drain terminal experiences the resistance of a load resistor R (e.g., R||r ds ) in parallel with the drain-source resistance r ds . The resistance r ds is greater than 1 / gm in a metal-oxide-semiconductor field-effect transistor (MOSFET). The small-signal voltage gain Aυ of the MOSFET for the drain current is a function of the load resistance of the resistor R and the second-order non-linear drain current gm2V gs 2 . The small-signal gain Aυ of the PDET is -gm2×Vgs 2 ×((r ds ×R) / (r dsThe small-signal gain (+R) is high. In one example, the small-signal gain of the PDET is approximately 13 dB higher than the small-signal voltage gain (Aυ) of a conventional PDET. The higher small-signal gain of the PDET allows it to detect weaker interfering RF signals than a conventional PDET without degrading the performance of the LNA. Furthermore, the PDET improves the small-signal voltage gain (Aυ) without increasing power loss compared to a conventional PDET.

[0015] Figure 1 is a block diagram of a wireless receiver (RX) circuit 100 including a PDET according to various examples. In one example, the wireless receiver circuit 100 uses a PDET to detect the signal strength (e.g., signal power) of an interfering RF signal. The PDET uses the signal power of the interfering RF signal to determine the signal value supplied to the AGC circuit in order to control the voltage gain of the LNA and move the LNA from saturation to a linear mode of operation. In some examples, the wireless receiver circuit 100 is used in wireless local area network (LAN) receivers for WiFi, Bluetooth, and other wireless applications such as television receivers, mobile phones, modems, network devices, wireless radios, etc.

[0016] As shown in Figure 1, the wireless receiver circuit 100 includes an RX chain 102 for processing the RF signal received by the wireless receiver circuit 100. The RX chain 102 includes an antenna 104, an LNA 106, a mixer 108, a filter 110, and an analog-to-digital converter (ADC) 112. The antenna 104 is coupled to the input of the LNA 106. The output of the LNA 106 is coupled to the input of the mixer 108. The output of the mixer 108 is coupled to the input of the filter 110. The output of the filter 110 is coupled to the input of the ADC 112. The first input of the AGC 136 is coupled to the output of the ADC 112, the second input of the AGC 136 is coupled to the output of the comparator 132, and the output of the AGC 136 is coupled to the LNA 106 and the filter 110. The output of the LNA 106 is coupled to the input of the PDET 130. The inputs of PDET130 and mixer 108 receive the signal from the output of LNA106 as a differential. The output node of PDET130 is coupled to the first input of comparator 132. The second input of comparator 132 receives the threshold voltage value 134.

[0017] In operation, antenna 104 provides the LNA 106 with an AC signal (e.g., an RF signal) to be transmitted wirelessly. In one example, if the wireless receiver circuit 100 is located near an access point of a communication system, antenna 104 may provide the LNA 106 with an in-band interference RF signal, an out-of-band interference RF signal, or both in-band and out-of-band interference signals as a multi-tone RF signal. A multi-tone RF signal consists of multiple single sine waves or tones having unique amplitudes, phases, and frequencies. In one example, antenna 104 provides a desired RF signal component 114, an in-band interference RF signal component 115, and an out-of-band interference RF signal component 116. In one example, antenna 104 provides a multi-tone RF signal including an RF signal component 114 having a frequency of 2.401 gigahertz (GHz), an in-band interference RF signal component 115 having a frequency of 2.37 GHz, and an out-of-band interference RF signal component 116 having a frequency of 2.3 GHz.

[0018] In one example, the LNA106 includes an amplifier and a single-ended to differential converter to generate a differential signal after amplification of a multitone RF signal. In one example, the differential signal includes a positive multitone RF signal and a negative multitone RF signal, where each multitone RF signal includes an RF signal component. The LNA106 amplifies the RF signals 114, 115, and 116 to increase the amplitude of the RF signal components 114, 115, and 116, thereby increasing the SNR of the RF signal components 114, 115, and 116. In one example, at its output, the LNA106 amplifies the RF signal component 114 to generate an RF signal component 118 with a higher amplitude, amplifies the interference RF signal component 115 to generate an RF interference signal component 119 with a higher amplitude, and amplifies the interference RF signal component 116 to generate an RF interference signal component 120 with a higher amplitude. In one example, the LNA 106 generates RF signal component 118, interference RF signal component 119, and interference RF signal component 120 as components of the differential signal. For clarity, although not shown in the diagram, it is understood that downstream circuit components of the LNA 106 process the differential multitone signal generated by the LNA 106.

[0019] Mixer 108 is coupled to LNA 106 and filter 110. Mixer 108 receives a local oscillator (LO) signal 122 from LO (not shown) and a differential signal from LNA 106. In one example, the LO signal 122 is a large-signal voltage signal with a frequency of 2.4 GHz. However, in some examples, the frequency of the LO signal 122 changes as the frequency of the RF signal component 118 changes. Mixer 108 uses the LO signal 122 to downconvert the frequencies of the RF signal component 118, RF interference signal component 119, and RF interference signal component 120 in the differential signal to an intermediate frequency (IF) multitone IF signal with an intermediate frequency (IF) signal component at an even lower frequency. In one example, mixer 108 multiplies the LO signal 122 by the output RF signal component 118 to obtain the IF signal component 124, multiplies the LO signal 122 by the RF interference signal component 119 to obtain the IF signal component 125, and multiplies the LO signal 122 by the RF interference signal component 120 to obtain the interference IF signal component 126. In one example where the RF signal component 118 is 2.401 GHz, the RF interference signal component 120 is 2.3 GHz (e.g., an out-of-band interference signal), the LO signal is 2.4 GHz, the frequencies of the IF signal components 124 and 126 can be 1 megahertz (MHz) and 100 MHz, respectively, and the IF signal component 126 is an out-of-band IF signal. For RF signal component 118 at a frequency of 2.401 GHz and RF interference signal component 119 at a frequency of 2.37 GHz (e.g., an in-band interference signal), the frequencies of IF signal components 124 and 125 are 1 MHz and 30 MHz, respectively, with IF signal component 125 being an in-band IF signal component.

[0020] Filter 110 is an IF filter that receives a multitone IF signal including IF signal components 124, 125, and 126. Filter 110 has a bandwidth for attenuating out-of-band signals. Therefore, filter 110 provides an output signal including an IF signal 127 corresponding to IF signal 124. In one example where IF signal 126 is an out-of-band interference signal, filter 110 attenuates IF signal component 126 to produce an output signal having a substantially lower amplitude interference IF signal component 129 corresponding to signal component 126. However, in one example where IF signal component 126 is an in-band interference, filter 110 produces an output signal including a relatively unfiltered IF signal component 128 corresponding to IF signal component 126. Thus, the output of filter 110 includes a multitone IF signal including the desired IF signal component 127, the interference IF signal component 128, and the lower amplitude interference IF signal component 129. The desired IF signal component 127 and the interference IF signal component 128 are input to the ADC 112, which converts the desired IF signal component 127 and the interference IF signal component 128 into digital signals for processing.

[0021] In at least one example, the interfering RF signal component 116 (e.g., an out-of-band interfering RF signal component) is high power and saturates the LNA 106 and mixer 108 (e.g., damaging the RX chain 102). In some such examples, when the interfering RF signal component 116 has similar intensity / power to the RF signal component 114, the coupled RF signal components 114 and 116 can cause the LNA 106 to operate in the saturation region, thereby reducing the gain of the LNA 106. In at least one example, amplifying the interfering RF signal component 116 in the LNA 106 generates an equally amplified RF interfering signal component 120 at the output of the LNA 106. In one example, the amplified RF interfering signal component 120 causes the mixer 108 to operate in the saturation region. In one example, if the LNA 106 and mixer 108 are saturated, the interfering RF signal component 116 is high power and reduces the sensitivity of the LNA 106 and mixer 108 (for example, damaging the RX chain 102), so the filter 110 cannot filter out the interfering IF signal component 126. To prevent the high-power interfering RF signal component 116 from damaging the RX chain 102, in at least one example, the wireless receiver circuit 100 includes a feedback path that provides interference signal information to the AGC 136 to control the gain of the LNA 106.

[0022] In the first feedback path from ADC112 through AGC136 to LNA106 and filter110, the out-of-band interference signal component, interference IF signal component 126, is filtered by filter 110. Since the interference IF signal component 126 is outside the filter 110's cutoff frequency (e.g., passband), which is 10 MHz in one example, the power of the interference IF signal component 126 is attenuated by filter 110 and provided as interference IF signal component 129. Because filter 110 filters the interference IF signal component 126 to reduce its RF power, ADC112 does not detect this interference IF signal component 129 at its input. In another example, if the interference IF signal component 126 is an in-band interference IF signal component (e.g., at a frequency of 30 MHz), the interference IF signal component 129 corresponding to the interference IF signal component 126 is detected by ADC112. In one example, the ADC112 senses the power of the input signal to the ADC112, which includes the interference IF signal component 126. Since the interference IF signal component 126 is within the passband of the filter 110, the interference IF signal component 126 is not filtered out and is sensed by the ADC112. In one example, the ADC112 obtains the intensity (e.g., RF power) of the interference IF signal component 126, and this intensity is sent to the AGC136. The AGC136 uses the intensity of the interference IF signal component 129 to provide a gain control signal for adjusting the gain of the LNA106 (e.g., increasing or decreasing the gain), so that the LNA106 operates in the linear region of operation.

[0023] In the second feedback path from PDET130 to AGC136, the interfering RF signal component 116 is an out-of-band interfering signal component (for example, the interfering IF signal component 116 has a frequency of 2.3 GHz) and has an intensity similar to that of the RF signal component 114, which can saturate the LNA106. In one example, PDET130 receives a differential signal of a multitone RF signal from the LNA106, which includes the RF signal component 118, the RF interference signal component 119, and the RF interference signal component 120. In one example, PDET130 detects the power of the multitone RF signal, which includes the power of the RF signal component 118, the power of the interfering RF signal component 119, and the power of the interfering RF signal component 120. The power of the interfering RF signal component 119 is less intense than that of the interfering RF signal component 120 and the RF signal component 118, and can therefore be ignored in this particular example. In one example, PDET130 outputs a voltage value (e.g., an analog value) representing the power of the multitone RF signal. These outputs are provided to comparator 132. In one example, comparator 132 compares the analog voltage value of the output from PDET 130 with a threshold voltage value 134. The threshold voltage value 134 may be a user-defined threshold voltage value. If the analog voltage value of PDET 130 is greater than the threshold voltage value 134, comparator 132 provides a trigger signal to AGC 136, indicating a high-power interference RF signal component 120. In at least one example, AGC 136 is configured to provide a gain control signal to LNA 106 to adjust the gain of LNA 106 (e.g., increase or decrease the gain) when it receives a trigger signal to operate LNA 106 in the linear domain.

[0024] Figures 2A and 2B illustrate a portion of the AC equivalent circuit of a PDET circuit 200 used to detect the power of an interfering RF signal using the small-signal linear and nonlinear drain currents of the PDET circuit 200, according to various examples. In particular, Figure 2A is annotated to show the primary effect of the signal applied to the PDET circuit 200, and Figure 2B is annotated to show the secondary effect of the signal applied to the PDET circuit 200. In one example, the PDET circuit 200 uses the secondary nonlinear drain current of the transistor in the PDET circuit 200 when a multitone differential signal is applied to the transistor to acquire the power of a differential RF signal, according to various examples. In one example, the PDET circuit 200 corresponds to the PDET 130 shown with reference to Figure 1 and described above.

[0025] As shown in Figures 2A and 2B, the PDET circuit 200 includes a differential pair of transistors 202 and 204. In one example, transistors 202 and 204 are N-channel MOSFETs (NMOS). In other examples, P-channel MOSFET (PMOS) transistors or bipolar junction transistors (BJTs) may be used. In one example, transistors 202 and 204 are coupled together as a differential pair using a common source configuration. For example, the drain terminals / nodes of transistors 202 and 204 are coupled together, and the source terminals of transistors 202 and 204 are coupled together. The source terminals of transistors 202 and 204 are coupled to a ground terminal (e.g., ground voltage potential). A load resistor R is coupled in parallel with capacitor C. In one example, the first end of resistor R is coupled to the first end of capacitor C, and the second end of resistor R is coupled to the second end of capacitor C. The first end of the resistor-capacitor (RC) coupling is coupled to the drain terminals of transistors 202 and 204, and the second end of the RC coupling is coupled to a positive voltage supply VDD. In one example, the RC coupling is an RC filter that filters (e.g., attenuates) a signal using frequencies other than the desired RF signal. In one example, the passband of the RC filter may be modified to be concentrated around the center frequency of the desired RF signal and have bandwidth for filtering other frequency tones. Gate-source voltage (V gs )206 is the small signal gate-source voltage between the gate and source terminals of transistor 202, V gs 208 is the small-signal gate-source voltage between the gate and source terminals of transistor 204. gmV gs 210 is the small-signal linear drain current flowing through transistor 202, and is gmV. gs 212 is the small-signal linear drain current flowing through transistor 204. In one example, gm2V gs 2 214 is the small-signal nonlinear drain current flowing through transistor 202, and gm2V gs 2 216 is the small-signal nonlinear drain current flowing through transistor 204.

[0026] In operation, as shown in Figures 2A and 2B, the RC coupling filters the small-signal AC signal at the drain terminals of transistors 202 and 204. In one example, the PDET circuit 200 is biased with DC voltages at the drain and gate terminals to operate transistors 202 and 204 at their DC operating points. However, the DC bias connections and components used to DC bias transistors 202 and 204 are not shown. Differential multitone signals containing small-signal voltage components are applied to the gate terminals of transistors 202 and 204. In one example, a differential pair positive multitone signal containing small-signal RF components and small-signal interference RF components is applied to the gate terminal of transistor 202. In one example, a differential pair negative multitone signal containing small-signal RF components and small-signal interference RF components is applied to the gate terminal of transistor 204. The positive and negative small-signal multitone RF signals have equal magnitude and frequency but are out of phase with respect to each other. As described above, small-signal transistor operation is analyzed as a series of linear and nonlinear voltage and current sources. In an example of small-signal transistor operation, the drain current i of transistors 202 and 204 is d gmV gs +gm2V gs 2 +gm3V gs 3 It can be modeled by higher-order terms. gm is the first-order linear transconductance parameter, gm2 is the second-order nonlinear transconductance parameter, and gm3 is the third-order nonlinear transconductance parameter. In a transistor, gm > gm2 > gm3. For the sake of discussion, the higher-order nonlinear transconductance parameter gm x These are not described in detail because they are several orders of magnitude smaller than, for example, the second-order nonlinear transconductance parameter gm2. However, their applications follow those of the first- and second-order parameters described.

[0027] In one example, the differential signal, which includes small-signal voltage components at the gate terminals of transistors 202 and 204, is a positive input voltage signal VINP (e.g., Asin(ωt)) supplied from an input node coupled to transistor 202, and a negative input voltage signal VINM (e.g., -Asin(ωt)) at a second input node coupled to transistor 204. In one example, VINP is applied to the gate terminal of transistor 202, and VINM is applied to the gate terminal of transistor 204. In one example, VINP is an input signal from the output of an LNA (e.g., LNA106 in Figure 1). VINM is obtained from VINP by applying a phase shift to VINP. In one example, VINP is a multi-tone RF signal containing an interfering RF signal, which is out of phase with VINM. The PDET circuit 200 rejects odd-order current components and drain current i to obtain the output voltage VOUTP, as shown and described below. d The even-order components are passed through.

[0028] In operation, referring to transistors 202 and 204 in Figure 2A, when VINP is applied to the gate terminal of transistor 202, Vgs206 causes the primary small-signal linear drain current gmVgs210 in transistor 202 to flow from the drain terminal to the source terminal. Also, when a negative input voltage signal VINM (e.g., -Asin(ωt)) is applied to the gate terminal of transistor 204, Vgs208 of transistor 204 causes the primary small-signal linear drain current gmVgs212 in transistor 204 to flow from the source terminal to the drain terminal. The small-signal linear drain currents gmVgs210 and 212 are equal, but they flow in opposite directions between the drain terminal and the source terminal. In one example, the small-signal linear drain currents gmVgs210 and gmVgs212 flow through the loop between transistors 202 and 204 (for example, through the loop between the drain and source terminals of transistors 202 and 204). These gmVgs210 and 212, which are equal in magnitude but opposite in direction, flow continuously through the loop between transistors 202 and 204 and do not flow out of transistors 202 and 204, and as a result their net contribution to the output voltage at VOUTP is zero.

[0029] In operation, referring to Figure 2B, the PDET circuit 200 controls the gm2Vgs of transistor 202. 2 gm2Vgs of transistors 214 and 204 2 216 is used to detect the power of the interfering RF signal. In one example, when a positive input voltage signal VINP (e.g., Asin(ωt)) is applied to the gate terminal of transistor 202, the Vgs206 of transistor 202 is forward biased (e.g., the gate terminal is positive relative to the source terminal), and gm2Vgs in transistor 202 2214 flows from the drain terminal to the source terminal of transistor 202. Also, when a negative input voltage signal VINM (e.g., -Asin(ωt)) is input to the gate terminal of transistor 204, the Vgs208 of transistor 204 is biased in the reverse direction (e.g., the gate terminal is negative relative to the source terminal). VINM is the gate-source voltage (e.g., Vgs) applied at the gate terminal of transistor 204, and gm2Vgs 2 216 produces a negative gate-source voltage squared operation (e.g., Vgs squared) and a positive gm²Vgs 2 The current 216 flows from the drain terminal to the source terminal of transistor 204. gm2Vgs 2 214 and 216 exit the drain nodes of transistors 202 and 204, and at the drain terminals of transistors 202 and 204, they are -2 gm 2 Vgs. 2 It is coupled as follows: gm2Vgs exits the drain terminal and goes into resistor R. 2 214 and 216 are Vgs 2 It is equal to the square of gm2Vgs. 2 The currents in 214 and 216 are DC currents (for example, A 2 ( / 2) and AC current (A 2 The DC current is ( / 2)cos(2ωt), where A is the amplitude. The DC current passes through resistor R to provide the voltage drop across resistor R and becomes the output voltage VOUTP at the drain terminals of transistors 202 and 204. DC current (e.g., A 2 (A) provides power to the interfering RF signal using the voltage-current (VI) relationship. In one example, the resistor R and capacitor C form an RC filter. Second-order nonlinear AC drain current (A) 2 / 2)cos(2ωt) is filtered out by the RC filter. Also, in one example, the primary linear AC drain current gmVgs does not leave transistors 202 and 204 and does not need to be filtered by the RC filter. The impedance at the drain node of transistors 202 and 204 is the drain-source resistance r dSand the resistance of resistor R. As a result of a PDET circuit using a common drain configuration, the secondary nonlinear current exits the source terminal and couples at the source node. At the source terminal for these PDETs, the impedance seen from the source terminal is 1 / gm, which is small. The small-signal gain Aυ is defined as the output voltage divided by the input voltage (voltage out / voltage in). The output impedance of a PDET circuit using a common drain configuration is 1 / gm in parallel with the load resistor R. Therefore, the small-signal gain Aυ is (-gm² / gm) × Vgs 2 Therefore, the small-signal source voltage gain Aυ of the PDET circuit 200 (for example, in a common source configuration) is given by the load resistance and gm²Vgs. 2 This is a function of the following: In one example, the load of the PDET circuit 200 is the drain-source resistor rd s This is the resistance of resistor R in parallel with it. In one example, the small signal gain Aυ of the PDET circuit 200 is -gm² × Vgs 2 ×((r ds ×R) / (r ds +R)) is. ds Since is greater than 1 / gm, the small-signal gain of the interfering RF signal in the PDET circuit 200 is higher than the small-signal gain in a PDET circuit using a common drain configuration. In one example, the small-signal gain Aυ of the PDET is approximately 13 dB higher than that of a conventional PDET. The even higher small-signal gain Aυ of the PDET allows for the detection of weaker interfering RF signals than a conventional PDET without degrading the performance measurement of the LNA and mixer in the receiver chain, thereby improving the sensitivity of the PDET compared to a conventional PDET.

[0030] Figure 3 is a block diagram of a PDET circuit 300 for detecting the intensity of an interfering RF signal, according to various examples. In one example, the PDET circuit 300 corresponds to the PDET circuit 130 and includes components corresponding to the components of the PDET circuit 200 shown and described above with reference to Figures 1 and 2A to 2B. As shown in Figure 3, the PDET 300 includes NMOS transistors 302, 304, 306, and 308, resistors 310 and 312, capacitors 314 and 316, a common-mode detection circuit 318, an input voltage signal VINP, a negative input voltage signal VINM, output voltages VOUTP and VOUTM, and a DC bias voltage VBIAS. The input voltage signal VINP includes a small-signal AC signal (e.g., Asin(ωt)), and the input voltage signal VINM includes a negative small-signal AC signal (e.g., -Asin(ωt)). In one example, transistors 302 and 304 are coupled together in a common-source configuration. In one example, the drain terminals of transistors 302 and 304 are coupled together, the source terminals of transistors 302 and 304 are coupled together to the ground terminal / node (e.g., ground voltage potential), and resistor 310 is coupled in parallel to capacitor 314 (e.g., RC component). RC components 310 and 314 are coupled at one end to the drain terminals of transistors 302 and 304, and at a second end to a positive voltage supply VDD. In one example, transistors 302 and 304 are coupled together in a common source configuration. In one example, the drain terminals of transistors 306 and 308 are coupled together, the source terminals of transistors 306 and 308 are coupled together to the ground terminal / node (e.g., ground voltage potential), and resistor 312 is coupled in parallel to capacitor 316 (e.g., RC component). The RC components 312 and 316 are coupled at one end to the drain terminals of transistors 306 and 308, and at a second end to a positive voltage supply VDD. The common-mode detection circuit 318 includes an input node and an output node. In one example, the common-mode detection circuit 318 receives an input voltage signal VINP at one input node and an input voltage signal VINM at another input node.The common-mode detection circuit 318 generates a DC bias voltage VBIAS (e.g., DC voltage) as the output voltage using the average value of VINP and VINM (e.g., 1 / 2(VINP+VINM)).

[0031] In operation, differential small-signal input voltage signals (e.g., AC signals) are applied to the gate terminals of transistors 302 and 304. In one example, the input voltage signal VINP is applied to the gate terminal of transistor 302 at a node coupled to the gate terminal of transistor 302, and the negative input voltage signal VINM is applied to the gate terminal of transistor 304 from a node coupled to the gate terminal of transistor 304. In one example, the input voltage signal VINP includes an interfering RF signal, and the power of this interfering RF signal is detected. Since the input voltage signals VINP and VINM are differential signals, the input voltage signal VINP is 180 degrees out of phase with the input voltage signal VINM (e.g., Vgs). The input voltage signal VINP in transistor 302 has a second-order nonlinear drain current gm²Vgs 2 This current flows from the drain terminal of transistor 302 to the source terminal of transistor 302. In one example, the input voltage signal VINM is equal to the second-order nonlinear drain current gm2Vgs 2 This current flows from the drain terminal of transistor 304 to the source terminal of transistor 304. The secondary nonlinear drain current of transistor 302 is gm2Vgs. 2 This is the secondary nonlinear drain current gm2Vgs of transistor 304 (for example, from the drain terminal to the source terminal of transistor 304). 2 The current flows in the same direction (for example, from the drain terminal to the source terminal of transistor 302). Secondary nonlinear drain current gm2Vgs in transistors 302 and 304. 2 At the drain nodes of transistors 302 and 304, the voltage is -2gm2Vgs. 2 They are coupled as follows: Second-order nonlinear drain current gm2Vgs 2 However, the squares of the input voltage signals VINP and VINM at the gate terminal (for example, (Asin(wt)) 2 and (-Asin(wt) 2) Therefore, the input voltage signal VINP (for example, (Asin(wt) 2 ) and VINM (for example, (-Asin(wt) 2 ) is DC (for example, A 2 ( / 2) and AC current (A 2 The result is ( / 2)cos(2ωt). The DC through the load resistor 310 is used to obtain the output voltage VOUTP. The DC is also used to obtain the DC power of the small signal voltage signal in transistors 302 and 304 as VI. In one example, the AC component (A 2 / 2)cos(2ωt) is filtered out by RC components 310 and 314.

[0032] The common-mode detection circuit 318 operates in common mode to output a value common to the input voltage signals VINP and VINM. In one example, the common-mode detection circuit 318 receives the input voltage signals VINP and VINM and outputs a DC bias voltage VBIAS as a DC voltage at the output node of the common-mode detection circuit 318. The DC bias voltage VBIAS has a value common to the input voltage signals VINP and VINM. In one example, the DC bias voltage VBIAS is the average value of the input voltage signals VINP and VINM. In one example, the common-mode detection circuit 318 is implemented as a resistor divider circuit capable of obtaining the average value of the input voltage signals VINP and VINM. In one example, the DC bias voltage VBIAS is applied to the gate terminals of the differential pair of transistors 306 and 308 at a node coupled to the gate terminals of transistors 306 and 308. For example, the DC bias voltage VBIAS is applied to an input node coupled to the gate terminal of transistor 306, and the DC bias voltage VBIAS is applied to an input node coupled to the gate terminal of transistor 308. The DC bias voltage VBIAS biases the gate terminals of transistors 306 and 308, turning on transistors 306 and 308 and allowing drain current to flow through them. The voltage drop across resistor 312 (e.g., V=IR) provides the output voltage VOUTM. Capacitor 316 is a decoupling capacitor for the load. The output voltages of PDET300 are VOUTP and VOUTM, which are analog DC voltages sent to comparator 132 (as shown above in Figure 1), and comparator 132 provides a trigger signal to AGC136 based on the difference between VOUTP and VOUTM, which is compared with a threshold voltage in comparator 132. The difference between the threshold voltage and VOUTP and VOUTM is used to adjust the gain of LNA106 (for example, by increasing or decreasing the gain) when LNA106 receives a trigger signal (as shown in Figure 1) in order to operate LNA106 in the linear domain. In one example, the small-signal gain Aυ of the PDET is approximately 13 dB higher than that of a conventional PDET.The PDET's higher small-signal gain Aυ allows it to detect weaker interfering RF signals than conventional PDETs without degrading the performance measurement of LNAs and mixers in the receiver chain, thereby improving the PDET's sensitivity compared to conventional PDETs.

[0033] Figures 4 and 5 are waveform diagrams illustrating the operation of the PDET according to various examples. In one example, the PDET is the PDET130 shown and described above with reference to Figure 1.

[0034] The waveform diagram 400 in Figure 4 includes the x-axis 402 as the input RF power (e.g., in dBm units) of the interfering RF signal (e.g., interfering RF signal 116), the y-axis 404 as the DC voltage (e.g., in dBm units) of the interfering RF signal measured at the drain terminal of the PDET (e.g., the output voltage VOUTP in Figure 2B), the DC voltage curve 408 of a similar PDET, and the DC voltage curve 410 of the PDET described in some of the above examples (e.g., PDET130). In operation, the described PDET improves the small-signal voltage gain Aυ of the PDET by approximately 13 dB compared to a similar PDET by increasing the DC voltage of the interfering RF signal at the output of the PDET. In one example, when the RF power of the interfering RF signal is in the range of -50 dB to -10 dB, the DC voltage curve 410 of the described PDET is approximately 13 dB higher than the DC voltage 408 of a similar PDET, which represents the improved gain Aυ of the PDET compared to a similar PDET.

[0035] The waveform diagram 500 in Figure 5 includes the x-axis 502 as the input RF power (e.g., in dBm units) of the interfering RF signal (e.g., interfering RF signal 116), the y-axis 504 as the DC voltage (e.g., in dBm units) of the interfering RF signal (e.g., output voltage VOUTP in Figure 2B) of the interfering RF signal measured at the drain terminal of the PDET, the minimum DC voltage 506 input to the comparator (e.g., comparator 132), the DC voltage curve 508 of a similar PDET, and the DC voltage curve 510 of a PDET (e.g., PDET 130) described in some of the above examples. In one example, the minimum DC voltage 506 is -36 dBm (or 5 millivolts (mV)). In operation, the PDET improves the sensitivity of the PDET for detecting out-of-band interfering RF signals compared to a similar PDET by detecting the interfering RF signal at an even lower input RF power (e.g., -37 dBm). In one example, the PDET described outputs a minimum DC voltage 506 of -36 dBm when an interfering RF signal with an input RF power of -37 dBm is detected. In another example, a similar PDET outputs a minimum DC voltage 506 of -36 dBm when an interfering RF signal with an input RF power of -24 dBm is detected. In another example, the PDET described detects weaker input RF power of interfering RF signals than a similar PDET, representing an improvement in sensitivity of approximately 13 dB compared to a conventional PDET. In another example, when an even weaker input RF power (e.g., -37 dBm) is detected by the PDET, the AGC (e.g., AGC136) controls the LNA (e.g., LNA106 in Figure 1) to operate in the linear region of operation before the LNA saturates. This is what might happen with a similar PDET when an interfering RF signal at -24 dBm is received.

[0036] Figure 6 is a block diagram of a computing device 600 according to various examples. For example, the computing device 600 is an electronic system 629, or is incorporated into or coupled to an electronic system 629. The electronic system 629 is a computer, an electronic control "box" or display, a communication device (including a transmitter or receiver), or any type of electronic system that operates to process information.

[0037] In some examples, the computing device 600 includes a megacell or system-on-a-chip (SoC) with control logic such as a power supply 610, a central processing unit (CPU 612), storage 614 (e.g., random access memory (RAM)), a user interface 616, a display 618, and input-output (I / O) ports 628. In some examples, the CPU 612 is a CISC-type (complex instruction set computer) CPU, a RISC-type (reduced instruction set computer) CPU, an MCU-type (microcontroller unit), or a digital signal processor (DSP). The CPU 612 includes one or more processors. One or more processors are arranged to execute code to convert one or more processors into a special-purpose machine or to improve the functionality of other components in the computing device 600, thereby providing a desired output without performing similar operations of one or more processors. The CPU 612 includes memory and logic for storing information that is frequently accessed from the storage 614.

[0038] In some examples, storage 614 is memory such as an on-processor cache, off-processor cache, RAM, flash memory, or disk storage for storing one or more software applications 630 (e.g., embedded applications). When executed by the CPU 612, one or more software applications 630 (e.g., embedded applications) perform functions related to the computing device 600 described herein.

[0039] In one example, the user controls the computing device 600 using UI 616. In another example, while the software application 630 is running, the user provides input to the computing device 600 via UI 616 and receives output from the computing device 600. In some examples, the output is provided via a display 618, indicator lights, a speaker, vibration, etc. Inputs are received using audio and / or video input (e.g., using voice or image recognition), as well as electrical and / or mechanical devices such as a keypad, switches, proximity detectors, gyroscopes, accelerometers, etc.

[0040] The CPU 612 and power supply 610 are coupled to I / O port 628. In one example, I / O port 628 provides an interface configured to receive input from (and / or provide output to) a networked device 631. The networked device 631 may include any device (including test equipment) capable of point-to-point and / or networked communication with the computing device 600. The computing device 600 may be coupled to peripherals and / or the computing device, including tangible non-temporary media (such as flash memory) and / or wired or wireless media. These and other input and output devices are selectively coupled to the computing device 600 by external devices using wireless or wired connections. Storage 614 is accessible, for example, by the networked device 631. Furthermore, the CPU 612, storage 614, and power supply 610 are optionally connected to an external power supply (not shown), which is configured to receive power from a power source (such as a battery, solar cell, power cord "connected to a power source", induced magnetic field, fuel cell, capacitor, etc.).

[0041] In one example, the power supply 610 is a switched-mode power supply (e.g., a “switched converter”) that operates to operate in discontinuous conduction mode (DCM) or continuous conduction mode (CCM). In some examples, the power supply 610 is the same physical assembly as the computing device 600, or is coupled to the computing device 600. The power supply 610 includes a peak detector circuit 632. The peak detector circuit 632 is illustrated as being included in the power supply 610 as a single unit, but in some examples, various parts of the peak detector circuit 632 are included in the same module or different modules (e.g., formed by dies produced in semiconductor manufacturing). Not shown in Figure 6, the power supply 610 includes power generating components. The power generating components include one or more power switches. Each of these switches is independently controlled to generate power so as to supply power to various components of the computing device 600 at various input voltages. The computing device 600 operates in various power-saving modes, thereby the individual voltages are supplied (and / or turned off) by power switches according to the selected power-saving mode and various components located within a specific power domain.

[0042] In one example, the peak detector circuit 632 operates in the power supply 610 to regulate the output voltage ripple voltage using one or more control loops. The peak detector circuit 632 operates to detect the power of a relatively weak interfering RF signal without degrading the performance measurement of the LNA and mixer in the receiver chain. In one example, the detected interfering power is provided to the AGC circuit to adjust the gain of the LNA, thereby moving the LNA operating point from the saturation region to the linear region of operation. In various examples, the teachings disclosed herein can be applied to virtually all communication systems and protocols, including WiFi, Bluetooth, LTE, etc.

[0043] The term “coupled” is used throughout this specification. This term may encompass any connection, communication, or signaling path that enables a functional relationship compatible with this description. For example, if device A generates a signal to control device B in order to perform a certain action, in the first example, device A is coupled to device B, or in the second example, device A is coupled to device B via an intervening component C, in which case the intervening component C does not substantially alter the functional relationship between device A and device B, and device B is controlled by device A via the control signal generated by device A.

[0044] Circuits or devices described herein as comprising several components may instead be adapted to be coupled to such components in order to form the described circuit element or device. For example, a structure described as comprising one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may instead comprise only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources in order to form the described structure, either during or after manufacturing, for example, by an end user and / or a third party.

[0045] While some components may be described in this application as specific processing techniques, these components may be interchangeable for components of other processing techniques. The circuits described in this application are reconfigurable, including the substituted components, to provide functionality at least partially similar to the functionality available before the component substitution. Unless otherwise specified, components indicated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the indicated resistor. For example, a resistor or capacitor indicated and described in this application as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor indicated and described in this application as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes, respectively, as single resistors or capacitors.

[0046] The use of the term "ground voltage potential" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings herein. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value. Modifications to the examples described within the claims are possible, and other examples are possible.

Claims

1. 1. A system for detecting the power of a signal, comprising: an antenna configured to transmit a first signal; an amplifier coupled to the antenna, the amplifier configured to receive the first signal and provide a second signal based on the first signal; a peak detector coupled to the amplifier, A transistor pair, a first transistor having a first control terminal configured to receive the first differential component of the second signal, a first current terminal, and a second current terminal; a second transistor including a second control terminal configured to receive a second differential component of the differential signal, a third current terminal coupled to the first current terminal to form an output node of the peak detector configured to provide a third signal, and a fourth current terminal coupled to the second current terminal; the transistor pair, a parallel resistive-capacitive circuit having a first end coupled to the first current terminal and the third current terminal and a second end configured to be coupled to a voltage supply; the peak detector, an automatic gain control (AGC) circuit coupled to an output node of the peak detector and to the amplifier, the AGC circuit configured to provide a gain control signal to the amplifier based on the third signal; Including, the system.

2. 10. The system of claim 1, the parallel resistive-capacitive circuit includes a resistor having a first end coupled to the first current terminal and the third current terminal and a second end coupled to the voltage supply.

3. 3. The system of claim 2, the parallel resistive-capacitive circuit further includes a capacitor having a first end coupled to the first end of the resistor and a second end configured to be coupled to the voltage supply.

4. 10. The system of claim 1, The system further comprising a mixer coupled to the amplifier, the mixer configured to receive the second signal and to provide a fourth signal based on the second signal.

5. 5. The system of claim 4, The system further comprising: a filter coupled to the mixer, the filter configured to receive the fourth signal and to provide a fifth signal based on the fourth signal.

6. 6. The system of claim 5, The system further includes an analog-to-digital converter (ADC) coupled to the filter and the AGC circuit, the ADC configured to provide a sixth signal to the AGC circuit based on the fifth signal.

7. 10. The system of claim 1, The system further includes a comparator coupled to the peak detector, the comparator configured to receive the third signal and to output a trigger signal based on a comparison of the third signal with a threshold signal.

8. 1. An apparatus comprising: A transistor pair, a first transistor having a first control terminal configured to receive a first component of the differential signal and a first current terminal; a second transistor having a second control terminal configured to receive a second component of the differential signal and a second current terminal coupled to the first current terminal to form an output node configured to output a third signal; the transistor pair, a parallel resistive-capacitive circuit having a first end coupled to the first current terminal and the second current terminal, and a second end configured to be coupled to a voltage supply; 1. An apparatus comprising:

9. 9. The apparatus of claim 8, The apparatus further includes a resistor having a first end coupled to the first current terminal and the second current terminal and a second end configured to be coupled to the voltage supply.

10. 10. The apparatus of claim 9, The apparatus further includes a capacitor having a first end coupled to the first end of the resistor and a second end configured to be coupled to the voltage supply.

11. 9. The apparatus of claim 8, 1. An apparatus, wherein a first component of the differential signal is configured to generate a first current in the first transistor and a second component of the differential signal is configured to generate a second current in the second transistor.

12. 12. The apparatus of claim 11, The apparatus, wherein the first current comprises a first DC current signal and a first AC current signal.

13. 13. The apparatus of claim 12, The apparatus, wherein the second current comprises a second DC current signal and a second AC current signal.

14. 14. The apparatus of claim 13, The apparatus, wherein a third signal at the output node is proportional to the first DC current signal and the second DC current signal.

15. 1. A system comprising: an antenna configured to transmit a first signal; an amplifier coupled to the antenna, the amplifier configured to receive the first signal and provide a second signal, the second signal being a differential signal, based on the first signal; a mixer coupled to the amplifier, the mixer configured to receive the second signal and provide a third signal based on the second signal; a filter coupled to the mixer, the filter configured to receive the third signal and to provide a fourth signal based on the third signal; and an analog-to-digital converter (ADC) coupled to the filter, the ADC configured to provide a fifth signal based on the fourth signal; and a peak detector coupled to the amplifier, the peak detector configured to receive the second signal and to provide a sixth signal based on the second signal; a comparator coupled to the peak detector, the comparator configured to receive the sixth signal and to output a trigger signal based on a comparison of the sixth signal with a threshold signal; an automatic gain control (AGC) circuit coupled to the comparator and the amplifier, the AGC circuit configured to provide a gain control signal to the amplifier based on the trigger signal; Including, The peak detector a pair of transistors having respective current terminals coupled to each other, each transistor of the pair having a control terminal configured to receive a respective component of the differential signal; a parallel resistive-capacitive circuit having a first end coupled to a respective current terminal of the transistor pair and a second end configured to be coupled to a voltage supply; Including, the system.

16. 16. The system of claim 15, The transistor pair a first metal oxide semiconductor field effect transistor (MOSFET) having a first gate terminal as the respective control terminal, a first drain terminal as the respective current terminal, and a first source terminal; a second MOSFET having a second gate terminal as the respective control terminal, a second drain terminal as the respective current terminal, and a second source terminal coupled to the first source terminal, the second drain terminal being coupled to the first drain terminal; Including, The peak detector a first input node formed by the first gate terminal; a second input node formed by the second gate terminal; an output node formed by the first drain terminal and the second drain terminal, the output node configured to output the sixth signal proportional to the power of the first signal and the second signal; Including, the system.

17. 17. The system of claim 16, the parallel resistive-capacitive circuit includes a resistor having a first end coupled to the first drain terminal and the second drain terminal and a second end configured to be coupled to the voltage supply.

18. 18. The system of claim 17, the parallel resistive-capacitive circuit further includes a capacitor having a first end coupled to the first end of the resistor and a second end configured to be coupled to the voltage supply.

19. 17. The system of claim 16, The system is configured such that the second signal generates a first drain current in the first MOSFET and a second drain current in the second MOSFET.

20. 20. The system of claim 19, The system, wherein the first drain current comprises a first DC current signal and a first AC current signal, and the second drain current comprises a second DC current signal and a second AC current signal.

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