Integrated test circuit, and test device and method for testing integrated circuit
Patent Information
- Application Number
- JP2022172369
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-10-29
- Filing Date
- 2022-10-27
- Publication Date
- 2025-07-17
AI Technical Summary
The high cost and inefficiency of system-level testing for integrated circuits, particularly microcontrollers, due to the significant overhead and routing costs associated with implementing multiple ring oscillators for performance measurement.
A method and apparatus that utilizes a ring oscillator circuit with multiple logic paths connected through input multiplexers, forming an original loop to reduce routing costs and self-activate the oscillator, thereby eliminating the need for additional control signals and feedback lines.
Reduces routing costs, allows for efficient performance testing of integrated circuits by forming a functional ring oscillator without additional area overhead, and provides accurate performance representation with reduced oscillation frequency variation.
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Abstract
Description
Technical Field
[0001] Embodiments generally relate to integrated circuits, test apparatuses and methods for testing integrated circuits.
Background Art
[0002] For example, integrated circuits for vehicles, such as microcontrollers (MCUs), must meet high quality standards and are therefore thoroughly tested. Performance screening is part of this testing. In performance screening, the performance of an integrated circuit is the maximum clock frequency of the integrated circuit under worst-case (i.e., worst-case conditions). Circuits (e.g., chips) that do not pass the performance screening are typically sorted out and excluded.
[0003] However, the performance of, for example, a microcontroller is related to a number of device parameters and ambient conditions. In the case of direct performance measurement, a comprehensive system-level test would be required to test all application cases in which the microcontroller is used. However, system-level testing is associated with a lot of effort and huge test costs for mass-produced products with high cost pressure, such as microcontrollers.
[0004] Therefore, test structures are usually used to indirectly measure performance. However, when indirect measurements are used to specify parameters (here performance, etc.), the accuracy of the measurement is significantly affected by the quality of the test structure. One type of test structure that can achieve high accuracy is a ring oscillator (RO), especially a functional ring oscillator formed from gates provided for its normal function within an integrated circuit. Here, appropriate lateral inputs are supplied to the gates of the scan flip-flops provided within the integrated circuit (e.g., for performing other tests and for normal operation), thereby causing these gates to form a logic path.
[0005] However, implementing numerous ring oscillators (also known as functional ring oscillators) within an integrated circuit typically results in significant overhead, particularly routing costs. Therefore, a more efficient approach to testing the performance of integrated circuits is desired. [Overview of the Initiative] [Means for solving the problem]
[0006] According to one embodiment, an integrated circuit is presented which has at least one ring oscillator circuit, the at least one ring oscillator circuit having a plurality of logic paths, each logic path having one path input side, one path output side, and one input-side multiplexer having an output side connected to the path input side of the logic path, each of these logic paths being assigned a successor logic path, starting with a first logic path, this assignment is made by connecting the path output side of the logic path to the data input side of the input-side multiplexer of the successor logic path, the last logic path of these logic paths being assigned the first logic path as the successor logic path, and for each logic path, the input-side multiplexer is configured to connect the data input side of the input-side multiplexer to the path input side of the logic path when a control signal indicating test mode is supplied to the input-side multiplexer.
[0007] According to another embodiment, a test apparatus and method for testing integrated circuits as described above are presented.
[0008] The drawings are not intended to reproduce the actual size and situation, but rather to illustrate the principles of various different embodiments. Hereafter, various embodiments will be described in relation to the following drawings. [Brief explanation of the drawing]
[0009] [Figure 1]This figure shows an integrated circuit (or chip) according to one embodiment. [Figure 2] This is a diagram showing a ring oscillator. [Figure 3] This diagram shows a circuit that forms a functional ring oscillator within an integrated circuit. [Figure 4] This diagram shows the routing cost on the chip when implementing three functional ring oscillators, each formed from three logical paths. [Figure 5] This figure shows an example of a subset of a chip's logical paths, where responsiveness is determined by a single path delay pattern. [Figure 6] This figure shows an original loop ring oscillator according to one embodiment. [Figure 7] This figure shows the reduction in routing costs in the example shown in Figure 4. [Figure 8] This figure shows an integrated circuit according to one embodiment. [Modes for carrying out the invention]
[0010] The following detailed description relates to the accompanying drawings illustrating details and embodiments. These embodiments are described in detail so that those skilled in the art can carry out the invention. Other embodiments are also possible, and these embodiments can be modified in structural, logical and electrical terms without departing from the constituent elements of the invention. The different embodiments are not necessarily mutually exclusive, and different embodiments can be combined with each other to obtain new embodiments. Within the framework of this specification, the terms “connected,” “linked,” and “joined” are used to describe direct and indirect connections, direct or indirect connections, and direct or indirect combinations.
[0011] Figure 1 shows an integrated circuit (or chip) 100 according to one embodiment.
[0012] The integrated circuit 100 is, for example, a microcontroller for an ECU (electronic control unit) in a vehicle, or a chip card module for chip cards of various form factors.
[0013] As is typical, the integrated circuit 100 has a plurality of logic gates 101 (AND gates, NOR gates, exclusive OR gates, inverters, etc.) interconnected via connecting lines. The logic gates 101 are cells from a chip design library and may be more complex circuits (e.g., composite gates).
[0014] The integrated circuit further includes a flip-flop 103 connected to logic gate 101. At least a portion of the flip-flop 103 is provided as a scan flip-flop, allowing a test pattern for testing the integrated circuit to be loaded onto the scan flip-flop. The scan flip-flop is a D flip-flop with a multiplexer attached to its input side, in which case one input side of the multiplexer functions as the function input side D and the other input side is used as the scan-in input side (SI). The test pattern is pushed to the flip-flop 103, for example, via one or more test input pins 102 (each via the scan-in input side). A scan-enable signal (or test-enable signal, not shown in Figure 1) switches the scan flip-flop's multiplexer from the data input side (D) to the scan-in input side (SI) for testing. The scan-enable signal is a general signal that is the same for all scan flip-flops (and therefore does not need to be routed separately).
[0015] One way to measure performance is to use a chain of logic gates 101 (or generally cells) already provided within the integrated circuit 100 to form a ring oscillator.
[0016] Figure 2 shows the ring oscillator 200.
[0017] The ring oscillator 200 has a chain of logic gates 201, 202, and 203 (generally cells) connected in series. Each logic gate 201, 202, and 203 has an input side and an output side that connect each logic gate 201, 202, and 203 to the chain, and the output side of the last logic gate 203 in the chain is connected to the input side of the first logic gate 201 in the chain via a return line (i.e., a feedback line or feedback connection) 204. The other input side of the logic gates 201, 202, and 203 (e.g., the second input side of a NAND gate or the second input side of a NOR gate), hereafter referred to as the lateral input side, is set to a fixed value, and each logic gate 201, 202, and 203 forms an inverter with respect to the input side and output side that connect each logic gate 201, 202, and 203 to the chain. If the number of logic gates N is odd, the chain as a whole has an inverting effect, and the loop formed with the chain oscillates via the return line 204.
[0018] The inputs to the side inputs of logic gates 201, 202, and 203, which make them function as inverters, are called side inputs. These side inputs together form a single side input pattern. These are supplied by scan flip-flop 103 and loaded appropriately (by storing an appropriate test pattern containing the side input pattern in the scan flip-flop). If it is not possible to make a gate with appropriate side inputs function as an inverter (e.g., an AND gate), the side inputs are selected so that they have a non-inverting effect (i.e., simply act as buffers), the number of logic gates 201, 202, and 203 is adjusted, or an inverter is provided in the return line. This results in an inverting characteristic again as a whole, and the loop oscillates.
[0019] The frequency of such vibrations, i.e., the oscillation frequency of the ring oscillator thus formed, can be observed and used to test the performance of integrated circuit 100. The quality of the test is related to the information content of the oscillation frequency of ring oscillator 100, i.e., the quality of the test must represent as accurately as possible the timing characteristics (and thus the performance) of the entire chip. However, especially when the chain of formed logic gates fits well with the chip design, the oscillation frequency typically correlates well with the performance of the integrated circuit. Nevertheless, typically, a large number of ring oscillators are required.
[0020] The ring oscillator described while referring to FIG. 2 is a so-called functional ring oscillator, i.e., a functional pass ring oscillator, i.e., it is formed from a plurality of logic gates 101 as described above, and these logic gates 101 are provided within the integrated circuit (for its normal function, i.e., for normal operation, different from the test operation). This avoids the ring oscillator causing additional area cost and energy cost as in the case where the ring oscillator is formed from additional logic gates (i.e., not formed from the originally provided logic gates).
[0021] FIG. 3 shows a circuit for forming a functional ring oscillator within an integrated circuit.
[0022] As described while referring to FIG. 2, the combinational logic path 302 (i.e., the functional path) is formed by a chain of logic gates supplied with appropriate lateral inputs. The feedback is performed via a return line 303 connected to the input side of the (input-side) multiplexer 304 (to which an inverter is provided if the combinational logic path 302 is not self-inverting).
[0023] As described above, the basic idea of the functional ring oscillator is that the functional combinational logic path 302 provided for the normal functions of the integrated circuit (i.e., by design) can be seen as being used to form a ring oscillator.
[0024] The multiplexer 304 on the input side of the path enables switching from the functional mode (i.e., the use of the logic path 302 for normal operation, here the input side "0" of the multiplexer) to the oscillation mode. In the oscillation mode, the multiplexer 304 supplies the signal of the feedback line to the logic path 302 (here the input side "1" of the multiplexer 304). For normal operation, the multiplexer 304 passes, for example, the input signal from the input-side flip-flop 306 (which may be a flip-flop of a memory or a register) through the logic path 302. The output of the logic path 302 is sent to the output-side flip-flop 307 (e.g., a flip-flop of a memory or a register). The input-side flip-flop 306 is also referred to as the launch flip-flop.
[0025] The oscillation frequency of the ring oscillator can be observed via the measurement terminal 305.
[0026] As described above, appropriate lateral inputs for forming the logic path 302 are applied to the logic gates forming the logic path 302. For this purpose, an industrial automatic test pattern generation (ATPG: Automatic Test Pattern Generation) tool can be used in the path delay mode. The ATPG tool is executed on a test device (i.e., a test computer) and supplies test patterns to the integrated circuit via the test pin 102. Thus, by setting all lateral inputs to stable values, the ATPG tool gives reactivity to the logic path 302.
[0027] In this way, testing using functional ring oscillators can be easily incorporated into normal industrial test flows by applying design-feedback (DFT) techniques.
[0028] The functional ring oscillator accurately represents the actual chip characteristics without generating significant area overhead. The only additional components required to form the ring oscillator are the multiplexer 304 and the return line 303.
[0029] Each functional ring oscillator on the chip can be activated by an individual central control signal 308 ("enable" signal), which is routed in the integrated circuit to a multiplexer 304. Since not all ring oscillators should be activated simultaneously during testing, such control signals are separate for each functional ring oscillator. This approach incurs high routing costs for routing the control signals 308. This can be avoided by an architecture in which the ring oscillators activate themselves. In this architecture, some scan flip-flops provided on the chip are used to activate the ring oscillators, with different scan flip-flops used for activation of different ring oscillators. This eliminates the need for control connections to a central control device on the chip.
[0030] However, in order to measure the frequency at the GPIO pin, an observation signal must be guided from the output side 305 through the chip to the GPIO pin, and further routing costs are incurred for the return line (or feedback line) 303 that connects the termination point (output side) of the logic path 302 to the starting point (input side).
[0031] Figure 4 shows the routing cost on chip 400 when implementing three functional ring oscillators consisting of three logic paths 401, 402, and 403, passing through line 404 for the enable signal, line 405 for the observation signal, and return line 406. The multiplexers at the input side of logic paths 401, 402, and 403, through which line 404 for the enable signal and return line 406 are connected, are not shown for clarity.
[0032] In this example, both line 404 for the enable signal and line 405 for the observation signal are connected to the central control unit 407. Line 405 for the observation signal may also be connected to an output pin located elsewhere than the central control unit 407. However, the routing cost remains the same in this case as well.
[0033] When there are only a few ring oscillators on a chip, the role of routing cost is minimal. However, in today's CMOS technology, process changes, especially changes within the chip, typically require numerous test structures distributed across the chip to cover process-change-induced variations and detect the overall performance of the chip. However, adding multiple, for example, hundreds of, ring oscillators to the chip increases routing costs. Furthermore, to reduce test costs, the test duration must be short.
[0034] Ultimately, a compromise is made between the number of test structures (i.e., ring oscillators in this case) and the high routing cost to those test structures.
[0035] In particular, the return line 406 incurs significantly high routing costs, especially for logic paths 401, 402, and 403 that extend over long distances on the chip 400. In this case, additional buffers are typically required to achieve appropriate edge steepness. This, in turn, necessitates additional logic circuits in relation to the length of the return line.
[0036] Various embodiments present approaches to reduce the routing costs of functional ring oscillators.
[0037] This is achieved, according to various different embodiments, by combining two or more logical paths 401, 402, and 403 to form a functional ring oscillator without requiring a long return line. Specifically, this is done by replacing (at least a large portion of) the return line with a logical path, thereby making it additionally unnecessary. That is, the logical path specifically forms both the forward and return directions in a ring oscillator, which will hereafter also be referred to as the "original loop (Natuerliche-Schleife)" ring oscillator. Such a ring oscillator is a ring oscillator formed by a loop, and its components are, in any case, located on the chip according to the "original," i.e., the function provided for the chip. By combining this approach so that the functional ring oscillator is self-activating, routing costs can be further reduced.
[0038] As described above, the logic path 302 is given reactivity using the ATPG tool by setting all the lateral inputs of the logic gates forming the logic path 302 to static values, which allows an oscillation signal to be generated in the ring oscillator formed by the logic path, or allows an oscillation signal to pass through the ring oscillator. This reactivity is thus given via a robust path delay pattern that is loaded (e.g., pushed) into a set of scan flip-flops by the ATPG tool.
[0039] Typically, the space of such ATPG path delay patterns is large enough, and therefore sufficient degrees of freedom, so that all lateral inputs to the logic paths forming a functional ring oscillator can be appropriately selected (e.g., consistent with the ring oscillator). An ATPG path delay pattern selected to give responsiveness to the logic paths to a ring oscillator on a chip typically gives responsiveness to multiple logic paths on the chip. This allows selection from all these responsive logic paths, particularly to form the original loop, i.e., to replace at least some of the feedback to the logic paths for which the ATPG path delay pattern was originally selected to give responsiveness.
[0040] Figure 5 shows an example of a subset of the chip's logic paths where responsiveness is given by a single ATPG path delay pattern.
[0041] As can be seen from the example in Figure 5, the multiple logical paths from which selection can be made are distributed across the chip and have different lengths.
[0042] In the simplest case, according to one embodiment, two logical paths are used, which are given responsiveness by the same ATPG path delay pattern and extend in different directions, as shown in Figure 6.
[0043] Figure 6 shows an original loop ring oscillator 600 according to one embodiment.
[0044] The original loop ring oscillator 600 has a first (combined) logic path 601 and a second (combined) logic path 602, which are each formed by a chain of logic gates to which appropriate lateral inputs are supplied (i.e., resulting in responsiveness for logic paths 601 and 602).
[0045] Each of the logic paths 601 and 602 is provided with a multiplexer 603 or 604 on its input side, which enables switching from functional mode (i.e., using the logic path for normal operation, in this case the input side "0" of the multiplexer) to oscillation mode.
[0046] For normal operation, multiplexers 603 and 604 pass input signals from each input flip-flop (transmitter flip-flop) 605 and 606 (which may be memory or register flip-flops) through logic paths 601 and 602. The outputs of each logic path 601 and 602 are sent to each output flip-flop 607 and 608 (for example, memory or register flip-flops).
[0047] The output side of the first logic path 601 is connected to the data input side of the input-side multiplexer 604 of the second logic path 602, and the multiplexer 604 switches to allow this to pass through in oscillation mode (i.e., test mode) (in this case, input side "1" of the multiplexer 604). Similarly, the output side of the second logic path 602 is connected to the data input side of the input-side multiplexer 603 of the first logic path 601, and the multiplexer 603 switches to allow this to pass through in oscillation mode (in this case, input side "1" of the multiplexer 603). In other words, in oscillation mode, a loop is formed, and in this case, the two directions of this loop are formed by the two logic paths 601 and 602.
[0048] By forming a ring oscillator using the original loop, routing costs can be significantly reduced.
[0049] Figure 7 shows the reduction in routing costs in the example shown in Figure 4.
[0050] As explained with reference to Figure 6, an original loop ring oscillator consisting of two logic paths 701 and 702 (corresponding to logic paths 401 and 402 in Figure 4 on chip 400) is formed on chip 700.
[0051] To connect the output side of the first logic path 701 to the input-side multiplexer of the second logic path 702, and to connect the output side of the second logic path 702 to the input-side multiplexer of the first logic path 701, only a short track 706 is required instead of the return track 406 for the two logic paths 401 and 402. As shown in Figure 4, the multiplexers on the input side of logic paths 701, 702, and 703 are not shown for clarity.
[0052] Furthermore, in this example, the observation line 405 from the output side of the first logic paths 401, 701 to the central control units 407, 707 is omitted. The observation line 705 can be placed at an appropriate point in the entire ring oscillator, for example, thereby keeping routing costs low. The enable signal line 704 leading to the central control unit 707 can be avoided by self-activating the switching of the input-side multiplexer.
[0053] The above approach of forming a functional ring oscillator using the original loop is particularly advantageous for long logical paths, which will require long return lines and many buffers along those lines. It should be considered that a single original loop can also be formed from two or more logical paths when, from a routing cost perspective, connecting three or more logical paths is advantageous.
[0054] By forming a functional ring oscillator using the original loop, it becomes possible to average out the voltage drops that occur, which could otherwise lead to measurement errors. In other words, the oscillation frequency is measured in a test mode where additional voltage drops may occur between chip partitions that are active only in test mode. The original loop averages out the effects of the voltage drops, reducing the resulting errors.
[0055] Furthermore, when two or more logic paths are combined, the oscillation frequency is reduced. The design implies a maximum frequency that the chip can physically support. Accordingly, the oscillation frequency of the ring oscillator should be below this physical boundary. However, if logic paths with short delays are used, the oscillation frequency becomes extremely high. By using the original loop, the ring oscillator as a whole has a relatively long logic path (first logic path 601 + second logic path 602 in the example in Figure 6), thus reducing the oscillation frequency, and also allowing monitoring of the shorter logic paths that are part of the original loop.
[0056] The approach of forming an original loop on a logical path is also applicable to bus connections of data buses on a chip, provided that the bus has unidirectional lines in both directions. The data bus transmits data signals through the chip. Such data bus signals can affect the maximum performance of the chip. A bus with unidirectional lines has a leading line (transmitting line) and a return line (receiving line). Therefore, an original line ring oscillator can be formed by connecting two lines according to the approach described above. Here, the transmit line and the receive line (which, for example, consist of a chain of buffers) are used to form the loop.
[0057] In summary, according to various different embodiments, an integrated circuit (e.g., a chip) like the one shown in Figure 8 is provided.
[0058] Figure 8 shows the integrated circuit 800.
[0059] The integrated circuit has at least one ring oscillator circuit 801.
[0060] The ring oscillator circuit 801 has multiple logic paths 802, each logic path having one path input side 803, one path output side 804, and one input side multiplexer 805, the input side multiplexer 805 having an output side 806 connected to the path input side 803 of the logic path.
[0061] Each of these logical paths 802 is assigned a subsequent logical path, starting with the first logical path. This assignment is made by connecting the path output side 804 of the logical path to the data input side 807 of the input side multiplexer 805 of the subsequent logical path, where the first logical path is assigned as the subsequent logical path for the last logical path in these logical paths.
[0062] The input-side multiplexer 805 is configured such that when a control signal 808 indicating test mode is supplied to the input-side multiplexer (the control input side of the input-side multiplexer), the input-side multiplexer connects the data input side 807 to the path input side 803 of the logical path (to which the input-side multiplexer belongs).
[0063] In other words, a ring oscillator is formed when multiple logic paths are connected sequentially in test mode, creating a loop (and therefore no return line is needed).
[0064] In normal operation mode (i.e., non-test mode), logical paths that are connected sequentially in test mode are, for example, separated. In other words, logical paths are connected sequentially for testing purposes, and these logical paths are not connected (at least not directly) in normal operation mode, i.e., they do not cooperate (directly). That is, none of these logical paths receive the processing results of another logical path. These logical paths are bit logical paths according to various different embodiments.
[0065] As described above, the approach in Figure 8 allows for reduced routing costs (which is particularly important when there are many ring oscillators, thereby improving scalability and enabling a larger number of test structures), averages out voltage drops, keeps the resulting oscillation frequencies low, and consequently allows for monitoring more functional logic paths.
[0066] The following sections will show various different examples.
[0067] Example 1 is an integrated circuit as described with reference to Figure 8.
[0068] Example 2 is an integrated circuit according to Example 1, in which each logic path has a chain of multiple logic gates connected sequentially and / or has a data bus line.
[0069] Example 3 is an integrated circuit according to Example 1 or Example 2, in which the input-side multiplexer has a further data input side, and the input-side multiplexer is configured to connect the further data input side to the path input side of the logic path when a control signal indicating the normal operating mode is supplied to the input-side multiplexer.
[0070] Example 4 is an integrated circuit according to one of Examples 1 to 3, in which the input-side multiplexer is a 2:1 multiplexer.
[0071] Example 5 is an integrated circuit according to one of Examples 1 to 4, wherein at least one ring oscillator circuit has a test output side, and the integrated circuit has a test terminal connected to this test output side.
[0072] Example 6 is an integrated circuit according to Example 5, in which the test output side is located at the connection point between one of the logic paths and the subsequent logic path.
[0073] Embodiment 7 is an integrated circuit according to any one embodiment of Embodiments 1 to 6, wherein each logic path among the plurality of logic paths has a chain of a plurality of logic gates connected sequentially, and one or more scan flip-flops are assigned to at least one ring oscillator circuit, and the one or more scan flip-flops are connected to the input side of at least some of the logic gates of the logic path chain of the ring oscillator circuit as follows: that is, when one or more scan flip-flops store a predefined lateral input pattern, the logic gates of the logic path chain are connected to each logic path of the ring oscillator circuit such that they form a serial 1-bit logic path from the input side of the first logic gate of the logic path chain to the output side of the last logic gate of the logic path chain.
[0074] Example 8 is an integrated circuit according to any one of Examples 1 to 7, wherein each logic path is assigned a scan flip-flop group containing at least one scan flip-flop, and the input-side multiplexer of the logic path is controlled to connect the data input side of the input-side multiplexer to the path input side of the logic path in relation to the bits stored by at least one scan flip-flop in the scan flip-flop group assigned to the logic path.
[0075] Embodiment 9 is an integrated circuit according to any one embodiment of Embodiments 1 to 8, which has a plurality of ring oscillator circuits, each of which has a plurality of logic paths, each logic path having one path input side, one path output side, and one input-side multiplexer having an output side connected to the path input side of the logic path, each of these logic paths is assigned a subsequent logic path, starting with the first logic path, this assignment is done by connecting the path output side of the logic path to the data input side of the input-side multiplexer of the subsequent logic path, the first logic path is assigned as the subsequent logic path to the last of these logic paths, and for each logic path, the input-side multiplexer is configured to connect the data input side of the input-side multiplexer to the path input side of the logic path when a control signal indicating test mode is supplied to the input-side multiplexer.
[0076] Example 10 is an integrated circuit according to Example 9, in which each logic path of each ring oscillator circuit is assigned one scan flip-flop group containing at least one scan flip-flop, and the input-side multiplexer of the logic path is controlled to connect the data input side of the input-side multiplexer to the path input side of the logic path in relation to the bits stored by at least one scan flip-flop in the scan flip-flop group assigned to the logic path, and different scan flip-flop groups are assigned to the logic paths of different ring oscillator circuits.
[0077] Example 11 is a test apparatus for testing an integrated circuit according to Example 9 or Example 10. This test apparatus is configured to supply a control signal indicating a test mode to the input multiplexer of the logic path of each ring oscillator circuit and each logic path, and to receive a measurement signal generated in test mode by the ring oscillator circuit.
[0078] Example 12 is a test apparatus according to Example 11, which has an analytical instrument configured to determine the performance of an integrated circuit from the oscillation frequency of a received measurement signal.
[0079] Example 13 is a method for testing an integrated circuit according to Example 9 or Example 10, which includes supplying a control signal indicating a test mode to the input multiplexer of the logic path of each ring oscillator circuit and each logic path, and receiving a measurement signal generated in test mode by the ring oscillator circuit.
[0080] While the present invention has been illustrated and described with particular reference to specific embodiments, those familiar with the art will understand that many modifications to the structure and details can be made without departing from the essence and scope of the invention as defined by the following claims. Therefore, the scope of the invention is determined by the appended claims and is intended to include all modifications that fall within the literal meaning or equivalent scope of the claims. [Explanation of Symbols]
[0081] 100 Integrated Circuits 101 Logic Gates 102 Test Input Pins 103 Flip-flops 200 Ring Oscillator 201-203 Logic Gates 204 Return track 302 Logical Path 303 Return track 304 Multiplexer 305 Measurement terminals 306 Transmitter's flip-flop 307 Output flip-flop 308 Control signal 400 chips 401-403 Logical Path 404 Enable Track 405 Observation Track 406 Return track 407 Central Control Unit 600 Original Loop Ring Oscillator 601,602 Logical Paths 603,604 Multiplexer 605,606 Input-side flip-flops 607, 608 Output flip-flops 700 chips 701-703 Logical Path 704 Enable Track 705 Observation Track 706 Return track 707 Central Control Unit 800 Integrated Circuits 801 Ring Oscillator Circuit 802 Logical Path 803 Path Input Side 804 Path output side 805 Input Multiplexer 806 Multiplexer Output Side 807 Multiplexer data input side 808 Control signal
Claims
1. An integrated circuit, wherein the integrated circuit has at least one ring oscillator circuit, and the at least one ring oscillator circuit has a plurality of logic paths, each logic path having one path input side, one path output side, and one input side multiplexer connected to the path input side of the logic path and having an output side, to each logic path of the logic paths, a first logic path is started and each subsequent logic path is assigned, and the assignment is made by connecting the path output side of the logic path to the data input side of the input side multiplexer of the subsequent logic path, and the first logic path is assigned as a subsequent logic path to the last logic path of the logic paths, for each logic path, when a control signal indicating a test mode is supplied to the input side multiplexer, the input side multiplexer is configured to connect the data input side of the input side multiplexer to the path input side of the logic path, Integrated circuit.
2. Each logic path has a chain of a plurality of logically connected logic gates connected in succession and / or has a data bus line, The integrated circuit according to claim 1.
3. The input side multiplexer has a further data input side, and when a control signal indicating a normal operation mode is supplied to the input side multiplexer, the input side multiplexer is configured to connect the further data input side to the path input side of the logic path, The integrated circuit according to claim 1.
4. The input side multiplexer is a 2-to-1 multiplexer, The integrated circuit according to claim 1.
5. The at least one ring oscillator circuit has a test output side, and the integrated circuit has a test terminal connected to the test output side, The integrated circuit according to claim 1.
6. The test output side is arranged at a connection between one of the logic paths of the logic paths and the subsequent logic path, The integrated circuit according to claim 5.
7. Each of the plurality of logical paths has a chain of a plurality of logically connected gates connected in sequence, and one or more scan flip-flops are assigned to the at least one ring oscillator circuit. The one or more scan flip-flops are connected to at least a part of the input sides of the gates of the chain of the logical path of the ring oscillator circuit as follows: that is, when the one or more scan flip-flops store a pre-defined lateral input pattern, for each logical path of the ring oscillator circuit, the gates of the chain of the logical path are connected so as to form a serial 1-bit logical path from the input side of the first gate of the chain of the logical path to the output side of the last gate of the chain of the logical path. The integrated circuit according to claim 1.
8. One scan flip-flop group including at least one scan flip-flop is assigned to each logical path, and the input-side multiplexer of the logical path is controlled such that the input-side multiplexer connects the data input side of the input-side multiplexer to the path input side of the logical path in relation to the bit stored by the at least one scan flip-flop of the scan flip-flop group assigned to the logical path. The integrated circuit according to claim 1.
9. The integrated circuit has a plurality of ring oscillator circuits, and each ring oscillator circuit has a plurality of logical paths, and each logical path has one path input side, one path output side, and one input-side multiplexer having an output side connected to the path input side of the logical path. To each logical path of the logical paths, a first logical path starts and each subsequent logical path is assigned. The assignment is made by connecting the path output side of the logical path to the data input side of the input-side multiplexer of the subsequent logical path, and the first logical path is assigned as a subsequent logical path to the last logical path of the logical path. For each logic path, when a control signal indicating the test mode is supplied to the input-side multiplexer, the input-side multiplexer is configured to connect the data input side of the input-side multiplexer to the path input side of the logic path. The integrated circuit according to claim 1.
10. One scan flip-flop group including at least one scan flip-flop is assigned to each logic path of each ring oscillator circuit. The input-side multiplexer of the logic path is controlled to connect the data input side of the input-side multiplexer to the path input side of the logic path in relation to the bit stored by the at least one scan flip-flop among the scan flip-flop groups assigned to the logic path, and different scan flip-flop groups are assigned to the logic paths of different ring oscillator circuits. The integrated circuit according to claim 9.
11. A test apparatus for testing the integrated circuit according to claim 9 or 10, wherein the test apparatus is configured to supply the control signal indicating the test mode to the input-side multiplexer of the logic path of each ring oscillator circuit and each logic path, and to receive the measurement signal generated in the test mode by the ring oscillator circuit. Test apparatus.
12. The test apparatus has an analyzer configured to determine the performance of the integrated circuit from the oscillation frequency of the received measurement signal. The test apparatus according to claim 11.
13. A method for testing the integrated circuit according to claim 9 or 10, the method comprising: supplying, for each ring oscillator circuit and each logic path, the control signal indicating the test mode to the input-side multiplexer of the logic path of the ring oscillator circuit; receiving the measurement signal generated in the test mode by the ring oscillator circuit. A method including the above steps.