Battery voltage monitoring device
Patent Information
- Application Number
- JP2022060951
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-03-31
- Publication Date
- 2025-04-16
- Estimated Expiration
- 2042-03-31
AI Technical Summary
Existing battery systems face challenges in miniaturization due to the external configuration of voltage monitoring circuits, which complicates integration into the system.
A battery voltage monitoring device is integrated into the system, utilizing a signal input section, analog-to-digital conversion circuit, and clock generation circuits with N-type and P-type transfer transistors to monitor bus bar voltages, allowing for miniaturization and efficient voltage measurement.
Enables the integration of a battery voltage monitoring device within the battery system, facilitating miniaturization while effectively monitoring bus bar voltages.
Smart Images
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a battery voltage monitoring device. [Background technology]
[0002] A battery system uses a battery pack in which battery cells are connected in series or parallel. The voltage of each battery cell is monitored by a battery voltage monitoring device such as a battery voltage monitoring IC (Integrated Circuit) that measures the voltage of each battery cell. In addition, the individual battery cells in the battery pack are physically connected to the bus bars with screws. If the screws connecting the bus bars become loose, problems such as voltage abnormalities and heat generation may occur, so the battery pack is equipped with a circuit that monitors the voltage at both ends of the bus bars. A technology for monitoring the voltage across a bus bar in a battery system is known (see, for example, Patent Document 1). According to this technology, the battery system has a voltage detection unit that monitors the voltage across the bus bar. The circuit of the voltage detection unit is not included in the battery voltage monitoring IC or control IC, but is configured as a discrete component outside the IC. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-83960 Summary of the Invention [Problem to be solved by the invention]
[0004] There is a demand for smaller battery systems, but with the technology mentioned above, the circuit that monitors the voltage at both ends of the bus bar is configured outside the IC, making it difficult to meet this demand. An object of the present invention is to provide a battery voltage monitoring device that can be built into a battery system. [Means for solving the problem]
[0005] A battery voltage monitoring device of the present invention is a battery voltage monitoring device comprising: a signal input unit having input terminals to which the voltages at both ends of a bus bar are input; and an analog-to-digital conversion circuit that measures the differential voltage between the voltages at both ends, and monitors the voltage at both ends of the bus bar; a clock generation circuit that generates, based on an input reference clock, a plurality of clocks including a first clock, a second clock having an opposite polarity to the first clock, a third clock that is at a low level while the first clock is at a high level, and a fourth clock that is at a high level while the second clock is at a low level and has an opposite polarity to the third clock; a first N-type transfer transistor and a second N-type transfer transistor that are N-type field effect transistors having their sources and back gates connected; and a first P-type transfer transistor and a second P-type transfer transistor that are P-type field effect transistors having their sources and back gates connected; a switch circuit, the drain of one transfer transistor being connected to the source of the other transfer transistor, the source of one transfer transistor being connected to a first signal input terminal, the drain of the other transfer transistor being connected to a first signal output terminal, and the drain of one of the second N-type transfer transistor and the second P-type transfer transistor being connected to the source of the other transfer transistor, the source of one transfer transistor being connected to the first signal input terminal, and the drain of the other transfer transistor being connected to a second signal output terminal; a first control signal generation circuit, configured to be able to generate a first control signal that controls the on / off state of the first P-type transfer transistor based on a voltage of the first signal input terminal and the second clock, and to generate a second control signal that controls the on / off state of the second P-type transfer transistor based on the voltage of the first signal input terminal and the fourth clock;a second control signal generation circuit configured to be able to generate a third control signal that controls the on / off state of the first N-type transfer transistor based on the voltage of the first signal input terminal and the first clock, and a fourth control signal that controls the on / off state of the second N-type transfer transistor based on the voltage of the first signal input terminal and the third clock. [Effects of the Invention]
[0006] According to the present invention, it is possible to provide a battery voltage monitoring device that can be built into a battery system. [Brief explanation of the drawings]
[0007] [Figure 1] 1 is a diagram illustrating an example of the configuration of a battery system according to an embodiment of the present invention. [Figure 2] FIG. 4 is a diagram illustrating an example of a second ADC of the battery system according to the present embodiment. [Figure 3] 2 is a diagram illustrating an example of a first switch included in a battery voltage monitoring IC of the battery system according to the present embodiment. FIG. [Figure 4] FIG. 3 is a diagram illustrating details of a first switch. [Figure 5] FIG. 4 is a diagram showing an example of a timing chart of a first switch of the battery system according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0008] Next, a battery voltage monitoring device according to the present embodiment will be described with reference to the drawings. The embodiment described below is merely an example, and the embodiments to which the present invention is applied are not limited to the following embodiment. In all the drawings for explaining the embodiments, the same reference numerals are used for components having the same functions, and repeated explanations will be omitted. Furthermore, in this application, "based on XX" means "based on at least XX," and includes cases where it is based on other elements in addition to XX. Furthermore, "based on XX" is not limited to cases where XX is used directly, but also includes cases where it is based on XX that has been calculated or processed. "XX" is any element (for example, any information).
[0009] (Embodiment) (Battery system) Fig. 1 is a diagram showing an example of the configuration of a battery system according to an embodiment of the present invention. In Fig. 1, the battery system 1 includes a battery cell 10-1, a battery cell 10-2, a bus bar 20, a battery voltage monitoring IC 30-1, and a battery voltage monitoring IC 30-2. The battery voltage monitoring IC 30-1 and the battery voltage monitoring IC 30-2 are examples of battery voltage monitoring devices. Battery cell 10-1 is, for example, n batteries (n is an integer greater than 0) connected in series. Battery cell 10-2 is, for example, n batteries connected in series. An example of the batteries is a lithium battery. The bus bar 20 is an electrode that connects the battery cell 10-1 and the battery cell 10-2. The battery voltage monitoring IC 30-1 has terminals C0 to Cn to which the voltages VC0 and VCn across the battery cell 10-1 and the voltages VC1 to VCn-1 between the n batteries included in the battery cell 10-1 are input via resistors R. Resistor R is a protective resistor.
[0010] The battery voltage monitoring IC 30-1 has a terminal VSS and a terminal VDD to which the voltages VC0 and VCn across the battery cell 10-1 are input. The battery voltage monitoring IC 30-1 is fabricated on, for example, a P-type semiconductor substrate. The battery voltage monitoring IC 30-1 includes a multiplexer 32-1 connected to each of terminals C0 to Cn, a first analog-to-digital converter (ADC) 34-1 connected to the multiplexer 32-1, terminals BB and TB to which the voltages VBB and VTB at both ends of the bus bar 20 are input via a resistor R, and a second ADC 36-1 connected to terminals BB and TB and measuring the differential voltage between voltages VBB and VTB.
[0011] The battery voltage monitoring IC 30-2 has terminals C0 to Cn to which the voltages VC0 and VCn across the battery cell 10-2 and the voltages VC1 to VCn-1 between each of the n batteries included in the battery cell 10-2 are input via resistors R. The battery voltage monitoring IC 30-2 has a terminal VSS and a terminal VDD to which the voltages VC0 and VCn across the battery cell 10-2 are input. The battery voltage monitoring IC 30-2 includes a multiplexer 32-2 connected to each of terminals C0 to Cn, a first ADC 34-2 connected to the multiplexer 32-2, terminals BB and TB to which the voltages VBB and VTB at both ends of the bus bar (not shown) are input via a resistor R, and a second ADC 36-2 connected to terminals BB and TB and measuring the differential voltage between voltages VBB and VTB.
[0012] Since the battery voltage monitoring IC 30-1 and the battery voltage monitoring IC 30-2 have the same configuration, the battery voltage monitoring IC 30-1 will be mainly described below. 2 is a diagram showing an example of a second ADC 36-1 in the battery system according to this embodiment. The second ADC 36-1 measures the voltage between terminals BB and TB to which voltages VBB and VTB at both ends of the bus bar 20 are input via resistor R. The second ADC 36-1 must measure positive and negative voltages because charging and discharging currents flow through the bus bar 20. Therefore, the second ADC 36-1 has a different input switch configuration than the first ADC 34-1. An oversampling ADC can be used for the second ADC 36-1. Figure 2 shows an example of an integration circuit at the first stage of an oversampling ADC.
[0013] The second ADC36-1 includes a first switch SW1, a second switch SW2, a third switch SW3-1, a third switch SW3-2, a first sampling capacitance Cs-1, a second sampling capacitance Cs-2, a first capacitance Cd-1, a second capacitance Cd-2, an amplifier AMP, a first integral capacitance Cint-1, a second integral capacitance Cint-2, a reset switch SW-1, and a reset switch SW-2.
[0014] The first switch SW1 includes switches SW1-11, SW1-12, SW1-21, and SW1-22. Terminal BB and the first sampling capacitor Cs-1 are connected via switch SW1-11. Terminal BB and the second sampling capacitor Cs-2 are connected via switch SW1-22. Terminal TB and the first sampling capacitor Cs-1 are connected via switch SW1-21. Terminal BB and the second sampling capacitor Cs-2 are connected via switch SW1-12. The second switch SW2 includes a switch SW2-11, a switch SW2-12, a switch SW2-21, and a switch SW2-22. The third switch SW3-1 includes a switch SW3-11 and a switch SW3-12. The third switch SW3-2 includes a switch SW3-21 and a switch SW3-22.
[0015] The terminal RFP to which the reference voltage Vrfp is applied and the first capacitor Cd-1 are connected via the switches SW2-11 and SW3-12, and the terminal RFP and the second capacitor Cd-2 are connected via the switches SW2-11 and SW3-21. The terminal RFP and the first capacitor Cd-1 are connected via the switch SW2-22 and the switch SW3-11, and the terminal RFP and the second capacitor Cd-2 are connected via the switch SW2-22 and the switch SW3-22.
[0016] The terminal RFN to which the reference voltage Vrfn is applied and the first capacitor Cd-1 are connected via the switches SW2-12 and SW3-11, and the terminal RFN and the second capacitor Cd-2 are connected via the switches SW2-12 and SW3-22. The terminal RFN and the first capacitor Cd-1 are connected via the switches SW2-21 and SW3-12, and the terminal RFN and the second capacitor Cd-2 are connected via the switches SW2-21 and SW3-21.
[0017] The first sample capacitor Cs-1 and the second capacitor Cd-2 are grounded via a switch SWIC-2, and are connected to the non-inverting input terminal of the amplifier AMP via a switch SWI-1. The second sample capacitor Cs-2 and the first capacitor Cd-1 are grounded via a switch SWIC-1, and are connected to the inverting input terminal of the amplifier AMP via a switch SWI-2. A first integral capacitance Cint-1, a second integral capacitance Cint-2, a reset switch SW-1 and a reset switch SW-2 are connected to the input and output terminals of the amplifier AMP. The output of the amplifier AMP is input to the quantizer QUA via the next stage, for example, an amplifier, etc. The output of the quantizer QUA is input to the second switch SW2.
[0018] The operation of the second ADC 36-1 will be described. First, in order to discharge (reset) the first integral capacitor Cint-1 and the second integral capacitor Cint-2 by short-circuiting both ends of each of them, the reset switches SW-1 and SW-2 are closed once, and then opened after a predetermined time, and maintained in the open state for a predetermined period of time.
[0019] During this predetermined period, the clock signal Φcko turns on the switches SW1-11 and SW1-12 of the first switch SW1, the switch SW3-11 of the third switch SW3-1, the switch SW3-21 of the third switch SW3-2, the switches SWIC-1 and SWIC-2. The clock signal Φcko will be described later.
[0020] During this predetermined period, the clock signal Φcko turns off the switches SW1-21 and SW1-22 of the first switch SW1, the switch SW3-12 of the third switch SW3-1, the switch SW3-22 of the third switch SW3-2, the switches SWI-1 and SWI-2. The terminal voltage VBB of the bus bar 20 is applied to the first sample capacitor Cs-1, and a charge is stored in the first sample capacitor Cs-1. The terminal voltage VTB of the bus bar 20 is applied to the second sample capacitor Cs-2, and a charge is stored in the second sample capacitor Cs-2.
[0021] The quantizer QUA is reset to an initial value. Depending on the initial value of the quantizer QUA, the second switch SW2 selects either the switches SW2-12 and SW2-21 or the switches SW2-11 and SW2-22. By selecting either the switches SW2-12 and SW2-21 or the switches SW2-11 and SW2-22, the reference voltage Vrfp or the reference voltage Vrfn is applied to the first capacitance Cd-1 and the second capacitance Cd-2, and charge is stored in the first capacitance Cd-1 and the second capacitance Cd-2.
[0022] In each of the first sample capacitor Cs-1 and the second capacitor Cd-2, the other end opposite the switches SW1-11 and SW3-21 is biased to the input common by turning on the switch SWIC-2. In each of the second sample capacitor Cs-2 and the first capacitor Cd-1, the other end opposite the switches SW1-12 and SW3-11 is biased to the input common by turning on the switch SWIC-1.
[0023] Next, as the clock signal Φcko changes, the switches SW1-11 and SW1-12 of the first switch SW1, the switch SW3-11 of the third switch SW3-1, the switch SW3-21 of the third switch SW3-2, the switches SWIC-1 and SWIC-2 are turned off. As the clock signal Φcko changes, the switches SW1-21 and SW1-22 of the first switch SW1, the switch SW3-12 of the third switch SW3-1, the switch SW3-22 of the third switch SW3-2, the switches SWI-1 and SWI-2 are turned on.
[0024] By turning off the input common switch SWIC-1 and the input common switch SWIC-2, the first sample capacitor Cs-1, the second sample capacitor Cs-2, the first capacitor Cd-1, and the second capacitor Cd-2, which are biased to the input common, are disconnected from the input common. By turning on the switch SWI-1, the first sample capacitor Cs-1, the second sample capacitor Cs-2, the first capacitor Cd-1, and the second capacitor Cd-2 are connected to the amplifier AMP.
[0025] The terminal voltage VTB of the bus bar 20 is applied to the first sample capacitor Cs-1, and charge is stored in the first sample capacitor Cs-1. The charge stored in the first sample capacitor Cs-1, together with the previously stored charge, is transferred to the integral capacitor Cint-2 located between the input and output of the amplifier AMP, and the voltage is integrated. Furthermore, the charge stored in the second capacitor Cd-2 is transferred to the integral capacitor Cint-2 located between the input and output of the amplifier AMP, and the voltage is integrated.
[0026] The terminal voltage VBB of the bus bar 20 is applied to the second sample capacitor Cs-2, and charge is stored in the second sample capacitor Cs-2. The charge stored in the second sample capacitor Cs-2, together with the previously stored charge, is transferred to the integral capacitor Cint-1 located between the input and output of the amplifier AMP, and the voltage is integrated. Furthermore, the charge stored in the first capacitor Cd-1 is transferred to the integral capacitor Cint-1 located between the input and output of the amplifier AMP, and the voltage is integrated, thereby performing an integral operation.
[0027] The integral operation changes the output of the quantizer QUA. The change in the output of the quantizer QUA causes the second switch SW2 to switch between the switches SW2-12 and SW2-21, and the switches SW2-11 and SW2-22. By switching between the switches SW2-12 and SW2-21 and the switches SW2-11 and SW2-22, the reference voltage Vrfp or the reference voltage Vrfn is applied to the first capacitor Cd-1 and the second capacitor Cd-2, and charge is stored in the first capacitor Cd-1 and the second capacitor Cd-2. This is repeated for a predetermined period thereafter each time the clock signal Φcko changes. By repeating the above operations, an analog-to-digital converted value corresponding to the input busbar voltage Vbb can be obtained from the series of stream data output by the quantizer QUA. Because an analog-to-digital converted value corresponding to the busbar voltage Vbb can be obtained, the voltage across the busbar 20 can be monitored.
[0028] The first switch SW1 will now be described. Since the polarities of the terminal voltages VTB and VBB of the bus bar 20 are reversed, the first switch SW1 is configured to prevent a reverse current flow. FIG. 3 is a diagram showing an example of a first switch included in the battery voltage monitoring IC of the battery system according to this embodiment. The first switch SW1 includes a first clock bootstrap circuit 40-1, a second clock bootstrap circuit 40-2, a first switch 41-1, a second switch 41-2, and a non-overlapping clock generation circuit 42. The first switch 41-1 and the second switch 41-2 are examples of switch circuits, and the non-overlapping clock generation circuit 42 is an example of a clock generation circuit. The non-overlapping clock generating circuit 42 has a clock input terminal 42-1 and eight clock output terminals 42-21, 42-22, 42-23, 42-24, 42-25, 42-26, 42-27, and 42-28.
[0029] The first clock bootstrap circuit 40-1 has a first step-down circuit 40-11 and a first step-up circuit 40-12. The first step-down circuit 40-11 is an example of a first control signal generation circuit, and the first step-up circuit 40-12 is an example of a second control signal generation circuit. The first clock bootstrap circuit 40-1 is configured to be able to generate control signals that control the on and off states of FETs (Field Effect Transistors) included in each of the first step-down circuit 40-11 and the first step-up circuit 40-12.
[0030] The first switch 41-1 includes a first MOS (metal-oxide-semiconductor field-effect transistor) switch 41-11 and a second MOS switch 41-12. The first MOS switch 41-11 has at least one NMOS transistor Mns11 (first N-type transfer transistor Mns11) which is an N-type FET, and at least one PMOS transistor Mps11 (first P-type transfer transistor Mps11) which is a P-type FET. As an example, Fig. 3 shows a case where the first MOS switch 41-11 has one NMOS transistor Mns11 and one PMOS transistor Mps11.
[0031] The second MOS switch 41-12 has at least one NMOS transistor Mns21 (second N-type transfer transistor Mns21) which is an N-type FET, and at least one PMOS transistor Mps21 (second P-type transfer transistor Mps21) which is a P-type FET. Fig. 3 shows, as an example, a case where the second MOS switch 41-12 has one NMOS transistor Mns21 and one PMOS transistor Mps21.
[0032] The second clock bootstrap circuit 40-2 has a second step-down circuit 40-21 and a second step-up circuit 40-22. The second step-down circuit 40-21 is an example of a third control signal generation circuit, and the second step-up circuit 40-22 is an example of a fourth control signal generation circuit. The second clock bootstrap circuit 40-2 is configured to be able to generate control signals that control the on and off states of the FETs included in each of the second step-down circuit 40-21 and the second step-up circuit 40-22. The second switch 41-2 has a first MOS switch 41-21 and a second MOS switch 41-22.
[0033] The first MOS switch 41-21 has at least one NMOS transistor Mns12 (third N-type transfer transistor Mns12) which is an N-type FET, and at least one PMOS transistor Mps12 (third P-type transfer transistor Mps12) which is a P-type FET. As an example, Fig. 3 shows a case where the first MOS switch 41-21 has one NMOS transistor Mns12 and one PMOS transistor Mps12.
[0034] The second MOS switch 41-22 has at least one NMOS transistor Mns22 (fourth N-type transfer transistor Mns22) which is an N-type FET, and at least one PMOS transistor Mps22 (fourth P-type transfer transistor Mps22) which is a P-type FET. Fig. 3 shows, as an example, a case where the second MOS switch 41-22 has one NMOS transistor Mns22 and one PMOS transistor Mps22.
[0035] The non-overlapping clock generation circuit 42 is connected to a first clock bootstrap circuit 40-1, which is connected to a first switch 41-1. More specifically, the first step-down circuit 40-11 is connected to the clock output terminals 42-21 and 42-22. The first step-down circuit 40-11 is also connected to the gate of the PMOS transistor Mps11 included in the first MOS switch 41-11 and the gate of the PMOS transistor Mps21 included in the second MOS switch 41-12. The first boost circuit 40-12 is connected to the clock output terminals 42-23 and 42-24. The first boost circuit 40-12 is also connected to the gate of the NMOS transistor Mns11 included in the first MOS switch 41-11 and the gate of the NMOS transistor Mns21 included in the second MOS switch 41-12.
[0036] The first step-down circuit 40-11 has two capacitors Ccn and CcnH, two P-type field effect transistors (FETs) PMOS transistors Mp21 and Mp11, and two Zener diodes ZD-1 and ZD-2. The capacitor Ccn is an example of a first capacitor, and the capacitor CcnH is an example of a second capacitor. The PMOS transistor Mp21 is an example of a first P-type FET, and the PMOS transistor Mp11 is an example of a second P-type FET. The Zener diode ZD-1 is an example of a first Zener diode, and the Zener diode ZD-2 is an example of a second Zener diode. One end of the capacitor Ccn is connected to the clock output terminal 42-21. One end of the capacitor CcnH is connected to the clock output terminal 42-22. The other end of the capacitor Ccn is connected to the drain of the PMOS transistor Mp21 and the gate of the PMOS transistor Mp11. This connection point is referred to as node N1.
[0037] The source of PMOS transistor Mp21 is connected to the source of PMOS transistor Mp11. The PMOS transistors Mp11 and Mp21 have their sources and back gates connected together. That is, the source and back gate of PMOS transistor Mp21 are connected to the source and back gate of PMOS transistor Mp11. This connection point is referred to as node N3. The drain of PMOS transistor Mp11 is connected to the other end of capacitor CcnH and the gate of PMOS transistor Mp21. This connection point is referred to as node N2.
[0038] A Zener diode ZD-2 is further connected between the node N1 and the node N3. The Zener diode ZD-2 has an anode connected to the node N1 and a cathode connected to the node N3.
[0039] Furthermore, a Zener diode ZD-1 is further connected between the node N2 and the node N3. The Zener diode ZD-1 has an anode connected to the node N2 and a cathode connected to the node N3.
[0040] The first step-down circuit 40-11 configured in this manner operates as a step-down circuit that steps down and outputs an input voltage. The first step-down circuit 40-11 is configured to be able to output control signals that control the operating states of the PMOS transistors from nodes N1 and N2, respectively. The breakdown voltages of capacitors Ccn and CcnH are selected in consideration of the voltage input to the first step-down circuit 40-11.
[0041] The first boost circuit 40-12 has two capacitors Ccp and CcpL, two N-type field-effect transistors, NMOS transistors Mn21 and Mn11, and two Zener diodes ZD-3 and ZD-4. The capacitor Ccp is an example of a third capacitor, and the capacitor CcpL is an example of a fourth capacitor. The NMOS transistor Mn21 is an example of a first N-type FET, and the NMOS transistor Mn11 is an example of a first N-type FET. The Zener diode ZD-3 is an example of a third Zener diode, and the Zener diode ZD-4 is an example of a fourth Zener diode. One end of the capacitor Ccp is connected to the clock output terminal 42-23. One end of the capacitor CcpL is connected to the clock output terminal 42-24. The other end of the capacitor Ccp is connected to the drain of the NMOS transistor Mn21 and the gate of the NMOS transistor Mn11. This connection point is referred to as a node N4.
[0042] The source of the NMOS transistor Mn21 is connected to the source of the NMOS transistor Mn11. The NMOS transistors Mn21 and Mn11 have their sources and back gates connected together. That is, the source and back gate of the NMOS transistor Mn21 are connected to the source and back gate of the NMOS transistor Mn11. This connection point is referred to as node N6. The drain of the NMOS transistor Mn11 is connected to the other end of the capacitor CcpL and the gate of the NMOS transistor Mn21. This connection point is referred to as node N5.
[0043] A Zener diode ZD-4 is further connected between the node N4 and the node N6. The Zener diode ZD-4 has an anode connected to the node N6 and a cathode connected to the node N4. A Zener diode ZD-3 is further connected between the node N5 and the node N6. The Zener diode ZD-3 has an anode connected to the node N6 and a cathode connected to the node N5.
[0044] The first boost circuit 40-12 configured in this manner operates as a boost circuit that boosts and outputs an input voltage. The first boost circuit 40-12 is configured to be able to output control signals that control the operating state of the NMOS transistors from nodes N4 and N5, respectively. The breakdown voltages of capacitors Ccp and CcpL are selected in consideration of the voltage input to the first boost circuit 40-12.
[0045] The first step-down circuit 40-11 and the first step-up circuit 40-12 are connected to each other at nodes N3 and N6. Nodes N3 and N6 are also connected to a connection point between terminal BB, the source of NMOS transistor Mns11 of the first MOS switch 41-11, and the source of NMOS transistor Mns21 of the second MOS switch 41-12. Node N3, node N6, terminal BB, the source of NMOS transistor Mns11, and the source of NMOS transistor Mns21 form the same node.
[0046] In the first switch 41-1, the first MOS switch 41-11 includes one NMOS transistor Mns11 and one PMOS transistor Mps11. In the first MOS switch 41-11, the NMOS transistor Mns11 and the PMOS transistor Mps11 are connected. The NMOS transistor Mns11 and the PMOS transistor Mps11 have their sources and back gates connected to each other.
[0047] The source of the NMOS transistor Mns11 is connected to the terminal BB and the back gate of the NMOS transistor Mn11. The drain of the NMOS transistor Mns11 is connected to the source of the PMOS transistor Mps11. The drain of the PMOS transistor Mps11 is connected to the signal output terminal To1. The gate of the NMOS transistor Mns11 is connected to the cathode of the Zener diode ZD-3, the drain of the NMOS transistor Mn11, the gate of the NMOS transistor Mn21, and the other end of the capacitor CcpL. The gate of the PMOS transistor Mps11 is connected to the anode of the Zener diode ZD-1, the drain of the PMOS transistor Mp11, the gate of the PMOS transistor Mp21, and the other end of the capacitor CcnH.
[0048] The non-overlapping clock generation circuit 42 is connected to a second clock bootstrap circuit 40-2, which is connected to a second switch 41-2. More specifically, the second step-down circuit 40-21 is connected to the clock output terminals 42-27 and 42-28. The second step-down circuit 40-21 is also connected to the gate of the PMOS transistor Mps12 (third P-type transfer transistor Mps12) included in the first MOS switch 41-21 and the gate of the PMOS transistor Mps22 (fourth P-type transfer transistor Mps22) included in the second MOS switch 41-22. The second boost circuit 40-22 is connected to the clock output terminals 42-25 and 42-26. The second boost circuit 40-22 is also connected to the gate of the NMOS transistor Mns12 (third N-type transfer transistor Mns12) included in the first MOS switch 41-21 and the gate of the NMOS transistor Mns22 (fourth N-type transfer transistor Mpn22) included in the second MOS switch 41-22.
[0049] The second step-down circuit 40-21 has two capacitors Ccn and CcnH, two P-type field effect transistors (FETs) PMOS transistors Mp12 and Mp22, and two Zener diodes ZD-7 and ZD-8. The capacitor Ccn is an example of a first capacitor, and the capacitor CcnH is an example of a second capacitor. The PMOS transistor Mp22 is an example of a first P-type FET, and the PMOS transistor Mp12 is an example of a second P-type FET. The Zener diode ZD-7 is an example of a first Zener diode, and the Zener diode ZD-2 is an example of a second Zener diode. One end of the capacitor Ccn is connected to the clock output terminal 42-28. One end of the capacitor CcnH is connected to the clock output terminal 42-27. The other end of the capacitor Ccn is connected to the drain of the PMOS transistor Mp22 and the gate of the PMOS transistor Mp12. This connection point is referred to as node N7.
[0050] The source of the PMOS transistor Mp22 is connected to the source of the PMOS transistor Mp12. The PMOS transistors Mp12 and Mp22 have their sources and back gates connected together. That is, the source and back gate of the PMOS transistor Mp22 are connected to the source and back gate of the PMOS transistor Mp12. This connection point is referred to as node N9. The drain of the PMOS transistor Mp12 is connected to the other end of the capacitor CcnH and the gate of the PMOS transistor Mp22. This connection point is referred to as node N8. A Zener diode ZD-8 is further connected between the node N7 and the node N9. The Zener diode ZD-8 has an anode connected to the node N7 and a cathode connected to the node N9.
[0051] Furthermore, a Zener diode ZD-7 is further connected between the node N8 and the node N9. The Zener diode ZD-7 has an anode connected to the node N8 and a cathode connected to the node N9.
[0052] The second step-down circuit 40-21 configured in this manner operates as a step-down circuit that steps down and outputs an input voltage. The second step-down circuit 40-21 is configured to be able to output control signals that control the operating states of the PMOS transistors from nodes N7 and N8, respectively. The breakdown voltages of capacitors Ccn and CcnH are selected in consideration of the voltage input to the second step-down circuit 40-21.
[0053] The second boost circuit 40-22 has two capacitors Ccp and CcpL, two N-type field-effect transistors, NMOS transistors Mn12 and Mn22, and two Zener diodes ZD-5 and ZD-6. The capacitor Ccp is an example of a third capacitor, and the capacitor CcpL is an example of a fourth capacitor. The NMOS transistor Mn22 is an example of a first N-type FET, and the NMOS transistor Mn12 is an example of a second N-type FET. The Zener diode ZD-5 is an example of a third Zener diode, and the Zener diode ZD-8 is an example of a fourth Zener diode.
[0054] One end of the capacitor Ccp is connected to the clock output terminal 42-26. One end of the capacitor CcpL is connected to the clock output terminal 42-25. The other end of the capacitor Ccp is connected to the drain of the NMOS transistor Mn22 and the gate of the NMOS transistor Mn12. This connection point is referred to as a node N10.
[0055] The source of the NMOS transistor Mn22 is connected to the source of the NMOS transistor Mn12. The NMOS transistors Mn12 and Mn22 have their sources and back gates connected together. That is, the source and back gate of the NMOS transistor Mn22 are connected to the source and back gate of the NMOS transistor Mn12. This connection point is referred to as node N12. The drain of the NMOS transistor Mn12 is connected to the other end of the capacitor CcpL and the gate of the NMOS transistor Mn22. This connection point is referred to as node N11.
[0056] A Zener diode ZD-5 is further connected between the node N11 and the node N12. The Zener diode ZD-5 has a cathode connected to the node N11 and an anode connected to the node N12. Furthermore, a Zener diode ZD-6 is further connected between the node N10 and the node N12. The Zener diode ZD-6 has a cathode connected to the node N10 and an anode connected to the node N12.
[0057] The second boost circuit 40-22 configured in this manner operates as a boost circuit that boosts and outputs an input voltage. The second boost circuit 40-22 is configured to be able to output control signals that control the operating states of the NMOS transistors from nodes N10 and N11, respectively. The breakdown voltages of the capacitors Ccp and CcpL are selected in consideration of the voltage input to the second boost circuit 40-22.
[0058] The second step-down circuit 40-21 and the second step-up circuit 40-22 are connected to each other at nodes N9 and N12. Nodes N9 and N12 are also connected to the connection point between terminal TB, the source of NMOS transistor Mns12 of the first MOS switch 41-21, and the source of NMOS transistor Mns22 of the second MOS switch 41-22. Node N9, node N12, terminal TB, the source of NMOS transistor Mns12, and the source of NMOS transistor Mns22 form the same node.
[0059] In the second switch 41-2, the first MOS switch 41-21 includes one NMOS transistor Mns12 and one PMOS transistor Mps12. In the first MOS switch 41-21, the NMOS transistor Mns12 and the PMOS transistor Mps12 are connected together. The NMOS transistor Mns12 and the PMOS transistor Mps12 have their sources and back gates connected together.
[0060] The source of the NMOS transistor Mns12 is connected to the terminal TB and the back gate of the NMOS transistor Mn12. The drain of the NMOS transistor Mns12 is connected to the source of the PMOS transistor Mps12. The drain of the PMOS transistor Mps12 is connected to the signal output terminal To2. The gate of the NMOS transistor Mns12 is connected to the cathode of the Zener diode ZD-5, the drain of the NMOS transistor Mn12, the gate of the NMOS transistor Mn22, and the other end of the capacitor CcpL. The gate of the PMOS transistor Mps12 is connected to the anode of the Zener diode ZD-7, the drain of the PMOS transistor Mp12, the gate of the PMOS transistor Mp22, and the other end of the capacitor CcnH.
[0061] 4 is a diagram showing the details of the first switch. As an example, the first MOS switch 41-11 included in the first switch 41-1 will be described. As described above, the first MOS switch 41-11 has an NMOS transistor Mns11 and a PMOS transistor Mps11. Furthermore, the first MOS switch 41-11 has a parasitic diode Diod1 and a parasitic diode Diod2. In the first MOS switch 41-11, the NMOS transistor Mns11 and the PMOS transistor Mps11 are connected. The NMOS transistor Mns11 has its source and backgate connected to the anode of the parasitic diode Diod1, and its drain connected to the cathode of the parasitic diode Diod1. The PMOS transistor Mps11 has its source and backgate connected to the cathode of the parasitic diode Diod2, and its drain connected to the anode of the parasitic diode Diod2.
[0062] The switch-on and switch-off cases will be described separately. When the switch is on, equations (1) and (2) hold. ΦnH=VBB+vd (1) ΦpL=VBB-vd (2) In equations (1) and (2), vd is a desired voltage, and vd>>|vth| (vth: threshold voltage of the MOS transistors (NMOS transistor Mns11, PMOS transistor Mps11)). The NMOS transistor Mns11 and the PMOS transistor Mps11 are in a conductive state and are turned on as a switch, resulting in Vil=VBB.
[0063] When the switch is off, equation (3) holds. ΦnH=ΦpL=VBB (3) As a result, the MOS is turned off. Since it was on before it turned off, CSS becomes VBB. After switching off, Vil becomes VTB. (1) When Vil = VTB < VBB, the PMOS transistor Mps11 is in the non-conducting state and the switch is off. (2) When Vil = VTB > VBB, the parasitic diode Diod2 is forward-biased, and the terminal Vil and CSS are conducting. CSS has a voltage higher than VBB, but the parasitic diode Diod1 is reverse-biased and there is no conduction between VBB and CSS. Since there is no conduction between VBB and Vil, the switch is off.
[0064] Returning to FIG. 3, the operation of the first switch SW1 will be described. The first switch SW1 generates four types of non-overlapping clocks from the clock signal Φcko in the non-overlap clock generation circuit 42. The first switch 41-1 and the second switch 41-2 switch and output the voltages VBB and VTB at both ends of the bus bar 20 to the output terminal Vi1 and the output terminal Vi2. The first clock bootstrap circuit 40-1 boosts or降压 the gate signals for controlling the on / off states of the NMOS transistor Mns11, PMOS transistor Mps11, NMOS transistor Mns21, and PMOS transistor Mps21 included in the first switch 41-1 by a voltage vd with reference to the voltage VBB of the bus bar 20. The second clock bootstrap circuit 40-2 boosts or降压 the gate signals for controlling the on / off states of the NMOS transistor Mnsb12, PMOS transistor Mps12, NMOS transistor Mns22, and PMOS transistor Mps22 included in the second switch 41-2 by a voltage vd with reference to the voltage VTB of the bus bar 20.
[0065] FIG. 5 is a diagram showing an example of the timing chart of the first switch of the battery system according to the present embodiment. A clock signal Φcko, which serves as a reference clock, is input from a clock input terminal 42-1 to the non-overlapping clock generation circuit 42. Based on the input clock signal Φcko input from the clock input terminal 42-1, the non-overlapping clock generation circuit 42 generates a plurality of different clocks, including clock signals Φnck, ΦnckH, Φpck, and ΦpckL. Clock signal ΦnckH is an example of a first clock, clock signal ΦpckL is an example of a second clock, clock signal Φnck is an example of a third clock, and clock signal Φpck is an example of a fourth clock. The clock signals Φnck, ΦnckH, Φpck, and ΦpckL transition between high level (hereinafter referred to as "H level") and low level (hereinafter referred to as "L level") at the timings shown in FIG.
[0066] Specifically, the clock signals Φnck and ΦnckH are generated at timings where they are not at H level for the same period. That is, the clock signal ΦnckH is at L level while the clock signal Φnck is at H level. The clock signals Φpck and ΦpckL are generated at timings where they are not at L level for the same period. That is, the clock signal ΦpckL is at H level while the clock signal Φpck is at L level. Furthermore, clock signals Φnck and Φpck are generated at timings where they have opposite polarities to each other. Furthermore, clock signals ΦnckH and ΦpckL are generated at timings where they have opposite polarities to each other. The voltage difference between the H level and the L level of input clock signals Φcko, Φnck, ΦnckH, Φpck, and ΦpckL is voltage vd.
[0067] The non-overlapping clock generating circuit 42 outputs the generated clock signals Φpck, ΦpckL, Φnck, and ΦnckH to clock output terminals 42-21, 42-22, 42-23, and 42-24, respectively. The clock signal Φpck input to the clock output terminal 42-21, the clock signal ΦpckL input to the clock output terminal 42-22, the clock signal Φnck input to the clock output terminal 42-23, and the clock signal ΦnckH input to the clock output terminal 42-24 are applied to the gate of the PMOS transistor Mps21 of the second MOS switch 41-12, the gate of the PMOS transistor Mps11 of the first MOS switch 41-11, the gate of the NMOS transistor Mns21 of the second MOS switch 41-12, and the gate of the NMOS transistor Mns11 of the first MOS switch 41-11, respectively.
[0068] In the first step-down circuit 40-11, the voltage VBB at the terminal BB is applied to the sources and back gates of the PMOS transistors Mp21 and Mp11, respectively. The PMOS transistors Mp21 and Mp11 operate exclusively in response to the input clock signals Φpck and ΦpckL. That is, when the PMOS transistor Mp21 is on, the PMOS transistor Mp11 is off, and when the PMOS transistor Mp11 is on, the PMOS transistor Mp21 is off. Note that the PMOS transistors Mp21 and Mp11 are allowed to be off for the same period.
[0069] Through the above operation, the voltages of the nodes N1 and N2 are controlled between the voltage VBB, which is a reference voltage, and a voltage (hereinafter referred to as a "down-regulated voltage") that is lower than this reference voltage. That is, the first step-down voltage circuit 40-11 generates a signal that sets the voltage VBB, which serves as the reference voltage, to an H level and the down-regulated voltage to an L level, based on the voltage VBB and the voltages of the clock signals Φpck and ΦpckL. The generated signals are output from nodes N1 and N2 as control signals that control the on / off states of PMOS transistors Mps21 and Mps11, respectively. The signal Φp1 output from node N1 is input to the gate of PMOS transistor Mps21. The signal ΦpL1 output from node N2 is input to the gate of PMOS transistor Mps11.
[0070] In the first boost circuit 40-12, the voltage VBB of the terminal BB is applied to the sources and back gates of the NMOS transistors Mn21 and Mn11, respectively. The NMOS transistors Mn21 and Mn11 operate exclusively in response to the input clock signals Φnck and ΦnckH. That is, when the NMOS transistor Mn21 is on, the NMOS transistor Mn11 is off, and when the NMOS transistor Mn11 is on, the NMOS transistor Mn21 is off. Note that the NMOS transistors Mn21 and Mn11 are allowed to be in the off state during the same period.
[0071] Through the above operation, the voltages of the nodes N4 and N5 are controlled between the voltage VBB as a reference voltage and a voltage (hereinafter referred to as a "boost adjustment voltage") that is higher than this reference voltage. That is, the first boost circuit 40-12 generates a signal that sets the voltage VBB, which serves as the reference voltage, to an L level and sets the boost adjustment voltage to an H level, based on the voltage VBB and the voltages of the clock signals Φnck and ΦnckH. The generated signals are output from nodes N4 and N5 as control signals that control the on / off states of NMOS transistors Mns11 and Mns21, respectively. The signal Φn1 output from node N4 is input to the gate of NMOS transistor Mns21. The signal ΦnH1 output from node N5 is input to the gate of NMOS transistor Mns11.
[0072] The first switch 41-1 functions as a switching device that can switch between an ON state and an OFF state based on signals Φp1, ΦpL1, Φn1, and ΦnH1 input from the first clock bootstrap circuit 40-1. In the ON state, the voltage VBB input to terminal BB is output from signal output terminal To1. On the other hand, in the OFF state, the voltage VBB input to terminal BB is not output from signal output terminal To1.
[0073] The first switch 41-1 establishes electrical continuity between the terminal BB and the signal output terminal To1 when the clock signal ΦpckL is at L level and the clock signal ΦnckH is at H level. The first switch 41-1 establishes electrical continuity between the terminal BB and the signal output terminal To2 when the clock signal Φpck is at L level and the clock signal Φnck is at H level. The first switch 41-1 is in the ON state when the terminal BB is electrically connected to the signal output terminal To1 or To2. The first switch 41-1 is in the OFF state during periods other than the above, specifically, during periods when a voltage equal to the voltage VBB is applied to the gates of the NMOS transistors Mns11, Mns21 and the PMOS transistors Mps11, Mps21.
[0074] The non-overlapping clock generating circuit 42 outputs the generated clock signals Φpck, ΦpckL, Φnck, and ΦnckH to clock output terminals 42-28, 42-27, 42-26, and 42-25, respectively. The clock signal Φpck input to the clock output terminal 42-28, the clock signal ΦpckL input to the clock output terminal 42-27, the clock signal Φnck input to the clock output terminal 42-26, and the clock signal ΦnckH input to the clock output terminal 42-25 are applied to the gate of the PMOS transistor Mps22 of the second MOS switch 41-22, the gate of the PMOS transistor Mps12 of the first MOS switch 41-21, the gate of the NMOS transistor Mns22 of the second MOS switch 41-22, and the gate of the NMOS transistor Mns12 of the first MOS switch 41-21, respectively.
[0075] In the second step-down circuit 40-21, the voltage VTB at the terminal TB is applied to the sources and back gates of the PMOS transistors Mp22 and Mp12, respectively. The PMOS transistors Mp22 and Mp12 operate exclusively in response to the input clock signals Φpck and ΦpckL. That is, when the PMOS transistor Mp22 is on, the PMOS transistor Mp12 is off, and when the PMOS transistor Mp12 is on, the PMOS transistor Mp22 is off. Note that the PMOS transistors Mp22 and Mp12 are allowed to be off for the same period.
[0076] Through the above operation, the voltages of nodes N7 and N8 are controlled between voltage VTB, which is a reference voltage, and a voltage (hereinafter referred to as a "down-regulated voltage") that is lower than this reference voltage. That is, based on voltage VTB and the voltages of clock signals Φpck and ΦpckL, second step-down circuit 40-21 generates a signal that sets voltage VTB, which serves as the reference voltage, to an H level and sets the down-regulated voltage to an L level. The generated signals are output from nodes N7 and N8, respectively, as control signals that control the on / off states of PMOS transistors Mps22 and Mps12. Signal Φp2 output from node N7 is input to the gate of PMOS transistor Mps22. Signal ΦpL2 output from node N8 is input to the gate of PMOS transistor Mps12.
[0077] In the second boost circuit 40-22, the voltage VTB of the terminal TB is applied to the sources and back gates of the NMOS transistors Mn22 and Mn12, respectively. The NMOS transistors Mn22 and Mn12 operate exclusively in response to the input clock signals Φnck and ΦnckH. That is, when the NMOS transistor Mn22 is on, the NMOS transistor Mn12 is off, and when the NMOS transistor Mn12 is on, the NMOS transistor Mn22 is off. Note that the NMOS transistors Mn22 and Mn12 are allowed to be off during the same period.
[0078] By the above operation, the voltages of the nodes N10 and N11 are controlled between the voltage VTB as a reference voltage and a voltage (hereinafter referred to as a "boost adjustment voltage") that is higher than the reference voltage. That is, the second boost circuit 40-22 generates a signal that sets the voltage VTB, which serves as the reference voltage, to an L level and sets the boost adjustment voltage to an H level based on the voltage VTB and the voltages of the clock signals Φnck and ΦnckH. The generated signals are output from nodes N10 and N11 as control signals that control the on / off states of NMOS transistors Mns12 and Mns22, respectively. The signal Φn2 output from node N10 is input to the gate of NMOS transistor Mns22. The signal ΦnH2 output from node N11 is input to the gate of NMOS transistor Mns12.
[0079] The second switch 41-2 functions as a switching device that can switch between an ON state and an OFF state based on the signals Φp2, ΦpL2, Φn2, and ΦnH2 input from the second clock bootstrap circuit 40-2. In the ON state, the voltage VTB input to the terminal TB is output from the signal output terminal To2. On the other hand, in the OFF state, the voltage VTB input to the terminal TB is not output from the signal output terminal To2.
[0080] The second switch 41-2 establishes electrical continuity between the terminal TB and the signal output terminal To2 during periods when the clock signal ΦpckL is at L level and the clock signal ΦnckH is at H level. The second switch 41-2 establishes electrical continuity between the terminal TB and the signal output terminal To1 during periods when the clock signal Φpck is at L level and the clock signal Φnck is at H level. The above-mentioned state in which the terminal TB is conductive with the signal output terminal To1 or the signal output terminal To2 is the ON state of the second switch 41-2. The second switch 41-2 is in the OFF state during periods other than the above, specifically during periods when a voltage equal to the voltage VTB is applied to the gates of the NMOS transistors Mns12 and Mns22 and the PMOS transistors Mps12 and Mps22.
[0081] As described above, the battery voltage monitoring device according to this embodiment can be incorporated into a battery system because it is configured to prevent reverse current flow even when a voltage difference is applied between the input and output of the switch while the switch circuit is in the off state. Because the current flowing through the busbar is reversed during charging and discharging, the voltage generated at both ends of the busbar is reversed in magnitude. In other words, the polarity is reversed during charging and discharging. The polarity of the terminal voltages VTB and VBB of the busbar 20 is reversed, which prevents reverse current flow in the switch circuit.
[0082] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and design changes and the like are also included within the scope that does not deviate from the gist of the present invention. For example, although the second ADC 36-1 of the battery voltage monitoring IC 30-1 is fabricated on the higher voltage side than the first ADC 34-1 in the above description, the present invention is not limited to this example. For example, the second ADC 36-1 of the battery voltage monitoring IC may be fabricated on the lower voltage side than the first ADC 34-1. [Explanation of symbols]
[0083] REFERENCE SIGNS LIST 1... battery system, 10-1, 10-2... battery cells, 20... bus bars, 30-1, 30-2... battery voltage monitoring ICs, 32-1, 32-2... multiplexers, 34-1, 34-2... first ADCs, 36-1, 36-2... second ADCs, 40-1... first clock bootstrap circuit, 40-2... second clock bootstrap circuit, 40-11... first step-down circuit, 40-12... first step-up circuit, 40-21... second step-down circuit, 40-22... second step-up circuit, 41-1... first switch, 41-2... second switch, 41-11, 41-21... first MOS switches, 41-12, 41-22... second MOS switches, 42... non-overlapping clock generation circuit, 42-1... clock input terminal, 42-21 to 42-28... clock output terminals
Claims
1. A battery voltage monitoring device comprising: a signal input unit having input terminals to which voltages at both ends of a bus bar are input; and an analog-to-digital conversion circuit that measures a differential voltage between the voltages at both ends, and monitors the voltages at both ends of the bus bar, a clock generation circuit that generates, based on an input reference clock, a plurality of clocks including a first clock, a second clock having an opposite polarity to the first clock, a third clock that is at a low level while the first clock is at a high level, and a fourth clock that is at a high level while the second clock is at a low level and has an opposite polarity to the third clock; a switch circuit having a first N-type transfer transistor and a second N-type transfer transistor, which are N-type field effect transistors having their sources and back gates connected together, and a first P-type transfer transistor and a second P-type transfer transistor, which are P-type field effect transistors having their sources and back gates connected together, wherein the drain of one of the first N-type transfer transistor and the first P-type transfer transistor is connected to the source of the other transfer transistor, the source of the one transfer transistor is connected to a first signal input terminal, and the drain of the other transfer transistor is connected to a first signal output terminal; and wherein the drain of one of the second N-type transfer transistor and the second P-type transfer transistor is connected to the source of the other transfer transistor, the source of the one transfer transistor is connected to the first signal input terminal, and the drain of the other transfer transistor is connected to a second signal output terminal; a first control signal generation circuit configured to be able to generate a first control signal that controls the on state and off state of the first P-type transfer transistor based on a voltage at the first signal input terminal and the second clock, and to be able to generate a second control signal that controls the on state and off state of the second P-type transfer transistor based on the voltage at the first signal input terminal and the fourth clock; a second control signal generation circuit configured to be able to generate a third control signal that controls the on state and off state of the first N-type transfer transistor based on a voltage of the first signal input terminal and the first clock, and to be able to generate a fourth control signal that controls the on state and off state of the second N-type transfer transistor based on the voltage of the first signal input terminal and the third clock; A battery voltage monitoring device comprising:
2. the clock generation circuit has a clock input terminal to which the reference clock is input, a first clock output terminal for outputting the first clock, a second clock output terminal for outputting the second clock, a third clock output terminal for outputting the third clock, and a fourth clock output terminal for outputting the fourth clock; the first control signal generation circuit includes: a first P-type FET which is a P-type field effect transistor having a source and a back gate connected to each other; a second P-type FET having a source connected to the source and back gate of the first P-type FET and its own back gate; a first capacitor having one end connected to the fourth clock output terminal and the other end connected to the drain of the second P-type FET and the gate of the first P-type FET; a second capacitor having one end connected to the second clock output terminal and the other end connected to the drain of the first P-type FET and the gate of the second P-type FET; a first Zener diode having an anode connected to the drain of the first P-type FET and a cathode connected to the source and back gate of the second P-type FET; and a second Zener diode having an anode connected to the drain of the second P-type FET and a cathode connected to the source and back gate of the first P-type FET, the second control signal generation circuit includes: a first N-type FET which is an N-type field effect transistor having a source and a back gate connected to each other; a second N-type FET having a source connected to the source and back gate of the first N-type FET and its own back gate; a third capacitor having one end connected to the third clock output terminal and the other end connected to the drain of the second N-type FET and the gate of the first N-type FET; a fourth capacitor having one end connected to the first clock output terminal and the other end connected to the drain of the first N-type FET and the gate of the first N-type FET; a third Zener diode having a cathode connected to the drain of the first N-type FET and an anode connected to the source and back gate of the first N-type FET; and a fourth Zener diode having a cathode connected to the drain of the second N-type FET and an anode connected to the source and back gate of the second N-type FET, a connection point between the first signal input terminal and the source of the one transfer transistor is connected to a first node and a second node; the first node is a node to which a source and a back gate of the first P-type FET, a source and a back gate of the second P-type FET, a cathode of the first Zener diode, and a cathode of the second Zener diode are connected; 2. The battery voltage monitoring device according to claim 1, wherein the second node is a connection point between a source and a back gate of the first N-type FET, a source and a back gate of the second N-type FET, an anode of the third Zener diode, and an anode of the fourth Zener diode.
3. the first control signal generating circuit has a third node and a fourth node; the second control signal generating circuit has a fifth node and a sixth node; the third node is a connection point between the drain of the first P-type FET of the first control signal generation circuit, the gate of the second P-type FET, the other end of the first capacitor, and the anode of the second Zener diode, the fourth node is a connection point between the drain of the second P-type FET of the first control signal generation circuit, the gate of the first P-type FET, the other end of the second capacitor, and the anode of the first Zener diode, the fifth node is a connection point among the drain of the first N-type FET of the second control signal generation circuit, the gate of the second N-type FET, the other end of the third capacitor, and the anode of the fourth Zener diode, the sixth node is a connection point among the drain of the second N-type FET of the second control signal generation circuit, the gate of the first N-type FET, the other end of the fourth capacitor, and the anode of the third Zener diode, the first P-type transfer transistor includes a gate connected to the third node; the second P-type transfer transistor includes a gate connected to the fourth node; the first N-type transfer transistor includes a gate connected to the fifth node; 3. The battery voltage monitoring device according to claim 2, wherein said second P-type transfer transistor includes a gate connected to said sixth node.
4. a third control signal generation circuit having the same configuration as the first control signal generation circuit, and generating a fifth control signal that is the same as the first control signal and a sixth control signal that is the same as the second control signal; a fourth control signal generation circuit having the same configuration as the second control signal generation circuit, and generating a seventh control signal having an opposite polarity to the fifth control signal and being at a low level while the fifth control signal is at a high level, and an eighth control signal having an opposite polarity to the sixth control signal and being at a low level while the sixth control signal is at a high level; the third control signal generating circuit has a seventh node and an eighth node; the fourth control signal generating circuit has a ninth node and a tenth node; the seventh node is a connection point among the drain of the second P-type FET of the third control signal generation circuit, the gate of the first P-type FET, the other end of the first capacitor, and the anode of the first Zener diode; the eighth node is a connection point between the drain of the first P-type FET, the gate of the second P-type FET, the other end of the second capacitor, and the anode of the second Zener diode of the third control signal generation circuit, the ninth node is a connection point among the drain of the second N-type FET of the fourth control signal generation circuit, the gate of the first N-type FET, the other end of the third capacitor, and the cathode of the third Zener diode, the tenth node is a connection point among the drain of the first N-type FET, the gate of the second N-type FET, the other end of the fourth capacitor, and the cathode of the fourth Zener diode of the fourth control signal generation circuit, the signal input unit further includes a second signal input terminal; the switch circuit further includes a third N-type transfer transistor and a fourth N-type transfer transistor, the sources of which are connected to the back gates of the transistors, and a third P-type transfer transistor and a fourth P-type transfer transistor, the sources of which are connected to the back gates of the transistors, a drain of one of the third N-type transfer transistor and the third P-type transfer transistor is connected to a source of the other transfer transistor, a source of the one transfer transistor is connected to the second signal input terminal, and a drain of the other transfer transistor is connected to a drain of one of the second N-type transfer transistor and the second P-type transfer transistor and to the second signal output terminal; a drain of one of the fourth N-type transfer transistor and the fourth P-type transfer transistor is connected to a source of the other transfer transistor, a source of the one transfer transistor is connected to the second signal input terminal, and a drain of the other transfer transistor is connected to a drain of one of the first N-type transfer transistor and the first P-type transfer transistor and to the first signal output terminal; the third P-type transfer transistor includes a gate connected to the seventh node when the first P-type FET includes a gate connected to the fourth node, and includes a gate connected to the eighth node when the first P-type FET includes a gate connected to the third node; the third N-type transfer transistor includes a gate connected to the seventh node when the first P-type FET includes a gate connected to the third node, and includes a gate connected to the eighth node when the first P-type FET includes a gate connected to the fourth node; the fourth P-type transfer transistor includes a gate connected to the ninth node when the first N-type FET includes a gate connected to the sixth node, and includes a gate connected to the tenth node when the first N-type FET includes a gate connected to the fifth node; 4. The battery voltage monitoring device according to claim 3, wherein the fourth N-type transfer transistor includes a gate connected to the ninth node when the first N-type FET includes a gate connected to the fifth node, and includes a gate connected to the tenth node when the first P-type FET includes a gate connected to the sixth node.
5. 5. The battery voltage monitoring device according to claim 1, wherein the first control signal generation circuit is configured to generate the first control signal and the second control signal, each of which includes a first level having the same voltage as that of the first signal input terminal and a second level having a voltage lower than that of the first level.
6. 6. The battery voltage monitoring device according to claim 1, wherein the second control signal generation circuit is configured to generate the third control signal and the fourth control signal, each of which includes a first level having the same voltage as that of the first signal input terminal and a third level having a voltage higher than that of the first level.