Radiation detector and radiation imaging system

Abstract

To provide a radiation detector with enhanced radiation tolerance.SOLUTION: A radiation detector has a pixel array in which pixels each having a radiation detector element that converts radiation into electric charge and an amplifying transistor that amplifies and outputs a signal from the radiation detector element are arranged in matrix form and a signal wiring provided on each pixel column. In the plan view, the signal wiring does not overlap with an active layer in which the amplifying transistors are arranged.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The present invention relates to a radiation detector and a radiation imaging system.

Background Art

[0002] Patent Document 1 discloses a method of improving the detection accuracy of energy rays by defining the thickness of the detection region of an energy ray detector (radiation detector).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A radiation detector may deteriorate when radiation is incident thereon.

[0005] An object of the present invention is to provide a radiation detector with enhanced radiation resistance.

Means for Solving the Problems

[0006] One aspect of the present disclosure is a pixel array in which pixels each having a radiation detection element that converts radiation into charge and an amplification transistor that amplifies and outputs a signal from the radiation detection element are arranged in a matrix, signal wirings provided for each pixel column, and in a plan view, the signal wirings do not overlap with an active layer in which the amplification transistors are arranged. A radiation detector characterized by

Effects of the Invention

[0007] According to the present invention, a radiation detector with enhanced radiation resistance can be provided. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the configuration of the imaging device according to the first embodiment. [Figure 2] Equivalent circuit diagram of a pixel according to the first embodiment [Figure 3] Top view of a pixel according to the first embodiment [Figure 4] This figure shows the configuration of the imaging device according to the second embodiment. [Figure 5] Equivalent circuit diagram of a pixel according to the second embodiment [Figure 6] Top view of a pixel according to the second embodiment [Figure 7] Top view of a pixel according to the third embodiment [Figure 8] Top view of a pixel according to the fourth embodiment [Figure 9] Top view of a pixel according to the fifth embodiment [Figure 10] Top view of a pixel according to the sixth embodiment [Figure 11] Top view of a pixel according to the 7th embodiment [Figure 12] Top view of a pixel according to the 8th embodiment [Figure 13] Top view of a pixel according to the 9th embodiment [Figure 14] Top view of a pixel according to the 10th embodiment [Figure 15] Top view of a pixel according to the 11th embodiment [Figure 16] Schematic diagram illustrating the radiation imaging system according to the 12th embodiment. [Figure 17] Schematic diagram illustrating the radiation imaging system according to the 13th embodiment. [Modes for carrying out the invention]

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the embodiments shown below are merely specific examples of the technical idea of the present invention and do not limit the present invention. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential for the invention, and the plurality of features may be arbitrarily combined.

[0010] The sizes and positional relationships of the members shown in each drawing may be exaggerated for clarity of explanation. In the following description, the same components may be given the same numbers and the description may be omitted.

[0011] The deterioration in the radiation detector is understood as follows.

[0012] When radiation enters the radiation detector, the charges generated in the insulating layer are retained in the insulating layer. The charges retained in the insulating layer vary the potential of the channel of the in-pixel transistor, shifting the threshold value. Therefore, the operating point of the in-pixel transistor is varied. Also, the charges retained in the insulating layer change the depletion layer width of the PN junction such as the source and drain of the in-pixel transistor, varying the parasitic capacitance. Furthermore, the charges retained in the insulating layer affect the potential of the detection diode, increasing the dark current. Alternatively, the charges retained in the insulating layer increase the dark current of the floating node, causing the operating point of the pixel circuit to vary.

[0013] These factors due to the charges retained in the insulating layer affect the sensor output, preventing the desired signal from being output.

[0014] Since the amount of charge retained in the insulating layer increases according to the radiation dose, the pixel output deviates from the desired output according to the dose. Therefore, in the following description, this phenomenon is referred to as deterioration of the sensor due to radiation.

[0015] <First Embodiment> (Configuration of Imaging Device) Figure 1 shows the configuration of the imaging device (radiation detector) of this embodiment. The imaging device of this embodiment has signal wiring 10-1 and pixels 11. The pixels 11 are arranged in a matrix across multiple rows and multiple columns in the pixel array 13. One signal wiring 10-1 is provided for each pixel column in which pixels 11 are arranged. The imaging device also has a vertical scanning circuit 14. A row of pixels 11 arranged across multiple columns is connected to the vertical scanning circuit 14 via a control line 12. The vertical scanning circuit 14 controls the storage period of the pixels 11.

[0016] The imaging device includes a column circuit section 15, a horizontal scanning circuit 16, and an output circuit 17. The column circuit section 15 comprises multiple column circuits. One of the multiple column circuits is arranged in correspondence with signal wiring 10-1. Each of the multiple column circuits processes the signal output from the pixel 11 to signal wiring 10-1 and outputs it to the output circuit 17. This processing includes, for example, AD conversion and amplification.

[0017] The horizontal scanning circuit 16 sequentially selects from the multiple column circuits provided by the column circuit unit 15. The signals held by each of the multiple column circuits are then sequentially output to the output circuit 17. The output circuit 17 outputs the signal to the outside of the imaging device. The signal output by the output circuit 17 is the signal output by the imaging device.

[0018] The imaging device further includes a control circuit (control unit) 18. The control circuit 18 is connected to the vertical scanning circuit 14, the column circuit section 15, and the horizontal scanning circuit 16 via drive lines that supply drive signals, and controls these circuits.

[0019] (Pixel circuit configuration) Figure 2 is a circuit diagram showing the circuitry for 2 rows and 2 columns of the pixel 11 shown in Figure 1. In the following explanation, it is assumed that the charge accumulated by the detection diode D1, which is a radiation detection element, is electrons. Therefore, in this embodiment, all transistors in the pixel 11 are N-type transistors. On the other hand, the charge accumulated by the detection diode may be holes, in which case the transistors in the pixel 11 may be P-type transistors. In other words, the specifications for the conductivity type used in the following explanation can be changed depending on the polarity of the charge to be treated as a signal.

[0020] Pixel 11 includes a detection diode D1 which is a radiation detection element (photoelectric conversion unit), a transfer transistor M1, a charge holding unit C1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

[0021] The detection diode D1 converts radiation into electric charge. The radiation detected by the detection diode D1 may be ionizing radiation such as X-rays or gamma rays, or particle radiation such as alpha rays, beta rays, electron beams, neutron beams, proton beams, heavy ion beams, or meson beams. In this embodiment, the detection diode D1 detects electron beams. The detection diode D1 has, for example, a single-crystal semiconductor layer of silicon or germanium, but it may also have a polycrystalline semiconductor layer.

[0022] The transfer transistor M1 is located in the electrical path between the node to which the charge holding unit C1, reset transistor M2, and amplification transistor M3 are connected, and the detection diode D1. The drains of the reset transistor M2 and amplification transistor M3 are each supplied with the power supply voltage. The selection transistor M4 is located in the electrical path between the amplification transistor M3 and the signal wiring 10-1. The amplification transistor M3 is electrically connected to the signal wiring 10-1 via the selection transistor M4. The charge holding unit C1 includes a floating diffusion unit (floating diffusion capacitance) provided within the semiconductor substrate and the parasitic capacitance of the electrical path from the transfer transistor M1 to the amplification transistor M3 via the floating diffusion unit.

[0023] Signals RES, TX, and SEL are signals supplied from the vertical scanning circuit 14 shown in Figure 1 via control lines 12. In Figure 2, the pixel row to which the signal is supplied is appended to the end of each signal. For example, signal RES(m) means that signal RES is supplied to the pixel in the mth row.

[0024] A current source (not shown) is connected to signal wiring 10-1. When the signal SEL(m) reaches an active level, the selection transistor M4 of the m-th row pixel 11 is turned on. As a result, current is supplied from the current source to the amplification transistor M3 of the m-th row pixel 11. In the m-th row pixel 11, a source follower circuit is formed by the power supply voltage VDD, the amplification transistor M3, and the current source (not shown) connected to signal wiring 10. With this source follower circuit formed, the amplification transistor M3 outputs a signal based on the potential of the charge holding section C1 to signal wiring 10-1 via transistor M4.

[0025] Furthermore, when the signal SEL(m+1) reaches an active level, the selection transistor M4 of the pixel 11 in the m+1th row is turned on. As a result, current is supplied from the current source to the amplification transistor M3 in the m+1st row. In the pixel 11 of the m+1th row, a source follower circuit is formed by the power supply voltage VDD, the amplification transistor M3, and a current source (not shown) connected to the signal wiring 10-1. With the formation of this source follower circuit, the amplification transistor M3 transmits a signal based on the potential of the charge holding section C1 via transistor M4. The signal is then output to signal wiring 10-1.

[0026] (Plan view of pixels) Figures 3(a) to 3(c) are schematic diagrams illustrating the layout of pixel 11 shown in Figure 1. The legend in the figures indicates the active region, polysilicon layer, first wiring layer, second wiring layer, contact plug, and via plug. The active region is the surface of the semiconductor substrate where elements such as transistors are formed. The area of ​​the semiconductor substrate surface other than the active region can be the element isolation region. The element isolation region is an insulator such as STI (Shallow Trench Isolation). The structure may include a polysilicon layer, or it may be a PN separation structure utilizing the conductivity type of the semiconductor. The polysilicon layer may be formed on the surface of the semiconductor substrate. The polysilicon layer constitutes, for example, the gate electrode of a transistor. The polysilicon layer is not limited to polysilicon, but may be other metals. The first and second wiring layers are made of a conductor and are arranged on the surface of the semiconductor substrate. They are arranged in the order of the first wiring layer and the second wiring layer from the surface of the semiconductor substrate. An interlayer insulating film is placed between the semiconductor substrate and the first wiring layer, and an interlayer insulating film is placed between the first wiring layer and the second wiring layer. The contact plug is made of a conductor and electrically connects the semiconductor substrate and the first wiring layer, and the polysilicon layer and the first wiring layer. The via plug is made of a conductor and electrically connects the first wiring layer and the second wiring layer. The wiring structure is not limited to this and may have the first and second wiring layers in between and a third wiring layer in between.

[0027] Figure 3(a) is a schematic top view showing the active region, polysilicon layer, and contact plug. Figure 3(b) is a schematic top view showing Figure 3(a) with the first wiring layer and via plug added. The contact plug is located between the semiconductor substrate and the first wiring layer, but in Figure 3(b), the contact plug is drawn on top of the first wiring layer. This is to facilitate understanding the position of the contact plug. Figure 3(c) is a schematic top view showing Figure 3(b) with the second wiring layer added. In Figure 3(c), as with the contact plug in Figure 3(b), the via plug is drawn on top of the second wiring layer for ease of understanding. Contact plugs and via plugs are drawn similarly in subsequent figures as well.

[0028] In Figure 3(a), the active region includes region 33, gate electrode 34, charge holding portion 38, gate electrode 35, and region 40. Region 33 is the region where the detection diode D1 is located. The transfer transistor M1 includes gate electrode 34, region 33, and charge holding portion 38. The charge holding portion 38 is the charge holding portion C1 shown in Figure 2. The reset transistor M2 includes charge holding portion 38, gate electrode 35, and region 40. Another active region includes the amplification transistor M3 and the selection transistor M4, and includes the gate electrode 36 of the amplification transistor M3 and the gate electrode 37 of the selection transistor M4. Region 41 is a region for supplying potential to the well. A well is a semiconductor region on which each element is provided. For example, the signal charge can be electrons, the transistor can be an N-type transistor, and the well can be a P-type semiconductor region.

[0029] In this embodiment, the detection diode region is defined by the active layer, but it may also be defined by a semiconductor region of the same conductivity type as the well of a transistor utilizing PN isolation.

[0030] As shown in Figure 3(b), the first wiring layer contains multiple wires. Wire 42 supplies the control signal RES to the gate electrode 35 of the reset transistor M2. Wire 43 supplies the control signal TX to the gate electrode 34 of the transfer transistor M1. Wire 44 supplies the control signal SEL to the gate electrode 37 of the selection transistor M4. Wire 45 is a signal output line that electrically connects the signal wires to the source / drain region of the selection transistor M4. Wire 46 is a wire for supplying voltage to the well. For example, if the signal charge is electrons, the voltage supplied by wire 46 can be ground (GND). Wire 47 is a wire that electrically connects the charge holding section 38 and the gate electrode 36 of the amplification transistor M3. The capacitive component includes wiring 47, charge holding section 38, and gate electrode 36. Wiring 48 is for supplying voltage to region 40. For example, if the signal charge is electrons, the voltage supplied by wiring 48 can be the power supply voltage VDD. Wiring 49 is for supplying voltage to region 36-2. For example, if the signal charge is electrons, the voltage supplied by wiring 49 can be the power supply voltage VDD. Here, wirings 42-46 are global wirings provided in common to multiple pixels. The longitudinal sides of wirings 42-46 are along the X direction and are parallel to each other.

[0031] As shown in Figure 3(c), the second wiring layer contains multiple wires. Power wire 31 is electrically connected to the source / drain region of the amplification transistor M3 via via plugs, wire 48, and contact plugs. Power wire 31 supplies the power supply voltage to the source / drain region of the amplification transistor M3. Power wire 32 is electrically connected to region 41 via via plugs, wire 46, and contact plugs. Power wire 32 supplies GND to region 41. Signal wire 10-1 is a vertical output line. Signal wire 10-1 is electrically connected to the source / drain region of the selection transistor M4 via via plugs, wire 45, and contact plugs. Signal wire 10-1 outputs the pixel signal from the selection transistor M4. Thus, the wire 31 that supplies the power supply voltage to the amplification transistor M3, the power supply wire 32 that supplies potential to the well, and the signal wire 10-1 are formed on the same layer. The longitudinal lengths of these wires 31, 32, and 10-1 are along the Y direction and are parallel to each other.

[0032] The mechanism of radiation degradation discovered by the inventors is described below.

[0033] In radiation detectors, it is known that the charge generated in the insulating layer when radiation enters the detector is retained in the insulating layer. The charge retained in the insulating layer fluctuates the channel potential of the pixel driving transistor, shifting the threshold and thus causing the operating point of the pixel driving transistor to fluctuate. Furthermore, the charge retained in the insulating layer changes the depletion layer width of the PN junctions, such as the source and drain of the pixel driving transistor, causing parasitic capacitance to fluctuate. In addition, the charge retained in the insulating layer affects the potential of the detection diode, increasing the dark current. The increased dark current causes the potential of the charge retaining part to fluctuate. Due to these effects, the charge retained in the insulating layer affects the sensor output, preventing the output of the desired signal. Since the amount of retained charge increases in proportion to the absorbed dose, the pixel output deviates from the desired output depending on the irradiation dose. Therefore, this phenomenon manifests as sensor degradation due to radiation.

[0034] The inventors have found that the amount of charge retained in the insulating layer due to radiation irradiation depends on the electric field of the insulating layer at the time of radiation irradiation. Furthermore, the degree of characteristic degradation during sensor operation depends on the electric field surrounding the retained charge. A larger electric field increases the influence of the retained charge, resulting in a lower degradation resistance of the detector.

[0035] Therefore, the inventors focused on the layout relationship between the signal wiring 10-1 and the active layer of the amplification transistor M3, and found that it is effective to arrange them so that the signal wiring 10-1 and the active layer of the amplification transistor M3 do not overlap.

[0036] For example, consider the distance between the active layer of the amplification transistor M3 and the signal wiring 10-1 when the interlayer thickness of the wiring is several hundred nanometers and the pixel pitch is several micrometers. Compared to the case where the signal wiring 10-1 passes over the active layer of the amplification transistor M3 in a plan view, when the signal wiring 10-1 passes away from the active layer of the amplification transistor M3 and at the edge of the pixel, this distance can be increased by, for example, about 10 times. As a result, the electric field between the active layer of the amplification transistor M3 and the signal wiring 10-1 is reduced by an order of magnitude. Consequently, the radiation degradation resistance of the detector is improved by more than an order of magnitude. Thus, according to this embodiment, the active layer of the amplification transistor M3 Since the electric field between the layer and signal wiring 10-1 can be significantly reduced, the detector's resistance to degradation due to radiation irradiation can be reduced. The active layer of a transistor can also be described as the active layer on which the transistor is located.

[0037] In addition to the retained charge in the insulating film mentioned above, the increase in interface states due to the total dose effect and ejection damage effect is also one of the causes of sensor degradation due to radiation irradiation.

[0038] The inventors have found that the increase in interface energy levels due to radiation irradiation depends on the electric field around the interface at the time of irradiation. If the electric field around the interface is small, the increase in interface energy levels can be suppressed, thereby reducing the degradation tolerance of the sensor.

[0039] In a configuration where the signal wiring passes over the active layer of the transistor, the electric field around the active layer of the transistor is prone to fluctuations in accordance with the potential of the signal wiring, which changes depending on the detected radiation dose. Since the increase in interface levels depends on the surrounding electric field at the interface, in the aforementioned configuration, pixel degradation changes in accordance with the potential of the signal wiring. In other words, the degree of degradation of each pixel row changes depending on the output image pattern of the sensor, causing phenomena such as image burn-in.

[0040] In this embodiment, as shown in Figure 3(c), the signal wiring 10-1 does not pass over the active layer of the transistor; in other words, the signal wiring 10-1 and the active layer of the transistor do not overlap in a plan view. This reduces fluctuations in the ambient electric field of the transistor's active layer due to the signal wiring potential, thereby reducing burnout.

[0041] Furthermore, the charge held in the insulating film affects the potential of the gate channel of the pixel driving transistor, causing the transistor's threshold value to fluctuate.

[0042] This embodiment is characterized in that the signal wiring 10-1 does not pass over the gate channel region of the transistor, or in other words, the signal wiring 10-1 does not overlap with the gate channel region of the transistor in a plan view. This reduces the influence of retained charge in the insulating film on the channel of the pixel driving transistor, which fluctuates depending on the potential of the signal wiring. Therefore, it is possible to reduce the phenomenon of streaks appearing in each column or row due to degradation caused by radiation, which was a problem identified by the inventors. The mechanism discovered by the inventors is described below.

[0043] Furthermore, the depletion layer width of the PN junction in the transistor's diffusion region changes due to the influence of charge held in the insulating film. As a result, the parasitic capacitance of the pixel transistor fluctuates, and the time constant for driving the pixel circuit changes. On the other hand, the amount of charge held depends on the electric field applied to the insulating film during radiation irradiation. When signal wiring is formed on top of the PN junction, the amount of charge held in the insulating film becomes non-uniform for each pixel row, depending on the difference in signal wiring potential for each pixel row during the period of radiation irradiation. As a result, in the degraded image, fixed pattern noise for each pixel row appears in the sensor output. In this phenomenon, slight differences between rows that were not visible before degradation are amplified and become apparent depending on the degree of degradation. Causes of differences between rows include differences in the parasitic capacitance of the vertical signal line, differences in the layout position of the drive circuit connected to the vertical signal line, and differences in the power supply impedance of the circuit driving the vertical signal line.

[0044] Furthermore, the inventors have found that the leakage current at the PN junction formed at the source and drain of the pixel driving transistor increases due to the charge held near the PN junction. As is known in general CMOS sensor technology, leakage current degrades imaging performance. The effect is particularly pronounced when the sensor operates as a floating node, such as in the input section of a detection diode or amplification transistor.

[0045] Therefore, in this embodiment, the signal wiring 10-1 is laid out so that it does not pass over the top of the transistor's diffusion region (source-drain region), in other words, the signal wiring 10-1 and the transistor's diffusion region do not overlap in a plan view. By adopting such a layout, the increase in leakage current due to radiation irradiation can be reduced. As a result, it is possible to reduce the degradation of imaging performance due to radiation irradiation. In addition, it is possible to reduce the asymmetry of radiation degradation caused by asymmetry in rows or columns, or the impedance of the drive circuit. As a result, it is possible to improve radiation immunity in terms of periodic noise in the image.

[0046] This embodiment is a surface-irradiation type radiation detector (imaging device) capable of imaging by irradiating a semiconductor substrate with radiation from the surface side where the wiring is formed. The irradiated radiation can penetrate the wiring layer and interlayer insulating film to reach the detection diode.

[0047] Furthermore, the radiation detected by the imaging device according to this embodiment may be ionizing radiation such as X-rays or gamma rays, or it may be particle beams such as alpha rays, beta rays, neutron beams, proton beams, electron beams, heavy ion beams, or meson beams.

[0048] <Second Embodiment>

[0049] In the first embodiment, a configuration in which there is one signal line per pixel row was described. In this embodiment, a configuration in which there are multiple signal lines per pixel row will be described.

[0050] (Configuration of the imaging device) Figure 4 shows the configuration of the imaging device according to this embodiment. In this embodiment, each of the multiple rows outputs from the array of pixels 11 to signal wiring 10-1 to signal wiring 10-5, respectively. Although the array of pixels 11 is an equivalent circuit consisting of repeating cells, the physical layout may differ in parts corresponding to the connected signal wiring. In this embodiment, a configuration in which five signal wirings are provided for one pixel row is described, but the number is not limited as long as two or more are provided.

[0051] (Pixel circuit configuration) Figure 5 is an equivalent circuit diagram showing 2 rows and 2 columns of the pixel 11 shown in Figure 4. The pixel in the mth row and the pixel in the m+1th row are connected to signal wires 10-1 and 10-2, respectively. Similarly, the pixel in the m+2nd row (not shown) is connected to signal wire 10-3, the pixel in the m+3rd row is connected to signal wire 10-4, and the pixel in the m+4th row is connected to signal wire 10-5. Signal wires 10-2 to 10-5 are connected to current sources (not shown) in the same way as signal wire 10-1 in the first embodiment.

[0052] When the signal SEL(m) reaches an active level, the selection transistor M4 of the m-th row pixel is turned on. This supplies current from the current source to the amplification transistor M3 of the m-th row pixel. In the m-th row pixel, a source follower circuit is formed by the power supply voltage VDD, the amplification transistor M3, and a current source (not shown) connected to signal wiring 10-1. With this source follower circuit formed, the amplification transistor M3 outputs a signal based on the potential of the charge holding section C1 to signal wiring 10-1 via transistor M4.

[0053] Furthermore, when the signal SEL(m+1) reaches an active level, the selection transistor M4 of the m+1 row of pixels is turned on. This supplies current from the current source to the amplification transistor M3 of the m+1 row. In the pixels of the m+1 row, the power supply voltage VDD and the amplification transistor... A source follower circuit is formed by transistor M3 and a current source (not shown) connected to signal wiring 10-2. With this source follower circuit formed, the amplifying transistor M3 outputs a signal based on the potential of the charge holding section C1 to signal wiring 10-2 via transistor M4.

[0054] Thus, the pixels in row m and row m+1 are connected to different signal lines. Similarly, the pixels in rows m+2 through m+4 (not shown) are also connected to different signal lines.

[0055] According to this, the detector can be made faster by using multiple signal lines. Furthermore, even in this case, the effects described in Embodiment 1 can be obtained because the signal lines are not formed on the upper part of the active layer of the amplification transistor.

[0056] (Plan view of pixels) Figures 6(a) to 6(c) are schematic diagrams illustrating one of the pixel 11 layouts shown in Figure 4. Signal lines 10-1 to 10-5 are arranged adjacent to each other and are formed sandwiched between power supply lines 32 and 60. Signal lines 10-1 to 10-5 are formed on the same layer as power supply line 31, which supplies power voltage to the amplification transistor M3, and power supply line 32, which supplies potential to the well.

[0057] Thus, in this embodiment, there are multiple signal lines, and these signal lines are arranged adjacent to each other. "Arranged adjacent to each other" can mean, for example, that no wiring other than signal lines is placed between signal lines, at least on the same wiring layer.

[0058] In this embodiment, signal wiring 10-1 is adjacent to signal wiring 10-2 and power wiring 32, while signal wiring 10-5 is adjacent to signal wiring 10-4 and power wiring 60. On the other hand, signal wirings 10-2, 10-3, and 10-4 are adjacent to other signal wirings on the left and right. In other words, by arranging the signal wirings so that they are adjacent to each other, the symmetry of crosstalk occurring between signal wirings 10-2 to 10-4 can be improved. The symmetry of the electric field generated around signal wirings 10-2 to 10-4 is also improved. As a result, the non-uniformity of the electric field strength between adjacent wirings for each signal wiring can be reduced, thereby reducing the difference in degradation from pixel to pixel due to radiation irradiation and reducing fixed pattern noise due to radiation irradiation degradation.

[0059] Furthermore, the spacing between adjacent signal lines is smaller than the spacing between a signal line adjacent to a power line and that power line. That is, the spacing between adjacent signal lines is smaller than the spacing between power line 32 and signal line 10-1 and the spacing between power line 60 and signal line 10-5. In this way, by widening the spacing between power lines and signal lines compared to the spacing between signal lines, the electric field around the signal lines can be reduced. This reduces the influence of charge held in the insulating film on each signal line, thereby reducing noise after degradation. In addition, the increase in interface states due to radiation irradiation at the interface around the signal lines can be reduced, thus reducing resistance to degradation due to radiation. Note that the spacing between adjacent signal lines does not have to be constant; the spacing between power line 32 and signal line 10-1 and the spacing between power line 60 and signal line 10-5 do not have to be the same. Generally, the largest spacing between adjacent signal lines should be smaller than both the spacing between power line 32 and signal line 10-1 and the spacing between power line 60 and signal line 10-5.

[0060] <Third Embodiment> A third embodiment according to the present invention is shown in Figure 7. The explanation for the same part numbers as in Figures 6(a) to 6(c) is the same as in Figures 6(a) to 6(c). Figure 7 shows the active region and the polysilicon layer. This diagram shows the contact plug, via plug, first wiring layer, and second wiring layer. The layer structure can be understood by referring to other embodiments, so the individual layer diagrams are omitted.

[0061] The connection wiring 70 is connected to the source 71 of the selected transistor, is formed on a different wiring layer from the signal wirings 10-1 to 10-5, and is connected to the connection wiring via via plugs (via holes) 72. A connection wiring 70 is provided for each amplification transistor M3. Furthermore, the connection wiring 70 is laid out to be approximately orthogonal in a plan view to at least one of the signal wirings 10-1 to 10-5.

[0062] In this embodiment, the asymmetry of parasitic capacitance between the wiring 70 connecting the amplification transistors and each signal wiring 10-1 to 10-5 can be reduced, thereby reducing the difference in degradation tolerance for each pixel row and reducing fixed pattern noise after radiation irradiation.

[0063] The wiring 70 has a wider section 74 of a certain width that is thicker than the rest of the wiring in the portion that overlaps with the signal wirings 10-1 to 10-5, and a via hole 72 is provided at the position where the wider section 74 overlaps with the signal wiring to which the pixel signal is output. Therefore, although the position of the via hole 72 differs depending on the pixel, the planar layout of each pixel in the pixel array can be made substantially the same shape except for the via hole 72. In this embodiment, the via holes 72 take on periodically different arrangements on the same pixel row in units of a predetermined number of repetitions. In this embodiment, the output of the m-th row amplification transistor is connected to the signal wiring 10-1 via the via hole 72, the m+1-th row is connected to the signal wiring 10-2 via the via plug 73, and so on. In other words, it is possible to accommodate changes in the pixel layout due to differences in the signal wiring to be read out using only via holes. This improves the coupling symmetry with other wiring for each pixel, such as charge holding sections and amplification transistors, so that the difference in degradation between pixels can be further reduced and fixed pattern noise after radiation irradiation can be reduced.

[0064] In this embodiment, the overlapping area of ​​the signal lines 10-1 to 10-5 and the connecting line 70 at their intersections in a plan view can be made approximately the same for all pixel intersections. Therefore, periodic asymmetry between pixel rows can be reduced. As a result, the difference in the degree of degradation between rows can be further reduced, and fixed pattern noise after radiation irradiation can be reduced.

[0065] <Fourth Embodiment> The pixel layout of the fourth embodiment according to the present invention is shown in Figures 8(a) to 8(c). In this embodiment, there is a power supply wiring 31 that supplies the drain potential of the amplification transistor, a power supply wiring 32 that supplies the well potential, a power supply wiring 80 that supplies the drain potential of the reset transistor M2, and a contact 81 that supplies the well potential to the semiconductor substrate. In this embodiment, the power supply wiring 32 is arranged to be sandwiched between the power supply wiring 31 and the power supply wiring 80.

[0066] In general, in NMOS type pixel configurations, the well potential is a low potential like the ground potential, while the drain potential and reset potential of the amplification transistor are high potentials. Also, in the reset state, the potential of the pixel signal wiring follows the drain potential of the reset transistor and becomes a high potential. In this embodiment, power supply wiring 80 (same pixel) and power supply wiring 31 (adjacent pixel) are placed next to signal wiring 10-1. By placing signal wiring 10-1 next to power supply wiring 80 and signal wiring 10-1 next to power supply wiring 31, the lateral electric field around signal wiring 10-1 can be reduced compared to a layout where signal wiring 10-1 and power supply wiring 32 are adjacent. Therefore, the influence of charge held in the insulating film can be reduced, and noise after degradation can be reduced.

[0067] <Fifth Embodiment> A fifth embodiment of the present invention will be described with reference to Figures 9(a) to 9(c).

[0068] The fifth embodiment differs from the fourth embodiment in the arrangement of power supply wirings 31, 32 and 80. In this embodiment, power supply wiring 31, power supply wiring 80, and power supply wiring 32 are arranged in that order, with power supply wiring 80 sandwiched between power supply wiring 31 and power supply wiring 32. This reduces capacitive coupling due to parasitic capacitance between power supply wiring 80 and signal wiring 10-1. Power supply wiring 80 may experience transient voltage fluctuations during sensor reset operation. In this embodiment, the shielding effect of power supply wiring 32 shields signal wiring 10-1 from the effects of voltage fluctuations in power supply wiring 80. This reduces transient fluctuations in the lateral electric field around the signal wiring, thereby reducing fluctuations in the pixel output after degradation depending on the pixel voltage state.

[0069] <Sixth Embodiment> The sixth embodiment has a configuration that combines the first to fifth embodiments described above. This embodiment will be described with reference to Figures 10(a) to 10(c).

[0070] In this embodiment, the signal wiring does not pass over the active layer of the amplification transistor, there are multiple signal wirings, each of which is arranged adjacent to another, and each has a connecting wire that is orthogonal to any of the signal wirings. Except for vias connecting the connecting wires and signal wirings, the pixel layout of the pixel array is identical in plan view, the area where the signal wiring and connecting wires are orthogonal in plan view is the same for all signal wirings, and there are three power supply wires.

[0071] According to this, sensors that suppress the impact of radiation degradation on image quality will be able to read out at high speeds, making it possible to manufacture detectors that can acquire image data at high frame rates.

[0072] <Seventh Embodiment> This embodiment describes an example of achieving high-speed imaging while obtaining the effect of improved radiation resistance. Figures 11(a) to 11(c) are schematic diagrams illustrating the pixel layout in this embodiment. Here, an example with a pixel pitch of 2 μm is shown. The numbers of each component are the same as in the description in the above embodiment. Here, the L / S (line and space) of the wiring is 0.2 μm, and the channel width of the amplification transistor is 0.4 μm. Signal wiring 10- Lines 1 through 10-3 are arranged so as not to overlap with the channel, source, or drain of the amplification transistor. Therefore, in this embodiment, the signal wiring is placed above the detection diode D1 (region 33). In addition, the power supply wiring 110 for driving the pixels is placed above the region where the transistors constituting the pixel circuit are located. Although only one power supply wiring 110 is shown in the figure, there may be multiple power supply wirings 110. For example, power supply wiring 31 that supplies the drain potential of the amplification transistor, power supply wiring 32 that supplies the well potential, and power supply wiring 80 that supplies the drain potential of the reset transistor M2 are placed above the region where the transistors are located (see Figures 9 and 10).

[0073] In this embodiment, while maintaining the layout according to the present invention, the number of signal lines per pixel pitch can be increased to three or more, making it possible to achieve both radiation resistance and high speed.

[0074] <Eighth Embodiment> In the eighth embodiment, a configuration is described in which the sensitivity of the detector can be improved by arranging the amplification transistor so as to be enclosed within the radiation detection element in a plan view.

[0075] In this embodiment, as shown in Figure 12, the radiation detection element D1 (region 33) is defined by an active layer 120 and a frame-shaped inactive layer 121 provided for each unit pixel. This is a pixel separation structure formed to surround the radiation detection element D1, and multiple radiation detection elements D1 are separated by the inactive layer 121. The active region 33 of the radiation detection element D1 is located within the region surrounded by the inactive layer 121, which is the pixel separation structure.

[0076] In this embodiment, the charge holding unit 38 is arranged so as to be surrounded by the active region 33 of the detection element D1, and similarly, the gate 36 of the amplification transistor is also arranged so as to be surrounded by the active region 33 of the detection element D1. More specifically, both the charge holding unit and the amplification transistor are located in the region inside the inactive layer 121 (pixel separation structure) and surrounded by the active region 33. The "region surrounded by the active region" is a region in which the active region exists substantially in all directions. Viewed in plan, the entire outer perimeter of the region may be surrounded by a single active region, or a part of the entire outer perimeter may be a separation region. By adopting such an arrangement, the charge holding unit 38 and the gate 36 of the amplification transistor can be placed in close proximity. As a result, the parasitic capacitance of the charge holding unit can be reduced, making it possible to increase the sensitivity of the detector.

[0077] In this embodiment, a configuration in which the detection element is defined by the active layer was described with reference to Figure 12, but similar effects can be obtained by defining the detection element by the conductivity type or concentration of the semiconductor region.

[0078] <Ninth Embodiment> In the ninth embodiment of the present invention, a configuration using a pixel circuit method known as the 3-transistor method in CMOS area sensor technology, which does not have a transfer transistor and in which the radiation detection element and the charge holding unit are electrically connected, will be described. In this embodiment, the sensitivity of the detector can be improved by arranging the amplification transistor so that it is surrounded by the detection diode in a plan view.

[0079] In this embodiment, as shown in Figure 13, the radiation detection element 33 of a unit pixel is defined by an active layer and an inactive layer, and is separated from the radiation detection elements 33 of adjacent pixels by a frame-shaped inactive layer 121. In this embodiment, the wiring 131 connects the extraction unit 132, which extracts charge from the radiation detection element, to the gate 36 of the amplification transistor.

[0080] In this embodiment, by arranging the gate 36 of the amplification transistor so as to be surrounded by the radiation detection element 33, a layout is possible where the radiation detection element's extraction section 132 and the amplification transistor's gate 36 are close together. As a result, the wiring 131 connecting them can be shortened. This reduces the parasitic capacitance of the radiation detection element and makes it possible to increase the conversion gain. Consequently, the detector becomes more sensitive.

[0081] In addition, compared to a radiation detector having pixels that include a transfer transistor M1, this embodiment eliminates the effect of radiation-induced degradation of the transfer transistor M1, thus improving radiation degradation resistance.

[0082] In this embodiment, a configuration in which the detection element is defined by the active layer was described with reference to Figure 13, but similar effects can be obtained by defining the detection element by the conductivity type or concentration of the semiconductor region.

[0083] Furthermore, even in configurations where multiple signal lines are arranged in a single pixel row, the wiring 131 connecting the charge holding unit and the gate of the amplification transistor can be shortened, thus achieving a similar effect.

[0084] <Tenth Embodiment> In the tenth embodiment, the relative positions of the signal wiring and the connection wiring orthogonal to the signal wiring, and the relative positions of the pixel separation layout and the signal wiring layout which are translationally symmetric on a pixel-by-pixel basis will be described.

[0085] As shown in Figure 14, in this embodiment, the pixel 11 has a connecting wire 141 that connects the amplification transistor and the signal wiring. The connecting wire 141 is provided for each amplification transistor, is formed on a different metal layer from the signal wiring, and is perpendicular to at least one of the signal wirings. The connecting wire and the signal wiring are connected via vias. The connecting wire extends only in the direction of the signal wiring, which is arranged together on one side of the pixel in a plan view (the right side in the figure), starting from a contact for connecting the connecting wire and the transistor. Note that the portion of the connecting wire 141 that overlaps with the signal wiring may have a wider portion of a certain width that is thicker than the other portions (see Figure 7).

[0086] As shown in Figure 14, in the pixel array 13, the signal lines 10-1 to 10-6 of one pixel row are arranged with the same period as the pixel pitch. In this case, the positional relationship between the center of the area where multiple signal lines are arranged and the center of the detection diode area is approximately half a phase shift within the repeating period. By arranging in this way, it is possible to maintain a distance between the extraction position of the detection diode and the vertical signal line, thereby mitigating the electric field in the insulating film. Therefore, radiation resistance can be improved.

[0087] In addition, pixels 11 have the same layout in a plan view except for the vias, and only the vias are arranged periodically in different configurations on the same pixel row in predetermined repeating units. Furthermore, in this embodiment, the overlapping area of ​​the parts where signal lines 10-1 to 10-6 and connection lines 141 intersect in a plan view can be made to be approximately the same value for all pixel intersections. This improves the symmetry other than the signal lines, and thus further reduces the difference in degradation resistance of each pixel after radiation irradiation.

[0088] Furthermore, in this embodiment, the spacing between adjacent signal lines is smaller than the spacing between a signal line adjacent to a power line and that power line. That is, the spacing between adjacent signal lines is smaller than the spacing between signal line 10-1 and the power line 31 of the same pixel, and the spacing between signal line 10-6 and the power line 31 of an adjacent pixel. In this way, by widening the spacing between power lines and signal lines compared to the spacing between signal lines, the electric field around the signal lines can be reduced. This reduces the influence of charge held in the insulating film on each signal line, thereby reducing noise after degradation. In addition, the increase in interface states due to radiation irradiation at the interface around the signal lines can be reduced, thus reducing resistance to degradation due to radiation. Note that the spacing between adjacent signal lines does not have to be constant; the spacing between power line 31 (same pixel) and signal line 10-1 and the spacing between power line 31 (adjacent pixel) and signal line 10-6 do not have to be the same. Generally, the maximum distance between adjacent signal lines should be smaller than both the distance between power line 31 (same pixel) and signal line 10-1, and the distance between power line 31 (adjacent pixel) and signal line 10-6. In this embodiment, a configuration in which six signal lines are arranged for one pixel row is described, but the number is not limited as long as two or more lines are arranged.

[0089] <Embodiment 11> The first to tenth embodiments described so far can be arbitrarily combined without hindering the effects of each other. In the eleventh embodiment, a configuration combining the embodiments described so far will be explained with reference to Figure 15.

[0090] In this embodiment, the signal wiring does not pass over the active layer of the amplification transistor, there are multiple signal wirings, each of which is arranged adjacent to the others, and each has a connecting wire that is orthogonal to any of the signal wirings. Except for the vias connecting the connecting wires and signal wirings, the pixel layout of the pixel array is identical in plan view, and the area where the signal wiring and connecting wires are orthogonal in plan view is the same for all signal wirings. In addition, there are three power supply wires. In a plan view, the power supply wiring is arranged to overlap with the amplification transistors, while the signal wiring does not overlap with the amplification transistors and is arranged so that three or more overlap on the active layer of the radiation detection element. The amplification transistors are located inside the pixel separation structure in a plan view, employing a pixel circuit method called the 3-transistor system. The connection wiring starts from the contacts for connecting to the transistors and extends only in the direction of the signal wiring, which is grouped together on the right side of the pixel in a plan view.

[0091] It will be easy to understand that combinations of the first to tenth embodiments are possible in addition to those described above. For example, instead of a three-transistor system, a four-transistor system employing a transfer transistor (first embodiment) may be used. Also, instead of a configuration in which power supply wiring 31, power supply wiring 32, and power supply wiring 80 are arranged in that order, a configuration in which power supply wiring 31, power supply wiring 80, and power supply wiring 32 (fifth embodiment) may be used.

[0092] According to this embodiment, since the sensor, which suppresses the impact of radiation degradation on image quality, can be read out at high speed, it becomes possible to manufacture a detector that can acquire image data at a high frame rate.

[0093] <Twelfth Embodiment> Referring to Figure 16, a radiation imaging device 801 incorporating a radiation detector according to any of the first to eleventh embodiments described above, and a radiation imaging system 800 using the radiation imaging device will be described.

[0094] The radiation imaging system 800 is configured to electrically capture an optical image formed by radiation and obtain an electrical radiation image (i.e., radiation image data). The radiation imaging system 800 includes, for example, a radiation imaging device 801, an exposure control unit 802, a radiation source 803, and a computer 804. The radiation imaging system 800 can display the captured radiation image on a display device (not shown) or transmit the radiation image data to an external device via a communication device (not shown). The radiation imaging system 800 can be suitably used, for example, in fields such as medical imaging diagnosis and non-destructive testing.

[0095] The radiation source 803, which emits radiation, begins irradiating in accordance with the exposure command from the exposure control unit 802. The radiation emitted from the radiation source 803 passes through a subject (not shown) and irradiates the radiation imaging device 801. The radiation source 803 stops emitting radiation in accordance with the stop command from the exposure control unit 802.

[0096] The radiation imaging device 801 includes a radiation detector 100 according to any of the first to eleventh embodiments described above, a control unit 805 for controlling the radiation detector 100, and a signal processing unit 806 for processing signals output from the radiation detector.

[0097] The signal processing unit 806 can, for example, perform A / D conversion on the signal output from the radiation detector 100 if it is an analog signal, and output it to the computer 804 as radiation image data. The signal processing unit 806 may also, for example, generate a stop signal to stop the irradiation of radiation from the radiation source 803 based on the signal output from the radiation detector 100. The stop signal is supplied to the exposure control unit 802 via the computer 804, and the exposure control unit 802 sends a stop command to the radiation source 803 in response to the stop signal.

[0098] The control unit 805 is, for example, a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), or a general-purpose computer with a program embedded in it, or These can be composed of all or a combination of parts thereof.

[0099] Furthermore, although the signal processing unit 806 is shown as being located within the control unit 805 or as a function of the control unit 805, it is not limited to this. The control unit 805 and the signal processing unit 806 may be configured separately. Moreover, the signal processing unit 806 may be located separately from the radiation imaging device 801. For example, the computer 804 may have the functions of the signal processing unit 806. For this reason, the signal processing unit 806 can be included in the radiation imaging system 800 as a signal processing device that processes signals output from the radiation imaging device 801.

[0100] Computer 804 can control the radiation imaging device 801 and the exposure control unit 802, and can receive radiation image data from the radiation imaging device 801 and process it for display as a radiation image. Computer 804 can also function as an input unit for the user to input conditions for capturing radiation images.

[0101] As an example of a sequence, the exposure control unit 802 has an exposure switch, and when the user turns on the exposure switch, it sends an exposure command to the radiation source 803 and also sends a start notification to the computer 804 indicating the start of radiation emission. Upon receiving the start notification, the computer 804 responds by notifying the control unit 805 of the radiation imaging device 801 of the start of radiation irradiation. In response, the control unit 805 causes the radiation detector 100 to generate a signal corresponding to the incident radiation.

[0102] In the radiation imaging apparatus and radiation imaging system using this embodiment, even when the radiation detector is cooled during imaging, it is possible to effectively prevent excessive force from being applied to the thin, mechanically weak semiconductor layer due to an imbalance in thermal contraction of each part. Therefore, it is possible to realize a radiation imaging apparatus that is highly reliable and durable and can obtain high-quality radiation images, making it practical for use in various fields, including medical and industrial applications.

[0103] <13th Embodiment> A transmission electron microscope (TEM) system incorporating a radiation detector according to any of the first to eleventh embodiments described above will be described with reference to the schematic configuration diagram in Figure 17. The instrument EQP, as a transmission electron microscope, includes an electron source 1002 (electron gun), an irradiation lens 1004, a vacuum chamber 1001 (microscope tube), an objective lens 1006, a magnification lens system 1007, and a radiation detector 1100.

[0104] The electron beam 1003, which is radiation emitted from the electron source 1002 (electron gun) as a radiation source, is focused by the irradiation lens 1004 and irradiated onto the sample S, which is the object of analysis and is held in the sample holder. The space through which the electron beam 1003 passes is defined by the vacuum chamber 1001 (microscope tube) of the instrument EQP, and this space is maintained under vacuum.

[0105] The electron beam 1003 that passes through the sample S is magnified by the objective lens 1006 and the magnifying lens system 1007, and is imaged onto the light-receiving surface of the radiation detector 1100. The electron optical system for irradiating the sample S with the electron beam is called the irradiation optical system, and the electron optical system for imagering the electron beam that has passed through the sample S onto the light-receiving surface of the radiation detector 1100 is called the imaging optical system. The radiation detector 1100, or the radiation detector 1100 and the electron optical system together, may also be called a direct electron detector.

[0106] The electron source 1002 is controlled by the electron source control device 1011. Irradiation lens 10 04 is controlled by the irradiation lens control device 1012. The objective lens 1006 is controlled by the objective lens control device 1013. The magnifying lens system 1007 is controlled by the magnifying lens system control device 1014. The sample holder control mechanism 1005 is controlled by the holder control device 1015, which controls the drive mechanism of the sample holder.

[0107] The electron beam 1003 that passes through the sample S is detected by the radiation detector 1100. The output signal from the radiation detector 1100 is processed by the signal processing device 1016 and the image processing device 1018 to generate an image signal. The generated image signal (transmission electron image) is displayed on the image display monitor 1020 and the analysis monitor 1021, which are used as display devices.

[0108] In the transmission electron microscope (TEM) system of this embodiment, which is equipped with a radiation detector according to any of the first to eleventh embodiments, it is possible to realize a transmission electron microscope (TEM) system that is highly reliable and durable and capable of obtaining high-quality images.

[0109] Furthermore, the electron microscope according to this embodiment is not limited to the example transmission electron microscope (TEM), but may also be a scanning electron microscope (SEM) or a scanning transmission electron microscope (STEM). In addition, it may be an electron microscope equipped with processing functions such as ion beam milling or ion beam-induced deposition (IBID), or a dual-beam electron microscope equipped with a focused ion beam (FIB), such as a FIB-SEM.

[0110] <Note> This embodiment includes the following configurations and methods. (Composition 1) A pixel array in which pixels are arranged in a matrix, each having a radiation detection element that converts radiation into electric charge and an amplification transistor that amplifies and outputs a signal from the radiation detection element, Signal wiring provided for each pixel row, It has, In a plan view, the signal wiring does not overlap with the active layer on which the amplification transistor is located. A radiation detector characterized by the following features. (Configuration 2) The active layer on which the amplification transistor is arranged is the channel region of the amplification transistor. A radiation detector according to configuration 1, characterized by the above. (Composition 3) The active layer on which the amplification transistor is arranged is the diffusion region of the amplification transistor. A radiation detector according to configuration 1, characterized by the above. (Composition 4) The aforementioned signal wiring is arranged in pairs or more for each pixel row of the pixel array. A radiation detector characterized by any of the configurations 1 to 3 described above. (Composition 5) The signal wiring is formed on the same layer as the wiring that supplies the power supply voltage to the amplification transistor, and The aforementioned signal wiring is arranged adjacent to each other. A radiation detector according to configuration 4, characterized by the features described above. (Composition 6) Each of the aforementioned amplification transistors is provided with a connecting wire that is orthogonal to at least one of the aforementioned signal wires, The signal wiring and the connection wiring are formed on different layers and are electrically connected via via holes. The planar layout of the aforementioned pixels is substantially the same shape, except for the via holes. A radiation detector according to configuration 4 or 5, characterized by the above. (Composition 7) The overlapping area of ​​the signal wiring and the connection wiring at their intersections is approximately the same at every intersection. A radiation detector according to configuration 6, characterized by the above. (Composition 8) The aforementioned pixel has power supply wiring arranged parallel to the signal wiring, The spacing between adjacent signal wires is smaller than the spacing between a signal wire adjacent to a power supply wire and that power supply wire. A radiation detector according to any one of configurations 4 to 7, characterized by the above. (Composition 9) The aforementioned pixel is equipped with a reset transistor, The power supply wiring includes a first power supply wiring that supplies the drain potential of the amplification transistor, a second power supply wiring that supplies the well potential, and a third power supply wiring that supplies the drain potential of the reset transistor. A radiation detector according to configuration 8, characterized by the above. (Composition 10) The second power supply wiring is positioned between the first power supply wiring and the third power supply wiring. A radiation detector according to configuration 9, characterized by the features described therein. (Composition 11) The third power supply wiring is positioned between the first power supply wiring and the second power supply wiring. A radiation detector according to configuration 9, characterized by the features described therein. (Composition 12) The first power supply wiring, the second power supply wiring, and the third power supply wiring are arranged above the region where the amplification transistor is located. A radiation detector according to any one of configurations 9 to 11, characterized by the above. (Composition 13) The signal wiring is positioned above the area where the radiation detection element is located. The aforementioned signal wiring is characterized by having three or more lines per pixel row. A radiation detector as described in any of configurations 1 to 12. (Composition 14) The aforementioned radiation detector is of the surface irradiation type. A radiation detector according to any one of configurations 1 to 12, characterized by the above. (Composition 15) A radiation detector as described in any one of items 1 to 14, A signal processing unit that processes the signal output by the radiation detector, A radiation imaging system characterized by having the following features. (Composition 16) A radiation detector as described in any one of items 1 to 14, Radiation source and A radiation imaging system characterized by having the following features. [Explanation of symbols]

[0111] 10-1~10-5 Signal Wiring 11 pixels 33. Radiation detection element 36-1 Channel region of an amplifying transistor 36-2 Diffusion region of an amplifying transistor 121 Inactive layer (pixel separation structure) M3 Amplifying Transistor

Claims

1. a pixel array in which pixels are arranged in a matrix, each pixel having a radiation detection element that converts radiation into an electric charge and an amplification transistor that amplifies and outputs a signal from the radiation detection element; signal wiring provided for each pixel column; and In a plan view, the signal wiring does not overlap an active layer in which the amplification transistor is disposed. A radiation detector comprising:

2. the active layer in which the amplifying transistor is disposed is a channel region of the amplifying transistor; 2. The radiation detector according to claim 1.

3. the active layer in which the amplifier transistor is disposed is a diffusion region of the amplifier transistor; 2. The radiation detector according to claim 1.

4. Two or more of the signal wirings are arranged for one pixel column.

2. The radiation detector according to claim 1, wherein:

5. The signal wiring is formed in the same layer as a wiring that supplies a power supply voltage to the amplification transistor, and The signal wirings are arranged adjacent to each other.

5. The radiation detector according to claim 4.

6. a connection wiring provided for each of the amplification transistors and orthogonal to one of the signal wirings of the corresponding pixel column; the signal wiring and the connection wiring are formed in different layers and are electrically connected to each other through via holes; The planar layout of the pixels has substantially the same shape except for the via holes.

5. The radiation detector according to claim 4.

7. overlapping regions at the intersections of the signal wiring and the connection wiring have substantially the same area; 7. The radiation detector according to claim 6.

8. The pixel has a power supply wiring arranged in parallel with the signal wiring, the interval between the adjacent signal wirings is smaller than the interval between the signal wiring adjacent to the power supply wiring and the power supply wiring; 5. The radiation detector according to claim 4.

9. the pixel comprises a reset transistor; the power supply wiring includes a first power supply wiring that supplies a drain potential of the amplification transistor, a second power supply wiring that supplies a well potential, and a third power supply wiring that supplies a drain potential of the reset transistor; 9. The radiation detector according to claim 8.

10. the second power supply wiring is disposed between the first power supply wiring and the third power supply wiring; 10. The radiation detector according to claim 9.

11. the third power supply wiring is disposed between the first power supply wiring and the second power supply wiring; 10. The radiation detector according to claim 9.

12. the first power supply wiring, the second power supply wiring, and the third power supply wiring are arranged above a region in which the amplification transistor is arranged; 10. The radiation detector according to claim 9.

13. the signal wiring is arranged above an area in which the radiation detection elements are arranged, The signal wiring is characterized in that there are three or more signal wirings per pixel column.

2. The radiation detector according to claim 1.

14. the radiation detector is a front-illuminated type; 2. The radiation detector according to claim 1.

15. A radiation detector according to any one of claims 1 to 14; a signal processing unit that processes a signal output by the radiation detector; A radiation imaging system comprising:

16. A radiation detector according to any one of claims 1 to 14; A radiation source; A radiation imaging system comprising:

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