Manufacturing method of plane emission laser device

Abstract

To provide a manufacturing method of a photonic crystal plane emission laser of which an oscillation wavelength and an outgoing beam characteristic are controlled with high accuracy.SOLUTION: A manufacturing method of a photonic crystal plane emission includes the steps of: (a) forming a first semiconductor layer containing a photonic crystal layer on a transparence substrate; (b) forming an active layer and a second semiconductor layer in this order by performing a crystal growth on the first semiconductor layer; (c) performing a spectrometry that radiates light from a front surface of the second semiconductor layer and measures a layer thickness until a reflection position of the radiation light by the photonic crystal layer from the surface; (d) forming a transparence electrode having a layer thickness calculated on the basis of an optical path corresponded to the layer thickness obtained by the spectrometry measurement, on the second semiconductor layer; and (e) forming an optical reflection layer on the transparence electrode. The layer thickness of the transparence electrode is defined so that a light strength of interference light of direct diffraction light emitted from the photonic crystal layer and ejected from a back surface of the substrate and reflection diffraction light emitted from the photonic crystal layer and reflected by the light reflection layer is larger than the light strength of the direct diffraction light.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a surface-emitting laser element, and more particularly to a method for manufacturing a surface-emitting laser element having a photonic crystal. [Background technology]

[0002] In recent years, development of photonic-crystal surface-emitting lasers (PCSELs) using photonic crystals (PCs) has been progressing.

[0003] For example, Patent Document 1 discloses a photonic crystal surface emitting laser that includes a p-side electrode that functions as a reflecting surface and is capable of emitting a main beam and a sub-beam.

[0004] Non-Patent Document 1 discloses a photonic crystal surface-emitting laser that uses a semiconductor DBR as a p-side reflection structure, and Non-Patent Document 2 discloses a high-power photonic crystal surface-emitting laser that has a p-side electrode that functions as a reflection surface.

[0005] Furthermore, Non-Patent Document 3 discloses a formulation of diffracted light from a photonic crystal surface-emitting laser, and a profile of diffracted radiation waves diffracted in a photonic crystal layer and emitted in a direction perpendicular to the photonic crystal layer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-149403 [Non-patent literature]

[0007] [Non-Patent Document 1] Yoshida, M. et al., Double-lattice photonic-crystal resonators enabling high-brightness semiconductor lasers with symmetric narrow-divergence beams. Nat. Mater. 18, 121 (2019). [Non-patent document 2] Hirose, K. et al. Watt-class high-power, high-beam-quality photonic-crystal lasers. Nat. Photon. 8, 406-411 (2014). [Non-patent document 3] Y. Liang et al.: Phys.Rev. B vol.84, 195119 (2011) Summary of the Invention [Problem to be solved by the invention]

[0008] In a photonic crystal surface-emitting laser (PCSEL), light oscillated by two-dimensional in-plane resonance in a photonic crystal layer is diffracted in the direction perpendicular to the surface, and the emitted light is extracted from the substrate side.

[0009] In this case, the light diffracted from the photonic crystal layer toward the substrate (direct diffracted light) interferes with the light diffracted in the opposite direction and reflected by the reflective surface (reflected diffracted light).This interference significantly changes the characteristics of the emitted light, such as the slope efficiency.

[0010] The interference between the direct diffracted light and the reflected diffracted light is determined by the optical path length in the semiconductor layer between the photonic crystal layer and the reflecting surface, but it is extremely difficult to grow the semiconductor layer while controlling the layer thickness with such precision that the optical path length can be determined. Therefore, it has been difficult to manufacture a photonic crystal surface-emitting laser in which the characteristics of the emitted light are controlled with high precision.

[0011] The present invention has been made in light of the above points, and aims to provide a method for manufacturing a photonic crystal surface-emitting laser in which the oscillation wavelength and emission characteristics are controlled with high precision. Another aim is to provide a photonic crystal surface-emitting laser having high-performance emission characteristics such as high slope efficiency, and a manufacturing method for manufacturing the photonic crystal surface-emitting laser with a high yield. [Means for solving the problem]

[0012] A method for manufacturing a surface-emitting laser element according to one embodiment of the present invention includes the steps of: (a) forming a first semiconductor layer of a first conductivity type including a photonic crystal layer on a light-transmitting substrate; (b) forming an active layer and a second semiconductor layer of a second conductivity type in this order by performing crystal growth on the first semiconductor layer; (c) irradiating the surface of the second semiconductor layer with light and performing spectroscopic measurement to measure the layer thickness from the surface to the position where the irradiated light is reflected by the photonic crystal layer; (d) forming a translucent electrode on the second semiconductor layer, the translucent electrode having a layer thickness calculated based on an optical path length corresponding to the layer thickness obtained by the spectroscopic measurement; (e) forming a light-reflecting layer on the translucent electrode; The thickness of the translucent electrode is determined so that the intensity of the interference light between the direct diffracted light emitted from the photonic crystal layer and emitted from the back surface of the substrate and the reflected diffracted light emitted from the photonic crystal layer and reflected by the light reflecting layer is greater than the intensity of the direct diffracted light. [Brief explanation of the drawings]

[0013] [Figure 1A] 1 is a cross-sectional view schematically showing an example of the structure of a photonic crystal surface-emitting laser element 10 according to an embodiment of the present invention. [Figure 1B] 1B is a partially enlarged cross-sectional view schematically showing an air hole layer 14P (photonic crystal layer) of FIG. 1A and air holes 14K arranged in the air hole layer 14P. FIG. [Figure 2A]FIG. 1 is a plan view schematically showing the top surface of a PCSEL device 10 (with pad electrodes 33 removed). [Figure 2B] 2 is a cross-sectional view schematically showing a cross section of a hole layer 14P in a plane parallel to the n-side guide layer 14. FIG. [Figure 2C] FIG. 2 is a plan view schematically showing the bottom surface of the PCSEL device 10. [Figure 3] FIG. 10 is a diagram schematically showing an example of a hole arrangement in a plane parallel to a photonic crystal layer 14P. [Figure 4] 1 is a manufacturing process flow diagram showing a method for manufacturing the PCSEL device 10. FIG. [Figure 5] FIG. 10 is a diagram schematically showing the upper surface of the wafer WF after crystal growth is completed. [Figure 6] 10 is a graph showing the spectral reflectance curve of the wafer WF after growth is completed. [Figure 7] 10 is a diagram showing a schematic diagram of surface reflected light ES and reflected light ER by a photonic crystal 14P when irradiation light EM of a spectroscopic reflectance measurement device is irradiated onto a wafer WF. FIG. [Figure 8] 10 is a diagram schematically showing interference between reflected diffracted light Lr that is reflected by the light reflecting layer 32 and emitted from the light emitting surface, and diffracted light Ld that is directly emitted from the light emitting surface. FIG. [Figure 9A] 1 is a graph plotting the slope efficiency versus the oscillation wavelength of the PCSEL device 10 of Example (EX). [Figure 9B] 10 is a graph plotting slope efficiency versus oscillation wavelength for a PCSEL device of a comparative CMP. DETAILED DESCRIPTION OF THE INVENTION

[0014] In the following, preferred embodiments of the present invention will be described, but these may be modified and combined as appropriate. In the following description and accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0015] [First embodiment] 1. Structure of photonic crystal surface-emitting laser (a) Device structure A photonic crystal surface-emitting laser (hereinafter also referred to as PCSEL) is an element that has a resonator layer parallel to the semiconductor light-emitting structure layers (n-side guide layer, light-emitting layer, p-side guide layer) that constitute the light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.

[0016] In a photonic crystal surface-emitting laser (PCSEL), light waves propagating in a plane parallel to the photonic crystal layer are diffracted by the diffraction effect of the photonic crystal to form a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to the parallel plane. In other words, in a photonic crystal surface-emitting laser, the light extraction direction is perpendicular to the resonance direction (in the plane parallel to the photonic crystal layer).

[0017] Fig. 1A is a cross-sectional view schematically illustrating an example of the structure of a photonic crystal surface-emitting laser device (hereinafter referred to as a PCSEL device) 10 according to an embodiment of the present invention. Fig. 1B is an enlarged cross-sectional view schematically illustrating a photonic crystal layer 14P and air hole pairs 14K arranged in the photonic crystal layer 14P in Fig. 1A.

[0018] 1A, a semiconductor structure layer 11 is formed on a light-transmitting substrate 12. The semiconductor layers are stacked perpendicularly to the central axis CX of the semiconductor structure layer 11.

[0019] The semiconductor structure layer 11 is made of a hexagonal nitride semiconductor. In this embodiment, the semiconductor structure layer 11 is made of, for example, a GaN-based semiconductor.

[0020] More specifically, a semiconductor structure layer 11 consisting of a plurality of semiconductor layers is formed on a substrate 12, namely, an n-clad layer (first clad layer of a first conductivity type) 13, an n-side guide layer (first guide layer) 14 which is a guide layer provided on the n-side, an active layer (ACT) 15, a p-side guide layer (second guide layer) 16 which is a guide layer provided on the p-side, an electron barrier layer (EBL: Electron Blocking Layer) 17, a p-clad layer (second clad layer of a second conductivity type) 18, and a p-contact layer 19, which are formed in this order.

[0021] Although the case where the first conductivity type is n-type and the second conductivity type opposite to the first conductivity type is p-type will be described, the first conductivity type and the second conductivity type may be p-type and n-type, respectively.

[0022] Substrate 12 is a hexagonal GaN single crystal substrate with high transmittance for light emitted from active layer 15. More specifically, substrate 12 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is the +c plane, which is the {0001} plane with Ga atoms arranged at the outermost surface. The back surface (light emission surface) is the -c plane, which is the (000-1) plane with N atoms arranged at the outermost surface. The -c plane is suitable as a light emission surface because it is resistant to oxidation and the like.

[0023] Although the substrate 12 is not limited to this, a so-called just substrate or, for example, a substrate whose main surface is offset by about 1° in the m-axis direction is preferable. For example, a substrate offset by about 1° in the m-axis direction can achieve mirror-finish growth under a wide range of growth conditions.

[0024] The substrate surface (back surface, light emission surface) on which the light emission region 20L is provided, facing the main surface, is the "-c" plane, which is the (000-1) plane with N atoms arranged on the outermost surface. The -c plane is resistant to oxidation and is therefore suitable as a light extraction surface.

[0025] The composition, thickness, and other configurations of each semiconductor layer will be explained below, but these are merely examples and can be modified as appropriate.

[0026] The n-clad layer 13 is made of, for example, n-Al having an Al composition of 4%. 0.04 Ga 0.96 The N layer has a thickness of 2 μm. The aluminum (Al) composition ratio is set so that the refractive index is smaller than that of the layer adjacent to the active layer 15 (that is, the n-side guide layer 14).

[0027] The n-side guide layer 14 is composed of a lower guide layer 14A, an air-hole layer 14P, which is a photonic crystal layer (PC layer), and a buried layer 14B. As shown in FIG. 1B, the air-hole layer 14P has a layer thickness (depth) d PC The buried layer 14B has a thickness d EMB It has.

[0028] The lower guide layer 14A is, for example, n-GaN having a layer thickness of 20 to 500 nm. The air-hole layer 14P is n-GaN having a layer thickness (or the depth of the air holes 14K) of 60 to 150 nm.

[0029] The buried layer 14B is made of n-GaN, n-InGaN, undoped GaN, or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked. The buried layer 14B has a thickness of, for example, 50 to 150 nm.

[0030] The active layer 15, which is a light-emitting layer, is a multiple quantum well (MQW) layer having, for example, two quantum well layers. The barrier layer and quantum well layer of the MQW are GaN (layer thickness 6.0 nm) and InGaN (layer thickness 3.0 nm), respectively. The gain wavelength of the active layer 15 is 432 nm.

[0031] The active layer 15 is preferably located within 180 nm of the hole layer 14P, in order to obtain a high resonance effect due to the hole layer 14P.

[0032] The p-side guide layer 16 is made of, for example, undoped GaN or undoped InGaN and has a thickness of 100 to 350 nm. The p-side guide layer 16 is an undoped layer in consideration of light absorption by dopants, but may be doped with magnesium (Mg) or the like to obtain good electrical conductivity.

[0033] Alternatively, the p-side guide layer 16 may have a structure in which an undoped layer and a doped layer are stacked. Alternatively, an InGaN layer and a GaN layer may be stacked as the p-side guide layer 16, and the In composition and thickness of the InGaN layer may be selected appropriately.

[0034] The electron barrier layer (EBL) 17 is a magnesium (Mg) doped p-type Al 0.2 Ga 0.8 The N layer has a thickness of, for example, 15 nm.

[0035] The p-cladding layer 18 is made of Mg-doped p-Al 0.06 Ga 0.94 The Al composition of the p-cladding layer 18 is preferably selected so that the refractive index is smaller than that of the p-side guide layer 16.

[0036] The p-contact layer 19 is a Mg-doped p-GaN layer having a thickness of, for example, 25 nm. The carrier density of the p-contact layer 19 is set to a concentration that allows for ohmic contact with the transparent electrode 31 provided on the surface of the p-contact layer 19. Instead of p-type GaN, p-type InGaN may be used. Alternatively, a layer in which a GaN layer and an InGaN layer are stacked may be used.

[0037] In this specification, "n-side" and "p-side" do not necessarily mean n-type and p-type. For example, an n-side guide layer means a guide layer provided on the n-side of the active layer, and may be an undoped layer (or i-layer).

[0038] The n-cladding layer 13 may be composed of multiple layers, not just a single layer. In this case, all layers do not need to be n-layers (n-doped layers), and may include undoped layers (i-layers). The same applies to the guide layer 16 and the p-cladding layer 18.

[0039] Furthermore, it is not necessary to provide all of the semiconductor layers described above, and it is sufficient to have a configuration that includes a first semiconductor layer of a first conductivity type including a photonic crystal layer, a second semiconductor layer of a second conductivity type, and an active layer (light-emitting layer) sandwiched between these layers.

[0040] The side and top surfaces of the semiconductor structure layer 11 are covered with an insulating film 21 such as SiO2. The insulating film 21 has an opening OP with a diameter RA (central axis CX) that exposes the top surface of the semiconductor structure layer 11 (i.e., the top surface of the p-contact layer 19).

[0041] The insulating film 21 also functions as a protective film, protecting the aluminum (Al)-containing crystal layers that make up the PCSEL device 10 from corrosive gases and other contaminants. It also prevents short circuits caused by deposits or solder creeping up during mounting, contributing to improved reliability and yield. The material for the insulating film 21 is not limited to SiO2, but can also be ZrO2, HfO2, TiO2, Al2O3, SiNx, Si, etc.

[0042] A transparent electrode 31 (anode) is provided on the p-contact layer 19 exposed from the opening OP, and is in ohmic contact with the p-contact layer 19. More specifically, the transparent electrode 31 is formed to fill the opening OP, with its peripheral edge lying on the insulating film 21. For ease of understanding, the region of the transparent electrode 31 within the opening OP will be described as an anode region RA, using the same reference symbol as the diameter of the opening OP.

[0043] The transparent electrode 31 is formed of a transparent conductor, for example, indium tin oxide (ITO). Note that the material of the transparent electrode 31 is not limited to ITO, and other transparent conductors such as zinc tin oxide (ZTO), GZO (ZnO:Ga), and AZO (ZnO:Al) can be used.

[0044] A silver alloy (Ag alloy) layer is provided on the translucent electrode 31 as a light-reflecting layer 32. The light-reflecting layer 32 is provided so as to cover at least the entire opening OP when viewed from above. The light-reflecting layer 32 has a flat surface (upper surface) parallel to the hole layer 14P.

[0045] The light reflecting layer 32 may also be made of Ag, Al, an Al alloy, a dielectric DBR (Distributed Bragg Reflector), or the like.

[0046] A pad electrode 33 made of nickel / palladium / gold (Ni / Pd / Au) is provided on the light reflecting layer 32 so as to cover the entire light reflecting layer 32. The pad electrode 33 may also be made of Ni / Au, platinum / gold (Pt / Au), Pt / Pd / Au, titanium / gold (Ti / Au), Ti / Pt / Au, tungsten / palladium / gold (W / Pd / Au), W / Au, W / Pt / Au, or the like.

[0047] A circular cathode electrode 20A is formed on the back surface of the substrate 12. An anti-reflection (AR) coating layer 27 is formed on the inner surface of the cathode electrode 20A.

[0048] The cathode electrode 20A is made of Ti / Pt / Au and is in ohmic contact with the substrate 12. In addition to Ti / Pu / Au, the electrode material can also be selected from Ti / Al, Ti / Rh, Ti / Al / Pt / Au, Ti / Au, vanadium / aluminum (V / Al), V / Rh, V / Al / Pt / Au, V / Pt / Au, and the like.

[0049] The light emitted from the active layer 15 is diffracted by the air hole layer (PC layer) 14P. The light diffracted by the air hole layer 14P and directly emitted from the air hole layer 14P (direct diffracted light Ld: first diffracted light) and the light diffracted by the air hole layer 14P and reflected by the light reflecting layer 32 (reflected diffracted light Lr: second diffracted light) are emitted to the outside from a light emitting region 20L (FIG. 2C) on the back surface (emission surface) 12R of the substrate 12.

[0050] 2A is a plan view schematically showing the top surface of the PCSEL device 10. For clarity and ease of understanding, the top surface is shown with the pad electrodes 33 removed.

[0051] 2B is a cross-sectional view of the hole layer 14P taken along a plane parallel to the n-side guide layer 14, and FIG. 2C is a plan view of the bottom surface of the PCSEL device 10. As shown in FIG.

[0052] As shown in Fig. 2B, in the hole layer 14P, the holes 14K are periodically arranged within, for example, a rectangular hole-forming region 14R. As shown in Fig. 2C, the anode region RA is formed so as to be included within the hole-forming region 14R.

[0053] The cathode electrode 20A is provided as a ring-shaped electrode outside the hole formation region 14R so as not to overlap with the hole formation region 14R when viewed from a direction perpendicular to the hole layer 14P.

[0054] The region inside the cathode electrode 20A is the light emitting region 20L. Also provided is a bonding pad 20C that is electrically connected to the cathode electrode 20 and to which a wire for supplying power from the outside is connected.

[0055] (b) Photonic crystal layer As shown in FIGS. 1A and 1B, photonic crystal layer 14P has regularly arranged air holes that cause light emitted from active layer 15 to resonate in a horizontal plane.

[0056] 3 is a diagram schematically illustrating an example of a hole arrangement in a plane parallel to the photonic crystal layer 14P. That is, it is a plan view schematically illustrating a hole pair 14K (hereinafter sometimes simply referred to as hole 14K) consisting of a main hole 14K1 and a sub-hole 14K2 arranged at a square lattice position in the plane of the photonic crystal layer 14P, as viewed from above.

[0057] That is, photonic crystal layer 14P has a double lattice structure. For clarity of the drawing, main holes 14K1 and sub-holes 14K2 are shown hatched.

[0058] More specifically, the main voids 14K1 are arranged such that their centers of gravity CD1 are arranged at square lattice positions with a period PK in two mutually perpendicular directions (x direction and y direction).Similarly, the sub-voids 14K2 are arranged such that their centers of gravity CD2 are arranged at square lattice positions with a period PK in the x direction and y direction.

[0059] Main hole 14K1 has a long hexagonal shape surrounded by m-planes, which are {10-10} planes, in top view (i.e., when viewed from a direction perpendicular to photonic crystal layer 14P). Subhole 14K2 also has a shape surrounded by m-planes.

[0060] The x and y directions are inclined at 45° with respect to the long axis direction (<11-20> direction) and the short axis direction (<1-100> direction) of the main hole 14K1, respectively. In this specification, the x and y coordinates are also referred to as the hole coordinates.

[0061] The center of gravity CD2 of the sub-hole 14K2 is spaced apart from the center of gravity CD1 of the main hole 14K1 by Δx in the x-direction and Δy in the y-direction. Here, Δx=Δy=0.46PK. That is, the center of gravity CD2 of the sub-hole 14K2 is spaced apart from the center of gravity CD1 of the main hole 14K1 in the <1-100> direction.

[0062] Here, the distance Δx between the centers of gravity in the x direction and the distance Δy between the centers of gravity in the y direction can be appropriately adjusted according to laser characteristics such as, for example, the current value required for a device to which the laser element is applied, the slope efficiency of the laser output intensity, etc.

[0063] Although the photonic crystal layer 14P has a double lattice structure in this example, the present invention is not limited to this. The photonic crystal layer 14P may have a single lattice structure or a multiple lattice structure.

[0064] 2. PCSEL Device Manufacturing Method Next, a method for manufacturing the PCSEL device 10 will be described with reference to the manufacturing process flow shown in Figure 4. In the following Example (EX), an investigation was conducted into improving the slope efficiency of the PCSEL device 10 with an oscillation wavelength of 432 nm.

[0065] (S1: Crystal growth step) Using an MOVPE (Metalorganic Vapor Phase Epitaxy) device, an n-Al cladding layer 13 was deposited on a +c-plane GaN substrate 12. 0.04 Ga 0.96 The N layer was formed to a thickness of 2 μm, and then an n-GaN layer was formed on the n-clad layer 13 to a thickness of 500 nm.

[0066] (S2: Patterning step) A SiNx film approximately 100 nm thick was formed on the n-GaN layer using plasma CVD. Next, an electron beam lithography resist was spin-coated onto the SiNx film and placed in an electron beam lithography system (EB system) to form a two-dimensional periodic pattern corresponding to the two-dimensional photonic crystal structure described above.

[0067] At this time, in order to be able to examine the influence of phase, the resist was patterned so that different void periods PKj were formed in the plurality of void formation regions Wj, so that elements with oscillation wavelengths of 429 nm to 440 nm could be obtained on the same substrate.

[0068] After developing the patterned resist, the SiNx was selectively dry-etched using an inductively coupled plasma reactive ion etching (ICP-RIE) system, resulting in the formation of vacancies arranged in a square lattice pattern that penetrated the SiNx film.

[0069] The resist was then removed, and the n-GaN layer was dry-etched using the SiNx hard mask in an ICP-RIE system with Cl2, BCl3, and Ar gases. The etching depth was approximately 190 nm. The SiNx hard mask was then removed using buffered hydrofluoric acid (BHF).

[0070] (S3: Recrystallization growth step) The substrate on which the photonic crystal was formed was placed back into the MOVPE apparatus, and buried growth was performed to leave voids. That is, undoped GaN was grown to a thickness of 70 nm and undoped InGaN was grown to a thickness of 50 nm to form buried layer 14B. This resulted in the formation of n-side guide layer 14 including photonic crystal layer 14P.

[0071] Subsequently, two pairs of InGaN / GaN active layers 15 (MQW layers) were grown on the burying layer 14B (i.e., on the n-side guide layer 14). Subsequently, undoped InGaN and undoped GaN were grown on the active layer 15 to a thickness of 70 nm and 180 nm, respectively, to form the p-side guide layer 16.

[0072] Next, a p-AlGaN electron barrier layer 17 was grown to a thickness of 15 nm, and a p-AlGaN layer (p-clad layer 18) was grown to a thickness of 300 nm on the electron barrier layer 17. Next, a p-contact layer 19 consisting of a p-GaN / p-InGaN layer was grown to a thickness of 25 nm.

[0073] The entire semiconductor layer formed on the n-side guide layer 14 is referred to as an upper guide layer semiconductor layer 11K.

[0074] 5 is a diagram schematically illustrating the upper surface of the wafer WF after the crystal growth formed as described above is completed. Specifically, it shows that regions Wj (W1 to W9) in which holes are arranged at different hole periods PKj (j = 1 to 9) are provided in the photonic crystal layer 14P formed in the n-side guide layer 14.

[0075] More specifically, the hole period PKj of each of the regions W1 to W9 is set to an integer multiple of the resonance wavelength (λ). To achieve an oscillation wavelength of 429 nm to 440 nm, the hole periods PKj are set to PK1=172 nm, PK2=173.2 nm, . . . , PK9=182.8 nm in 1.2 nm increments.

[0076] Air holes 14K1 and 14K2 have a hexagonal shape surrounded by m-planes, which are {10-10} planes, when viewed from above. Main air holes 14K1 of photonic crystal layer 14P have a depth of 90 nm, and sub-air holes 14K2 have a depth of 70 nm.

[0077] Here, a wafer WF having a different hole period PKj for each region Wj was formed for evaluation by spectral reflectance measurement, which will be described later. However, in the wafer WF for actually manufacturing the PCSEL device 10, it is sufficient to form a photonic crystal layer 14P with a single hole period PK.

[0078] (S4: Spectral reflectance measurement step) Light was irradiated onto the topmost growth surface (i.e., the surface of the p-contact layer 19) of the above-described grown wafer WF (hereinafter also simply referred to as wafer WF), and spectral reflectance measurement was performed. Based on the spectral reflectance measurement results, the thickness of the transparent electrode 31 (transparent conductor film) to be formed subsequently was determined. The method of spectral reflectance measurement and the results thereof will be described in detail later.

[0079] (S5: insulating film formation step) On the grown wafer WF, SiO2 was deposited by sputtering to a thickness of 100 nm to form an insulating film 21. Subsequently, after patterning a resist by photolithography, the SiO2 was removed by BFH to form an opening OP with a diameter of 300 μm, through which the top surface of the p-contact layer 19 was exposed.

[0080] (S6: Transparent electrode formation step) Next, a transparent electrode 31, which is an ITO film that covers the upper surface of the insulating film 21 and fills the opening OP, was formed by sputtering.

[0081] Subsequently, the resist was patterned by photolithography, and then wet etching was carried out to remove the ITO film from unnecessary regions, thereby forming a transparent electrode 31 having a flat surface and parallel to photonic crystal layer 14P.

[0082] From the results of the spectral reflectance measurement, the layer thickness of the transparent electrode 31 was set to 135 nm in the wafer WF of the example (EX). The wafer of the comparative example (CMP) was also set to the same 135 nm as the wafer of the example (EX) for the evaluation of device characteristics.

[0083] That is, in the example (EX), the layer thickness of the translucent electrode 31 was set to a layer thickness that satisfied the condition in which the phases of the direct diffracted light Ld and the reflected diffracted light Lr match and they are most constructively interfering with each other through interference, while in the comparative example (CMP), the layer thickness was set to a layer thickness that did not satisfy the condition in which they are most constructively interfering with each other (however, the light intensity is greater than that of the direct diffracted light Ld).

[0084] Here, the condition (interference condition) for the constructive interaction of the light intensities of the interference light of the direct diffracted light Ld and the reflected diffracted light Lr is sufficient as long as the light intensity of the interference light is greater than the light intensity of the direct diffracted light Ld. Preferably, the condition is such that the phases of the direct diffracted light Ld and the reflected diffracted light Lr emitted from the PCSEL device 10 match and they constructively interact with each other to the greatest extent possible.

[0085] The thickness of the transparent electrode 31 may be set to a thickness that satisfies the condition that the optical intensities of the interference light of the direct diffracted light Ld and the reflected diffracted light Lr weaken each other.

[0086] (S7: Light reflecting layer forming step) A silver (Ag) alloy film was formed to a thickness of 150 nm on the translucent electrode 31 to form a light-reflecting layer 32. By forming the light-reflecting layer 32, a light-reflecting surface SR was formed at the interface between the translucent electrode 31 and the light-reflecting layer 32.

[0087] (S8: Electrode and anti-reflection layer formation step) On the light reflecting layer 32, Ni / Pd / Au films were successively formed to thicknesses of 10 nm / 200 nm / 800 nm to form the pad electrode 33.

[0088] Next, the back surface of the substrate was polished and then mirror-finished by chemical mechanical polishing (CMP) to obtain a wafer WF with a thickness of 170 nm. Subsequently, a Ti / Pt / Au film (layer thickness: 50 nm / 50 nm / 500 nm) was formed on the polished surface to form a cathode electrode 20A.

[0089] Furthermore, a SiN film is formed on the rear surface of the substrate in the inner region of the cathode electrode 20A (i.e., the light emitting region 20L). x / SiO2 (layer thickness: 32 nm / 53 nm) was deposited to form a non-reflective coating layer 27 as an anti-reflection layer.

[0090] (S9: Singulation step) Finally, the wafer WF was scribed using a laser scriber or a diamond scriber, and then separated into individual pieces using a cleavage device, yielding 80 PCSEL devices 10 with different void periods PK (laser wavelengths λ). 3. Spectral reflectance measurement and evaluation results The method and results of the spectral reflectance measurement in the spectral reflectance measurement step (S4) will now be described.

[0091] Fig. 6 is a graph showing the spectral reflectance curve of the wafer WF after growth is completed. Fig. 7 is a diagram showing the surface reflected light ES and the reflected light ER from the photonic crystal 14P when the wafer WF is irradiated with irradiation light EM from a spectral reflectance measurement device. For clarity of illustration, the main void 14K1 and the sub-void 14K2 of the photonic crystal layer 14P are shown as a void pair 14K.

[0092] Photonic crystal layer 14P is a layer containing voids, and has a lower refractive index than other semiconductor layers. Therefore, the observed spectral reflectance curve shown in Figure 6 is the result of interference between surface-reflected light ES and reflected light ER from photonic crystal 14P, as shown schematically in Figure 7.

[0093] Since the rear surface of the GaN substrate 11 is rough, light is scattered and rear surface reflection can be almost ignored. In addition, the refractive index difference between other semiconductor layers (for example, between GaN / AlGaN layers) is 10-1 ~10 -2 Therefore, reflection at these interfaces has almost no effect.

[0094] The thickness of each semiconductor layer of semiconductor layer 11K on the guiding layer was found from the spectral reflectance curve shown in Fig. 6, assuming that the semiconductor layers on the guiding layer are GaN. In detail, semiconductor layer 11K on the guiding layer includes a layer of mixed crystal composition (InAlGaN layer), and the optical path length from photonic crystal layer 14P to the surface of p-contact layer 19 is important. Therefore, calculations and fitting were performed assuming that semiconductor layer 11K on the guiding layer is a single layer of GaN, and the layer thickness was found.

[0095] The thickness of each semiconductor layer in the semiconductor layer 11K on the guide layer may be measured in detail using a spectroscopic ellipsometer, which can be measured using existing techniques based on basic Fresnel reflection.

[0096] In this manner, the layer thickness DP (or optical path length) from the surface of p-contact layer 19 (i.e., the surface of wafer WF) to the reflection position RP of irradiated light EM in photonic crystal layer 14P was determined. As a result, the layer thickness DP of Example EX was 735 nm.

[0097] Furthermore, a wafer grown under the same conditions as the wafer WF of Example EX was formed as the wafer WC of Comparative Example CMP. That is, the wafer WC of Comparative Example CMP has the n-guide layer 14 and photonic crystal 14P of the same structure as the wafer WF of Example EX.

[0098] In other words, due to the reproducibility of layer thickness during crystal growth, it is expected that the grown layer thickness (layer thickness of the semiconductor layer 11K on the guide layer) will be different between the wafer WF of Example EX and the wafer WC of Comparative Example CMP, even if the crystal growth is performed under the same conditions.

[0099] In fact, as shown in Figure 6, it was found that the spectral reflectance curve was slightly shifted to the long wavelength side compared to the wafer WF of Example EX. From the measured spectral reflectance curve, the layer thickness DP of the wafer WC of Comparative Example CMP was calculated, and it was found to be DP = 755 nm. Therefore, it was found that the layer thickness of the guide layer-over-semiconductor layer 11K differed by about 3% from the wafer WF of Example EX.

[0100] 4. Characterization of PCSEL Devices Figure 8 shows a schematic diagram of the interference between reflected diffracted light Lr emitted from the photonic crystal layer 14P, reflected by the light reflecting layer 32 (light reflecting surface SR), and emitted from the back surface (light emitting surface) of the substrate 12, and directly diffracted light Ld emitted from the photonic crystal layer 14P toward the back surface of the substrate 12.

[0101] The direct diffracted light Ld and the reflected diffracted light Lr interfere with each other due to an optical path difference corresponding to the layer thickness DP. As is clear from FIG. 8, the optical path difference between the direct diffracted light Ld and the reflected diffracted light Lr is equal to twice the distance, which is the sum of the layer thickness DP and the layer thickness of the translucent electrode 31 (the layer thickness from the surface of the p-contact layer 19 to the light-reflecting layer 32). Therefore, by determining the layer thickness DP, the layer thickness of the translucent electrode 31 that satisfies the interference condition can be calculated. In the example (EX), the layer thickness of the translucent electrode 31 is determined so that the phases of the direct diffracted light Ld and the reflected diffracted light Lr match. In addition, the comparative example (CMP) has a translucent electrode 31 with a layer thickness that does not satisfy the condition for the phases of the direct diffracted light Ld and the reflected diffracted light Lr to match.

[0102] Since spectral reflectance measurement is used, the reflection position RP within the photonic crystal 14P can be directly measured. In addition, since it is a non-destructive measurement, the optical path length can be calculated with high precision even for a stack of multiple layers with different refractive indices. In other words, the optical path length difference between the direct diffracted light Ld and the reflected diffracted light Lr can be measured directly and with high precision.

[0103] Specifically, the precision of the optical path length difference is within 1%, which translates to a semiconductor layer thickness of within 2-3 nm.

[0104] The diffraction position (wave source position) WS of the diffracted light in the photonic crystal layer 14P may be slightly different from the reflection position RP in the spectroscopic measurement due to differences between the oscillation wavelength and the wavelength of the irradiated light in the spectroscopic measurement (FIG. 8).

[0105] For example, from Non-Patent Document 3, the wave source (diffraction plane) of the diffracted wave by the air hole layer 14P and the diffracted radiation wave radiated in the direction perpendicular to the air hole layer 14P can be calculated using coupled wave theory.

[0106] However, if the controllability and reproducibility of the semiconductor layer thickness during crystal growth are taken into consideration, the diffraction position (wave source position) WS can be sufficiently approximated by the reflection position RP obtained by spectral reflectance measurement.

[0107] FIG. 9A is a graph plotting the slope efficiency versus the oscillation wavelength of the PCSEL device 10 of Example (EX) obtained from the wafer WF (with a transparent electrode 31 having a layer thickness of 135 nm).

[0108] FIG. 9B is a graph plotting the slope efficiency versus the oscillation wavelength of a PCSEL device of comparative example CMP obtained from wafer WC (transparent electrode 31 layer thickness: 135 nm).

[0109] Specifically, pulse current was injected into the PCSEL device 10 of the example (EX) and the PCSEL device of the comparative example CMP, and the optical output was measured, and the results of measuring the slope efficiency are shown.

[0110] 9A, the PCSEL device 10 of Example (EX) exhibited a maximum slope efficiency at an oscillation wavelength of approximately 432 nm (dash-dotted line in the figure), which is the target oscillation wavelength. This is due to the effect of interference, and as the oscillation wavelength changes, the optical path length and therefore the slope efficiency also change.

[0111] 9B, the PCSEL device of Comparative Example CMP exhibited a maximum slope efficiency at an oscillation wavelength of approximately 438 nm, which is offset from the target oscillation wavelength. Furthermore, the distribution of the slope efficiency was wider than that of Example (EX) PCSEL device 10, resulting in a low yield of devices with the desired oscillation wavelength and slope efficiency.

[0112] In other words, in the wafer WC of the comparative CMP, in order to obtain the maximum slope efficiency at an oscillation wavelength of 432 nm, as in the wafer WF of the example (EX), the layer thickness of the transparent electrode 31 should be 110 nm.

[0113] Even when the photonic crystal layer 14P has a multiple lattice structure, the layer thickness DP (or optical path length) up to the reflection position RP can be measured with high accuracy, because in a multiple lattice structure, the reflection position RP can vary significantly depending on the relative sizes of the main and sub-holes, their relative positions in the depth direction, and their shapes.

[0114] Furthermore, although the crystal growth has been described using the MOVPE method, it is not limited to this method, and other vapor phase growth methods such as MBE (molecular beam epitaxy), hydride vapor phase epitaxy (HVPE), and sputtering, as well as liquid phase growth methods, can also be used.

[0115] As explained above, spectral reflectance measurement is performed on the wafer after crystal growth to analyze the thickness of the semiconductor layer, and the thickness of the transparent electrode 31 is determined in accordance with the layer thickness. This makes it possible to obtain a photonic crystal surface-emitting laser in which the oscillation wavelength and emitted light characteristics are controlled with high precision, and also to provide a manufacturing method for manufacturing the photonic crystal surface-emitting laser with a high yield. [Explanation of symbols]

[0116] 10: PCSEL element, 11: semiconductor structure layer, 11K: semiconductor layer above n-guide layer, 12: substrate, 13: first cladding layer, 14: first guide layer, 14A: lower guide layer, 14P: photonic crystal layer, 14B: buried layer, 14K: air holes, 15: active layer, 16: second guide layer, 17: electron barrier layer, 18: second cladding layer, 19: contact layer, 20A: cathode electrode, 21: insulating film, 31: light-transmitting electrode, 32: light-reflecting layer, 33: pad electrode, DP: layer thickness between surface and reflection position, OP: opening, RP: reflection position, SR: reflection surface

Claims

1. (a) forming a first semiconductor layer of a first conductivity type including a photonic crystal layer on a light-transmitting substrate; (b) growing crystals on the first semiconductor layer to form an active layer and a second semiconductor layer of a second conductivity type in this order; (c) irradiating the surface of the second semiconductor layer with light and performing spectroscopic measurement to measure the layer thickness from the surface to a position where the irradiated light is reflected by the photonic crystal layer; (d) forming a transparent electrode on the second semiconductor layer, the transparent electrode having a layer thickness calculated based on an optical path length corresponding to the layer thickness obtained by the spectroscopic measurement; (e) forming a light-reflecting layer on the transparent electrode; a thickness of the translucent electrode is determined so that the intensity of interference light between direct diffracted light emitted from the photonic crystal layer and emitted from the back surface of the substrate and reflected diffracted light emitted from the photonic crystal layer and reflected by the light reflecting layer is greater than the intensity of the direct diffracted light.

2. 2. The method for manufacturing a surface-emitting laser element according to claim 1, wherein the spectroscopic measurement is performed using a spectroscopic ellipsometer.

3. The method for manufacturing a surface-emitting laser element according to claim 1 , wherein the photonic crystal layer has a multi-lattice structure.

4. 2. The method for manufacturing a surface-emitting laser element according to claim 1, wherein the active layer and the second semiconductor layer are crystal-grown by MOVPE.

5. 5. The method for manufacturing a surface-emitting laser element according to claim 1, wherein the thickness of the transparent electrode is determined so that the phases of the direct diffracted light and the reflected diffracted light coincide with each other.

Images