Semiconductor storage device

Abstract

To provide a semiconductor storage device having a storage device drive circuit capable of efficiently performing a screening test of the semiconductor storage device.SOLUTION: A semiconductor storage device includes a write voltage supply circuit 750, a write voltage switching circuit 250, a bit line discharge control circuit 850, a bit line discharge circuit 450, and a memory array 300. The write voltage supply circuit is connected to the memory array via the write voltage switching circuit, the bit line discharge control circuit is connected to the memory array via the bit line discharge circuit, the write voltage supply circuit supplies at least two types of sense line write voltages to the write voltage switching circuit, the write voltage switching circuit individually supplies voltage to at least two groups of sense lines of the memory array, the bit line discharge control circuit outputs at least two types of bit line discharge control signals to the bit line discharge circuit, and the bit line discharge circuit individually supplies discharge voltage to at least two groups of bit lines of the memory array.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device.

Background Art

[0002] In a FLOTOX (Floating Gate Tunnel Oxide) type EEPROM semiconductor memory device, correct data may not be writable or readable due to insulation failure between adjacent wirings of semiconductor elements. In order to detect such a location of insulation failure, the manufacturing process of the semiconductor memory device includes a step of applying a voltage stress between adjacent wirings of the semiconductor element for inspection (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Patent Document 1 discloses the principle of applying a voltage stress between adjacent wirings inside a semiconductor memory device for inspection. However, a specific circuit for generating a signal for applying the voltage stress is not disclosed. An object of the present invention is to provide a semiconductor memory device having a memory element drive circuit capable of efficiently performing a screening test of the memory device.

Means for Solving the Problems

[0005] The semiconductor memory device of the present invention includes a write voltage supply circuit, a write voltage switching circuit, a bit line discharge control circuit, a bit line discharge circuit, and a memory array. The write voltage supply circuit is connected to the memory array via the write voltage switching circuit, and the bit line discharge control circuit is connected to the memory array via the bit line discharge circuit.

Effects of the Invention

[0006] By applying a voltage stress between adjacent wirings and performing an inspection, the screening test of the semiconductor memory device can be efficiently carried out.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0008] Hereinafter, with reference to the drawings, the present invention Embodiment will be described. FIG. 1 is a block diagram showing an example of a semiconductor memory device according to the present embodiment.

[0009] Referring to FIG. 1, the configuration of the semiconductor memory device of this embodiment will be described. The semiconductor memory device of this embodiment includes a data latch circuit 100, a write voltage supply circuit 750, a write voltage switching circuit 250, a bit line discharge control circuit 850, a bit line discharge circuit 450, a row decoder 600, a column decoder 500, and a memory array 300. The write voltage switching circuit 250, the memory array 300, the bit line discharge circuit 450, and the column decoder 500 constitute a memory array circuit 2000.

[0010] The connection of the semiconductor memory device of this embodiment will be described. The data latch circuit 100 and the write voltage supply circuit 750 are connected to the memory array 300 via the write voltage switching circuit 250, and the bit line discharge control circuit 850 and the column decoder 500 are connected to the memory array 300 via the bit line discharge circuit 450.

[0011] Referring to FIG. 2, the configuration of the write voltage supply circuit 750 of this embodiment will be described. The write voltage supply circuit 750 includes an input terminal 7 terminals, an output terminal 3 terminals, four 2-input OR circuits 751 to 754 from the first to the fourth, and three level shift circuits 950 to 952 from the first to the third. The first to third level shift circuits 950 to 952 include a power supply terminal VIN, a first input terminal IN1X, a second input terminal IN2, and an output terminal OUT. The seven input terminals are a write voltage input terminal 701, a first erase cycle control signal input terminal 702, a second erase cycle control signal input terminal 703, a first write cycle control signal input terminal 704, a second write cycle control signal input terminal 705, an odd sense line test signal input terminal 756, and an even sense line test signal input terminal 757. The three output terminals are an even sense line write voltage output terminal 767, an odd sense line write voltage output terminal 768, and a bit line write voltage output terminal 769.

[0012] The connection of the write voltage supply circuit 750 of this embodiment will be described. The write voltage input terminal 701 is connected to the power supply terminal VIN of the first level shift circuit 950, the power supply terminal VIN of the second level shift circuit 951, and the power supply terminal VIN of the third level shift circuit 952. The first erase cycle control signal input terminal 702 is connected to the first input terminal of the first two-input OR circuit 751 and the first input terminal of the third two-input OR circuit 753. The second erase cycle control signal input terminal 703 is connected to the first input terminal of the second two-input OR circuit 752 and the first input terminal of the fourth two-input OR circuit 754. The odd sense line test signal input terminal 756 is connected to the second input terminal of the first two-input OR circuit 751 and the second input terminal of the second two-input OR circuit 752. The even sense line test signal input terminal 757 is connected to the second input terminal of the third two-input OR circuit 753 and the second input terminal of the fourth two-input OR circuit 754.

[0013] The output terminal of the first two-input OR circuit 751 is connected to the first input terminal IN1X of the first level shift circuit 950. The output terminal of the second two-input OR circuit 752 is connected to the second input terminal IN2 of the first level shift circuit 950. The output terminal of the third two-input OR circuit 753 is connected to the first input terminal IN1X of the second level shift circuit 951. The output terminal of the fourth two-input OR circuit 754 is connected to the second input terminal IN2 of the second level shift circuit 951. The first write cycle control signal input terminal 704 is connected to the first input terminal IN1X of the third level shift circuit 952. The second write cycle control signal input terminal 705 is connected to the second input terminal IN2 of the third level shift circuit 952. Thus, the write voltage supply circuit 750 of this embodiment outputs two types of voltages, namely, the odd sense line write voltage and the even sense line write voltage.

[0014] The output terminal OUT of the first level shift circuit 950 is connected to the odd sense line write voltage output terminal 768. The output terminal OUT of the second level shift circuit 951 is connected to the even sense line write voltage output terminal 767. The output terminal OUT of the third level shift circuit 952 is connected to the bit line write voltage output terminal 769.

[0015] Referring to FIG. 3, the configuration of the first level shift circuit 950 of the present embodiment will be described. The first level shift circuit 950 includes a power supply terminal VIN, a first input terminal IN1X, a second input terminal IN2, an output terminal OUT, first to fifth P-channel MOS transistors (hereinafter referred to as PMOS transistors) 901 to 905, first to third N-channel MOS transistors (hereinafter referred to as NMOS transistors) 906 to 908, a first inverter 909, and a second inverter 910.

[0016] The connection of the first level shift circuit 950 of the present embodiment will be described. The power supply terminal VIN is connected to the source terminals of the first PMOS transistor 901, the third PMOS transistor 903, the fifth PMOS transistor 905, and the back gate terminals of the first to fifth PMOS transistors 901 to 905. The first input terminal IN1X is connected to the gate terminal of the second PMOS transistor 902 and the gate terminal of the first NMOS transistor 906 via the first inverter 909, and to the gate terminal of the fourth PMOS transistor 904 and the gate terminal of the second NMOS transistor 907 via the second inverter 910. The second input terminal IN2 is connected to the gate terminal of the third NMOS transistor 908. The source terminals and back gate terminals of the first to third NMOS transistors 906 to 908 are connected to the GND terminal.

[0017] The drain terminal of the first PMOS transistor 901 is connected to the source terminal of the second PMOS transistor 902. The drain terminal of the third PMOS transistor 903 is connected to the source terminal of the fourth PMOS transistor 904. The drain terminal of the second PMOS transistor 902 is connected to the gate terminal of the third PMOS transistor 903, the gate terminal of the fifth PMOS transistor 905, and the drain terminal of the first NMOS transistor 906. The drain terminal of the fourth PMOS transistor 904 is connected to the gate terminal of the first PMOS transistor 901 and the drain terminal of the second NMOS transistor 907. The drain terminal of the fifth PMOS transistor 905 is connected to the drain terminal of the third NMOS transistor 908 and the output terminal OUT. The second level shift circuit 951 and the third level shift circuit 952 also have the same configuration as the first level shift circuit 950. Note that the level shift circuit may have a circuit configuration different from that of the level shift circuit described in this embodiment as long as it is a level shift circuit having a similar function.

[0018] Referring to FIG. 4, the configuration of the bit line discharge control circuit 850 according to this embodiment will be described. The bit line discharge control circuit 850 includes a first erase cycle control signal input terminal 702A, an odd bit line test signal input terminal 851, an even bit line test signal input terminal 852, an even bit line discharge control signal output terminal 862, an odd bit line discharge control signal output terminal 863, a seventh inverter 853, a fifth two-input OR circuit 856, and a sixth two-input OR circuit 857.

[0019] The connection of the bit line discharge control circuit 850 of this embodiment will be described. The first erase cycle control signal input terminal 702A is connected to the first input terminal of the fifth two-input OR circuit 856 and the first input terminal of the sixth two-input OR circuit 857 via the seventh inverter 853. The odd bit line test signal input terminal 851 is connected to the second input terminal of the fifth two-input OR circuit 856. The even bit line test signal input terminal 852 is connected to the second input terminal of the sixth two-input OR circuit 857. The output terminal of the fifth two-input OR circuit 856 is connected to the odd bit line discharge control signal output terminal 863. The output terminal of the sixth two-input OR circuit 857 is connected to the even bit line discharge control signal output terminal 862. Thus, the bit line discharge control circuit 850 of this embodiment outputs two types of signals, namely, the odd bit line discharge control signal and the even bit line discharge control signal.

[0020] With reference to FIGS. 5 to 8, the configuration of the memory array circuit 2000 of this embodiment will be described. FIG. 5 is a circuit diagram showing the entirety of the memory array circuit 2000, the data latch circuit 100, and the row decoder 600. In this embodiment, an example will be described in which the region having the MOS transistor 311 in the memory array 300 becomes the selected address region 310. With reference to FIGS. 6 to 8, each circuit constituting the memory array circuit 2000 will be described in detail. N With reference to FIGS. 6 to 8, an example in which the region having the MOS transistor 311 in the memory array 300 becomes the selected address region 310 will be described. Each circuit constituting the memory array circuit 2000 will be described in detail.

[0021] With reference to FIG. 6, the configuration of the write voltage switching circuit 250 of this embodiment will be described. The write voltage switching circuit 250 of this embodiment includes a bit line write voltage input terminal 205, an even sense line write voltage input terminal 257, an odd sense line write voltage input terminal 258, and the fourth to seventh NMOS transistors 253 to 256. Although a large number of NMOS transistors are provided in addition to the transistors shown in the figure, only the transistors related to the memory elements of interest will be described here.

[0022] The connection of the write voltage switching circuit 250 of this embodiment will be described. The bit line write voltage input terminal 205 is connected to the bit line write voltage output terminal 769 of the write voltage supply circuit 750 outside the write voltage switching circuit 250, and is connected to the source terminal of the fourth NMOS transistor 253 and the source terminal of the fifth NMOS transistor 254 inside the write voltage switching circuit 250. The even sense line write voltage input terminal 257 is connected to the even sense line write voltage output terminal 767 of the write voltage supply circuit 750 outside the write voltage switching circuit 250, and is connected to the source terminal of the sixth NMOS transistor 255 inside the write voltage switching circuit 250. The odd sense line write voltage input terminal 258 is connected to the odd sense line write voltage output terminal 768 of the write voltage supply circuit 750 outside the write voltage switching circuit 250, and is connected to the source terminal of the seventh NMOS transistor 256 inside the write voltage switching circuit 250.

[0023] The sixth NMOS transistor 255 has its gate terminal connected to the even sense line data latch signal line 201 of the data latch circuit 100, and its drain terminal connected to the even sense line 301 in the selected address area 310 of the memory array 300. The seventh NMOS transistor 256 has its gate terminal connected to the odd sense line data latch signal line 202 of the data latch circuit 100, and its drain terminal connected to the odd sense line 302 in the selected address area 310 of the memory array 300. The fourth NMOS transistor 253 has its gate terminal connected to the even bit line data latch signal line 203 of the data latch circuit 100, and its drain terminal connected to the even bit line 303 in the selected address area 310 of the memory array 300. The fifth NMOS transistor 254 has its gate terminal connected to the odd bit line data latch signal line 204 of the data latch circuit 100, and its drain terminal connected to the odd bit line 304 in the selected address area 310 of the memory array 300.

[0024] Referring to FIG. 7, the configuration of the memory array 300 of this embodiment will be described. Here, as described above, the NThe selected address area 310 in this embodiment is the area having the MOS transistor 311. Here, the configuration related to the selected address area 310 will be described.

[0025] The memory array 300 of this embodiment includes the eighth to fifteenth NMOS transistors 311 to 314, 321 to 324, the first to fourth floating gate MOS transistors (hereinafter referred to as FGMOS transistors) 331, 332, 341, 342, an even sense line 301, an odd sense line 302, an even bit line 303, an odd bit line 304, a word 0 selection line 305, and a word 1 selection line 306. The even sense line 301 and the odd sense line 302 are arranged adjacent to each other in the memory array 300. Similarly, the even bit line 303 and the odd bit line 304 are arranged adjacent to each other in the memory array 300.

[0026] The connection of the memory array 300 of this embodiment will be described. The even sense line 301 is connected to the drain terminal of the eighth NMOS transistor 311 and the drain terminal of the twelfth NMOS transistor 321. The odd sense line 302 is connected to the drain terminal of the ninth NMOS transistor 312 and the drain terminal of the thirteenth NMOS transistor 322. The even bit line 303 is connected to the drain terminal of the tenth NMOS transistor 313 and the drain terminal of the fourteenth NMOS transistor 323. The odd bit line 304 is connected to the drain terminal of the eleventh NMOS transistor 314 and the drain terminal of the fifteenth NMOS transistor 324.

[0027] The word 0 selection line 305 is connected to the gate terminal of the eighth NMOS transistor 311, the gate terminal of the ninth NMOS transistor 312, the gate terminal of the tenth NMOS transistor 313, and the gate terminal of the eleventh NMOS transistor 314. The word 1 selection line 306 is connected to the gate terminal of the twelfth NMOS transistor 321, the gate terminal of the thirteenth NMOS transistor 322, the gate terminal of the fourteenth NMOS transistor 323, and the gate terminal of the fifteenth NMOS transistor 324.

[0028] The source terminal of the eighth NMOS transistor 311 is connected to the gate terminal of the first FGMOS transistor 331 and the gate terminal of the second FGMOS transistor 332. The source terminal of the tenth NMOS transistor 313 is connected to the drain terminal of the first FGMOS transistor 331. The source terminal of the eleventh NMOS transistor 314 is connected to the drain terminal of the second FGMOS transistor 332. The source terminal of the twelfth NMOS transistor 321 is connected to the gate terminal of the third FGMOS transistor 341 and the gate terminal of the fourth FGMOS transistor 342. The source terminal of the fourteenth NMOS transistor 323 is connected to the drain terminal of the third FGMOS transistor 341. The source terminal of the fifteenth NMOS transistor 324 is connected to the drain terminal of the fourth FGMOS transistor 342.

[0029] Referring to FIG. 8, the configuration of the bit line discharge circuit 450 of the present embodiment will be described. The bit line discharge circuit 450 of the present embodiment includes an even bit line discharge control signal input terminal 452, an odd bit line discharge control signal input terminal 453, a sixteenth NMOS transistor 454, and a seventeenth NMOS transistor 455. Although a large number of NMOS transistors are provided in addition to the transistors shown in the figure, only the transistors related to the memory elements of interest here will be described.

[0030] The connection of the bit line discharge circuit 450 according to this embodiment will be described. The even bit line discharge control signal input terminal 452 is connected to the even bit line discharge control signal output terminal 862 of the bit line discharge control circuit 850 outside the bit line discharge circuit 450, and is connected to the gate terminal of the 16th NMOS transistor 454 inside the bit line discharge circuit 450. The odd bit line discharge control signal input terminal 453 is connected to the odd bit line discharge control signal output terminal 863 of the bit line discharge control circuit 850 outside the bit line discharge circuit 450, and is connected to the gate terminal of the 17th NMOS transistor 455 inside the bit line discharge circuit 450.

[0031] The drain terminal of the 16th NMOS transistor 454 is connected to the even bit line 303 of the memory array 300. The drain terminal of the 17th NMOS transistor 455 is connected to the odd bit line 304 of the memory array 300. The source terminals of the 16th NMOS transistor 454 and the 17th NMOS transistor 455 are connected to the GND terminal.

[0032] With reference to FIG. 8, the configuration of the column decoder 500 according to this embodiment will be described. The column decoder 500 according to this embodiment includes a column 0 selection signal input terminal 501, a sense line bias signal input terminal 503, and the 18th to 21st NMOS transistors 511 to 514. Although there are a large number of NMOS transistors other than the transistors shown in the figure, only the transistors related to the memory elements being focused on here will be described.

[0033] The connection of the column decoder 500 according to this embodiment will be described. The gate terminal of the 18th NMOS transistor 511 is connected to the sense line bias signal input terminal 503, and the source terminal is connected to the even sense line 301 of the memory array 300. The gate terminal of the 19th NMOS transistor 512 is connected to the sense line bias signal input terminal 503, and the source terminal is connected to the odd sense line 302 of the memory array 300. The gate terminal of the 20th NMOS transistor 513 is connected to the column 0 selection signal input terminal 501, and the source terminal is connected to the even bit line 303 of the memory array 300. The gate terminal of the 21st NMOS transistor 514 is connected to the column 0 selection signal input terminal 501, and the source terminal is connected to the odd bit line 304 of the memory array 300.

[0034] [Operation of odd sense line screening test] The operation of the odd sense line screening test of the semiconductor memory device according to this embodiment will be described. The odd sense line screening test of the semiconductor memory device according to this embodiment is performed in an erase cycle. The write voltage supply circuit 750 receives the voltage VPP at the write voltage input terminal 701, and low-level signals are input to the first erase cycle control signal input terminal 702, the second erase cycle control signal input terminal 703, and the even sense line test signal input terminal 757, while high-level signals are input to the first write cycle control signal input terminal 704, the second write cycle control signal input terminal 705, and the odd sense line test signal input terminal 756. The write voltage supply circuit 750 outputs the voltage VPP at the even sense line write voltage output terminal 767, and outputs 0V (= GND voltage) at the odd sense line write voltage output terminal 768 and the bit line write voltage output terminal 769. Here, the voltage VPP is a high voltage required when performing an erase operation or a write operation on the EEPROM.

[0035] The bit line discharge control circuit 850 has a low-level voltage input to the first erase cycle control signal input terminal 702, and regardless of the input voltages of the odd bit line test signal input terminal 851 and the even bit line test signal input terminal 852, high-level voltages are output from the even bit line discharge control signal output terminal 862 and the odd bit line discharge control signal output terminal 863. The bit line discharge circuit 450 has a signal from the bit line discharge control circuit 850 input thereto, and the 16th NMOS transistor 454 and the 17th NMOS transistor 455 are turned on.

[0036] The data latch circuit 100 outputs a voltage VPP to the even sense line data latch signal line 201 and the odd sense line data latch signal line 202. The write voltage switching circuit 250 Bit line has a write voltage supplied from the bit line write voltage output terminal 769 of the write voltage supply circuit 750 to the write voltage input terminal 205, Voltage VPP is has a write voltage supplied from the even sense line write voltage output terminal 767 of the write voltage supply circuit 750 to the even sense line write voltage input terminal 257, Voltage VPP is and has 0V supplied from the odd sense line write voltage output terminal 768 of the write voltage supply circuit 750 to the odd sense line write voltage input terminal 258. The write voltage switching circuit 250 has the 6th NMOS transistor 255 and the 7th NMOS transistor 256 turned on, outputs a voltage VPP to the even sense line 301, and outputs 0V to the odd sense line 302.

[0037] A voltage difference (voltage VPP - 0V) is generated between the adjacent even sense line 301 and odd sense line 302 of the memory array 300. The odd sense line screening test can generate a voltage stress for detecting in advance the occurrence of defects due to a fault between adjacent sense lines.

[0038] [Operation of the even sense line screening test] The operation of the even sense line screening test of the semiconductor memory device according to this embodiment will be described. The even sense line screening test of the semiconductor memory device according to this embodiment is performed in an erase cycle. The write voltage supply circuit 750 has a voltage VPP input to the write voltage input terminal 701, a low-level signal input to the first erase cycle control signal input terminal 702, the second erase cycle control signal input terminal 703, and the odd sense line test signal input terminal 756, and a high-level signal input to the first write cycle control signal input terminal 704, the second write cycle control signal input terminal 705, and the even sense line test signal input terminal 757. The write voltage supply circuit 750 outputs a voltage VPP from the odd sense line write voltage output terminal 768, and outputs 0V from the even sense line write voltage output terminal 767 and the bit line write voltage output terminal 769.

[0039] The bit line discharge control circuit 850 has a low-level voltage input to the first erase cycle control signal input terminal 702, and outputs a high-level voltage from the even bit line discharge control signal output terminal 862 and the odd bit line discharge control signal output terminal 863 regardless of the input voltages of the odd bit line test signal input terminal 851 and the even bit line test signal input terminal 852. The bit line discharge circuit 450 receives a signal from the bit line discharge control circuit 850, and the 16th NMOS transistor 454 and the 17th NMOS transistor 455 are turned on.

[0040] The data latch circuit 100 outputs a voltage VPP to the even sense line data latch signal line 201 and the odd sense line data latch signal line 202. The write voltage switching circuit 250 Bit lineA write voltage of 0V is supplied from the bit line write voltage output terminal 769 of the write voltage supply circuit 750 to the write voltage input terminal 205, a write voltage of 0V is supplied from the even sense line write voltage output terminal 767 of the write voltage supply circuit 750 to the even sense line write voltage input terminal 257, and a voltage VPP is supplied from the odd sense line write voltage output terminal 768 of the write voltage supply circuit 750 to the odd sense line write voltage input terminal 258. The write voltage switching circuit 250 turns on the sixth NMOS transistor 255 and the seventh NMOS transistor 256, outputs 0V to the even sense line 301, and outputs the voltage VPP to the odd sense line 302.

[0041] A voltage difference (0V - voltage VPP) occurs between the adjacent even sense line 301 and odd sense line 302 of the memory array 300. The even sense line screening test can generate a voltage stress for detecting in advance the occurrence of defects due to faults between adjacent sense lines.

[0042] [Operation of odd bit line screening test] The operation of the odd bit line screening test of the semiconductor memory device according to this embodiment will be described. The odd bit line screening test of the semiconductor memory device according to this embodiment is performed in a write cycle. The write voltage supply circuit 750 receives the voltage VPP at the write voltage input terminal 701, high-level signals are input to the first erase cycle control signal input terminal 702 and the second erase cycle control signal input terminal 703, and low-level signals are input to the first write cycle control signal input terminal 704, the second write cycle control signal input terminal 705, the odd sense line test signal input terminal 756, and the even sense line test signal input terminal 757. The write voltage supply circuit 750 outputs 0V at the even sense line write voltage output terminal 767 and the odd sense line write voltage output terminal 768, and outputs the voltage VPP at the bit line write voltage output terminal 769.

[0043] In the bit line discharge control circuit 850, a high level voltage is input to the first erase cycle control signal input terminal 702 and the odd bit line test signal input terminal 851, and a low level voltage is input to the even bit line test signal input terminal 852. In the bit line discharge control circuit 850, a low level voltage is output from the even bit line discharge control signal output terminal 862, and a high level voltage is output from the odd bit line discharge control signal output terminal 863. In the bit line discharge circuit 450, a signal from the bit line discharge control circuit 850 is input, and the 16th NMOS transistor 454 is turned off and the 17th NMOS transistor 455 is turned on.

[0044] The data latch circuit 100 outputs a voltage VPP to the even-bit line data latch signal line 203 and the odd-bit line data latch signal line 204 when the EEPROM write data is 0, and outputs 0V when the EEPROM write data is 1. The write voltage switching circuit 250 Bit line The bit line write voltage output terminal 769 of the write voltage supply circuit 750 is connected to the write voltage input terminal 205. Voltage VPP is The even sense line write voltage input terminal 257 is supplied with 0V from the even sense line write voltage output terminal 767 of the write voltage supply circuit 750, and the odd sense line write voltage input terminal 258 is supplied with 0V from the odd sense line write voltage output terminal 768 of the write voltage supply circuit 750.

[0045] The write data of the EEPROM on the even bit line data latch signal line 203 is set to 0, and the write data of the EEPROM on the odd bit line data latch signal line 204 is set to 1. In the write voltage switching circuit 250, the fourth NMOS transistor 253 is turned on to output the voltage VPP to the even bit line 303, and the fifth NMOS transistor 254 is turned off to output 0 V to the odd bit line 304.

[0046] A voltage difference (voltage VPP-0V) occurs between adjacent even bit lines 303 and odd bit lines 304 of the memory array 300. The odd bit line screening test can generate a voltage stress to detect in advance the occurrence of defects due to failures between adjacent bit lines.。

[0047] If the write data of the EEPROM on the even-bit line data latch signal line 203 is set to 1 and the write data of the EEPROM on the odd-bit line data latch signal line 204 is set to 0, a potential difference (0V - voltage VPP) can be generated in the same way.

[0048] [Normal Write Operation] The normal write operation of the semiconductor memory device according to this embodiment will be described. In the write cycle, the write voltage supply circuit 750 receives the voltage VPP at the write voltage input terminal 701, high-level signals at the first erase cycle control signal input terminal 702 and the second erase cycle control signal input terminal 703, and low-level signals at the first write cycle control signal input terminal 704, the second write cycle control signal input terminal 705, the odd sense line test signal input terminal 756, and the even sense line test signal input terminal 757. In the write cycle, the write voltage supply circuit 750 outputs 0V at the even sense line write voltage output terminal 767 and the odd sense line write voltage output terminal 768, and outputs the voltage VPP at the bit line write voltage output terminal 769.

[0049] In the write cycle, the bit line discharge control circuit 850 receives a high-level signal at the first erase cycle control signal input terminal 702 and low-level voltages at the odd bit line test signal input terminal 851 and the even bit line test signal input terminal 852. In the write cycle, the bit line discharge control circuit 850 outputs low-level signals from the even bit line discharge control signal output terminal 862 and the odd bit line discharge control signal output terminal 863. The bit line discharge circuit 450 receives the signal from the bit line discharge control circuit 850, and in the write cycle, the 16th NMOS transistor 454 and the 17th NMOS transistor 455 are turned off.

[0050] In a write cycle, when the even sense line data latch signal line 201 is selected as the address, the data latch circuit 100 outputs the voltage VPP to the even sense line data latch signal line 201. At the same time, the odd sense line data latch signal line 202 becomes the non-selected address, and in the write cycle, 0V is output to the odd sense line data latch signal line 202. When the write data of the even bits of the EEPROM is 0 and the write data of the odd bits is 1, the voltage VPP is output to the even bit line data latch signal line 203, and 0V is output to the odd bit line data latch signal line 204.

[0051] In a write cycle, the write voltage switching circuit 250 Bit line receives the voltage VPP from the bit line write voltage output terminal 769 of the write voltage supply circuit 750 at the write voltage input terminal 205, receives 0V from the even sense line write voltage output terminal 767 of the write voltage supply circuit 750 at the even sense line write voltage input terminal 257, and receives 0V from the odd sense line write voltage output terminal 768 of the write voltage supply circuit 750 at the odd sense line write voltage input terminal 258. In the write voltage switching circuit 250, the fourth NMOS transistor 253 and the sixth NMOS transistor 255 are turned on, and the voltage VPP is output to the even bit line 303 and 0V is output to the even sense line 301. The fifth NMOS transistor 254 and the seventh NMOS transistor 256 are turned off, putting the odd bit line 304 and the odd sense line 302 in a high impedance state.

[0052] In the memory array 300, one of the adjacent even sense line 301 and odd sense line 302 is at 0V and the other is in a high impedance state, and one of the adjacent even bit line 303 and odd bit line 304 is at the voltage VPP and the other is in a high impedance state. No voltage is applied between the adjacent lines, suppressing the voltage leakage between the lines. When the write data of the even bits of the EEPROM is 1 and the write data of the odd bits is 0, the voltage states of the even bit line 303 and the odd bit line 304 are swapped, but the same effect is obtained.

[0053] [Normal Erase Operation] The normal erasure operation of the semiconductor memory device according to this embodiment will be described. In an erasure cycle, the write voltage supply circuit 750 receives the voltage VPP at the write voltage input terminal 701, and low-level signals are input to the first erasure cycle control signal input terminal 702, the second erasure cycle control signal input terminal 703, the odd sense line test signal input terminal 756, and the even sense line test signal input terminal 757, while high-level signals are input to the first write cycle control signal input terminal 704 and the second write cycle control signal input terminal 705. In the erasure cycle, the write voltage supply circuit 750 outputs the voltage VPP from the even sense line write voltage output terminal 767 and the odd sense line write voltage output terminal 768, and outputs 0V from the bit line write voltage output terminal 769.

[0054] In an erasure cycle, the bit line discharge control circuit 850 receives low-level voltages at the first erasure cycle control signal input terminal 702, the odd bit line test signal input terminal 851, and the even bit line test signal input terminal 852. In the erasure cycle, the bit line discharge control circuit 850 outputs high-level signals from the even bit line discharge control signal output terminal 862 and the odd bit line discharge control signal output terminal 863. The bit line discharge circuit 450 receives a signal from the bit line discharge control circuit 850, and in the erasure cycle, the 16th NMOS transistor 454 and the 17th NMOS transistor 455 are turned on.

[0055] In an erasure cycle, when the even sense line data latch signal line 201 is selected as the address, the data latch circuit 100 outputs the voltage VPP to the even sense line data latch signal line 201. At the same time, the odd sense line data latch signal line 202 becomes the non-selected address and outputs 0V. Further, the voltage VPP is output to the even bit line data latch signal line 203 and the odd bit line data latch signal line 204.

[0056] In an erasure cycle, the write voltage switching circuit 250 Bit lineA write voltage of 0V is supplied from the bit line write voltage output terminal 769 of the write voltage supply circuit 750 to the write voltage input terminal 205, a voltage VPP is supplied from the even sense line write voltage output terminal 767 of the write voltage supply circuit 750 to the even sense line write voltage input terminal 257, and a voltage VPP is supplied from the odd sense line write voltage output terminal 768 of the write voltage supply circuit 750 to the odd sense line write voltage input terminal 258. In the write voltage switching circuit 250, the fourth NMOS transistor 253, the fifth NMOS transistor 254, and the sixth NMOS transistor 255 are turned on, output 0V to the even bit line 303 and the odd bit line 304, output the voltage VPP to the even sense line 301, the seventh NMOS transistor 256 is turned off, and the odd sense line 302 is put into a high impedance state.

[0057] In the memory array 300, one of the adjacent even sense line 301 and odd sense line 302 is at the voltage VPP and the other is in a high impedance state, and both of the adjacent even bit line 303 and odd bit line 304 are at 0V. No voltage is applied between the adjacent lines, and voltage leakage between the lines can be suppressed.

[0058] As described above, the semiconductor memory device of the present invention can efficiently perform a screening test of the semiconductor memory device by applying a voltage stress between adjacent wirings for inspection. Further, the semiconductor memory device of the present invention can perform an operation in which no voltage is applied between adjacent wirings during normal use, and can suppress leakage of the applied voltage. Further, although the semiconductor memory device of the present invention has been described by taking examples of two types, odd and even, the same effect can be obtained with three or more types of signal examples.

Explanation of Signs

[0059] 205 Bit line write voltage Input Terminal 250 Write voltage switching circuit 257 Even sense line write voltage Input Terminal 258 Odd sense line write voltage Input Terminal 300 Memory array 450-bit line discharge circuit 701 Write voltage input terminal 702, 702A First erase cycle control signal input terminal 703 Second erase cycle control signal input terminal 704 First write cycle control signal input terminal 705 Second write cycle control signal input terminal 750 Write voltage supply circuit 751 - 754 2-input OR circuit 756 Odd sense line test signal input terminal 757 Even sense line test signal input terminal 850 Bit line discharge control circuit 950 - 952 Level shift circuit

Claims

1. The memory cell includes a write voltage supply circuit, a write voltage switching circuit, a bit line discharge control circuit, a bit line discharge circuit, and a memory array; the write voltage supply circuit is connected to the memory array via the write voltage switching circuit; The bit line discharge control circuit is connected to the memory array via the bit line discharge circuit.

2. the write voltage supply circuit supplies at least two types of sense line write voltages to the write voltage switching circuit; The write voltage switching circuit supplies voltages to at least two groups of sense lines of the memory array individually; the bit line discharge control circuit outputs at least two types of bit line discharge control signals to the bit line discharge circuit; 2. The semiconductor memory device according to claim 1, wherein said bit line discharge circuit supplies a discharge voltage to at least two groups of bit lines of a memory array individually.

3. the write voltage supply circuit comprises a write voltage input terminal, a first erase cycle control signal input terminal, a second erase cycle control signal input terminal, a first write cycle control signal input terminal, a second write cycle control signal input terminal, an odd sense line test signal input terminal, an even sense line test signal input terminal, an odd sense line write voltage output terminal, an even sense line write voltage output terminal, a bit line write voltage output terminal, first to fourth OR circuits, and first to third level shift circuits; the write voltage input terminal is connected to the first to third level shift circuits; the first OR circuit is connected to the first erase cycle control signal input terminal, the odd sense line test signal input terminal, and the first level shift circuit; the second OR circuit is connected to the second erase cycle control signal input terminal, the odd sense line test signal input terminal, and the first level shift circuit; the third OR circuit is connected to the first erase cycle control signal input terminal, the even sense line test signal input terminal, and the second level shift circuit; the fourth OR circuit is connected to the second erase cycle control signal input terminal, the even sense line test signal input terminal, and the second level shift circuit; the odd sense line write voltage output terminal is connected to the first level shift circuit; the even sense line write voltage output terminal is connected to the second level shift circuit; 3. The semiconductor memory device according to claim 1, wherein said bit line write voltage output terminal is connected to said third level shift circuit.

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