Electrical component testing equipment

Abstract

To solve problems that a long period of time is required for changing connection of wires corresponding to test items, in order to test transistors, and a work space for changing connection is required, resulting in a larger test device.SOLUTION: A transistor 117 is arranged on a terminal substrate 502, an element terminal 226 of the transistor 117 is pressed by a pressing tool 501 for electrical connection. A fork connector 528, the terminal substrate 502 and a control circuit board 519 are fixed to a slide plate 505. A conductor plate 204 is attached to a partition wall 214a of a housing. Movement of the slide plate 505 toward the partition wall 214a side connects the fork connector 528 to the conductor plate 204. The conductor plate 204 and a fork plug 205 are fitted and electrically connected to each other, and a test current Id is supplied via the fork plug 205 from a power supply device 132.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention uses SiC, GaO, Ga 2 O 3 The present invention relates to a semiconductor element (electrical element) testing device, a power cycle testing device, a semiconductor element (electrical element) testing method, a semiconductor element (electrical element) evaluation device or evaluation method, a power cycle testing method, etc., for performing cycle testing of semiconductor elements such as GaN, IGBT, MOS-FET, Gan-FET, bipolar transistors, thyristors, diodes, triacs, posistors, thermistors, resistor elements, coils, crystal elements, capacitors, and other electrical elements. As shown in Fig. 62, the present invention can be applied to a wide variety of electrical elements. The present invention relates to a method and an attachment device for electrically connecting terminals of a semiconductor element when testing the semiconductor element.

[0002] The present invention provides a semiconductor element (electrical element) testing apparatus and a semiconductor element (electrical element) testing and evaluation method that can efficiently reproduce stresses similar to failure modes in the actual use environment and actual use state of semiconductor elements, and can evaluate and test power semiconductor elements and the like with high accuracy. [Background technology]

[0003] The lifespan of a power semiconductor element includes a lifespan caused by thermal fatigue caused by heat generation in the power semiconductor element itself, a lifespan caused by thermal fatigue caused by temperature changes in the external environment of the power semiconductor element, and a lifespan caused by voltage fatigue caused by the voltage applied to the gate insulating film of the power semiconductor element.

[0004] Generally, life tests of power semiconductor elements are conducted by repeatedly turning current on and off to the power semiconductor element. The test of the semiconductor element is carried out by applying a voltage to the emitter terminal (source terminal) and collector terminal (drain terminal) of the power semiconductor element, passing a test current, and applying a periodic on-off signal (operation / non-operation signal) to the gate terminal.

[0005] The current applied to the semiconductor element during testing is large, at several hundred amperes. Therefore, low-resistance connection wiring is required to avoid heat generation and voltage drop. In addition, there are many types of tests, and the connection wiring must be changed according to the type of test. Changing the connection wiring etc. took a long time.

[0006] Semiconductor elements (electrical elements) need to be tested according to the usage environment (temperature, humidity). However, it is not easy to create the usage environment (temperature, humidity) in a short time, and it is also difficult to place the semiconductor elements (electrical elements) appropriately in the usage environment (temperature, humidity). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2017-17822 Summary of the Invention [Problem to be solved by the invention]

[0008] Since the constant current applied to test semiconductor elements such as transistors is several hundred amperes or more, it is necessary to use thick wire with low resistance for the connection wiring. Thick connection wiring is hard and inflexible. Changing the connection of thick connection wiring to meet test items takes a long time.

[0009] Therefore, in order to test transistors, changing the wiring connections to correspond to the test items takes a long time, and there is a problem that the test equipment becomes large because a work space is required for changing the connections. It was also difficult to arrange the semiconductor elements (electrical elements) appropriately for the usage environment (temperature, humidity). [Means for solving the problem]

[0010] The frame is placed inside 526 of thermostatic chamber 523 and fixed inside thermostatic chamber 526. Slide plate 505 is attached to the frame. The slide plate can be inserted into and pulled out of the frame. A connector for supplying a test current is arranged on the front surface of the slide plate, as well as a signal connector for applying a control signal for power elements such as transistors.

[0011] The semiconductor device to be tested is attached to the terminals of the slide plate 505 with the slide plate pulled out. After the semiconductor device is attached, the slide plate is pushed into the frame and the door of the thermostatic chamber is closed. The temperature inside the thermostatic chamber is set to a predetermined temperature, and the semiconductor device is cooled or heated.

[0012] The transistor 117 is disposed on a terminal board 502, and an element terminal 226 of the transistor 117 is pressed and electrically connected by a pressing tool 501. The fork connector 528, the terminal board 502, and the control circuit board 519 are fixed to a slide plate 505. A conductor plate 204 is attached to the partition wall 214a of the housing.

[0013] By moving the slide plate 505 toward the partition wall 214a, the fork connector 528 is connected to the conductor plate 204. The conductor plate 204 and the fork plug 205 are fitted together and electrically connected, and the test current Id is supplied from the power supply device 132 via the fork plug 205. Alternatively, a semiconductor device to be tested is placed on a slide plate 505, and then placed in a chamber 526 of a thermostatic chamber 523. A test current Id is supplied from a power supply unit 132. Effect of the Invention

[0014] The semiconductor element 117 is mounted on a slide plate 505. By moving the slide plate 505, it can be easily electrically connected to the power supply device 132 that supplies the test current Id.

[0015] Moreover, the semiconductor element 117 to be tested can be easily selected by changing the position of the fork plug 205, and no working space is required for changing the connection. Therefore, the semiconductor element (electrical element) testing device can be made compact. Furthermore, the semiconductor element (electric element) 117 or the like to be tested can be easily inserted into and removed from the chamber 526 of the thermostatic chamber 523 by using the slide plate 505 . [Brief description of the drawings]

[0016] [Figure 1] 1 is a diagram showing the configuration of a semiconductor element (electrical element) testing device according to the present invention and an explanatory diagram of a semiconductor element (electrical element) testing method. [Diagram 2] 1 is a diagram showing the configuration of a semiconductor element (electrical element) testing device according to the present invention and an explanatory diagram of a semiconductor element (electrical element) testing method. [Diagram 3] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 4] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 5] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 6] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) mounting portion of a semiconductor element (electrical element) testing apparatus according to the present invention. [Figure 7] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) mounting portion of a semiconductor element (electrical element) testing apparatus according to the present invention. [Figure 8] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) mounting portion of a semiconductor element (electrical element) testing apparatus according to the present invention. [Figure 9] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 10] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 11] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 12]1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 13] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 14] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 15] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 16] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 17] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 18] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 19] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 20] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 21] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 22] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element). [Diagram 23] This is a diagram of the configuration and equivalent circuit of a semiconductor element (electrical element). [Figure 24] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 25] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 26] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 27] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 28] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 29]1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 30] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 31] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 32] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 33] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 34] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 35] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 36] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 37] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 38] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 39] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 40] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 41] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 42] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 43] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 44] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 45] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Diagram 46]1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 47] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 48] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. [Figure 49] FIG. 2 is an explanatory diagram of a semiconductor element (electrical element) testing method according to the present invention. [Figure 50] FIG. 2 is an explanatory diagram of a semiconductor element (electrical element) testing method according to the present invention. [Figure 51] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 52] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 53] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 54] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 55] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 56] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 57] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 58] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 59] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 60] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 61] FIG. 2 is a timing chart illustrating the semiconductor element (electrical element) testing method of the present invention. [Figure 62]1 is an explanatory diagram of a semiconductor device, an electric device, or an electronic device. [Figure 63] 1 is a configuration diagram and an explanatory diagram of a semiconductor element (electrical element) testing device of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a testing apparatus and a testing method for an electric element according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0018] The present invention relates to testing of electrical elements, particularly SiC, GaO, Ga 2 O 3 This relates to test equipment, testing, evaluation, inspection and methods for semiconductor elements such as GaN, IGBT, MOS-FET, Gan-FET, bipolar transistors, thyristors, diodes, and electrical elements such as capacitors and resistors. In the embodiments described in the specification, an IGBT is mainly used as an example of a semiconductor element (electrical element), but the present invention is not limited to this.

[0019] The present invention is not limited to IGBTs, but can be applied to various semiconductor elements such as SiC transistors, MOSFETs, JFETs, thyristors, diodes, thermistors, and posistors.

[0020] In the embodiments of the present invention, the control terminal for turning a transistor on or off is described as the gate terminal (G), but it goes without saying that the gate terminal (G) may be read as the base terminal (B). The gate terminal (G) and base terminal (B) are terminals for applying a signal for turning the transistor 117 on or off. It goes without saying that the collector terminal (C) and emitter terminal (E) may be read as the source terminal (S), drain terminal (D), etc.

[0021] In this embodiment, the semiconductor element (electrical element) 117 may be a single element as shown in Fig. 23 and Fig. 62, or may be a semiconductor element (electrical element) module in which a plurality of semiconductor elements (electrical elements) are combined as shown in Fig. 22(b) to Fig. 22(e). The concept of the semiconductor element (electrical element) 117 includes the semiconductor element (electrical element) 117 even if the semiconductor element (electrical element) 117 has a configuration in which a heat sink is attached, a configuration in which a heat pipe is attached, or the like.

[0022] In the embodiments of the present invention, the base terminal (B) is also described as the gate terminal (G). A terminal that controls the on / off of a transistor is described as a gate terminal, and a circuit connected to the gate terminal is described as a gate drive circuit.

[0023] In the present invention, an N-channel power transistor is exemplified as the semiconductor element component 117, but the present invention is not limited to this. It is not limited to a power transistor, and may be a small signal transistor. It goes without saying that the present invention is also applicable to a P-channel transistor, not limited to an N-channel transistor.

[0024] As shown in Fig. 62(a) to Fig. 62(i), the electric element (semiconductor element) testing apparatus and electric element (semiconductor element) testing method of the present invention may be applied to transistors of any type, such as MOS type or bipolar type. The transistors may be either N-channel or P-channel. Needless to say, the electric elements can be applied to electric components such as resistors (Fig. 62(i)), capacitors, coils, relays, and crystal oscillators (Fig. 62(k)) in addition to semiconductor elements such as diodes (Fig. 62(g)), thyristors (Fig. 62(h)), and triacs (Fig. 62(i)).

[0025] The present invention is not limited to semiconductor elements, and it goes without saying that the present invention can also be applied to electrical elements other than semiconductors, such as resistor elements, capacitors, coils, crystal elements, thermistors, posistors, and ZNR.

[0026] The object of testing by the electric element (semiconductor element) testing apparatus of the present invention is not limited to a single element such as a semiconductor element, an electric element, etc. For example, as shown in Fig. 22, it goes without saying that it is possible to inspect or test a semiconductor element or an electric element in which a plurality of elements are configured as a module.

[0027] Fig. 22(a1)(a2) shows a transistor with a built-in diode Di. Fig. 22(b1)(b2) shows a semiconductor module in which Fig. 22(a1)(a2) are connected in series. Fig. 22(c1)(c2) shows a configuration diagram of a module in which Fig. 22(a1)(a2) are electrically connected by external connection wiring. Fig. 22(d1)(d2) shows a configuration diagram of a module having a terminal of a diode D2 for temperature measurement. Fig. 22(e1)(e2) shows a configuration diagram of a transistor having a terminal of a diode D2 for temperature measurement connected externally to form a module. The present invention can be applied to any of these semiconductor elements and electric elements.

[0028] In Fig. 1, the transistor 117 to be tested will be described mainly as having a diode Di (diode Dis, diode Dim) as shown in Fig. 22(b1) and (b2). However, the present invention is not limited to this, and may be a transistor having separate temperature diode terminals (as, ks, am, km) as shown in Fig. 22(d) and Fig. 22(e).

[0029] As shown in Figures 62(e), 22(d), 22(e) and 62, the terminal of the diode Ds may be a semiconductor element or a semiconductor module, an electric element or an electric element module in which the terminal is separately arranged.

[0030] It goes without saying that the semiconductor element (electrical element) testing apparatus and semiconductor element (electrical element) testing method of the present invention can be applied to either a semiconductor element 117 having multiple transistors in one package, as in Figures 22(b) and 22(d), or a semiconductor module 117 in which multiple transistor elements are connected, as in Figures 22(c) and 22(e).

[0031] In each drawing for explaining the embodiment of the invention, elements having the same function or similarity are given the same reference numerals. Items not necessary for the explanation are omitted from the drawings, etc. In addition, the drawings, etc. are simplified or schematic to facilitate the explanation. Items and parts not necessary for the explanation may be omitted. Furthermore, explanations of parts similar or equivalent to other embodiments may be omitted.

[0032] In this specification and drawings, parts, portions, and descriptions that are not necessary for the explanation may be omitted, and illustrations may be omitted. In addition, each embodiment may be combined in whole or in part. In addition, the embodiments of the present invention may be combined with each other, or may be implemented with some modifications.

[0033] 1 is a block diagram and an explanatory diagram of an electric device (semiconductor device) testing device of the present invention. In FIG. 1, two power supply devices 132 (power supply device 132a, power supply device 132b2) are shown.

[0034] The electric element testing apparatus of the present invention separates a place (space) in the electric element testing apparatus where the transistors 117 to be tested, etc. are arranged, from the power supply device 132 which generates the test current for the transistors 117, etc. A partition wall 214a is provided in the thermostatic chamber (housing) 523 for separation.

[0035] In this specification, the drawings, etc., a member such as a plug used in a connection portion will be described as a connection plug or a fork plug 205. It is not limited to a connection plug or a fork plug 205, and any member of any shape, configuration, or structure may be used as long as it is detachable and can be fitted or otherwise electrically connected at its tip with another conductive member. For example, a fork connector 528 is exemplified. It may also be a connection connector, a crimp connector, etc.

[0036] The connecting members such as the fork plug 205 are not limited to being attached to all terminals, etc. For example, it goes without saying that they may be formed or placed at locations that are constantly detached or attached frequently, and other locations may be configured with screws, bolts, etc.

[0037] The transistor to be tested is connected to a circuit board having a switch circuit, etc., by inserting a connection plug (fork plug 205) through an opening 216 provided in a partition 214 and bringing the connection plug (fork plug 205) into electrical contact with a conductor plate 204 on the circuit board.

[0038] The conductive plate (copper bar) 204 is not limited to a plate shape. For example, it may be rod-shaped. It may also be cylindrical or foil-shaped. In this embodiment, it is expressed as a conductive plate 204, but the concept of the conductive plate 204 includes other shapes and configurations such as a conductive rod. The conductive plate 204 is formed or composed of a copper member, and its surface is nickel-plated.

[0039] The number of power supply devices 132 is not limited to two. For example, the semiconductor element (electrical element) test device of the present invention may have three or more power supply devices 132. Also, one power supply device 132 may be configured to be able to output two voltages or currents. The more the number of power supply devices 132 increases, the more diverse the waveforms of the test current Id that can be generated. In the embodiment of the present invention, the power supply device 132 is described, but the power supply device 132 is not limited to one that outputs a predetermined current Id or a constant current Id.

[0040] For example, a power supply device 132 capable of setting a maximum (limit) voltage or maximum current is used. An example is a device that functions to output a predetermined constant current at a set maximum voltage under certain conditions. In addition, when outputting a constant current, a configuration is used in which a predetermined maximum voltage can be set as the output terminal voltage.

[0041] A power supply wiring 212 is connected to the power supply device 132, and a switch circuit 122 is connected or disposed on the power supply wiring 212. The switch circuit 122 is mounted or disposed on a switch circuit board 201. By turning on (closing) the switch circuit 122, a test current Id is supplied to the electric element 117 to be tested. By turning off (opening) the switch circuit 122, the test current Id to the electric element 117 to be tested is stopped.

[0042] The switch circuit 122 or the switch circuit 124 is mounted or disposed on a switch circuit board 201 made of a printed circuit board. A conductive plate (copper bar) 204 is mounted or disposed on the printed circuit board.

[0043] The test current Id is output after checking whether each electrical connection is established. Examples include electrical connection between fork plug 205 and conductive plate 204, electrical connection between fork connector 528 and conductive plate 204, and electrical connection between connector 202 and each terminal of semiconductor element 117. Also, it is configured such that it can be checked whether electrical connection is established based on the pressing state of contact switch 529.

[0044] The fork plug 205 and the fork connector 528 may have any configuration, structure, form, style, or method that allows them to be electrically connected to an object such as the conductor plate 204 by press-fitting, pressure welding, insertion, crimping, clamping, sandwiching, fitting, etc.

[0045] Temperature sensors 510 are mounted or placed on the conductive plate 204 and the semiconductor element (electrical element) 117 to be tested to monitor the temperature. If the temperature exceeds a certain level, the controller circuit 111 stops the test or stops the semiconductor testing device.

[0046] If the temperature does not change to a certain level or higher after the test has started, the controller circuit 111 determines that there is a defect in the electric element 117, destruction of the electric element 117, or a defective electrical connection, and stops the test. Also, an alarm is issued. It goes without saying that the above matters are also applicable to other embodiments described in this specification and the drawings, and can be combined with other embodiments.

[0047] The power supply device 132 outputs a large constant current Id (or voltage Vd) for testing the transistor 117. The power supply device 132 supplies power (current, voltage) in synchronization with a control signal from the control circuit (controller) 111. The power supply device 132 can set a maximum voltage value to be output.

[0048] The power supply device 132 is connected to a switch circuit 122. The switch circuit 122 has a function of turning on (supply, application, close) and off (cutoff, open) the supply of the test current output by the power supply device 132.

[0049] When the output of the temperature sensor 510 attached to the conductive plate 204 or the like reaches or exceeds a predetermined temperature, or is outside a predetermined temperature range, the switch circuit 122 is controlled to be OFF (shutoff, open).

[0050] The temperature sensor 510 is also disposed in the semiconductor element 117 or the module 117 made of the semiconductor element or the like. It measures the temperature of the semiconductor element 117 or the like, and transmits a signal to the controller circuit 111 when the temperature exceeds a predetermined temperature or is outside a predetermined temperature range. The controller circuit 111 controls the processing circuit 524 and the power supply device 132 based on the transmitted signal.

[0051] Conductive plate 204 is not limited to being plate-shaped, and may be cylindrical, rod-shaped, connector-shaped, etc. Fork plug 205 may have any configuration, structure, form, style, or method that allows electrical connection to an object such as conductive plate 204 by fitting, press-fitting, pressure welding, insertion, crimping, clamping, or the like.

[0052] Conductive plate 204 is, for example, a copper plate with a thickness of 5 mm and a width of 50 mm. The length of conductive plate 204 is, for example, 250 mm. Figures 1 and 2 show the connection (contact) state between fork plug 205 and conductive plate 204. For ease of explanation, the following explanation will be given taking conductive plate 204 as an example.

[0053] In the embodiment of the present invention shown in Fig. 1, a fork plug 205 is exemplified as a connection plug. The fork plug 205c is electrically connected to the collector terminal of the transistor 117s. The fork plug 205b is electrically connected to the emitter terminal of the transistor 117s. The fork plug 205a is electrically connected to the emitter terminal of the transistor 117m.

[0054] It should be noted that the embodiment of the present invention is not limited to connecting the conductor plate 204 to the fork plug 205. It goes without saying that the conductor plate 204 and the power supply wiring 212 may be connected by screws or a crimp terminal.

[0055] A temperature sensor (temperature measurement circuit) 510 is disposed or connected in contact or in close contact with the conductive plate 204. If the electrical connection between the fork plug 205 and the conductive plate 204 is poor, the temperature sensor 510 detects heat generated at the connection (contact) and transmits information about an abnormal temperature to the controller circuit 111. Examples of the sensor portion of the temperature sensor 510 include a thermocouple, a thermistor, etc.

[0056] The sub-transistor (upper transistor) 117s and the main transistor (lower transistor) 117m are connected in series. In the embodiment of Fig. 1, the emitter terminal (E) of the upper transistor 117s and the collector terminal (C) of the lower transistor 117m are connected. The gate terminal (gs) of the sub-transistor (upper transistor) 117s is connected to the gate driver circuit 113 of the processing circuit 524s, and the gate terminal (gm) of the main transistor (lower transistor) 117m is connected to the gate driver circuit 113 of the processing circuit 524m.

[0057] A control circuit for the temperature sensor 510 and a temperature-voltage conversion table are configured or disposed in the device control circuit 209. A processing circuit 524s is connected to the upper transistor 117s. A processing circuit 524m is connected to the lower transistor 117m.

[0058] In the processing circuit 524, a sample connection circuit 203, a short circuit 137, an analog-to-digital (AD) converter circuit 127, a digital-to-analog (DA) converter circuit 128, a signal control circuit 112, and a temperature measurement circuit 115 are mounted or disposed. The device control circuit 209 and the sample connection circuit 203 are electrically connected via a connection pin 206 of a connector 208 .

[0059] Vdata is data that the controller circuit 111 applies to the DA converter circuit 128. The voltage output by the DA converter circuit 128 is determined, varied, or set by Vdata (as shown in FIGS. 52, 53, etc.). The voltage output by the DA converter circuit 128 is applied to the gate driver circuit 113 as a gate control signal Vg (Vgs, Vgm).

[0060] A fork connector 528 is electrically connected to the conductive plate 204. The conductive plate 204 is disposed so as to penetrate a hole provided in a partition wall 214a on the rear surface of the thermostatic chamber (housing) 523.

[0061] An output of the power supply device 132 is connected to a power supply wiring 212. A fork plug 205 is connected to one end of the power supply wiring 212, and the fork plug 205 and the conductive plate 204 are electrically connected by fitting, connection, or the like.

[0062] Conductive plate 204 may have any shape as long as it can be electrically connected to a structure such as fork plug 205 or fork connector 528. For example, it may be a structure such as a socket or connector. Conductive plate 204 may also be in the shape of a fork plug and connected to fork plug 205. The present invention is not limited to this. For example, the fork plug 205 may be omitted and the power supply wiring 212 may be electrically connected directly to the conductor plate 204.

[0063] The fork plug 205 will be described as being inserted into a component or structure that separates a space, such as the partition wall 214b. However, the present invention is not limited to this. For example, the fork plug 205 may be configured to be inserted into a cylindrical object that supports the fork plug 205, thereby electrically connecting the conductor plate 204 and the like.

[0064] The test current Id to be passed through the transistor 117 is supplied by operating the power supply device 132. The power supply device 132 is controlled to be activated / deactivated (on / off) by a signal from a control circuit (controller) 111. Also, the test current Id (Idm, Ids) is switched between output and non-output. The processing circuit 524 is controlled in timing by the control circuit (controller) 111.

[0065] In Fig. 1, the transistor 117 to be tested will be described as having a diode Di (diode Dis, diode Dim) as shown in Fig. 22(b). Needless to say, the present invention can be applied to a transistor 117 having terminals of diodes Ds and Dm as shown in Fig. 22(d) and 22(e). A constant current Ic is supplied to the terminals of diodes Ds and Dm, and the inter-terminal voltages of diodes Ds and Dm are measured to obtain the voltage Vi and temperature information Tj.

[0066] It goes without saying that the electrical element testing apparatus and electrical element testing method of the present invention can be applied to a semiconductor element 117 having multiple transistors in one package, as shown in Figures 22(b) and 22(d), or to a semiconductor module 117 in which multiple transistor elements are connected, as shown in Figures 22(c) and 22(e).

[0067] As shown in Fig. 22(a), it goes without saying that this embodiment can be applied to a semiconductor element composed of a single transistor 117. In addition, it is not limited to a transistor, and it may be a semiconductor element such as a diode or a thyristor. It goes without saying that the electric element to be tested may be an electric element such as a posistor, a thermistor, a capacitor, a coil, or a resistor.

[0068] The following description will be given on the assumption that the emitter terminal e of the transistor 117m is connected to ground or a predetermined potential. The processing circuit 524 is connected to the gate terminal g (gate terminal gs, gate terminal gm) of the transistor 117 (transistor 117s, transistor 117m) via the connector 202 for electrical connection.

[0069] The processing circuit 524 is disposed on the control circuit board 519. The processing circuit 524m applies a signal to the transistor 117m to control and process the transistor 117m. The processing circuit 524s applies a signal to the transistor 117s to control and process the transistor 117m. The processing circuit 524 is mainly composed of a sample connection circuit 203 and a device control circuit 209 .

[0070] As an example, the voltages output by the gate driver circuit 113 are an on-voltage V2, an on-voltage V1, and an off-voltage Voff (0V, V0 voltage). The gate driver circuit 113 can output voltages of three or more levels. The off-voltage Voff may be a Vn voltage (negative voltage) that is lower in potential than 0V. In this embodiment of the present invention, the gate driver circuit 113 generates on-voltages of two potential levels and applies them to the gate terminal g of the transistor 117 .

[0071] In one embodiment, an on-voltage V1 is applied to the gate terminal, and then an on-voltage V2 is applied to the gate terminal g (gate terminal gm, gate terminal gs). The application of the on-voltage V2 causes the transistor 117 to be strongly on. Therefore, the resistance between the channels of the transistor 117 can be reduced.

[0072] The V2 voltage is described as a voltage higher than the V1 voltage, but is not limited to this. The V2 voltage is a voltage of a potential other than the V1 voltage, and may be a voltage of a predetermined value set when the constant current Ic flows. When the V2 voltage is higher than the V1 voltage, the resistance between the channel terminals of the transistor 117 becomes smaller (the resistance value becomes lower than when the V1 voltage is applied, and the on-state is reached), and when the constant current Ic flows between the channels, the measured voltage Vi becomes stable.

[0073] The V1 voltage is a voltage that turns on the transistor 117, and is set by changing or adjusting if the part number or type of the transistor is different. The V0 voltage is a voltage that turns off the transistor 117, and is set by changing or adjusting if the part number or type of the transistor is different. The V2 voltage is a fixed voltage when applying a constant current Ic and measuring the channel inter-terminal voltage Vi.

[0074] The gate driver circuit 113 can output four or more levels of voltage, and can also output a triangular wave, a sine wave, etc. that change with time (FIG. 58(c), FIG. 59(b), etc.).

[0075] The transistor 117 is operated / non-operated (on / off) by the Vg signal voltage output from the gate driver circuit 113. While the transistor 117 is on, a test current Id (Idm, Ids) flows between the channels of the transistor 117.

[0076] The gate driver circuit 113 has a variable resistance circuit 125. The resistance value Vr of the variable resistance circuit 125 can be varied between 0 (Ω) and 500 (Ω). In addition, the gate driver circuit 113 is configured so that it can be set to a constant voltage or a voltage that changes over time. It should be noted that the variable resistance circuit 125 is not limited to a variable resistance, and may be a fixed resistance circuit that exhibits a constant resistance value. The gate driver circuit 113 is configured so as to be able to set (output) a voltage that changes periodically over time.

[0077] A voltage measuring circuit (not shown) is provided to measure the voltage across the resistance Vr. The voltage measuring circuit can measure the leakage current flowing through the gate terminal of the transistor 117, etc.

[0078] A resistor R (not shown) may be disposed between the gate terminal g and the emitter terminal e or the collector terminal c of the transistor 117. By adjusting the value of the resistor R of the variable resistor circuit 125, the inclination angle of the voltage waveform at the rising and falling edges of the gate signal can be adjusted or set.

[0079] The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate voltage Vg applied to the gate terminal g of the transistor 117. By separately adjusting the rise time Tr and the fall time Td, the on-time and on-characteristics of the transistor 117 are controlled to predetermined values.

[0080] As described above, the electrical element testing apparatus and testing method of the present invention can control, adjust, or set the resistance value of the variable resistance circuit 125 connected to the gate terminal of the transistor 117, or the rise time / fall time of the gate driver circuit 113.

[0081] 1 and other figures, the resistance value Vr of the variable resistance circuit 125 of the gate driver circuit 113 is variable, but this is not limiting. For example, it goes without saying that the variable resistance circuit 125 may be a fixed resistance element of an external resistor, and this resistor may be connected to the gate terminal g of the transistor 117 by a connector (not shown) or the like.

[0082] The constant current circuit 118 passes a predetermined constant current Ic. The constant current Ic is applied to the diode Di (Dim, Dis) or the diode Ds and diode Dm. When the temperature of the transistor 117 changes, the terminal voltage of the diode Di changes. By monitoring the terminal voltage Vi of the diode Di, the temperature change of the transistor 117 can be measured or observed. The temperature or the temperature change is called temperature information Tj. Therefore, the temperature information Tj is the voltage between the terminals (between the collector and emitter terminals of the transistor 117, and between the source and drain terminals of the transistor 117). For example, the temperature information Tj is the voltage between the anode and cathode terminals of the diode Di or the voltage between the collector and emitter terminals of the transistor 117 in FIG.

[0083] The diode Di may be a diode of another semiconductor chip mounted on the semiconductor chip on which the transistor 117 is formed. The diode Di may utilize a parasitic diode that is formed secondarily when the transistor 117 is formed.

[0084] The sample connection circuit 203 includes or is formed with a gate driver circuit 113, a variable resistance circuit 125, a constant current circuit 118, an operational amplifier (buffer circuit) 116, etc. The sample connection circuit 203 may be configured as a control circuit (substrate) 519.

[0085] The sample connection circuit 203 is separated from the device control circuit 209 so that it can be placed close to the transistor 117 under test, and is electrically connected to it by a connection pin 206 of a connector 208 .

[0086] The sample connection circuit 203 is connected to the transistor 117 via a connection pin 206 of the connector 202. The length (distance) between the gate driver circuit 113 and the gate terminal g of the transistor 117 is arranged to be short, 100 mm or less.

[0087] If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise or the like may be superimposed on the gate terminal g, and the noise may cause the transistor 117 to malfunction.

[0088] Processing circuit 524 is formed or mounted on control circuit board 519. Semiconductor element 117 is arranged or mounted on terminal board 502. As illustrated in FIG. 5 etc., terminal board 502 is attached to device stand 503. In addition, device stand 503 and control circuit board 519 are attached to slide plate 505. Slide plate 505 is moved along rail guides 507 and placed in thermostatic chamber (housing) 523 as illustrated in FIG. 3, FIG. 4 etc. By pulling out the slide plate 505 from within the tank, it becomes easy to mount, attach, remove, and replace the semiconductor element to be tested.

[0089] 1, a gate signal Vg is applied to a gate terminal g of a transistor 117 from a gate driver circuit 113. The gate driver circuit 113 has an operational amplifier circuit (voltage buffer circuit) .

[0090] 3, 4, etc., control circuit board 519 is placed in thermostatic chamber (housing) 523 of the electrical element test apparatus of the present invention. If necessary, slide plate 505 is attached to a frame rack (not shown), and the frame rack is placed in chamber interior 526 of thermostatic chamber 523. By inserting slide plate 505 back and forth into chamber interior 526 or pulling it out, the element to be tested is attached and removed.

[0091] A power supply unit 132 and a controller circuit 111 are installed in the upper part of the thermostatic chamber (housing) 523. The power supply unit 132 and the like are separated from the inside of the chamber 526 by a partition wall 214a.

[0092] A shield plate, a shield film, or the like that absorbs noise is formed or placed on the partition wall 214. The shield plate or the like can suppress malfunctions of the power supply device, the test circuit, and the test semiconductor element.

[0093] The power supply device 132, the switch circuit board 201, and the transistor 117 generate large noises by repeatedly operating and not operating. The noises can cause the circuit boards and other components to malfunction. Malfunctions can be prevented by providing electrostatic and electromagnetic shields to the partitions of each chamber. In the present invention, by operating the switch circuits 124 and 122 in synchronization with each other, the generation of noise is suppressed and malfunction of the test device is prevented.

[0094] The electrostatic shield and electromagnetic shield are realized by attaching or forming a conductive plate, conductive plate (conductor plate), conductive film, metal plate, metal film, or wire mesh around each chamber or on the surface or inside of the partition 214.

[0095] The sample connection circuit 203 is disposed in a position close to the transistor 117 to be tested. A connector 202b is disposed in the sample connection circuit 203. A connector 202a is disposed on the terminal board 202. The connectors 202a and 202b are connected by a coaxial cable or a shielded cable.

[0096] The sample connection circuits 203 are individually arranged corresponding to the transistors 117 to be tested, and the sample connection circuits 203 are configured so as to be easily removable by means of connectors 202 or the like.

[0097] The constant current circuit 118 supplies a constant current Ic to a diode Di, a diode Ds, or a diode Dm arranged or formed between the channels of the transistor 117. Alternatively, the constant current circuit 118 supplies a constant current Ic between the channels of the transistor 117. The operational amplifier circuit 116 buffers (lowers the output impedance) the terminal voltage of the diode Di or the voltage between the channel terminals of the transistor 117, and outputs it as a voltage Vi.

[0098] The Vi voltage is analog-to-digital converted by the temperature measurement circuit 115. The Vi voltage changes depending on the temperature of the transistor 117. Therefore, by measuring the Vi voltage, it is possible to obtain the temperature of the transistor 117. In other words, it is possible to obtain temperature information Tj of the transistor 117.

[0099] The terminal voltage Vi of the diode or transistor is applied to a temperature measurement circuit 115. The temperature measurement circuit 115 obtains temperature information Tj of the transistor 117 from the terminal voltage Vi of the diode, or measures the temperature, and transfers it to the control circuit 111. The gate driver circuit 113 applies a set on-voltage to the gate terminal g of the transistor 117 at a set frequency (on-off cycle t cycle). In one embodiment, as shown in FIG. 51(a), the on-off period of transistor 117 is 1 t cycle, and the on-time is ton.

[0100] In an embodiment of the present invention, the voltages output by the gate driver circuit 113 are an on-voltage V2, an on-voltage V1, and an off-voltage Voff (V0). The gate driver circuit 113 can output voltages of three or more levels. For example, the on-voltage V2, the on-voltage V1, the off-voltage Voff1 = 0V, and the off-voltage Voff2 = -2V which is lower than the off-voltage Voff1 are exemplified.

[0101] For example, in the embodiment of FIG. 52, the gate driver circuit 113 generates on-voltages (V1 voltage, V2 voltage) of two types of potential levels and applies them to the gate terminal g (gate terminal gm, gate terminal gs) of the transistor 117.

[0102] The on-voltage V1 is applied to the gate terminal, and then the on-voltage V2 is applied to the gate terminal. By applying the on-voltage V2, the transistor 117 becomes strongly on (the channel resistance between the channels of the transistor 117 decreases compared to the case of V1). Alternatively, the transistor 117 is turned on by a predetermined voltage. When V1 < V2, the resistance between the channels of the transistor 117 can be made smaller than in the case of V1. When the constant current Ic is supplied to the transistor 117 when the V2 voltage is applied, the voltage Vi between the channel terminals of the transistor 117 is measured. The Vi voltage is processed by integrating or adding coefficients or the like to obtain the temperature information Tj.

[0103] The gate driver circuit 113 can output voltages of four or more levels. Also, it can output a triangular wave, a sine wave, etc. that change with time (such as the period from t2 to t3 in FIG. 58(c)). Also, the voltage Vg can be randomly changed and applied to the gate terminal.

[0104] The transistor 117 operates / non-operates (turns on / off) according to the gate signal voltage Vg output from the gate driver circuit 113. During the period when the transistor 117 is on, a test current Id flows between the channels of the transistor 117. The gate driver circuit 113 includes a variable resistance circuit 125. The resistance value Vr of the variable resistance circuit 125 can be varied between 0 (Ω) and 500 (Ω).

[0105] As in the examples of Figures 51, 52, and 53, it is effective to change the value Vr when the V2 voltage is applied and when the V1 voltage is applied. For example, in one embodiment, the resistor Vr is set to 300Ω when the V1 voltage is applied, and is set to 20Ω when the V2 voltage is applied. By setting the resistance value of the resistor to a lower value when the V2 voltage is applied than when the V1 voltage is applied, the channel inter-terminal voltage Vi at the constant current Ic flowing through the transistor 117 becomes stable. The resistance value of the resistor Vr is set according to the voltage value (voltage V2, voltage V1, etc.) applied to the gate terminal g.

[0106] The resistance value of the resistor Vr connected to the gate terminal g is changed when the test current Id is supplied to the transistor 117 and when the constant current Ic is supplied to the transistor 117. Alternatively, the resistance value of the resistor Vr is made different or changed.

[0107] In addition, when changing from the V1 voltage to the V2 voltage, the resistance Vr is changed by synchronizing the timing of the change in the resistance Vr when the V1 voltage is applied with the timing of the change in the resistance Vr when the V2 voltage is applied. By changing the resistance Vr to a higher value, the occurrence of inrush current and surge voltage can be suppressed.

[0108] In the voltages Vn, V0, V1, and V2 applied to the gate terminal g, the occurrence of inrush current and surge voltage can be suppressed by varying or making different the resistance value Vr. Also, by making different the resistance value Vr, it is possible to intentionally generate inrush current and surge voltage.

[0109] The gate driver circuit 113 can be set to a constant voltage or a voltage that varies over time. The gate driver circuit 113 is also configured so that it can be set (output) to a voltage that varies periodically over time.

[0110] It is also effective to set the resistance value of resistor Vr when the V2 voltage is applied to the gate terminal g to a different value from the resistance value of resistor Vr when the V1 voltage is applied to the gate terminal g. The resistance between the channels of transistor 117 can be set by the resistance value Vr, so that the constant current Ic can be supplied and the inter-channel voltage Vi to be measured can be stabilized.

[0111] A resistor R (not shown) may be disposed between the gate terminal g and the emitter terminal e or between the collector terminal c of the transistor 117. By adjusting the value of the resistor R, the inclination angle of the voltage waveform at the rising and falling edges of the gate signal can be adjusted or set. Also, the occurrence of inrush current and surge voltage can be suppressed. Also, by varying the resistance value, inrush current and surge voltage can be intentionally generated.

[0112] The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate signal voltage applied to the gate terminal g of the transistor 117. By separately adjusting the rise time Tr and the fall time Td, the on-time and on-characteristics of the transistor 117 are controlled to predetermined values.

[0113] As described above, the electrical element (semiconductor element) testing apparatus and testing method of the present invention can control, adjust, or set the resistance value Vr of the variable resistance circuit 125 connected to the gate terminal of the transistor 117, or the rise time / fall time of the gate driver circuit 113.

[0114] A constant current circuit 118 supplies a predetermined constant current Ic. The constant current Ic is applied to a diode Di or a transistor 117. When the temperature of the transistor 117 changes, the terminal voltage of the diode Di or the voltage between the channel terminals of the transistor changes. By monitoring or measuring the terminal voltage Vi of the diode Di or the like, the temperature change of the transistor 117 can be measured or observed.

[0115] A test current Id may be supplied to the transistor 117, and the channel-to-channel voltage Vce of the transistor 117 may be measured while the test current Id is being supplied (FIG. 56, etc.). The channel-to-channel voltage Vce of the transistor 117 changes in voltage value due to deterioration or heat generation temperature of the transistor 117. The changing voltage Vi is measured, and is integrated or added / subtracted with a temperature coefficient K, etc. to obtain temperature information Tj.

[0116] The diode Di may be a diode D of another semiconductor chip mounted on the semiconductor chip on which the transistor 117 is formed. The diode Di may utilize a parasitic diode that is formed secondarily when the transistor 117 is formed.

[0117] The temperature information Tj may be provided or implemented in the transistor 117 or the like and information from the temperature measurement circuit 115 may be used. The temperature measurement circuit 115 is configured using a thermocouple, a thermistor, a posistor, or the like as the temperature sensor 510.

[0118] In order to prevent the transistor 117 from heating up due to the constant current Ic, the constant current Ic is set to a current value that is sufficiently smaller than the constant current Id flowing through the channel of the transistor 117 .

[0119] Specifically, the constant current Ic is set to 1 / 1000 or less of the current Id flowing through the transistor 117 during testing. Preferably, the current Ic flowing through the transistor 117 is set to 1×10 6 1 or more 1×10 4 The constant current Ic should be between 0.1mA and 100mA.

[0120] The channel current Id is changed, and the voltages of the diode Di and the like (the collector-emitter terminal voltage of the transistor 117, and the cathode-anode voltage of the diode) are measured to obtain the temperature coefficient K. The obtained temperature coefficient K is stored in the temperature measurement circuit 115 or the controller circuit 111.

[0121] 6 and 7, a heating / cooling plate 134 is disposed below the semiconductor element 117. A circulating water pipe (not shown) is incorporated in the heating / cooling plate 134. A refrigerant (cooling water, etc.) is circulated through the circulating water pipe. The heating / cooling plate 134 may be configured so that it can be cooled or heated by a Peltier element.

[0122] The heating / cooling plate 134 is not limited to a plate. For example, it may have a shape or configuration in which the semiconductor element 117 can be inserted in the center. The heating / cooling plate 134 may have any configuration as long as it has the function of a temperature regulator or temperature setter having at least one of the functions of heating and cooling.

[0123] Condensation occurs when cooling is performed using the heating and cooling plate 134, etc. Therefore, it is preferable to perform tests such as a power cycle test by blowing dry air onto the semiconductor element (electrical element) to be tested.

[0124] The heating / cooling plate 134 is not limited to a plate. For example, it may be a structure or device in which the transistor 117 is inserted or clamped in a temperature setting device. The heating / cooling plate 134 may be provided with pipes for circulating cooling water or the like.

[0125] The heating / cooling plate 134 may be configured with an oven, a mantle heater, a hot plate, an electric furnace, or a heater for heating, or with a heat pump or a nitrogen cooler for cooling. A test sample such as the transistor 117 may be clamped between heating and cooling plates, or may be inserted into a heating and cooling device and fixed therein.

[0126] The heating and cooling plate 134 includes devices for maintaining a constant temperature and dehumidification. For example, a constant temperature water bath, a circulating constant temperature water bath, an incubator, and a dehumidifier are applicable. Also, devices for humidification are included. In order to achieve good heat dissipation by closely contacting the heat pipe 223, it is also effective to apply heat dissipation grease 516 between the heat pipe 223 and the terminal board 502, etc. It is preferable to inject dry air into the space in which the semiconductor element 117 to be tested is placed, or to blow dry air onto the element to be tested.

[0127] The heater heating control system performs PID control calculations so that the target temperature (SV) and measured temperature (PV) match for one control point, and controls the heater supply power. When testing and evaluating semiconductor devices, it is necessary to control the heater and cooling mechanisms simultaneously. In the present invention, the heating and cooling control is performed by operating and controlling two output systems, heating output and cooling output, with one regulator.

[0128] The temperature coefficient K is obtained by heating the transistor 117 to a predetermined temperature using the heating / cooling plate 134 or the like, passing a constant current Ic through the diode Di, and measuring the collector terminal and emitter terminal voltages. By varying the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage Vi of the diode Di with respect to the temperature of the transistor 117 can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be obtained from the terminal voltage Vi of the diode Di with respect to the temperature.

[0129] The constant current Ic flows through the diode Di when the channel current Id does not flow. In other words, when the transistor 117 is not on, the constant current Ic flows and the inter-terminal voltage Vi of the diode Di is measured. The operational amplifier circuit (buffer circuit) 116 outputs the terminal voltage Vi (terminal c-terminal e) of the diode Di.

[0130] The operational amplifier circuit 116 is not limited to being configured from an operational amplifier element, but may be any circuit having an output impedance lower than the input impedance.

[0131] The temperature measuring circuit 115 obtains the temperature or temperature information Tj of the transistor 117 being tested from the stored temperature coefficient K and voltage Vi, or the temperature output by the temperature measuring circuit 115 is set as the temperature information Tj.

[0132] The obtained temperature information Tj is sent to a control circuit (controller) 111. When the temperature or the temperature information Tj becomes equal to or exceeds a predetermined set value, the control circuit (controller) 111 determines that the transistor 117 is in a predetermined stress state or deteriorated state, and changes the control of the test or stops the test.

[0133] The embodiments of Figures 2 and 22 are configured by adding a switch circuit 124 to the embodiment of Figure 1. In the embodiment of Figure 2, switch circuits 124d, 124b, and 124c use the symbols for the switch circuits.

[0134] Any device that has a small resistance (on-resistance) when closed (on) can be used as the switch circuit 122 and the switch circuit 124. Examples of such devices include transistors, mechanical relays, phototransistors, photodiode switches, and photoMOS relays. It is particularly preferable to use a power MOSFET for the switch circuit 124. A MOSFET is preferable because it has a small inter-channel voltage (Vsd).

[0135] When the switch circuit 124d is turned on (closed), the power supply wiring 212b and the power supply wiring 212c are short-circuited, and a short-circuit current Im flows. By turning on the switch circuit 124d, the charge between the power supply wiring 212b and the power supply wiring 212c can be discharged. In addition, the emitter terminal and the collector terminal of the transistor 117m are short-circuited, and the accumulated charge can be discharged.

[0136] When the switch circuit 124c is turned on (closed), the power supply wiring 212b and the power supply wiring 212c are short-circuited, and a short-circuit current Im flows. By turning on the switch circuit 124c, the charge between the power supply wiring 212b and the power supply wiring 212c can be discharged. In addition, the emitter terminal and the collector terminal of the transistor 117s are short-circuited, and the charged charge can be discharged.

[0137] When the switch circuit 124b is turned on (closed), the power supply wiring 212c and the power supply wiring 212a are short-circuited, and a short-circuit current Im flows. By turning on the switch circuit 124b, the charge between the power supply wiring 212c and the power supply wiring 212a can be discharged. In addition, the terminals of the semiconductor module 117 are short-circuited, and the accumulated charge can be discharged.

[0138] When starting a test of the semiconductor module 117, the switch circuit 124 is turned on (closed) and then the test is started. When ending the test of the semiconductor module 117, the switch circuit 124 is also turned on (closed). During the test of the semiconductor module 117, the switch circuit 124 is turned off (open).

[0139] The on state of the switch circuit 124 is linked to the contact switch 529. When the contact switch 529 is not in the on state, the switch circuit 124 maintains the on state, and the test current Id is not applied to the transistor 117 to be tested. It is also linked to the on / off state of the power supply device 132.

[0140] The power supply device 132 is linked to the open / closed state of the door 527. When the door 527 is open, the switch circuit 124 maintains the on state, and no current is supplied to the transistor 117 to be tested. The link is detected and implemented by a contact switch 529 or the like. When the switch circuit 124 a is turned off, the test current Id output by the power supply device 132 is supplied to the transistor 117 .

[0141] Switch circuit 122 and switch circuit 124 are mounted or formed on switch circuit board 201. Although not shown, conductive plate 204 is attached to switch circuit board 201. Each terminal of switch circuit 124 is connected to conductive plate 204. Conductive plate (copper bar) 204 is, for example, a plate made of copper with a thickness of 5 mm and a width of 50 mm. The length of conductive plate 204 is, for example, 250 mm.

[0142] 11(a), electrical connection is achieved by mechanically fitting fork plug 205 and conductor plate 204. When the U-shaped portion of fork plug 205 is inserted into conductor plate 204, the U-shaped portion slightly expands or comes into proper contact, so that fork plug 205 and conductor plate 204 are joined or fitted together satisfactorily.

[0143] Contact resistance may occur at the connection between fork plug 205 and conductive plate 204 and at the connection between fork connector 528 and conductive plate 204. If there is contact resistance, heat will be generated at the connection.

[0144] 12, in order to prevent heat generation due to contact resistance, a recess is formed in the conductive plate 204, and a heat pipe 223 is disposed or installed in the recess. A recess is formed in the conductive plate 204, and a heat pipe 223 is disposed or installed in the recess.

[0145] 13, the heat pipe 223 may be disposed or installed within the conductive plate 204. The heat pipe 223 may be configured to overlap the conductive plate 204.

[0146] 13, a connection bolt 219 is attached to the fork plug 205. A connection wire 211 is connected to or fitted into the connection bolt 219 or the like.

[0147] The conductive plate 204 and the fork plug 205 are in contact with each other at contact parts 220a and 220b formed on the fork plug 205. The contact parts 220 are made of phosphor bronze and nickel alloy, and have spring properties. The surface of the contact parts 220 is plated with gold or silver. The plating improves the electrical stability of the connection parts 220.

[0148] A heat pipe 223 is in intimate contact with a recess (not shown) on the surface of the conductive plate 204. The surface of the conductive plate 204 and 223 may be coated with thermally conductive grease or a silicone oil compound for heat dissipation.

[0149] The heat pipe 223 is disposed so as to fit into a recess (not shown). By disposing the heat pipe 223 in the recess, the risk of the heat pipe 223 being damaged is reduced. The conductive plate 204 is made of a material whose linear expansion coefficient is smaller than that of the heat pipe 223 .

[0150] The conductive plate 204 is heated during testing. The heat pipe 223 is also heated. The heat causes the heat pipe 223 to expand. The material of the heat pipe 223 expands more in the recess, and the heat pipe 223 is more firmly fitted into the recess. Therefore, the heat pipe 223 will not come off.

[0151] Examples of materials for the conductive plate 204 include copper (linear expansion coefficient 16.8), brass (linear expansion coefficient 19), iron (linear expansion coefficient 12.1), and stainless steel (SUS304) (linear expansion coefficient 17.3). Examples of materials for the heat pipe 223 include materials with a linear expansion coefficient larger than that of the conductive plate 204, such as aluminum (linear expansion coefficient 23), tin (linear expansion coefficient 26.9), and lead (linear expansion coefficient 29.1).

[0152] Among them, it is preferable to use copper (coefficient of linear expansion 16.8) as the material of the conductive plate 204, and aluminum (coefficient of linear expansion 23) as the material of the heat pipe 223. As the material of the conductive plate 204, carbon and the like other than metals can also be used. The heat pipe 223 is a sealed container in which a small amount of liquid (working liquid) is vacuum sealed, and the inner wall of the container is provided with a capillary structure (wick). As the working fluid, in addition to pure water, methanol (methyl alcohol), acetone, sodium, mercury, fluorocarbon refrigerants, and ammonia may be used. Wick materials include aluminum, copper, stainless steel, sintered alloy, wire mesh, foamed metal, and ceramics.

[0153] 3 and 4 are configuration and explanatory diagrams of the electrical element testing device of the present invention. The entire thermostatic chamber (housing) 523 of the electrical element testing device is illustrated typically. In Fig. 4, the door of the thermostatic chamber (housing) 523 is omitted, and the internal configuration or arrangement of the housing is illustrated clearly. Heating and cooling equipment parts 522 are arranged on the left and right side parts of a case (such as a thermostatic chamber) 523 of the electrical element test apparatus of the present invention. The electrical element test apparatus also has a humidifying and dehumidifying function.

[0154] The heating and cooling equipment section 522 has a thermostatic dryer / oven, a mantle heater, a hot plate, an electric furnace, and a heater for heating, and also has a freeze dryer, a cooling device, a refrigerator, and a freezer for cooling.

[0155] The heating and cooling equipment section 522 includes equipment for maintaining a constant temperature and dehumidifying. For example, a constant temperature water bath, a circulating constant temperature water bath, an incubator, and a dehumidifier are included. Also included are equipment for humidifying or dehumidifying.

[0156] The heater heating control system performs PID control calculations so that the target temperature (SV) and measured temperature (PV) match for one control point, and controls the heater supply power. When testing and evaluating semiconductor devices, it is necessary to control the heater and cooling mechanisms simultaneously. In the present invention, the heating and cooling control is performed by operating and controlling two output systems, heating output and cooling output, with one regulator.

[0157] Heating and cooling equipment section 522 is disposed on the left and right sides of the side section of thermostatic bath (housing) 523. It has a fan (gas agitator, gas agitator, etc.) 525, and circulates heated air or cooled air inside bath 525. It also has a humidifier and a dehumidifier for adjusting the humidity inside bath 525 to a predetermined humidity level, and circulates humidified or dehumidified air inside bath 525.

[0158] A fan 227 is provided inside the tank 525. The fan 227 is arranged below the slide plate 505, and maintains the semiconductor elements (electrical elements) 117 arranged on the slide plate 505 at a predetermined temperature or changes / sets the temperature to a predetermined temperature. A conductive plate 204 is attached to the partition wall 214a on the back surface of the thermostatic tank (housing) 523. Alternatively, the conductive plate 204 is inserted into a hole.

[0159] The conductive plates 204 are arranged so as to correspond to the position of the fork connector 528. When the transistor 117 has three terminals, the conductive plates 204 are arranged in groups of three, as shown by the dotted lines at the positions of the conductive plates 204 in Figures 4 and 14. The number of groups is the same as the number of transistors 117.

[0160] FIG. 4 shows an example in which four transistors 117 are mounted on the slide plate 505, four sets of light guide plates 204 are arranged, and three slide plates 505 are arranged.

[0161] By arranging the conductive plate 204 at the distance H (spacing H (see FIG. 9, etc.)), the connectivity between the fork connector 528 and the conductive plate 204 is improved. Also, the conductive plates 204 can be arranged at high density on the rear surface.

[0162] The test current applied to test the transistor 117 is large, at several tens of amperes (A). Therefore, it is necessary to use thick wires for the power supply wires 212 and the connection wires 211. Thick wires are rigid and hard, and therefore difficult to bend. The three connection wires 211 that supply power to the three terminals of the transistor 117 must electrically connect the terminals of the transistor 117 and the fork connector 528 so that there is no difference in resistance value. Therefore, it is preferable that the connection wires 211 are connected in a straight line with the shortest possible length.

[0163] 4 and 9, by arranging and connecting the connection wiring 211 as shown in FIG. 8 with the conductive plates 204 spaced apart by a distance H, the connection wiring 211 can be connected linearly with the shortest length. As shown in FIGS. 5 and 15, the slide plate 505 moves along a rail guide 507 and can be fixed to the rail guide 507 .

[0164] 15, cam followers 506 are attached to slide plate 505. Cam followers 506a1 and cam followers 506a2 are disposed near the tip end of slide plate 505 with their positions shifted.

[0165] Rail guide 507 is inserted between cam follower 506a1 and cam follower 506a2. Rail guide 507 is sandwiched between cam follower 506b1 and cam follower 506b2.

[0166] As described above, slide plate 505 is inserted into rail guide 507 from the tip end thereof. Next, rail guide 507 enters between cam follower 506b1 and cam follower 506b2, and slide plate 505 is introduced into rail guide 507. Cam follower 506c and cam follower 506d support rail guide 507 from below. The slide plate 505 moves on the cam follower 506a2, the cam follower 506b2, the cam follower 506c, and the cam follower 506d.

[0167] A handle 518 is attached to the slide plate 505. By holding the handle 518, the slide plate 505 can be moved from the front to the back (partition wall 214a) of the thermostatic chamber (housing) 523. Alternatively, by holding the handle 518, the slide plate 505 can be moved from the back (partition wall 214a) of the thermostatic chamber (housing) 523 to the front. By moving the slide plate 505 to the front, a test sample such as a transistor 117 can be easily removed and mounted or placed.

[0168] 5(a), the door 527 is opened, and the slide plate 505 is inserted into the rail guide 507. The slide plate 505 is pushed along the rail guide 507 into the partition wall 214a.

[0169] By pushing in the slide plate 505, the conductive plate (conductor plate) 204 is inserted into the fork connector 528, and the fork connector 528 and the conductive plate (conductor plate) 204 are fitted together or otherwise electrically connected. The conductive plate (conductor plate) 204 is preferably made of a metal such as copper, aluminum, or iron. When the slide plate 505 is pushed in, the fork connector 528 and the like contact the contact switch 529.

[0170] When the contact switch 529 is pressed, it detects that the fork connector 528 and the conductive plate (conductor plate) are electrically connected, and the confirmation lamp 530 lights up (FIG. 5(b)). The confirmation lamp 530 is attached to the outer surface of the thermostatic chamber (housing) 523 or to the front cover 753, as shown in FIGS.

[0171] 5(b), when the fork connector 528 and the conductive plate (conductor plate) 204 are connected, the contact switch 529 is pressed and the confirmation lamp 530 is turned on. When the connection between the fork connector 528 and the conductive plate (conductor plate) 204 is released, the contact switch 529 is opened and the confirmation lamp 530 is turned off. Depending on the state of the contact switch 529, the controller circuit 111 sets (starts, stops, etc.) or changes (changes the type of test, etc.) the control of the test. 6 and 8 are explanatory diagrams showing the arrangement and configuration of the terminal board 502, the connection wiring 211, the fork connector 528, etc.

[0172] The fork connector 528 is attached to the connector base 504 by a connecting bolt 219. The connector base 504 is fixed to the slide plate 505 through a fixing hole 531.

[0173] 8, as an example, four semiconductor elements 117 are arranged on a terminal board 502. The element terminals 226 of the semiconductor elements 117 are pressed by a pressing tool 501, and the element connection parts 535 and the element terminals 226 are pressure-welded and electrically connected.

[0174] It goes without saying that the pressing tool 501 etc. can use the configurations described in Figures 26, 29, etc., or can be substituted for them. In addition, it goes without saying that the pressing tool 501 etc. can use or be substituted for the configurations of the connecting fittings 722 etc. in Figures 32, 34, and 35, the configuration of the connecting fitting pin 781 in Figure 34, etc. In addition, the configurations in Figures 25 to 40 can be used or combined with the configurations in Figures 6, 7, 8, etc. as appropriate.

[0175] Furthermore, the configurations of Figures 41 to 50 can be used or combined as appropriate with the configurations of Figures 1 to 18. Furthermore, it goes without saying that the configuration of Figure 63 can be applied to an embodiment of the present invention.

[0176] Moreover, it goes without saying that the pressing tool 501 in Fig. 6 and Fig. 8 can be replaced with the configuration in Fig. 29 to Fig. 36, or can be combined with them. Moreover, it goes without saying that the matters and configurations described in Fig. 24 to Fig. 40 can be applied to the embodiments in Fig. 6 to Fig. 16, or can be combined with them. As described above, it goes without saying that the embodiments described in this specification, the drawings, etc. can be configured by using some or all of them together or in combination with each other to form an embodiment. Terminal board 226 is placed on device stand 503 , and terminal board 226 and device stand 503 are fixed to slide plate 505 by fixing holes 532 . The connection wiring 211 electrically connects the fork connector 528 and the land 515 in a straight line. By arranging and connecting the connection wiring 211 as shown in FIG. 8, the connection wiring 211 can be connected in a straight line with the shortest length.

[0177] The fork connector 528 is electrically connected to the conductive plate 204. When electrically connected, pressure is applied by the conductive plate 204. The device stand 503 and the connector stand 504 are spaced apart from each other. They are also attached to the same slide plate 505. The device stand 503 and the connector stand 504 are connected by a connection wiring 211 to provide shock absorbing properties.

[0178] Therefore, even if pressure is applied to fork connector 528 when fork connector 528 and conductive plate 204 are connected, semiconductor element 117 will not become misaligned because it is mounted on device base 503 .

[0179] 4, 17, 18, and 46, fans 227 are disposed under each slide plate 505 to cool or heat control circuit board 519, etc. Alternatively, cool air, hot air, etc. is blown from fan 227 onto electric element 117 to cool or heat electric element 117 to be tested. An opening 537 is formed in slide plate 505, and air from fan 227 is blown from opening 537 of slide plate 505 onto electric element (semiconductor element) 117. The fan 227 may blow air from the side of the electric element (semiconductor element) 117 to be tested, or from the top of the semiconductor element 117.

[0180] Fig. 18 is a schematic diagram and an explanatory diagram of an embodiment in which the conductive plate 204 is arranged in the vertical direction as in the configuration of Fig. 10. The figure shows a state in which the slide plate 505 is not arranged on the rail guide 507 at the left end.

[0181] Fig. 17 is a schematic diagram and an explanatory diagram of an embodiment in which the conductive plate 204 is arranged in the horizontal direction as in the configuration of Fig. 8. The figure shows a state in which the slide plate 505 is not arranged on the rail guide 507 at the left end.

[0182] Although the present specification and drawings refer to the conductor plate 204, it is not limited to a plate shape and may be rod-shaped, cylindrical, or copper foil-shaped. It may also be a structure such as a socket or connector. The conductor plate 204 may also be connected in the shape of a fork plug. It may also be configured or formed in a cylindrical or pipe shape. The conductor plate 204 and the fork plug 528 or the like are electrically connected by fitting, crimping, pressure welding, or fitting their tips.

[0183] Conductive plate 204 electrically connects the inside of thermostatic chamber (housing) 523 such as a thermostatic chamber to the outside of thermostatic chamber (housing) 523, and a test current and a test voltage are supplied from power supply device 132 via conductive plate 204. Alternatively, as shown in FIG. 63, conductive plate 204 is mounted or placed on switch circuit board 201.

[0184] The conductive plate 204 is configured or arranged so as to be removable from the partition wall 214a. Urethane resin is formed or arranged around a hole formed in the partition wall 214a, so that the conductive plate 204 is insulated from the partition wall 214 and the conductive plate 204 is press-fitted. As shown in FIGS. 8 and 10, the conductive plate 204 is fixed to a protrusion provided on the partition wall 214a by a connecting bolt 219 so as not to come off.

[0185] A cam follower 506 is attached to the slide plate 505. The slide plate 505 is configured so as to be able to be inserted into the interior 525 of the thermostatic chamber 523 along a rail guide 507 and to be able to be taken out from the interior 525 of the thermostatic chamber 523.

[0186] It goes without saying that the structures or configurations of Figures 1 to 5 can be applied to the embodiments of the present invention shown in Figures 28 to 48. It goes without saying that they can also be combined with each other. 9 and 10 are configuration diagrams and explanatory diagrams for explaining the positions of the fork connector 528 and the like.

[0187] 22(b), for example, three terminals need to be connected by connection wiring 211. Fork connectors 528 are connected to the three connection wirings 211. As described in FIG. 8, in order to arrange the connection wirings 211 in a short distance and in a straight line, the three fork connectors 528 (fork connector 528a, fork connector 528b, fork connector 528c) are arranged or placed with a step of distance H. Also, conductor plate 204 (conductor plate 204a, conductor plate 204b, conductor plate 204c) are arranged or placed with a step of distance H.

[0188] Needless to say, the embodiments of Figures 23, 24, 25, 26, 27, etc. can be applied to the structures of Figures 6 and 7. Also, it goes without saying that the embodiments of Figures 29 to 38 can be applied to the structures of Figures 6 and 7.

[0189] As shown in FIG. 16, the connection wiring 211 is connected in accordance with the positions (steps H) of the fork connectors 528 (fork connector 528a, fork connector 528b, fork connector 528c).

[0190] As shown in FIGS. 15 and 16, fork connectors 528 (fork connector 528a, fork connector 528b, fork connector 528c) are attached to holder 520 and fixed to holder 520.

[0191] The holder 520 is configured so that it can be moved forward and backward (forward: +, rear: -) as shown in Fig. 15. By moving the holder 520, the contact switch 529 can be appropriately pressed by the movement of the slide plate 505 as described in Figs. 3 and 5.

[0192] The connection state between the fork connector 528 and the conductive plate 204 is detected and the state is grasped by a contact switch 529. When the contact switch 529 is pressed, the contact switch 529 is turned on and a confirmation lamp 530 is turned on.

[0193] 9 shows an embodiment in which conductive plate 204 is arranged in a horizontally long direction. Fork connector 528 is fixed to connector base 504. Fork connector 528a is fixed to connector base 504a, fork connector 528b is fixed to connector base 504b, and fork connector 528c is fixed to connector base 504c. The connector base 504a, the connector base 504b, and the connector base 504b are attached to the slide plate 505 so as to form a step H.

[0194] The connection wiring 211a is electrically connected to an element terminal 226a of the semiconductor module 117. The connection wiring 211b is electrically connected to an element terminal 226b of the semiconductor module 117. The connection wiring 211c is electrically connected to an element terminal 226c of the semiconductor module 117.

[0195] A connector 536a is attached to the conductive plate 204a with a connecting bolt 219. A connector 536b is attached to the conductive plate 204b with a connecting bolt 219. A connector 536c is attached to the conductive plate 204c with a connecting bolt 219. A test voltage (test current) is supplied to each bolt 219 from the power supply device 132. The bolts are screws.

[0196] Conductive plate 204 penetrates partition wall 214a, and also serves as an electrical path connecting the inside and outside of thermostatic chamber (housing) 523. Fork connector 528 is connected to one side of conductive plate 204, and connector 536 or fork plug 205 is connected to the other side. Connection bolt 219 is attached to connector 536 or fork plug 205. Connection bolt 219 connects power supply wiring 212. Fig. 9 shows an embodiment in which the conductive plate 204 is arranged in the horizontal direction, and Fig. 10 shows an embodiment in which the conductive plate 204 is arranged in the vertical direction.

[0197] 11(a), a set of three conductive plates 204 is arranged. The three conductive plates 204 are arranged at a distance H. By arranging them at the distance H and providing a step, the arrangement of the conductive plates 204 can be space-saving.

[0198] The electric element 117 to be tested is placed on the slide plate 505, and since the slide plate 505 is removable, it is easy to connect and fix the electric element 117. In addition, it is easy to check the connection state of the electric element 117.

[0199] By fixing the electric element 117 to the slide plate 505 and fitting the slide plate 505 along the rail guide 507 inside the tank 526 , electrical connection with the conductive plate 204 can be easily established.

[0200] The connection state between the conductive plate 204 and the fork connector 528 etc. can be confirmed by the on / off state of a contact switch 529 and the lighting state of a confirmation lamp 530 which displays the state of the contact switch 529 .

[0201] A fork plug 205 is connected to the conductive plate 204. A fork plug 205a is connected to the conductive plate 204a. A fork plug 205b is connected to the conductive plate 204b. A fork plug 205c is connected to the conductive plate 204c. The fork plug 205 is attached with a connecting bolt 219. A test voltage (test current Id) from the power supply unit 132 is supplied to each bolt 219.

[0202] Conductive plate 204 penetrates partition wall 214a and also serves as an electrical path connecting the inside and outside of thermostatic chamber (housing) 523. Fork connector 528 is connected or fitted to one side of conductive plate 204, and fork plug 205 is connected or fitted to the other side.

[0203] Fig. 11(a) is an explanatory diagram illustrating the configuration of Fig. 10 from the rear side of the thermostatic chamber (housing) 523. Three conductor plates 204 are arranged in the conductor plate group 517. The conductor plates 204 respectively correspond to three element terminals 226 of the semiconductor element 117, etc.

[0204] The conductive plate 204 is disposed in the vertical direction. A fork plug 205 is inserted into the conductive plate 204. When the conductive plate 204 and the fork plug 205 are electrically connected, a test current Id (test voltage) from the power supply device 132 can be applied to the semiconductor element 117.

[0205] Fig. 11(b) is an explanatory diagram showing the rear part of thermostatic chamber (housing) 523 from above. The connection position (selected conductor plate 204) between fork plug 205 and conductor plate 204 is realized by inserting fork plug 205 into opening 216 formed or disposed in partition wall 214b, as shown in Fig. 11(b). For example, by inserting fork plug 205 into opening 216a, it is possible to connect or fit with conductor plate 204a.

[0206] Fork plug 205 is attached in correspondence with the position of semiconductor element 117 to be tested. The current for testing semiconductor element 117 is large, and connection wiring 211 and power supply wiring 212 through which the large current flows are thick and hard. Therefore, it is not easy to change the wiring of connection wiring 211 and power supply wiring 212 in correspondence with the position of semiconductor element 117 to be tested.

[0207] In the present invention, by simply changing the fork plug 205 inserted into the opening 216, the connection to the semiconductor element 117 to be tested can be easily implemented or changed.

[0208] The current flowing through the transistor 117 under test is as large as several hundred amperes, so the thickness of the connection wiring 211 used is also large. Therefore, the large connection wiring 211 and the power supply wiring 212 are hard. Therefore, it is not easy to change the connection of the connection wiring 211 and the power supply wiring 212.

[0209] In the electrical device testing apparatus of the present invention, a fork plug 205 is inserted into any opening 216 in the partition wall 214b. By changing the position of the opening 216 into which the fork plug 205 is inserted, it is possible to connect to any transistor 117.

[0210] Therefore, when changing the connection of the transistor 117 according to the test conditions, it is not necessary to change the connection of the connection wiring 211, and it is only necessary to change the position of the opening 216 into which the fork plug 205 is inserted.

[0211] Contact resistance may occur at the connection between fork plug 205 and conductive plate 204, the connection between connector 536 and conductive plate 204, and the connection between fork connector 528 and conductive plate 204. If there is contact resistance, heat will be generated at the connection.

[0212] 12, in order to prevent heat generation due to contact resistance, a recess is formed in the conductive plate 204, and a heat pipe 223 is disposed or installed in the recess. A recess is formed in the conductive plate 204, and a heat pipe 223 is disposed or installed in the recess.

[0213] 13, heat pipes 223 may be arranged or installed within conductive plate 204. Heat pipes 223 may be configured to overlap conductive plate 204. Also, fans (not shown) for cooling conductive plate 204, fork connector 528, and fork plug 205 may be arranged or installed. Also, heat dissipation fins may be arranged or installed on any of these.

[0214] 12 and 13, the heat pipe 223 is arranged or configured on the conductive plate 204, but the present invention is not limited to this. For example, it goes without saying that the heat pipe 223 may be formed or arranged on the conductive plate 204 or the connector 536.

[0215] 8, as an example, four semiconductor elements 117 are arranged on a terminal board 502. The element terminals 226 of the semiconductor elements 117 are pressed by a pressing tool 501, and the element connection parts 535 and the element terminals 226 are pressure-welded and electrically connected. Terminal board 226 is placed on device stand 503 , and terminal board 226 and device stand 503 are fixed to slide plate 505 by fixing holes 532 . The connection wiring 211 electrically connects the fork connector 528 and the land 515 in a straight line. By arranging the connection wiring 211 as shown in FIG. 8 and connecting the connection wiring 211, the connection wiring 211 can be electrically connected in a linear manner with the shortest length.

[0216] One set of device stand 503 and connector stand 504 is attached to one slide plate 505. By inserting and removing each slide plate 505 from rail guides 507, the semiconductor element 117 to be tested can be easily installed, mounted, set, and removed in the thermostatic chamber (housing) 523.

[0217] 14, a conductor plate group 517 made up of conductor plates 204 corresponding to slide plate 505 is arranged on the back surface of thermostatic chamber (housing) 523. Four semiconductor elements 117 are arranged on slide plate 505a, and a conductor plate group 517a made up of four sets of three conductor plates 204 is arranged or configured corresponding to slide plate 505a.

[0218] Four semiconductor elements 117 are arranged on the slide plate 505b, and a conductor plate group 517b consisting of four sets of three conductor plates 204 is arranged or configured corresponding to the slide plate 505b.

[0219] Four semiconductor elements 117 are arranged or mounted on the slide plate 505c, and a conductor plate group 517c consisting of four sets of three conductor plates 204 is arranged or configured corresponding to the slide plate 505c.

[0220] 14 is a schematic diagram showing a state in which the testing machine section 533 having the above-mentioned components is configured or arranged in three stages. The bottom stage is the testing machine section 533a, the middle stage is the testing machine section 533b, and the top stage is the testing machine section 533c.

[0221] Tester section 533 is a unit for arranging groups of semiconductor elements 117 to be tested, each of which is loaded on slide plate 505. Therefore, in the embodiment of Fig. 14, there are 3 x 3 = 9 slide plates 505, and the maximum number of semiconductor elements 117 (electrical elements 117) that can be tested simultaneously is 3 x 3 x 4 = 36.

[0222] The above embodiment is a configuration using a conductive plate 204. The present invention is not limited to this. For example, a socket connector may be used as shown in Fig. 19. Fig. 19 is an explanatory diagram of a configuration corresponding to the configurations in Figs. 9 and 10.

[0223] A socket connector (female) 509 is attached to the bulkhead 214a. The connection wiring 211 and the socket connector (off) 508 are electrically connected. Parts not necessary for the explanation of the contact switch 529 and the like are omitted.

[0224] In this specification and drawings, parts, portions, and descriptions that are not necessary for the explanation may be omitted, and illustrations may be omitted. In addition, each embodiment may be combined in whole or in part. In addition, the embodiments of the present invention may be combined with each other, or may be implemented with some modifications.

[0225] By pushing the slide plate 505 toward the rear surface of the thermostatic chamber (housing) 523, the socket connector (female) 509 and the socket connector (male) 508 are electrically connected.

[0226] In the above embodiment, the conductive plate 204 penetrates or is inserted into the partition wall 214a on the back surface of the thermostatic chamber (housing) 523. However, the present invention is not limited to this. For example, as shown in FIG. 20, the conductive plate 204 may be configured to extend to the inside of the partition wall 214a.

[0227] The fork plug 205 is inserted into the opening 216 of the partition wall 214b inside the thermostatic chamber (housing) 523, and the fork plug 205 and the conductive plate 204 are electrically connected.

[0228] 3, a power supply device 132 and a controller circuit 111 are disposed above the thermostatic chamber (housing) 523. The power supply device 132 supplies a test current and a test voltage to the electric element 117. In the embodiment of FIG. 2, a switch circuit board 201 is disposed. The controller circuit 111 controls the power supply device 132, controls the electric elements 117 (semiconductor elements 117, transistors 117) and the like, and sets test conditions.

[0229] The controller circuit 111 sets test conditions by varying the current Id, gate voltage Vg, and collector-emitter voltage Vce so that the temperature information Tj of the electric element 117 (transistor 117) becomes a predetermined value, and performs a power cycle test or the like.

[0230] 4, two power supply devices 132a and 132b are shown. The number of power supply devices 132 is not limited to two. The electrical element testing device of the present invention has one or more power supply devices 132. In addition, the more the number of power supply devices 132 increases, the more diverse the test current Id that can be generated.

[0231] In the embodiment of the present invention, the power supply device 132 is not limited to one that outputs a constant current Id. For example, a power supply device that can set a maximum (limit) voltage is used as the power supply device 132. An example is one in which the power supply device 132 functions to output a predetermined constant current at a set maximum voltage under certain conditions.

[0232] In the case where a constant current of the test current Id is output, the output terminal voltage can be set to a predetermined maximum voltage. Also, the output current and output voltage can be changed in conjunction with the test state of the transistor 117.

[0233] When the gate leakage current, inter-channel voltage Vce, inter-channel resistance, etc. of the transistor 117 to be tested are outside a predetermined value range or exceed a predetermined value, the switch circuit 124 is turned on or off, and the power supply device 132 is turned on or off. Turning on the switch circuit 124 supplies a test current or test voltage, and turning on the switch circuit 124 stops the supply of the test current or test voltage. The power supply device 132 outputs a large test current Id for testing a semiconductor element (electrical element) 117 such as a transistor 117 .

[0234] The power supply device 132 supplies power (current, voltage) in synchronization with a control signal from the control circuit (controller) 111. The power supply device 132 can set a maximum voltage value to be output.

[0235] By applying an on-voltage and an off-voltage to the gate terminal of the transistor 117 periodically (one cycle: t cycle), a pulsed test current Id can be applied to the transistor 117.

[0236] 3 is a configuration diagram and explanatory diagram of the electrical element testing apparatus of the present invention, showing the thermostatic chamber (housing) 523 of the present invention viewed from the side. Conductive plate 204 is disposed on the rear surface of thermostatic chamber (housing) 523. By pressing slide plate 505 from door 527 toward the rear surface, fork connector 528 and conductive plate 204 are fitted together and electrically connected. The fitted or connected state of the fork connector 528 and the conductive plate 204 is detected by a contact switch 529 .

[0237] 5 is an explanatory diagram for explaining a method of connecting the conductive plate 204 and the fork connector 528. On the slide plate 505, a control circuit board 519, a terminal board 502, and a connector base 504 are attached.

[0238] The fork connector 528 is attached to a connector base 504. The terminal board 502 is attached to a device base 503. The connector base 504 and the terminal board 502 are connected by a connection wire 211.

[0239] Fork connector 528 is connected to or detached from conductor plate 204. At that time, a pressing or stretching pressure is applied. In the present invention, connector base 504 to which fork connector 528 is attached and device base 503 to which terminal board 502 is attached are separated and attached to slide plate 505. In addition, terminal board 502 and fork connector 528 are connected by connection wiring 211.

[0240] Mechanical pressure, etc., applied when fork connector 528 is connected to or disconnected from conductive plate 204 does not affect terminal substrate 502, and is absorbed by connection wiring 211. Therefore, the electrical connection state of transistor 117 can be maintained in a good condition. As shown in FIGS. 3 and 5, the sliding plate 505 is inserted / detached or placed / removed in the tank 526 by opening / closing the door 527 .

[0241] Slide plate 505 moves on rail guide 507 by cam follower 506 and rail guide 507. Conductive plate 204 is attached to partition wall 214a on the rear surface of thermostatic chamber (housing) 523. A fork connector 528 that electrically connects to conductive plate 204 is disposed on slide plate 505.

[0242] A handle 518 is disposed on the sliding plate 505. The handle 518 allows the sliding plate 505 to be easily inserted into the rail guide 507. In addition, the sliding plate 505 can be easily inserted into the inside of the tank 526 and removed from the inside of the tank 526. By pushing the slide plate 505 towards the rear surface of the housing, the fork connector 528 and the conductor plate 204 are fitted together, and an electrical connection is established.

[0243] The partition wall 214b has an opening 216 for inserting the fork plug 205. By inserting the fork plug 205 from the opening 216, the fork plug 205 and the conductive plate 204 are electrically connected to each other.

[0244] When the fork connector 528 and the conductive plate 204 are electrically connected, the confirmation lamp 530 turns on. The lighting of the confirmation lamp 530 is controlled by the controller circuit 111. The confirmation lamp 530 turns on.

[0245] Fig. 5(a) shows the state in which door 527 is open. Fig. 5(b) shows the state in which door 527 is closed. Door 527 is changed from the open state shown in Fig. 5(a) to the closed state shown in Fig. 5(b). Door 527 presses slide plate 505, pressing fork connector 528 against conductor plate 204, and fork connector 528 and conductor plate 204 are electrically connected.

[0246] 3 and 11, a fork plug 205 is connected to conductive plate 204 protruding from the rear surface of thermostatic chamber (housing) 523. Fork plug 205 is inserted through opening 216 of partition wall 214b. The inserted fork plug 205 is connected to conductive plate 204 corresponding to the position of fork plug 205.

[0247] Therefore, which conductive plate 204 is to be electrically connected can be easily implemented and changed by determining the opening 216 of the partition wall 214b into which the fork plug 205 is to be inserted.

[0248] 4, heating / cooling equipment section 522 is disposed on the left and right side surfaces of thermostatic bath (housing) 523. Heating / cooling equipment section 522 has a function of adjusting the humidity inside the housing to a predetermined value.

[0249] The heating and cooling equipment section 522 has a thermostatic dryer / oven, a mantle heater, a hot plate, an electric furnace, a heater, etc. for heating, and also has a freeze dryer, a cooling device, a refrigerator, and a freezer for cooling.

[0250] The heating and cooling equipment section 522 also includes equipment for heating, cooling, humidifying, and dehumidifying, such as a constant temperature water bath, a circulating constant temperature water bath, an incubator, and a dehumidifier.

[0251] Figures 6 and 7 are structural and explanatory diagrams of the device mounting portion of the electrical element testing apparatus of the present invention. Figures 6(a) and 7(a) are plan views seen from the terminal board 502 portion. Figures 6(b) and 7(b) are cross-sectional views taken along line AA' in Figures 6(a) and 7(a). Terminal board 502, which is a printed circuit board, has an opening 534 for inserting an element. An electric element to be tested, such as transistor 117, is inserted into element inserting part 534.

[0252] A heating / cooling plate 134 is disposed below the element insertion portion 534. The heating / cooling plate 134 brings the electric element 117 to be tested into close contact with the heating / cooling plate 134, and maintains the electric element 117 at a predetermined temperature during testing.

[0253] A temperature sensor 510 of a temperature measurement circuit (temperature measuring device, temperature acquisition unit) is attached to the transistor 117. The temperature sensor measures the temperature of the transistor 117 and controls the temperature during testing. The terminal board 502 is fixed to the device stand 503 with screws or the like through the fixing holes 514. The device stand 503 is fixed to the slide plate 505 with screws, bolts or the like.

[0254] The terminal board 502 is provided with a wiring pattern 511 that connects the lands 515 and the element connection portion 535. The terminal board 502 also has a connector 202a mounted thereon. As shown in FIG. 6, element terminal 226 and element connection portion 535 of transistor 117 are aligned and fixed.

[0255] A pressing tool 501 made of an insulating material is fixed to the aligned portion by screwing it into the fixing hole 514a. Examples of the insulating material of the pressing tool 501 include phenol, bakelite, etc. The pressing tool 501 electrically connects the element terminal 226 and the element connection part 535. As shown in FIG. 7, a fixing screw 221 is attached to a fixing hole 512 in the center of the land 515, and the connection wiring 211 is electrically connected.

[0256] In Fig. 7, a heat pipe 223 is attached to the pressing tool 501 in Fig. 6. The heat pipe 223 can transfer or dissipate heat generated in the element terminal 226 of the electric element 117. The heat pipe 223 is attached and fixed in the fixing hole 514.

[0257] The controller circuit 111 changes the test current Id, the constant current Ic, the gate voltage Vg, and the collector terminal-emitter terminal voltage Vce to set the test conditions and perform the test so that the temperature or temperature information Tj of the transistor 117 to be tested becomes a predetermined value.

[0258] When the temperature information Tj changes or changes to a predetermined value, it is determined that the transistor 117 has deteriorated or its characteristics have changed, and the test of the transistor 117 is stopped or the control method is changed.

[0259] For example, the change in temperature information Tj is used to determine or evaluate the change in characteristics of the transistor 117. Also, the change in characteristics, reliability, and lifespan of the transistor 117 are evaluated based on the time it takes for the voltage Vce to reach a predetermined voltage, the time it takes for the transistor 117 to break down, and the like.

[0260] In the semiconductor testing method of the present invention, the external conditions are changed in response to the deterioration or characteristic changes of transistor 117. For example, when transistor 117 generates heat, the temperature of heating / cooling plate 134 is lowered, or the current flowing through transistor 117 is reduced. This prevents the deterioration and characteristic changes of transistor 117 from progressing, and as a result, the lifespan of transistor 117 is extended. Therefore, the lifespan and reliability characteristics of transistor 117 for a given set of conditions can be quantitatively measured and determined.

[0261] The temperature of the transistor 117 is maintained at a specified or predetermined value by heating or cooling the circulating water of the heating and cooling plate 134. The temperature of the transistor etc. is periodically changed in accordance with the test conditions, and is cooled or heated at a constant level.

[0262] Temperature information Tj of the test transistor is measured, and the heating / cooling plate 134 is controlled so as to maintain the measured temperature information Tj at a constant value. Dry air is injected into the test chamber or tank to prevent condensation on the heating / cooling plate 134. Alternatively, dry air is blown onto the sample (device under test) 117.

[0263] The heating and cooling plate 134 keeps the temperature of the equipment, etc. constant by circulating the heat medium while managing the liquid temperature of the water or heat medium. The heating and cooling plate 134 is often used mainly for cooling, but it can also heat as well as cool. The heating and cooling plate 134 is configured to be able to control various temperatures.

[0264] 1 and 2, the partition wall 214a has a hole formed therein into which the conductive plate 204 is inserted. The partition wall 214b has a hole formed therein into which the fork plug 205 is inserted.

[0265] As shown in Figures 3 and 4, the upper part of the thermostatic chamber (housing) 523 has a power supply device 132 that supplies a test current and a test voltage to the semiconductor element 117, and a controller circuit 111 that controls the semiconductor element 117 etc. or sets test conditions.

[0266] The controller circuit 111 changes the current Id, the gate voltage Vg, and the voltage Vce to set test conditions and execute the test so that the temperature information Tj of the semiconductor element 117 becomes a predetermined value. The controller circuit 111 controls a power supply 132, which supplies a test voltage or current to the semiconductor device 117 under test.

[0267] When the temperature information Tj changes at a predetermined rate or reaches a predetermined value, it is determined that the semiconductor element 117 has deteriorated or its characteristics have changed, and the test of the semiconductor module 117 and the semiconductor element 117 is stopped or the test method or control method is changed.

[0268] The temperature of the semiconductor element 117 is maintained at a specified or predetermined value by heating or cooling the circulating water of the heating and cooling plate 134. The temperature of the semiconductor element, etc. is periodically changed in response to the test conditions, and the element is cooled or heated at a constant value. Temperature information Tj of the semiconductor element 117 is measured, and the heating and cooling plate 134 is controlled so as to maintain the measured temperature information Tj at a constant value.

[0269] The electric element testing apparatus and electric element testing method of the present invention can accommodate a wide variety of semiconductor elements 117 and semiconductor modules 117 as shown in Fig. 22, for example. The semiconductor element 117 in Fig. 22 has a P electrode terminal, an O electrode terminal, and an N electrode terminal to which a large current is applied or output. Fig. 22 is a schematic view and an equivalent circuit diagram of a semiconductor element, Fig. 22(a1)(a2) shows a configuration having one transistor 117 and a diode Di.

[0270] 22(b1) and (b2) show a configuration having a transistor 117 (transistor 117m, transistor 117s) and a diode Di (diode Dim, diode Dis).

[0271] 22(c1) and (c2) show a configuration in which a test is performed by connecting a plurality of transistors together by connecting the terminals of a semiconductor element having a transistor 117 (transistor 117m or transistor 117s) and a diode Di (diode Dim or diode Dis).

[0272] 22(d1) and (d2) show a configuration having a transistor 117 (transistor 117m, transistor 117s) and a diode D (diode Ds, diode Dm) having a terminal independent of the terminal of the transistor.

[0273] Figures 22(e1) and (e2) show a configuration in which a test is performed by connecting multiple transistors together by connecting the terminals of a semiconductor element having a transistor 117 (transistor 117m or transistor 117s) and a diode D (diode Dm or diode Ds) having a terminal independent of the terminal of the transistor.

[0274] The test current Id to be passed through the transistor 117 is supplied by operating a power supply device 132. The power supply device 132 is controlled to be operated / non-operated (on / off) by a signal from a control circuit (controller) 111. Also, the current Id can be switched between output and non-output.

[0275] It goes without saying that the electrical element testing apparatus and electrical element testing method of the present invention can be applied to a semiconductor element 117 having multiple transistors in one package, as shown in Figures 22(b) and 22(d), and a semiconductor module 117 in which multiple transistor elements are connected, as shown in Figures 22(c) and 22(e).

[0276] The following description will be given on the assumption that the emitter terminal e of the transistor 117 is grounded. The gate terminal g of the transistor 117 is connected to the gate driver circuit 113.

[0277] The sample connection circuit 203 is connected to the transistor 117 via a connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminal g of the transistor 117 are arranged so as to have a short distance of 100 mm or less between them. If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise or the like is superimposed on the gate terminal g, causing the transistor 117 to malfunction.

[0278] Fig. 21 is a block diagram and an explanatory diagram showing the connection state of each element part such as the switch circuit 124 of the semiconductor test device of the present invention in Fig. 1, Fig. 2, etc. In Fig. 21, the switch circuit 124d, the switch circuit 124b, and the switch circuit 124c use the symbols for the switch circuits. The switch circuit 124 or the switch circuit 122 is mounted or disposed on a switch circuit board 201 such as a printed circuit board.

[0279] Any device that has a small resistance (on-resistance) when closed (on) can be used as the switch circuit 122 and the switch circuit 124. Examples of such devices include transistors, mechanical relays, phototransistors, photodiode switches, and photoMOS relays.

[0280] It is particularly preferable to use a power MOSFET for the switch circuit 122 and the switch circuit 124. The MOSFET is preferable because the voltage (Vsd) between the channels is small. A heat sink (not shown) is attached to the switch circuit 122 and the switch circuit 124 for heat dissipation.

[0281] When the switch circuit 124d is turned on (closed), the power supply wiring 212b and the power supply wiring 212c are short-circuited, and a short-circuit current Im' flows. By turning on the switch circuit 124d, the charge between the channel terminals of the transistor 117m can be discharged. In addition, the charge between the output terminals of the power supply device 132b can be discharged.

[0282] The switch circuit 124e is a switch circuit that separates the power supply device 132b from the test device. By closing the switch circuit 124e, the output current Id of the power supply device 132b can be supplied to the transistor 117m. By turning off (opening) the switch circuit 124e, it can be separated from the semiconductor test device of the present invention.

[0283] By turning on the switch circuit 124d, the charge between the power supply wiring 212b and the power supply wiring 212c can be discharged. Also, the emitter terminal and the collector terminal of the transistor 117m are short-circuited, so that the accumulated charge can be discharged. A current Im is generated by discharging the charge.

[0284] When the switch circuit 124c is turned on (closed), the power supply wiring 212b and the power supply wiring 212c are short-circuited. By turning on the switch circuit 124c, the charge between the power supply wiring 212b and the power supply wiring 212c can be discharged. Also, the emitter terminal and the collector terminal of the transistor 117s are short-circuited, and the charged charge can be discharged. A current Im is generated by discharging the charge.

[0285] When the switch circuit 124b is turned on (closed), the power supply wiring 212c and the power supply wiring 212a are short-circuited, and a short-circuit current Im flows. By turning on the switch circuit 124b, the charge between the power supply wiring 212c and the power supply wiring 212a can be discharged. In addition, the terminals of the semiconductor module 117 (between the collector terminal of the transistor 117s and the emitter terminal of the transistor 117m) are short-circuited, and the accumulated charge can be discharged.

[0286] When starting a test of the semiconductor module 117, the switch circuit 124 is turned on (closed) and then the test is started. When ending the test of the semiconductor module 117, the switch circuit 124 is also turned on (closed). During the test of the semiconductor module 117, the switch circuit 124 is turned off (open).

[0287] The on / off state of the switch circuit 124 is linked to the contact switch 529. When the contact switch 529 is not in the on state, the switch circuit 124 maintains the on state, and the test current Id is not applied to the transistor 117 to be tested. It is also linked to the on / off state of the power supply device 132 (power supply device 132a, power supply device 132b).

[0288] It is interlocked with the open / closed state of door 527. When door 527 is open, switch circuits 124b and 124d maintain the on state, so that the output voltage (current) of power supply device 132 does not supply current to transistor 117 to be tested. Interlocking is performed by detection using contact switch 529 or the like. Alternatively, output switches such as switch circuit 124e are maintained in the open state.

[0289] By turning on the switch circuit 122b, the test current Id output by the power supply device 132a is supplied to the transistor 117s. By turning on the switch circuit 122a, the test current Id output by the power supply device 132b is supplied to the transistor 117m. Alternatively, by turning on the switch circuit 124c and the switch circuit 122a, the test current Id output by the power supply device 132a is supplied to the transistor 117m.

[0290] The switch circuit 122 and the switch circuit 124 are mounted or formed on a switch circuit board 201. When the switch circuit 122 (switch SWa) is turned on, a constant current Id outputted by the power supply circuit 121 of the power supply device 132 is supplied to the test circuit.

[0291] The switch circuit 124 is formed on the switch circuit board 201 as shown in Fig. 63. The switch circuit 124b is disposed on the switch circuit board 201b. The conductor plates 204c and 204d are attached to the switch circuit board 201b. The fork plug 205e is inserted from the opening 216 of the partition wall 214. The fork plug 205d is electrically connected to the conductor plate 204c. The fork plug 205d is electrically connected to the conductor plate 204d.

[0292] The switch circuit 124d is disposed on a switch circuit board 201d. A conductor plate 204a and a conductor plate 204b are attached to the switch circuit board 201d. The fork plug 205b is electrically connected to the conductor plate 204b.

[0293] The switch circuit 124c is disposed on a switch circuit board 201c. A conductor plate 204e and a conductor plate 204df are attached to the switch circuit board 201c. The fork plug 205a is electrically connected to the conductor plate 204e.

[0294] When the switch circuit 124b is turned on, the output of the power supply device 132 is short-circuited, and the test current Id output by the power supply device 132 flows to the ground. When the switch circuit 124a is turned on, the charge between the terminals of the semiconductor element component 117 to be tested and the charge of the power supply device 132 are discharged. The occurrence of surge voltages, transient currents, and the like is suppressed.

[0295] When the switch circuit 124b is turned on, the output of the power supply device 132a is short-circuited, and the electric charge of the power supply device 132a is discharged. When the switch circuits 124c and 124d are turned on at the same time, the output of the power supply device 132a is also short-circuited, and the electric charge of the power supply device 132a is discharged. In the case of this configuration or method, the switch circuit 124b is not necessary.

[0296] It is also effective to shift the timing at which the switch circuits 124c and 124d are turned on. For example, the switch circuit 124c turns on before the switch circuit 124d, causing a short circuit between the channels of the transistor 117s. Next, the switch circuit 124d turns on, causing a short circuit between the channels of the transistor 117m. Alternatively, the switch circuit 124d turns on before the switch circuit 124c, causing a short circuit between the channels of the transistor 117m. Next, the switch circuit 124c turns on, causing a short circuit between the channels of the transistor 117s. By sequentially shorting the channels, the occurrence of a surge voltage or the like occurring in the semiconductor element component 117 is further suppressed. When the switch circuit 124b is turned on, the current Id output by the power supply device 132a can be supplied to the semiconductor module 117 as the test current Id. The fork plug 205 is inserted through an opening 216 in the partition wall 214 and is electrically connected to the switch circuit board 201 .

[0297] 63, the switch circuit 124 is mounted on a switch circuit board 201. The switch circuit 124 is connected to a conductor plate 204 (metal plate, conductive plate).

[0298] Conductive plate 204 is, for example, a copper plate with a thickness of 5 mm and a width of 50 mm. Its length is the width of the circuit board plus the width required to connect fork plug 205. Conductive plate 204 is not limited to being plate-shaped. Any shape may be used as long as fork plug 205 and conductive plate 204 can be electrically connected. For example, conductive plate 204 may be rod-shaped or spherical.

[0299] The switch circuit 122 and the switch circuit 124 are disposed between two conductive plates 204. The conductive plates 204 are mounted or disposed on the switch circuit board 201.

[0300] Each terminal of the switch circuit 124 is connected to a conductive plate 204. The conductive plate (copper bar) 204 is, for example, a plate made of copper with a thickness of 5 mm and a width of 50 mm. The length of the conductive plate 204 is, for example, 250 mm. Fig. 23(a) is an external view of a package of a semiconductor element, and Fig. 23(b) is an equivalent circuit diagram of the semiconductor element.

[0301] 23(a), a hole 702 for attaching a heat sink is formed in the package of a semiconductor element (electrical element) 117. The semiconductor element 117 is placed or attached to an element mounting base 500.

[0302] 23, terminal 226a is the collector (C), element terminal 226b is the emitter (E), terminal 226c is the cathode (K), and element terminal 226g is the gate (G).

[0303] 24, a plurality of semiconductor elements (electrical elements) 117 are disposed on an element mounting base 500. A shield plate 705 is disposed between the semiconductor elements (electrical elements) 117. In addition, a shield plate 705 is disposed between the collector terminal (C) 226a and the emitter terminal (E) 226b.

[0304] 25, the shield plate 705 has a configuration in which an insulating sheet (or insulating film, insulating plate) 708 is disposed or formed on the surface of a conductor sheet (or conductor foil, conductor plate, conductive plate) 709 made of copper, iron or aluminum. The conductor sheet 709 is connected to a predetermined potential or ground potential and has a fixed potential.

[0305] The shield plate 705 may be a metal plate (conductor plate) or a metal film (conductor sheet). In that case, it is preferable to place or form an insulator or an insulating sheet between the shield plate 705 and the pressing tool 501, etc., so that the shield plate 705 does not come into contact with conductive objects such as the pressing tool 501.

[0306] The semiconductor testing device (power cycle testing device) of the present invention performs testing by supplying a high current or high voltage to the test object. When a high current flows or a high voltage is applied, noise is generated, making the test state unstable. Furthermore, the semiconductor testing device (power cycle testing device) malfunctions due to noise.

[0307] The location where high voltage or high current noise is likely to occur is between the collector terminal (C) and the emitter terminal (E). High current flows through the collector terminal (C) and the emitter terminal (E).

[0308] Noise also has a large effect between adjacent semiconductor elements. When multiple semiconductor elements are arranged and tested as shown in Fig. 24, it is rare that all of the semiconductor elements 117 perform the same operation at the same time. As an example, the test current Id is supplied to the multiple semiconductor elements 117 in sequence. For example, the test current Id flows through the semiconductor element 117a, the semiconductor element 117b, the semiconductor element 117c, the semiconductor element 117d, the semiconductor element 117e, the semiconductor element 117f, the semiconductor element 117a,...

[0309] When multiple semiconductor elements 117 are arranged as shown in FIG. 24 and a test is performed, if a test current is supplied to semiconductor element 117c and controlled to be on and off, noise is applied to adjacent semiconductor elements 117d and 117b, which is likely to cause malfunctions in adjacent semiconductor elements 117d and 117b.

[0310] 24, a shield plate 705a is disposed between the collector terminal (C) and emitter terminal (E) of a semiconductor element 117. A shield plate 705b is disposed between adjacent semiconductor elements 117.

[0311] The present invention can prevent malfunction of the semiconductor element 117 adjacent to the semiconductor element 117 being tested by supplying a test current or the like, by disposing the shield plate 705 between adjacent semiconductor elements 117. By setting the adjacent shield plates 705 at different potentials, malfunction and noise can be further prevented. As shown in FIG. 27, it is also effective to form projections and recesses on element mounting base 500 and place semiconductor element 117 on the projections and recesses.

[0312] Element mounting base 500 is formed or constructed by cutting a recess in a plate-like base. In the embodiment of Fig. 27, semiconductor elements 117a and 117c are arranged on the protrusions, and semiconductor element 117b is arranged in the recess.

[0313] By arranging the semiconductor elements 117 on the convex and concave portions, the distance between adjacent semiconductor elements 117 can be made longer compared to when the semiconductor elements 117 are arranged on a flat surface. The longer the distance, the less the effect of radiation noise on the adjacent semiconductor elements.

[0314] Semiconductor element 117b is placed in the recessed portion of element mounting base 500, and semiconductor elements 117a and 117c are placed in the protruding portion. Compared to a state in which semiconductor elements 117a, 117b, and 117c are placed on a flat surface, the distance between semiconductor elements 117a and 117b, and between semiconductor elements 117b and 117c can be made longer. Furthermore, by disposing a shield plate 705 between the collector terminal (C) and the emitter terminal (E), malfunction of each semiconductor element 117 does not occur.

[0315] An insulating plate 704c is disposed between the gate terminal (G) and the cathode terminal (K) of the semiconductor element 117. An insulating plate 704b is disposed between the cathode terminal (K) and the emitter terminal (E) of the semiconductor element 117. There is a narrow gap between the terminals 226 of the semiconductor element 117. By disposing an insulating plate 704 between the terminals 226, contact can be prevented.

[0316] 25, the conductive sheet 709b of the shield plate 705c is fixed at a predetermined potential, the conductive sheet 709a of the shield plate 705a is fixed at a predetermined potential, and the conductive sheet 709b of the shield plate 705b is fixed at a predetermined potential.

[0317] A pin connector 707 is inserted into the cathode terminal (K) and the gate terminal (G), and the connection wiring 211 and the element terminal 226 are connected as shown in Fig. 26. In Fig. 26, the gate terminal (G) 226d and the connection wiring 211b are connected, and the cathode terminal (K) 226c and the connection wiring 211a are connected.

[0318] Fig. 28 is an explanatory diagram of a mounting portion for mounting semiconductor elements 117 in the semiconductor testing apparatus of the present invention. As an example, Fig. 28 shows six semiconductor elements 117 to be tested arranged on device stand 503, and knurled nuts (screws) 714 for mounting device stand 503 and the like to slide plate 505 of the apparatus.

[0319] A knurled nut (screw) 714b attaches the device stand 503 to the slide plate 505. A knurled nut 714a attaches the terminal board 502 and the device stand 503 to the slide plate 505. The device stand 503 may be attached directly to the slide plate 505 without using the device stand 503. A heat dissipation fin 538 is arranged on the back surface of the device stand 503 to dissipate heat generated from the semiconductor element 117 as necessary.

[0320] A shield plate 705a or a shield plate 705b is disposed between the collector terminal 226a and the emitter terminal 226b of the semiconductor element 117. In addition, a pressing tool support (a pressing tool fixing support) is disposed between the shield plates 705.

[0321] Fig. 29 is a configuration diagram in which a pressing tool 501 is arranged in Fig. 28. The pressing tool 501 is used to establish electrical connection with the element terminal 226 of the semiconductor element (semiconductor module) 117. The pressing tool 501 is formed or composed of a metal or a conductive material.

[0322] 1 and the like, the semiconductor module 117 to be tested is composed of an upper transistor 117s and a lower transistor 117m. The emitter terminal (E) of the upper transistor 117s and the collector terminal (C) of the lower transistor 117m are electrically connected. The collector terminal (C) of the upper transistor 117s is connected to the voltage output of the power supply device 132, and the emitter terminal (E) of the lower transistor 117m is connected to ground or the ground terminal of the power supply device 132.

[0323] At least the surface of the pressing tool 501 that comes into contact with the element terminal 226 is made of or formed of a metal or conductive material.

[0324] 26, the pressing tool 501b presses the emitter terminal (E) of the upper transistor 117s and the collector terminal (C) of the lower transistor 117m together to electrically connect them. The pressing tool 501a presses the emitter terminal (E) of the lower transistor 117m together to electrically connect them. The pressing tool 501c presses the collector (C) of the upper transistor 117s together to electrically connect them. It goes without saying that the above matters and configurations regarding the pressing tool 501 can also be applied to the embodiments shown in Figs. 6, 7, 8, etc.

[0325] 26 and 30, the power supply wiring 212 is connected to the pressing tool 501c via a cable connector 712a. The power supply wiring 212 is connected to the pressing tool 501b via a cable connector 712b. The power supply wiring 212 is connected to the pressing tool 501a via a cable connector 712c. Therefore, the cable connector and the pressing tool 501a are connected, and the pressing tool 501a and the emitter terminal (E) of the lower transistor 117m are electrically connected.

[0326] In addition, the cable connector is connected to a pressing tool 501b, and the pressing tool 501b is electrically connected to the emitter terminal (E) of the upper transistor 117s and the collector terminal (C) of the lower transistor 117m. In addition, the cable connector is connected to a pressing tool 501c, and the pressing tool 501c is electrically connected to the collector terminal (C) of the upper transistor 117c.

[0327] 26, a pin connector 707a is connected to the cathode terminal (K) 211a and the gate terminal (G) 226d of the upper transistor 117a. A connection wiring 211a and a connection wiring 211b are connected to the pin connector 707a. The connection wiring 211a is electrically connected to the cathode terminal (K) of the upper transistor 117a, and the connection wiring 211b is electrically connected to the gate terminal (G) of the upper transistor 117a.

[0328] A pin connector 707a is connected to the cathode terminal (K) 211a and the gate terminal (G) 226d of the lower transistor 117b. A connection wiring 211a and a connection wiring 211b are connected to the pin connector 707b. The connection wiring 211a is electrically connected to the cathode terminal (K) of the lower transistor 117b, and the connection wiring 211b is electrically connected to the gate terminal (G) of the lower transistor 117b.

[0329] 29 is an explanatory diagram of a state in which pressing tool 501 is inserted into pressing tool support (pressing tool fixing support) 717 and fixed by fastener 737, in contrast to the explanatory diagram of FIG. 28. Pressing tool 501 is fastened by fastener 737, and pressing tool 501 is pressed against element terminal 226. Pressing tool 501 against element terminal 226 makes electrical connection with semiconductor element 117.

[0330] 30 and 31 are explanatory diagrams of the state in which the power supply wiring 212 is attached to the pressing tool 501. In Fig. 31, Fig. 31(a) is a configuration diagram of the mounting portion of the semiconductor element 117 as viewed from above. Fig. 31(b) is a configuration diagram of the mounting portion of the semiconductor element 117 as viewed from the front side. Fig. 31(c) is a configuration diagram of the mounting portion of the semiconductor element 117 as viewed from the side. The pressing tool 501 and the power supply wiring 212 are connected by a cable connector 712 and a screw (not shown) or the like.

[0331] 39 and 40, a fixing plate 802 is disposed on the upper surface of the pressing tool 501 (pressing tool 501a, pressing tool 501b, pressing tool 501c). The fixing plate 802 is made of or formed of an insulating material. Examples of the insulating material include ceramic, bakelite, and engineering plastic.

[0332] The fixing plate 802 is attached to spacer bases 801 (spacer base 801a, spacer base 801b) arranged on both ends of the group of pressing tools 501 with fixing screws 759. The height of the spacer bases 801 (spacer base 801a, spacer base 801b) is approximately the same as the height of the pressing tools 501.

[0333] The fixing plate 802 is arranged using the spacer base 801 (spacer base 801a, spacer base 801b) as a spacer or a support column. The fixing plate has screw holes (not shown). Pressure adjusters 757 and 758 are attached to the screw holes.

[0334] Pressure adjusters 757 and 758 are bolt-shaped. By rotating the head of the pressure adjuster to the right, the tip moves downward, and the tip of pressure adjuster 758 presses pressing tool 501. Pressing presses pressing tool 501, increasing the adhesion between pressing tool 501 and element terminal 226, and maintaining a good electrical connection. In addition, the position of pressing tool 501 can be fixed by pressure adjuster 758.

[0335] By rotating the head of pressure adjuster 758 to the left, the tip moves upward and the tip of pressure adjuster 758 separates from pressing tool 501. By the tip of pressure adjuster 758 separating from pressing tool 501, pressing tool 501 can be removed.

[0336] In Fig. 39, the lead pin 760 is connected to the element terminal 226. The lead pin 760a is connected to the element terminal 226a (collector (C) terminal). The lead pin 760b is connected to the element terminal 226b (emitter (E) terminal). The lead pin 760c is connected to the element terminal 226c (cathode (K) terminal). The lead pin 760a is connected to the element terminal 226a (gate (G) terminal).

[0337] The signal waveform of the element terminal 226a (collector (C) terminal) can be observed through the lead-out pin 760a. The signal waveform of the element terminal 226b (emitter (E) terminal) can be observed through the lead-out pin 760b. The signal waveform of the element terminal 226c (cathode (K) terminal) can be observed through the lead-out pin 760c. The signal waveform of the element terminal 226a (gate (G) terminal) can be observed through the lead-out pin 760a.

[0338] 30 is an embodiment in which the power supply wiring 212 is drawn out in a vertical direction relative to the device stand 503. In the embodiments in Figs. 39 and 40, as shown in the drawings, the power supply wiring 212 is drawn out in a horizontal direction relative to the device stand 503.

[0339] Screw holes are formed in the pressing tools 501a and 501c. A cable connector 712 is placed in the screw hole, and the cable connector 712 and the pressing tool 501c are connected and fixed by a screw.

[0340] 29 and 30 are configured to connect the element terminals 226 of the semiconductor element 117 by pressure contact with the pressing tool 501. Fig. 32 is a configuration diagram of an embodiment in which the element terminals 226 of the semiconductor element 117 are electrically connected by contact fittings 721. The connection portion that connects to the element terminal 226 is composed of a contact metal fitting 721, a connection metal fitting 722, a pressure screw 728, a connection pin 724, and the like.

[0341] The element terminal 226a or 226b is inserted between the contact metal fitting 721 and the connection metal fitting 722. By turning the pressure screw 728, the contact metal fitting 721 is pressed down and the element terminal 226 is sandwiched (clamped) between the contact metal fitting 721 and the connection metal fitting 722.

[0342] The contact surfaces (contact surfaces of the contact fittings 721 and the connection fittings 722) that come into contact with the element terminals 226 are knurled to form protrusions. A plurality of protrusions are formed over the entire surface of each contact surface. The number of protrusions is 25 to 100 [pieces / cm 2 ], and 50 to 75 [ 2 By contacting via the respective multiple protrusions, the current flows in a dispersed manner without concentrating at a specific location, and heat generation is suppressed.

[0343] A screw hole 710 is formed in the connecting fitting 722, and the cable connector 712 and the connecting fitting 722 are fixed with a screw 725 inserted into the screw hole. A connection pin 724 is inserted into the connecting fitting 722, and the connection pin 724 is fixed with a set screw 723. The voltage applied to the element terminal 226 can be monitored by the connection pin 724.

[0344] 33 is an explanatory diagram illustrating the connection state with the element terminal 226. A metal shaft 711 is formed on the contact fitting 721, and the metal shaft 711 is inserted into a shaft hole 713 of the connecting fitting 722. The position of the contact fitting 721 is adjusted by the insertion amount of the pressure screw 728. By pressing down the pressure screw 728, the distance between the connecting fitting 722 and the contact fitting 721 is narrowed, and by pressing up the pressure screw 728, the distance between the connecting fitting 722 and the contact fitting 721 is widened. The position of the metal shaft 711 is approximately fixed by the shaft hole 713.

[0345] In the configuration shown in FIG. 26, pin connectors 707 are directly inserted into the cathode terminal 226c and the gate terminal 226d, the cathode terminal 226c is connected to the connection wiring 211a, and the gate terminal 226d is connected to the connection wiring 211b.

[0346] 26, the distance between the gate terminal 226d, the cathode terminal 226c, and the emitter terminal 226b is narrower than the distance between the emitter terminal 226b and the collector terminal 226a. Therefore, when the semiconductor element 117 is misaligned, the connections between the gate terminal 226d, the cathode terminal 226c, and the emitter terminal 226b are prone to contact failure. 34 and 35 are configuration diagrams of the connection metal pins 781 for making contact with the gate terminal 226d, the cathode terminal 226c, and the emitter terminal 226b.

[0347] The separate fixing plate 782 is formed or configured from a resin material such as plastic, or an insulating material. The separate fixing plate 782 has portions formed or configured at portions A and B (the surface opposite portion A) into which the connecting metal pin 781 is inserted.

[0348] A connecting metal pin 781a is inserted into part A of the separated fixed plate 782. A connecting metal pin 781b is inserted into part B of the separated fixed plate 782. The lower surface of the connecting metal pin 781a contacts and is electrically connected to the element terminal (cathode terminal) 226c. The lower surface of the connecting metal pin 781b contacts and is electrically connected to the element terminal (gate terminal) 226d.

[0349] 34, a connecting metal pin 781a is disposed at part A of the separate fixed plate 782, and a connecting metal pin 781b is disposed at part B of the separate fixed plate 782 and they are integrated together. Part D of the connecting metal pin 781 contacts the underside of part C of the separate fixed plate 782, and the connecting metal pin 781 is pressed against the element terminal 226 to make contact. FIG. 26 shows a configuration in which pin connectors 707 are directly inserted into the cathode terminal 226c and the gate terminal 226d, and the element terminal 226 and the connection wiring 211 are connected.

[0350] 34, the pin of the connection fitting pin 781 is arranged on the upper side. The pin connector 707 is inserted into the pin portion of the connection fitting pin 781a and the pin portion of the connection fitting pin 781b arranged facing upward, and the connection fitting pin 781a is connected to the connection wiring 211a, and the connection fitting pin 781b is connected to the connection wiring 211b.

[0351] Figure 36 is an explanatory diagram showing from above the state in which a connecting metal pin 781a is arranged at part A of the separate fixing plate 782, and a connecting metal pin 781b is arranged at part B of the separate fixing plate 782, and is integrated and contacts the element terminal 226d and the element terminal 226c.

[0352] 34, the pin portion of the connecting metal pin 781a faces upward, so that it can be easily attached to and detached from the connector 707. The signal applied to the element terminal 226 can be monitored by the connecting metal pin 781.

[0353] 37 and 38 are configuration diagrams and explanatory diagrams in which separate fixing plate 782 described with reference to Figs. 34 and 35 is arranged on terminal board 502. Terminal board 502 is positioned by fixing plate pins 784. Element terminals 226 of semiconductor element 117 on terminal board 502 are arranged. Fixing plate supports 756 are attached to screw holes 783 of separate fixing plate 782. Spacer base 801 is fitted into fixing plate pins 784.

[0354] The connection metal pin 781b can be electrically connected to the element terminal 226d (gate terminal (G)), and the connection metal pin 781a can be electrically connected to the element terminal 226c (cathode terminal (K)).

[0355] 26, the emitter terminal (E) of the lower transistor 117m is connected by a pressing tool 501a. The collector terminal (C) of the lower transistor 117m and the emitter terminal (E) of the upper transistor 117s are connected by a pressing tool 501b. The collector terminal (C) of the upper transistor 117s is connected by a pressing tool 501c.

[0356] FIG. 41 is an explanatory diagram of an embodiment in which a device stand 503 is attached to a slide plate 505 and a semiconductor element (electrical element) 117 to be tested is arranged (mounted) on the device stand 503.

[0357] In the embodiment of Fig. 41, two slide plates 505 are attached to the frame 751 as shown in Fig. 42. However, the slide plates 505 may be configured so that three or more slide plates can be attached as shown in Fig. 3 and Fig. 4. Also, as shown in Fig. 3 and Fig. 14, the slide plates may be configured so that they can be arranged in multiple stages.

[0358] A handle 518 is attached to the slide plate 505. By using the handle 518, the slide plate 505 can be moved from the front of the frame 751 to the back (partition wall 214a). In addition, by using the handle 518, the slide plate 505 can be moved from the back of the frame 751 (partition wall 214a) to the front. By moving the slide plate 505 to the front, test samples such as transistors 117 can be easily removed and mounted or placed. The handle 518 may have any configuration so long as it is configured to allow the slide plate 505 or the like to be pulled out or inserted. Door 527 is opened, and slide plate 505 is inserted into rail guide 507. Slide plate 505 is moved along rail guide 507.

[0359] By pushing in the slide plate 505, the contact switch 529 comes into contact with or is connected to the connection detection unit 738. When the contact switch 529 is pressed, for example, it detects that the slide plate 505 has been properly inserted into the frame 751, and the confirmation lamp 530 turns on.

[0360] The confirmation lamp 530a is linked to the left sliding plate 505, and the confirmation lamp 530b is linked to the left sliding plate 505. In addition, the position of the sliding plate 505 and the contact switch 529 are linked to the confirmation lamp 530c of the housing main body as shown in FIG. The slide plate 505, rail guide 507, cam follower 506, and the configuration and method using these have been explained with reference to Figs. 1 to 21 and so on, and therefore explanation thereof will be omitted.

[0361] The on and off states of power supply device 132, switch circuit 124, and switch circuit 122 are linked to contact switch 529. When contact switch 529 is not in the on state, switch circuit 124 maintains the on state, and test current Id is not applied to transistor 117 to be tested. Furthermore, power supply device 132 does not output a test current (test voltage). Furthermore, switch circuit 122 is not turned on. Contact switch 529 is linked to the on and off states of power supply device 132.

[0362] The contact switch 529 is linked to the open / closed state of the door 527. When the door 527 is open, the switch circuit 124 maintains the on state, and no current is supplied to the transistor 117 to be tested. The link is detected by the contact switch 529 or the like. In addition, the power supply device 132 does not output the test current Id.

[0363] The processing circuit 524 is disposed on the control circuit board 519. The processing circuit 524m applies a signal to the transistor 117m to control and process the transistor 117m. The processing circuit 524s applies a signal to the transistor 117s to control and process the transistor 117s. The processing circuit 524 is mainly composed of a sample connection circuit 203 and a device control circuit 209 .

[0364] As an example, the voltages output by the gate driver circuit 113 are an on-voltage V2, an on-voltage V1, and an off-voltage Voff (0V). The off-voltage Voff (0V) can also be set to a negative voltage (Vn) below 0V. The gate driver circuit 113 can output voltages of three or more levels. In addition, it can be changed in one cycle as shown in Figs. 54 to 59.

[0365] A signal cable connector 712 is disposed on a front cover 753 of the slide plate 505. A gate signal voltage Vg of the semiconductor element 117 and the like are supplied to the signal connector 712. The signal supplied to the signal connector 712 is applied to a control circuit section (substrate) 519 via a signal cable 732 as shown in FIG. 46. The signal from the control circuit section (substrate) 519 is applied to the semiconductor element 117 via a connection wiring 211. In addition, the connection pin 724 and the lead pin 760 are connected to the control circuit section (substrate) 519 via the connection wiring 211, and are output to a device outside the apparatus via the signal cable connector 712.

[0366] The power supply wiring 212 connected to the pressing tool 501 is held in position by a cable spacer base 821, or the power supply wiring 212 is positioned, as shown in Figure 46, and passes through the back surface of the slide plate 505 and is connected to the power cable mounting terminal 755.

[0367] Frame 751 is made of a precision sheet metal frame. After a bending process of the part that will become the frame and the U-shaped part, a stud bolt is attached to one side of the frame. The U-shaped part with a weld nut is TIG welded at two points. Since it is a trapezoid with some angles that differ, the reinforcing parts at the four corners have slightly different shapes. To prevent mistakes in installing the reinforcing parts, the frame is fixed using a jig and each part is spot welded.

[0368] Frame fixing legs 752 are attached to frame 751. Frame 751 is positioned, installed, and fixed in chamber interior 526 of thermostatic chamber (constant temperature device, constant temperature and humidity device, etc.) 523 by frame fixing legs 752. The temperature, humidity, etc. of chamber interior 526 of thermostatic chamber 523 are set and operated by operation panel 762.

[0369] Figures 43 and 44 are perspective views of the frame 751. Figure 43 is a perspective view of the frame 751 seen from diagonally above, and Figure 44 is a perspective view of the frame 751 seen from the back side.

[0370] In the present invention, the device can be positioned and installed within chamber 526 of thermostatic chamber 523 by adjusting frame fixing legs 752 of frame frame 751. Power supply wiring 212 from power supply device 132, connection wiring 211, etc. are connected via external connection hole 791 of thermostatic chamber (housing) 523.

[0371] 44 and 46, an opening 537 is formed in the slide plate 505 at a portion where the semiconductor element 117 and the like are mounted. A fan 227 is disposed or installed at the portion where the opening 537 is located. The fan 227 cools or heats the semiconductor element 117 by rotating.

[0372] 47 and 48 are explanatory diagrams for explaining signal control and signal connection states of the present invention. The controller circuit 111 controls the processing circuit 524. As explained in Figs. 1, 2 and 21, the processing circuit 524 outputs the gate signal voltage Vg and the constant current Ic, and also acquires the Vi voltage of the transistor 117. These signals are transmitted via a signal cable connector 754. The signal cable connector 754 is connected to the control circuit section (board) 519 by a signal cable 732.

[0373] Matters relating to the signal cable connector 754, the device stand 503, the control circuit section (substrate) 519, the connection wiring 211, etc., and the connections therebetween are also described in the embodiments of FIGS. 1 to 10, etc., and so description thereof will be omitted. Moreover, it goes without saying that the embodiments described with reference to FIGS. 6 to 15 and the like can be applied to the arrangement, connection, and configuration of device stand 503 and semiconductor element 117.

[0374] The controller circuit 111 controls the power supply device 132. It also controls the switch circuit board 201. The test current Id output by the power supply device 132 is supplied to a power cable attachment terminal 755 by the power supply device 132 and the switch circuit board 201. The power cable attachment terminal 755 and the electric element 117 are connected by a power supply wiring 212. If an abnormality occurs in the processing circuit 524, the power supply device 132, etc., the controller circuit 111 turns on the confirmation lamp 530. It also issues an alarm.

[0375] 41, 42, 45, and 46, power cable attachment terminal 755 is arranged and power cable attachment terminal 755 is connected to power wiring 212, but this is not limited to this. For example, as shown in Figures 3 to 2, it goes without saying that the configuration and method may be such that connection to power wiring 212 is made using configurations, connections, arrangements, etc. of fork connector 528, socket connector 509, conductor plate 204, conductor plate group 517, etc.

[0376] As shown in FIG. 48, the controller circuit 111 controls a fan control unit 761 via a control interface circuit (control I / F) 763 to operate and control the stopping of the fan 227 and the strength of its rotation speed.

[0377] The controller circuit 111 has the function of measuring or acquiring the temperature of the element terminal 226 from a thermocouple or temperature sensor 510 attached to the element terminal 226 or in its vicinity, and controlling the test to stop or interrupt the test or issue an alarm if the temperature is above a predetermined level.

[0378] Water leakage sensors (not shown) are arranged around the device stand 503. When condensation or the like occurs on the semiconductor element 117 mounted on the device stand 503, the condensation sensor (not shown) is activated and is configured to stop the semiconductor element testing apparatus or issue an alarm. The inside of the tank 526 is configured so that dry air (dry gas, gas with a low dew point temperature) is injected.

[0379] 49 is an explanatory diagram regarding a method of controlling the fan 727. The controller circuit 111 detects the speed and stop of the fan 727. The rotation speed of the fan 727 is acquired, and a stoppage judgment of the fan and a change in the air volume are performed.

[0380] The output of the fan control unit 761 of the fan 727 is connected to a control interface (I / F) 763, and the fan control unit 761 application counts the pulses and calculates the fan rotation speed. Since the fan control unit 761 outputs two cycles of a square wave per rotation of the fan, the fan control unit 761 counts the number of pulses per unit time (1 second) to calculate the rotation speed. If the fan stops during a test, an alarm is generated from an alarm device 764 if a test is in progress.

[0381] Changes in air volume during the test are detected using changes in fan speed. As shown in FIG. 49, the upper and lower upper limit change rates for the fan speed at the start of the test are registered in advance on the fan control unit 761 or the settings screen of the application. The rotation speeds of Fan 1 and Fan 2 at the start of the test are set as reference values, and the upper and lower limit values ​​of the fan speed during the test are determined from the set upper and lower upper limit change rates. The determined upper and lower limit values ​​are displayed in the upper and lower limit value of the fan speed on the fan control unit 761 screen.

[0382] The fan control unit 761 monitors the fan rotation speed during the test, and if the measured rotation speed exceeds the upper or lower limit, it determines that there has been a change in the air volume and issues an alarm from the alarm 764. The control software (application) monitors this alarm and stops the test. The fan rotation speed at the start of the test is measured. This is the reference value. Upper limit of fan speed = Fan speed at the start of the test + (Fan speed at the start of the test x Upper limit of fan speed change rate / 100) Using the fan speed at the start of the test as the reference, calculate the lower limit of the fan speed during the test using the following formula. Fan speed lower limit = Fan speed at the start of the test - (Fan speed at the start of the test x Fan speed change rate upper / lower / 100) If the current measured value of the fan rotation speed exceeds the upper or lower limit, the fan control unit 761 generates an alarm.

[0383] The PC application (control software) monitors this alarm and stops the test. The PC application (control software) records the fan rotation speed during the test in a log file as debug information.

[0384] When starting up the test equipment, make sure that the semiconductor element (electrical element) to be tested is attached, and when the semiconductor element (electrical element) is not attached, make sure that the measurement terminal is not shorted to the main body. Make sure that the breaker on the thermostatic chamber side is turned on. If the breaker for the thermostatic chamber 523 is not turned on, the device will not start up. As shown in FIG. 49, the semiconductor device testing apparatus of the present invention sets the following test times. "Measurement delay": The waiting time from when the power is turned off until the temperature is measured (except for temperature-sensing diode measurements). "Power Delay": The delay time from when the previous device is powered off until the next device (such as the semiconductor element 117 to be tested) is powered on. "Power ON time": Power-on time. "Power OFF Time": The time it takes for the device to power up again after being powered off. If the time is outside the above range or if there is an abnormality, the application turns on confirmation lamp 530 and issues an alarm from alarm 764. The test device of the present invention has a function of automatically checking connections to confirm whether or not the mounted semiconductor element (electrical element) is connected correctly.

[0385] 51 is an explanatory diagram and a timing chart of the testing method for an electric element of the present invention. During periods tn1 and tn2, the resistance value Vr of the variable resistance circuit 125 connected to the gate terminal of the transistor 117 is set to 0 (Ω) or the lowest resistance value. A constant current Ic from a constant current circuit 118 is caused to flow through the transistor 117. The constant current Ic flows in the direction from the collector terminal c to the emitter terminal, and a voltage Vce is generated between the channel of the transistor 117, and the voltage Vce is measured and used as the voltage Vi. Temperature information Tj is obtained from the voltage Vi.

[0386] The semiconductor element (electrical element) testing device of the present invention has mechanical members such as pressing tool 501, connecting metal pin 781, connecting metal 722, etc., and can achieve a good electrical connection state with element terminal 226. Also, by controlling the on / off of switch circuit 122 and switch circuit 124, voltages V2, V1, etc. can be applied well to semiconductor element 117, inrush current and surge voltage can be suppressed, and good evaluation, testing, and inspection can be achieved.

[0387] The gate driver circuit 113 generates a predetermined voltage and applies it as a gate voltage Vg to the transistor 117. The predetermined voltage can be varied, and the voltage can be changed periodically.

[0388] By applying a predetermined gate voltage and measuring the relationship between the channel-to-channel voltage Vce and the temperature of the transistor 117, the temperature (temperature information Tj) of the transistor 117 can be determined from the channel-to-channel voltage Vce (or the terminal voltage of the diode Di).

[0389] As shown in Fig. 51(a), the on / off cycle of the transistor 117 is tcycle, and the on time is ton. The voltages output by the gate driver circuit 113 are an on voltage V2, an on voltage V1, and an off voltage Voff(V0). The gate driver circuit 113 can output voltages of three or more levels. V2>V1>Voff(V0)>Vn. In the embodiment of FIG. 51, the gate driver circuit 113 generates on-voltages (V2, V1) of two potential levels and applies them to the gate terminal of the transistor 117.

[0390] An on-voltage V2 is applied to the gate terminal for a period tn2, and then an on-voltage V1 is applied to the gate terminal for a period ton, etc. Next, the on-voltage V2 is applied for a period tn1. When the on-voltage V2 is being applied, the transistor 117 is strongly on (the resistance between the channels is smaller) compared to when the on-voltage V1 is applied. Therefore, by changing the magnitude of the on-voltage, the resistance between the channels of the transistor 117 can be changed.

[0391] The gate driver circuit 113 of the present invention can output voltages of four or more levels, and can also output triangular waves, sine waves, etc. that change with time.

[0392] The transistor 117 is operated / non-operated (on / off) by the Vg signal voltage output from the gate driver circuit 113. If a test current Id is supplied from the power supply device 132a while the transistor 117 is on, the test current Id flows between the channels of the transistor 117.

[0393] 1 and 2, when the switch circuit 122a connected to the power supply device 132b is turned on, a test current Id is applied to the transistor 117s. When the switch circuit 122b connected to the power supply device 132a is turned on, a test current Id is applied to the transistor 117m.

[0394] A short circuit 137 is disposed or connected between the gate terminal and the emitter terminal of the transistor 117. The short circuit 137 is exemplified by an analog switch. Alternatively, it may be a short pin or a short socket.

[0395] By turning on (closing) the short circuit 137s arranged between the gate terminal g and the emitter terminal e of the transistor 117s, the transistor 117s is turned off when the transistor 117 is an N-channel transistor, and a diode Dis is connected between the terminals of the transistor 117s.

[0396] By turning on (closing) a short circuit 137m disposed between the gate terminal and the emitter terminal of the transistor 117m, the transistor 117s is turned off when the transistor 117 is an N-channel transistor. The transistor 117m is connected to a diode Dim.

[0397] 1, 2, and 21, the short circuit 137 is formed or disposed between the gate (base) terminal and the emitter terminal of the transistor 117. The present invention is not limited to this. The short circuit 137 may be formed or disposed between the gate (base) terminal and the collector terminal of the transistor 117. When the short circuit 137 between the gate (base) terminal and the collector terminal of the transistor 117 is turned on, if the transistor 117 is an N-channel transistor, the transistor 117 becomes diode-connected.

[0398] By forming or placing a short circuit 137 between the gate (base) terminal and the collector terminal of the transistor 117 and turning the short circuit 137 on, the transistor 117 can be diode-connected.

[0399] The short circuit 137 may be formed or disposed both between the gate (base) terminal and the collector terminal of the transistor 117 and between the gate (base) terminal and the emitter terminal of the transistor 117 .

[0400] The test current Id in Fig. 51(b) is implemented by turning on (closing) the switch circuit 122. By turning on the switch circuit 122b, the test current Id is supplied to the transistor 117s. As shown in Fig. 51(b), by turning on the switch circuit 122a, the test current Id is supplied to the transistor 117m. When a test current flows through the transistor 117, the channel voltage (Vce) of the transistor 117 changes, as shown in FIG. 51(c).

[0401] When the test current Id flows, heat is generated in the transistor 117. By measuring the channel-to-channel voltage (Vce) of the transistor 117 during the period tn1, the temperature of the transistor 117 (temperature information Tj) can be obtained.

[0402] After the test current Id is supplied to the transistor 117, during a period tn1 during which the test current Id is not supplied, the constant current Ic is supplied from the constant current circuit 118 to the transistor 117. The supply of the test current Id causes the transistor 117 to heat up. The heat generation state correlates with a change in the characteristics or a deterioration state of the transistor 117.

[0403] The temperature (temperature information Tj) of the transistor 117 can be obtained by passing a constant current Ic through the transistor 117 and measuring the inter-terminal voltage Vi of the transistor 117. The inter-terminal voltage (Vce) Vi is obtained by a buffer amplifier (buffer circuit) 116.

[0404] Since the temperature information Tj is a value related to the temperature of the transistor 117, it changes from T1 to T2 when the constant current Id flows, as shown in Fig. 51(d), and decreases from T2 when the constant current Id stops.

[0405] Therefore, for accurate temperature measurement, it is preferable to measure the terminal voltage of the transistor 117 as soon as possible after the constant current Id is stopped. The terminal voltage Vi is acquired by the buffer amplifier 116. It is preferable to measure the output voltage of the buffer amplifier 116 within 1 msec after the constant current Id is stopped.

[0406] 51(f), the periods during which the constant current Ic flows and the voltage Vi is measured are exemplified as periods a, b, c, and d. The voltage Vi is obtained during period a within period A during which the constant current Ic flows. The voltage Vi is obtained during period b within period B during which the constant current Ic flows. The voltage Vi is obtained during period c within period C while the constant current Ic is flowing. The voltage Vi is obtained during period d within period D while the constant current Ic is flowing. Periods A and D are periods during which a voltage V2 is applied to the gate terminal g. Periods B and C are periods during which a voltage V1 is applied to the gate terminal g.

[0407] After the test current Id is applied, a constant current Ic is supplied to the transistor 117 during period D while the V2 voltage is applied to the gate terminal g, and the voltage Vi is measured. It is also effective to supply the constant current Ic to the transistor 117 and measure the voltage Vi during period A while the V2 voltage is applied to the gate terminal g before the test current Id is applied. By comparing the voltage Vi before and after the supply of the test current Id and measuring and evaluating the change in the voltage Vi, the change in the characteristic of the transistor 117 can be quantitatively measured.

[0408] It is also effective to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117 during a period C in which the V1 voltage is applied to the gate terminal g immediately after the test current Id is stopped after the application of the test current Id.

[0409] During period C, a voltage V1 is applied to the gate terminal g, and a constant current Ic is supplied to acquire the voltage Vi across the channel terminals of the transistor 117. During period D, a voltage V2 is applied to the gate terminal g, and a constant current Ic is supplied to acquire the voltage Vi across the channel terminals of the transistor 117. By comparing the voltage Vi measured during period c with the voltage Vi measured during period d and measuring and evaluating the change in the voltage Vi, the change in the characteristic of the transistor 117 can be quantitatively measured.

[0410] During period A when the V2 voltage is applied to the gate terminal g before the test current Id is applied, it is also effective to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117. Also, during period B when the V1 voltage is applied to the gate terminal g before the test current Id is applied, it is also effective to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117.

[0411] By comparing the voltage Vi measured in the period a with the voltage Vi measured in the period b and measuring and evaluating the change in the voltage Vi, the change in the characteristic of the transistor 117 can be quantitatively measured.

[0412] It is also effective to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117 during a period B in which the voltage V1 is applied to the gate terminal g before the application of the test current Id, and to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117 during a period C in which the voltage V1 is applied to the gate terminal g after the application of the test current Id.

[0413] By comparing the voltage Vi measured in the period b with the voltage Vi measured in the period c and measuring and evaluating the change in the voltage Vi, the change in the characteristics of the transistor 117 can be quantitatively measured.

[0414] It is also effective to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117 during a period A during which the voltage V2 is applied to the gate terminal g before the application of the test current Id, and to apply a constant current Ic to the transistor 117 and measure the voltage Vi of the transistor 117 during a period D during which the voltage V2 is applied to the gate terminal g after the application of the test current Id.

[0415] By comparing the voltage Vi measured in the period a with the voltage Vi measured in the period d and measuring and evaluating the change in the voltage Vi, the change in the characteristic of the transistor 117 can be quantitatively measured.

[0416] 51, the timing for obtaining the temperature (temperature information Tj) of the transistor 117 is a period during which the test current Id is not supplied to the transistor 117 and an on-voltage (V2 voltage or V1 voltage) is applied to the gate terminal g of the transistor 117. The constant current Ic is applied to the transistor 117 during any one of periods A, B, C, and D, and the terminal-to-terminal voltage of the transistor 117 is measured. Furthermore, it is preferable to measure the terminal-to-terminal voltage during a plurality of periods for comparison with the temperature information measured or obtained during periods tn2 and tn1 (or to use it as a baseline). It goes without saying that the measurement of the voltage Vi is not limited to every cycle (t cycle), and the voltage Vi may be measured over a number of cycles.

[0417] The temperature information Tj is sent to the control circuit 111 (controller circuit 111), and the control circuit 111 (controller circuit 111) tests the transistor 117 (semiconductor element component 117) in accordance with the temperature information Tj.

[0418] FIG. 51 is an explanatory diagram (timing chart) of signals applied to the transistor 117 etc., or operation signals of the transistor 117 etc., in the electric element testing apparatus of the present invention.

[0419] In the embodiments of FIGS. 51 to 62, for ease of explanation or understanding, the power supply device 132b shown in FIG. 21 is not present, or the switch circuit 124e is always off.

[0420] In addition, the switch circuit 124c and the switch circuit 122a are illustrated as two switch circuits, but the present invention is not limited to this. The switch circuit 124c and the switch circuit 122a may be configured as one switch circuit (for example, the switch circuit 124x). One terminal of the switch circuit 124x is connected to the power supply device 132a, and the other terminal of the switch circuit 124x is connected to the collector terminal of the transistor 117m.

[0421] In the embodiment of Figure 51, an off voltage is applied to the gate terminal (base terminal) of transistor 117s to maintain transistor 117s in an off state, and as shown in Figure 51(a), an on or off voltage is applied to the gate terminal (base terminal) of transistor 117m to turn transistor 117m on and off, thereby evaluating or testing transistor 117m.

[0422] The supply of the test current Id to the transistor 117m is performed by turning on the switch circuit 124c and the switch circuit 122a, and the discharge between the channels of the transistor 117m is performed by the switch circuit 124d or the switch circuit 124b.

[0423] When the transistor 117s is evaluated or tested independently, an off voltage V0 is applied to the gate terminal of the transistor 117m. The transistor 117m is constantly maintained in an off state. The gate signal voltage of FIG. 51(a) is applied to the gate terminal of the transistor 117s. The test current Id is supplied to the transistor 117s by turning on the switch circuits 122b, 122a, and 124d. Discharge between the channels of the transistor 117s is performed by turning on the switch circuit 124c or 124b.

[0424] When the V0 voltage (Voff) is applied to the gate terminal (base terminal) of the transistor 117, the transistor 117 is in the off state. When the V1 voltage or V2 voltage is applied to the gate terminal (base terminal) of the transistor 117, the transistor 117 is in the on state. The period during which the V0 voltage is applied is toff, and the period during which the on voltage is applied is ton. One cycle period is tcycle. The gate signal voltage Vg is a signal waveform applied to the gate terminals g (upper transistor Vgs, lower transistor Vgm) of the transistors 117 and the like.

[0425] Vdata is data that the controller circuit 111 applies to the DA converter circuit 128. The voltage output by the DA converter circuit 128 is determined, varied, or set by Vdata.

[0426] The gate signal voltage Vg is composed of voltages (Voff(V0), Vn) that turn off the transistor 117, and voltages V1 and V2 that turn on the transistor 117. The V1 voltage is the voltage Von that turns on the transistor 117. The V2 voltage is a voltage that is applied to the gate terminal g of the transistor 117 when a constant current Ic is supplied or applied to the transistor 117 or the diode Di, or when the channel-to-channel voltage Vi of the transistor 117 is measured.

[0427] In the embodiment of the present invention, V2>V1, but this is not limited to this. When testing transistors of the same type, the V2 voltage is made common (the same) and the test is performed. By making the V2 voltage a fixed (constant value) voltage, the terminal voltage of each transistor 117 when a constant current Ic is applied can be made consistent during measurement, and individual variation data for the transistors 117 can be obtained or evaluated. The V1 voltage and Voff voltage may be adjusted for each transistor, taking into account the off-leak current, etc.

[0428] In the embodiment of Fig. 51, the V2 voltage application period is divided into two periods, tn1 and tn2. A constant current Ic is applied during periods A and D of periods tn1, tn2, etc., and the channel of transistor 117 (between the collector and emitter or between the cathode and anode of diode Di) is measured. In addition, a constant current Ic is supplied during periods B and C of Fig. 51(f), and the voltage Vi is measured to obtain temperature information Tj.

[0429] Switch circuit 124 or switch circuit 122 is mounted or disposed on switch circuit board 201. By turning on switch circuit 124 and switch circuit 122, switch circuit 124 and switch circuit 124 are closed. By turning off switch circuit 124 and switch circuit 122, switch circuit 124 and switch circuit 124 are opened.

[0430] 2 and 21 show the connection states of the switch circuits 122 and 124. When the switch circuit 122b is turned on, the test current Id is supplied to the transistor 117s. When the switch circuit 124c and the switch circuit 122a are turned on, the test current Id is supplied to the transistor 117m.

[0431] When the test current Id is supplied to the upper transistor 117s, the switch circuit 122b, the switch circuit 122a, and the switch circuit 124d are turned on. An off voltage is applied to the gate terminal of the lower transistor 117m.

[0432] When the test current Id is supplied only to the lower transistor 117m, the switch circuit 124c and the switch circuit 122a are turned on, and an off voltage is applied to the gate terminal of the upper transistor 117s.

[0433] When the test current Id is supplied to both the upper transistor 117s and the lower transistor 117m at the same time, the switch circuit 122b is turned on, and an off voltage is applied to the gate terminals of the upper transistor 117s and the lower transistor 117m.

[0434] When the switch circuit 124b is turned on, the terminals of the power supply device 132a are short-circuited, and the collector terminal of the upper transistor 117s and the emitter terminal of the lower transistor 117m are short-circuited, discharging the electric charge. A short-circuit current Im flows through the switch circuit 124b.

[0435] When the switch circuit 124c is turned on, the collector terminal and the emitter terminal of the upper transistor 117s are shorted, and the charge between the channel of the upper transistor 117s is discharged. When the switch circuit 124d is turned on, the collector terminal and the emitter terminal of the upper transistor 117m are shorted, and the charge between the channel of the upper transistor 117m is discharged.

[0436] 51(e) illustrates the operation of the switch circuit 122 or the switch circuit 124. When the test current Id is supplied to both the lower transistor 117m and the upper transistor 117s, the switch circuit 122b is turned on. When the test current Id is supplied to the lower transistor 117m, the switch circuit 124c and the switch circuit 122a are turned on.

[0437] In the present invention, the pressing tool 501 and the like provide good electrical connection with the element terminal 226. Therefore, heat is not generated in the element terminal 226 when the test current Id and the constant current Ic are applied or supplied, and good testing can be performed. In addition, the generation of surge voltage and inrush current can be suppressed. In addition, the applied signal and the like can be monitored by the lead pin 760 and the connection metal pin 781, and the gate signal voltage and the like can be applied well.

[0438] The constant current Ic of the present invention is supplied to the transistor 117 etc. at least one of A, B, C, and D as shown in FIG. 51(f), and the voltage Vi between the channel of the transistor 117 etc. is measured.

[0439] Periods A and B are periods during the cycle period (tcycle) before the test current Id is supplied (before application) to the transistor 117. Periods C and D are periods during the cycle period (tcycle) after the test current Id is supplied (after application) to the transistor 117.

[0440] 51(f), the period A is the period tn2 of the voltage Vg, during which the voltage V2 is applied. The period B is the period during which the voltage V1 is applied as the voltage Vg, and the test current Id is not supplied.

[0441] Period D is the period tn1 of the gate signal voltage Vg, during which voltage V2 is applied. Period C is the period during which voltage V1 is applied as the gate signal voltage Vg and before the test current Id is supplied.

[0442] As shown in Figure 51(f), a constant current Ic is supplied to transistor 117 etc. at at least one point during periods A, B, C, and D, and as shown in Figure 51(g), a voltage Vi between the channel etc. of transistor 117 is measured or obtained at at least one point during periods a, b, c, and d.

[0443] As shown in Fig. 51(g), the voltage Vi between the channels of transistor 117m (transistor 117s) or between the terminals of diode Di (diode Di is connected to the channel of transistor 117) is measured or acquired during the period A during which constant current Ic is applied. In Fig. 51(g), period a is within the range of period A in Fig. 51(f).

[0444] In addition, during periods A, B, C, and D, at least one point is supplied (applied) to the diodes Ds and Dm shown in FIG. 22(d) and FIG. 22(e), the terminal voltages Vi of the diodes Ds and Dm are measured, and the temperature information Tj

[0445] Similarly, the voltage Vi between the channels of the transistor 117 or between the terminals of the diode Di is measured or obtained during the period B during which the constant current Ic is applied. In Fig. 51(g), the period b is a period within the range of the period B in Fig. 51(f).

[0446] Also, during the period c during which the constant current Ic is applied, the voltage Vi between the channels of the transistor 117 or between the terminals of the diode Di is measured or acquired. In Fig. 51(g), the period c is within the range of the period C in Fig. 51(f).

[0447] Also, during the period d during which the constant current Ic is applied, the voltage Vi between the channels of the transistor 117 or between the terminals of the diode Di is measured or acquired. In Fig. 51(g), the period d is within the range of the period D in Fig. 51(f).

[0448] When the V1 voltage or the V2 voltage is applied to the gate terminal g of the transistor 117, the transistor 117 is turned on. In the embodiment of the present invention shown in Fig. 51, the constant current Ic is explained as being supplied in the forward direction between the channels of the transistor 117. In the case of a MOS transistor, current flows in both directions. In a power cycle test in which a test current Id is supplied to the transistor 117, the supply of the test current Id causes the transistor 117 to deteriorate.

[0449] In tests, the parts of the transistor that deteriorate are often the junctions within the transistor 117. The semiconductor itself rarely deteriorates, but the junctions (bonding, die bonding, etc.) of the transistor 117 deteriorate, causing the resistance value of the junctions to increase. As the resistance value increases, the channel-to-channel voltage Vce increases, generating heat and raising the temperature of the transistor 117.

[0450] When a semiconductor deteriorates, it is often the deterioration of the gate oxide film (insulating film) of the transistor 117. When the gate oxide film deteriorates, the oxide film (insulating film) is short-circuited and the voltage Vce drops. Alternatively, the transistor 117 is turned off, no current flows through the transistor 117, and the voltage Vce rises to the maximum value of the power supply voltage.

[0451] As shown in Fig. 51(b), when a test current Id is applied to the transistor 117, the transistor 117 generates heat, and as a result of the heat generation, the temperature information Tj changes (the voltage Vi changes) as shown in Fig. 51(d) due to the heat generation of the channels, etc. Furthermore, when the test current Id is stopped, the temperature of the channels, etc. rises due to heat dissipation, and the temperature information Tj changes. As an example, the temperature information Tj is equivalent to the channel-to-channel voltage.

[0452] A test current Id is supplied to the transistor 117, and as the deterioration of the transistor progresses, heat generation increases. The heat generation is indicated by temperature information Tj or correlates with temperature. The temperature information Tj correlates with (depends on) the channel voltage of the transistor.

[0453] At the start of the test, the temperature information Tj varies between the minimum temperature T1 and the maximum temperature T2. When the test applies stress to the transistor 117, the Vce voltage of the transistor 117 changes, and the temperature information Tj usually changes in the direction of increasing. The temperature information Tj is, for example, the channel-to-channel voltage Vi of the transistor 117.

[0454] 51(d), the minimum temperature rises above temperature T1, and the maximum temperature approaches temperature information T2. ​​As transistor 117 deteriorates, the temperature becomes higher and the rate of rise becomes faster. In the method for testing a semiconductor device (electrical device) of the present invention, the test is terminated under any of the following conditions. When the temperature information Tj is outside the specified range. When the channel voltage Vce falls outside the specified voltage range. If the thermal resistance is outside the specified range.

[0455] It is preferable to measure the deterioration of the transistor 117 by supplying a test current Id to the transistor 117 and measuring the inter-terminal voltage Vi around the time when the test current Id is stopped, that is, during the period C or D in FIG.

[0456] Period C is immediately after the test current Id is stopped, and the amount of heat generated by transistor 117 is maintained. Therefore, by measuring the V1 voltage during period c and observing or evaluating the Vi voltage during period c, it is possible to test or evaluate transistor 117 properly.

[0457] The period D is a period during which the test current Id is stopped and the V2 voltage of the period tn1 is applied. The amount of heat generated by the transistor 117 is maintained, a V2 voltage higher than the V1 voltage is applied, the channel-to-channel resistance of the transistor 117 is reduced, and the V2 voltage is fixed as a steady voltage. Therefore, by measuring the V1 voltage during the period d and observing or evaluating the Vi voltage during the period d, a satisfactory test or evaluation of the transistor 117 can be achieved.

[0458] In Fig. 51, the tn1 period and the tn2 period can be variably set and adjusted. Also, the V2 voltage can be variably set. Also, in Fig. 51(e), the switch circuit 122 and the switch circuit 124 can be turned on and off to test or evaluate the transistor 117m and the transistor 117s independently.

[0459] In addition, it is effective to apply a constant current Ic and measure the channel-to-channel voltage (Vce, Vi) of the transistor 117 in both the period C and the period D. In the period C, the voltage V1 is applied to the gate terminal (base terminal) of the transistor 117. In the period D, the voltage V2 is applied to the gate terminal (base terminal) of the transistor 117.

[0460] By acquiring both the channel-to-channel voltage of transistor 117 when voltage V1 is applied and the channel-to-channel voltage of transistor 117 when voltage V2 is applied, the deterioration state, deterioration change rate, or operating state of transistor 117 can be quantitatively compared and evaluated.

[0461] The channel-to-channel voltage of the transistor 117 measured when the V1 voltage is applied and the channel-to-channel voltage of the transistor 117 measured when the V2 voltage is applied are obtained every cycle (t cycle) or every multiple cycles (t cycle), and the change or the rate of change is measured and evaluated. The above items can be similarly applied to other embodiments of the present invention.

[0462] It is also useful to measure the channel-to-channel voltage of transistor 117 during period A, and to measure the channel-to-channel voltage of transistor 117 during period D. Period A is before test current Id is applied (supplied) to transistor 117, and voltage V2 is applied. Transistor 117 dissipates heat and is cooled.

[0463] In period D, the same voltage V2 is applied after the test current Id is applied to the transistor 117. The transistor 117 hardly dissipates heat. By acquiring the channel-to-channel voltages in periods A and D, the deterioration state or operating state of the transistor 117 can be quantitatively compared and evaluated.

[0464] It is also effective to measure the channel-to-channel voltage of transistor 117 during period B, and to measure the channel-to-channel voltage of transistor 117 during period C. Period B is before the test current Id is applied (before it is supplied) to transistor 117, and voltage V1 is applied.

[0465] In period C, a voltage V1 is applied after the test current Id is applied (supplied) to the transistor 117. By acquiring the channel-to-channel voltage Vi in periods B and C, the deterioration state, change ratio, change speed, and / or operating state of the transistor 117 can be quantitatively compared and evaluated.

[0466] It is also effective to measure the channel-to-channel voltage of transistor 117 during period C, and measure the channel-to-channel voltage of transistor 117 during period D. Period C is the state immediately after the application of test current Id to transistor 117 is stopped, and voltage V1 is applied.

[0467] In period D, the test current Id is applied to the transistor 117 and then stopped, and voltage V2 is applied. By acquiring the channel-to-channel voltages in periods C and D, the deterioration state or operating state of the transistor 117 can be quantitatively compared and evaluated.

[0468] As described above, by applying a constant current Ic at multiple locations (periods) in one cycle (t cycle) or multiple cycles (t cycles) and measuring or acquiring the inter-channel voltage or rate of change of the transistor 117, etc., it is possible to perform good evaluation, quantitative evaluation, and testing of semiconductor elements such as the transistor 117.

[0469] In addition, by applying different voltages to the gate terminal in each measurement, good results can be obtained. It goes without saying that the above items can be applied to other embodiments of the present invention. Also, the present invention can be combined with other embodiments. In the embodiment of FIG. 51, periods (tn2 period, tn1 period) during which the V2 voltage is applied to two points in a cycle (tcycle) are set. The embodiment described in FIG. 51 can also be applied to other embodiments such as FIG.

[0470] Fig. 52 shows an embodiment in which a period (tn1 period) during which the V2 voltage is applied to one point in a cycle (tcycle) is set. Temperature information Tj is obtained during period D as shown in Fig. 52(d). Also, as necessary, the Vi voltage may be measured during periods C and D to obtain temperature information Tj, similar to the embodiment of Fig. 51.

[0471] 52(a), during the period when the V0 voltage is applied, the transistor 117 is in the off state, and during the period when the V1 voltage or the V2 voltage is applied, the transistor 117 is in the on state.

[0472] As shown in Fig. 51(a), the embodiment of Fig. 51 is an embodiment in which there is a period during which the V2 voltage is applied to two points. In Fig. 52, the application period of the V2 voltage is one point during the period tn1.

[0473] It should be noted that the change from voltage V1 to voltage V2 (t5) does not need to be a step change, and for example, the voltage may be smoothly changed from voltage V1 to voltage V2 from t4 to t6.

[0474] The test current Id is supplied to the transistor 117m (transistor 117s) by turning on the switch circuit 124c and the switch circuit 122a. The charge between the channels of the transistor 117m is discharged by turning on the switch circuit 124a or the switch circuit 124b.

[0475] 21, by turning on switch circuit 124b, both terminals of power supply device 132a (between the output terminal and a terminal such as ground) can be short-circuited. By turning on switch circuit 124d, both terminals of power supply device 132b (between the output terminal and a terminal such as ground) can be short-circuited.

[0476] 21, by turning on switch circuit 124b, the charge between the terminals of transistor 117s and transistor 117m can be discharged. Also, by turning on switch circuit 124c, both terminals of transistor 117s are short-circuited, and the charge can be discharged. By turning on switch circuit 124d, both terminals of transistor 117m are short-circuited, and the charge can be discharged.

[0477] The switch circuit 124b is turned on before the switch circuit 122a is turned on and a test current is supplied to the transistor 117m. When the switch circuit 124d is turned on, the charge between the channel of the transistor 117m is discharged. When the switch circuit 124b is turned on, both terminals (the output terminal and the setting terminal, etc.) of the power supply device 132a are short-circuited, and the charge between both terminals of the power supply device is discharged. Also, a short-circuit current Im flows.

[0478] After the switch circuit 124b is turned on, the switch circuits 122a and the like are turned on after a period tb2 has elapsed, and the test current Id is supplied to the transistor 117m. After the switch circuit 122a is turned on, the switch circuit 124b is turned off after a period tb1 has elapsed.

[0479] The time t1 when the switch circuit 122a changes from off to on is within the period (t0 to t2) when the switch circuit 124b is on. t1 can be variably set by the controller circuit 111 at tb1 and tb2. Alternatively, t1 can be adjusted.

[0480] When an on-voltage (V1 voltage, V2 voltage) is applied to the gate terminal of the transistor 117m, the transistor 117m turns on. Even if the transistor 117m turns on, the test current Id does not flow unless the switch circuit 122a is on and the switch circuit 124b is off. Therefore, after the switch circuit 124b turns off at t2, the test current Id flows.

[0481] Even if an on-voltage (V1 voltage or V2 voltage) is applied to the gate terminal of transistor 117m and transistor 117m is turned on, test current Id does not flow unless switch circuit 122a is turned on. Therefore, gate signal voltage Vg does not need to be set to V1 voltage at t0. It may be set to V1 voltage te time before. In other words, gate signal voltage Vg may be set to any voltage as long as it is set to any voltage before time t2 when switch circuit 124b is turned off. The time (timing) at which the gate signal voltage Vg changes from the V0 voltage to the V1 voltage can be set by the controller circuit 111 and can be made variable.

[0482] At time t0, the Vg voltage is set to the V1 voltage by Vdata. The V1 voltage is applied to the gate terminal of the transistor 117m (transistor 117s), and at t2 after a period tc, a current Id is supplied to the transistor 117m (transistor 117s). Next, the switch circuit 124b turns on during the period from t4 to t6, shorting the channel of the transistor 117 and discharging the charge.

[0483] At t5, the Vsg voltage becomes the V2 voltage due to Vdata, and the V2 voltage is applied to the gate terminal of the transistor 117, turning the transistor 117 strongly on (when V2 is a voltage higher than V1).

[0484] Before the switch circuit 122a is turned off, the switch circuit 124b is turned on. When the switch circuit 124b is turned on, the output terminals of the power supply device 132a are short-circuited, a short-circuit current Im flows, and the charge between the channels of the transistor 117 is discharged.

[0485] The switch circuit 124b is turned on at t4 and turned off at t6. The switch circuit 122a is controlled to change from the on state to the off state during the period from t4 to t6. The test current Id flows through the transistor 117 when the switch circuit 122a is in the on state and the switch circuit 124b is in the off state.

[0486] The switch circuit 124b turns on before ta2 when the switch circuit 122a turns from on to off. After the switch circuit 124a turns from on to off, the switch circuit 124b turns off after a period t1a.

[0487] During the period from t4 to t6, the switch circuit 122a is in the OFF state. During the period (D) from t4 to t6, the gate signal voltage changes from the V1 voltage to the V2 voltage. The V2 voltage lasts for a period tn1.

[0488] During a period tn1, a constant current Ic is applied to the transistor 117, and a voltage Vi between the channels of the transistor 117 is measured or acquired. As an example, the constant current Ic is applied (supplied) during a period tk from t6 to t7. The constant current Ic is output from a constant current circuit 118, and the magnitude of the constant current Ic can be set or changed by the controller circuit 111.

[0489] During the period when the constant current Ic is being applied, a voltage V2 is applied to the gate terminal g. During the period when the constant current Ic is being applied, a voltage Vi across the channel of the transistor 117 is measured. The voltage Vi is buffered by a buffer circuit 116 and output to a device control circuit 209 via a connector 208. The temperature measurement circuit 115 uses the voltage Vi to transfer data as temperature information Tj to a controller circuit 111. The controller circuit 111 stops, continues, changes settings, etc. of the semiconductor testing device based on the rate of change and change in the Tj data.

[0490] A constant current Ic is applied while a voltage that turns on the transistor 117, such as the V2 voltage, is applied. The constant current Ic flows between the channels, and a voltage is generated between the channels. The voltage generated between the channels changes according to the deterioration state of the transistor.

[0491] A constant current Ic for obtaining temperature information Tj is applied for a period tk to the transistor 117. The temperature measurement circuit 115 processes the temperature information Tj from the inter-terminal voltage Vi obtained during the application period of the constant current Ic.

[0492] The tf1 period is set to a period of 2 ms or less. Preferably, the tc period, the ta2 period, and the ta1 period are each set to a period of 1 ms or less. When the test current Id is applied, the transistor 117 generates heat and the temperature rises. The temperature rise due to heat generation occurs in response to a change in the characteristics of the transistor 117. Therefore, the deterioration state and characteristic changes of the transistor 117 can be grasped by acquiring or measuring the temperature of the transistor 117.

[0493] When the test current Id is stopped, the transistor 117 is cooled (heat is dissipated). Therefore, after the test current Id is stopped, it is necessary to apply a constant current Ic for a short period of time on the order of milliseconds to obtain temperature information Tj of the transistor 117 (it is necessary to measure the terminal voltage of the transistor 117).

[0494] The semiconductor testing device of the present invention can apply a constant current Ic and measure the inter-terminal voltage Vi within a short time of 2 ms after the test current Id is stopped, and obtain temperature information Tj and a characteristic curve equation. Therefore, since the temperature of the transistor 117 is maintained, the characteristic changes of the transistor 117 can be measured or obtained accurately and precisely.

[0495] 52, a load current Id is applied to the transistor 117, and after a period ta (ta1+ta2), a constant current Ic is applied to the transistor 117 to obtain temperature information. After the test current Id is stopped, a period ta2 is provided for applying the V2 voltage, and the V2 voltage is applied to the gate terminal g.

[0496] After the test current Id is stopped, a constant current Ic is applied for a period tk (period D) to obtain temperature information Tj within a period of 2 ms or less. The supply of the constant current Ic changes the Vi voltage as shown in FIG. 52(g).

[0497] 52, the V1 voltage is applied to supply the test current Id, and then the constant current Ic is supplied during the period in which the V2 voltage is applied, the inter-terminal voltage Vi is measured, and the temperature information Tj and the characteristic curve equation are obtained. The present invention is not limited to this.

[0498] 53 is an explanatory diagram of an embodiment in which temperature information Tj is obtained before and after application of current Id. As an example, the temperature information Tj is obtained by obtaining temperature information Tj in a state in which the transistor 117 is dissipating heat before application of current Id and a characteristic (curve) equation and temperature information Tj in a state in which the temperature rises after application of current Id.

[0499] By obtaining two pieces of temperature information Tj, that is, the temperature information Tj in the heat dissipation state and the temperature information Tj in the temperature rise state, the characteristic change and the deterioration state of the transistor 117 can be obtained with higher accuracy.

[0500] 53 is a timing chart of signals applied to the transistor 117 etc. The V2 voltage is applied before and after the test current Id is passed. While the V2 voltage is being applied, a constant current Ic is applied to the transistor 117, the inter-terminal voltage Vi is measured, and temperature information Tj is acquired or measured. Before applying the constant current Ic, the switch circuit 124b is turned on to discharge the electric charge between the channel of the transistor 117 (between the collector terminal and the emitter terminal).

[0501] During the period when the V0 voltage is applied, the transistor 117 is off. Also, as shown in Fig. 54(c), the off voltage is adjusted and set among voltages Vn lower than the V0 voltage.

[0502] In a period before t0, a voltage V2 due to Vdata is applied as Vg to the gate terminal of the transistor 117. During the period in which the voltage V2 is being applied, a constant current Ic is applied to the transistor 117 for a period te2, and the channel voltage Vi of the transistor is measured, as shown in FIG.

[0503] During the period before t0, the test current Id is not applied to the transistor 117. By applying the constant current Ic, it is possible to obtain the inter-terminal voltage Vi in a heat dissipating state (the test current Id is stopped at t4, and heat is dissipated until the next cycle). This inter-terminal voltage Vi also contains information on the deterioration state and characteristic changes of the transistor 117. Therefore, by comparing and understanding the changes in the inter-terminal voltage Vi during the load cycle test, useful information can be obtained.

[0504] At time t0, the Vg voltage is set to the V1 voltage by Vdata. The V1 voltage is applied to the gate terminal g of the transistor 117, and a current Id is supplied to the transistor 117 at t2 after a period tc (tb2+tb1). Next, the switch circuit 124b turns on during the period from t4 to t6, shorting the channel of the transistor 117 and discharging the charge.

[0505] At t5, the Vsg voltage becomes the V2 voltage due to Vdata, and the V2 voltage is applied to the gate terminal of transistor 117, turning transistor 117 strongly on. At t6, a constant current Ic is applied to transistor 117 for a period tk to obtain temperature information. From the inter-terminal voltage Vi obtained during the application period of the constant current Ic, the temperature measurement circuit 115 obtains and processes temperature information Tj (Figure 53(g)). This inter-terminal voltage Vi becomes the temperature information Tj of transistor 117 immediately after the test current Id is passed through.

[0506] 53(c), application of the test current Id during the period t2 to t4 causes the transistor 117 to generate heat and rise in temperature. The state of temperature rise of the transistor 117 changes depending on the characteristic change or characteristic degradation state of the transistor 117. The temperature rise due to heat generation occurs in response to the characteristic change state or characteristic state of the transistor 117. Therefore, by acquiring or measuring the temperature of the transistor 117, the deterioration state and characteristic changes of the transistor 117 can be grasped.

[0507] From temperature information Tj (terminal voltage Vi) before the test current Id is passed and temperature information Tj (terminal voltage Vi) after the test current Id is passed, it is possible to obtain the change state of the transistor 117 due to the application of the test current Id. Therefore, the characteristic change of the transistor 117 can be measured or obtained accurately and precisely.

[0508] 52 and 53 are timing charts showing application of a test current Id and a constant current Ic to the transistor 117. The load test and avalanche test are carried out by turning the transistor 117 on and off for tens of thousands of cycles or more.

[0509] In the embodiments of Figures 51 and 52, when supplying a test current Id to the transistor 117m, the switch circuit 122a is controlled to change from an off state to an on state while the switch circuit 124d or the switch circuit 124b that shorts the channel of the transistor 117m is on.

[0510] When the test current Id supplied to the transistor 117m is stopped, the switch circuit 122a is controlled to change from the ON to OFF state while the switch circuit 124d or the switch circuit 124b that shorts the channel of the transistor 117m is on.

[0511] The gate signal voltage Vg applied to the gate terminal (base terminal) of the transistor 117m becomes an on voltage before the switch circuit 122a is turned on, and an off voltage (V0) is applied after the switch circuit 124b or the switch circuit 124d is turned off.

[0512] The above matters are also applicable when testing transistor 117s. Transistors 117m and 117s are alternately selected to test or evaluate transistors 117m and 117s. Selection of transistors 117m and 117s is performed by controlling switch circuits 122, 124, etc. The control of switch circuits 122 and 124 is described in Figs. 1, 2, 21, etc.

[0513] In the embodiments of Figures 51 and 52, when supplying a test current Id to the transistor 117s, the switch circuit 122b is controlled to change from an off state to an on state while the switch circuit 124c, which shorts the channel of the transistor 117s, or the switch circuit 124b is on.

[0514] When the test current Id supplied to the transistor 117s is stopped, the switch circuit 122b is controlled to change from the ON to OFF state while the switch circuit 124c or the switch circuit 124b that shorts the channel of the transistor 117s is on.

[0515] The gate signal voltage Vg applied to the gate terminal (base terminal) of the transistor 117s becomes an on voltage before the switch circuit 122b turns on, and an off voltage (V0 to Vn) is applied after the switch circuit 124b or the switch circuit 124c turns off. 52 and 53 are embodiments in which the V1 voltage or the V2 voltage is a fixed value, but the present invention is not limited to this.

[0516] 54, during the periods (t1 to t2, t6 to t7) when the constant current circuit 118 supplies the constant current Ic to the transistor 117, the V2 voltage is applied to the gate terminal g, and the transistor 117 is set to a strong on state or a state in which the on resistance is small. Alternatively, by setting the voltage to V2, it is set so that measurement can be performed at a steady voltage. Alternatively, by changing the voltage V2, the inter-channel resistance of the transistor 117 is changed and set.

[0517] In one embodiment of the present invention, the relationship is V2>V1. The voltage V2 is a fixed value, and while V2 is applied to the gate terminal of the transistor 117, a constant current Ic is applied to the transistor 117 and the terminal (collector-emitter, source-drain) voltage of the transistor 117 is measured. Note that the constant current Ic may be supplied to the diode Di, diode Ds, or diode Dm, and the Vi voltage of the diode Di, etc. may be measured. As shown in FIG. 54(c), the V1 voltage can be varied or set in a direction that increases the voltage (direction b) or in a direction that decreases the voltage (direction a).

[0518] By changing the V1 voltage in the direction of the arrow b, a high voltage can be applied to the gate terminal g of the transistor 117. By acquiring the inter-terminal voltage Vi when the V1 voltage approaches the V2 voltage, the change in the characteristics of the transistor 117 can be quantitatively measured or evaluated.

[0519] By changing the V1 voltage in the direction of the arrow a, a low voltage can be applied to the gate terminal g of the transistor 117. By acquiring the inter-terminal voltage Vi when the V1 voltage approaches the V0 voltage, the change in the characteristics of the transistor 117 can be quantitatively measured or evaluated.

[0520] The off-voltage (V0) can be varied or set to a lower voltage (c) or a higher voltage (d). In particular, when the transistor 117 is made of silicon carbide (SiC), it is preferable to set the off-voltage to a voltage Vn lower than the voltage V0.

[0521] By changing the V0 voltage in the direction of the arrow c, a low voltage can be applied to the gate terminal g of the transistor 117. By acquiring the voltage between the resistive terminals of the resistive circuit 125 of the gate terminal when the V0 voltage is brought close to the Vn voltage, the leakage current and the change in the off characteristics of the transistor 117 can be quantitatively measured or evaluated.

[0522] The inter-terminal voltage of the Vr resistor of the variable resistance circuit 125 can be quantified by acquiring the measured voltage at the V2 voltage, the V1 voltage, and the inter-terminal voltage of the Vr resistor when the voltage is changed from V2 to V1, thereby quantifying the characteristic change and characteristic degradation of the transistor 117.

[0523] By changing the V0 voltage in the direction of the arrow d, a voltage higher than the off voltage can be applied to the gate terminal g of the transistor 117. By obtaining the voltage between the terminals of the Vr resistor when the V0 voltage is brought close to the V1 voltage, the leakage current and off characteristic changes of the transistor 117 can be quantitatively measured or evaluated. The leakage current, etc. can be obtained by measuring the voltage between the terminals of the Vr resistor.

[0524] In the present invention, the V1 voltage and the V0 voltage can be set individually for the transistor 117 to be tested, etc. By setting the V2 voltage as a common voltage for each transistor, the temperature information Tj can be compared and evaluated.

[0525] Needless to say, the above embodiment in which the V1 voltage, the V0 voltage, and the V2 voltage are changed or adjusted can be applied to other embodiments of the present invention. Also, it goes without saying that the measurement of the inter-terminal voltage of the Vr resistor connected to the gate terminal g when the V1 voltage, the V0 voltage, and the V2 voltage are changed or set, and the measurement of the inter-terminal voltage for one period or multiple periods can also be applied to other embodiments of the present invention.

[0526] As an aspect of the present invention, it is preferable that the change or setting of the V1 voltage or the V2 voltage in the directions a, b, c, and d shown in Figures 54 to 57 is performed based on the output data of the temperature sensor 510 or the output temperature of the temperature sensor 510. It is also preferable that this is performed based on the change or the rate of change of the Vi voltage of the transistor 117 to be tested.

[0527] The occurrence state of the surge voltage Vs and the inrush current Is differs depending on the voltages V2 and V1. Therefore, it is preferable to set and adjust the times and timings of t0, t1, t2 and t4, t5, and t6 in Figures 52 and 53. It is also preferable to be able to set and adjust the measurement timing of the temperature information Tj (terminal voltage Vi), and this ability to set and adjust is a feature.

[0528] In FIG. 54, t1 to t2 and t6 to t7 are periods for measuring (acquiring) the inter-terminal voltage Vi, which is the inter-channel voltage (voltage between terminals c and e) of transistor 117, and obtaining temperature information Tj (inter-terminal voltage Vi).

[0529] The inter-terminal voltage Vi does not need to be measured (acquired) during both periods t1 to t2 and t6 to t7, but may be measured only during the period t6 to t7. In that case, the V1 voltage may be applied to the gate terminal g during the period t1 to t2, instead of the V2 voltage. It goes without saying that the above-mentioned embodiment in which the V1 voltage, the V0 voltage, or the V2 voltage is changed or adjusted can be applied to other embodiments of the present invention.

[0530] FIG. 54 shows a method of applying a constant current Ic between the channels of a transistor 117 and obtaining a characteristic equation based on temperature information Tj (terminal voltage Vi) of the transistor 117 or a temperature change.

[0531] FIG. 55 is an explanatory diagram of an embodiment in which a constant current Ic is supplied or applied to a diode Di built into a transistor 117 (the transistor 117 and the diode are formed in the same process), or to a diode Di located in the vicinity, or to a parasitic diode Di of the transistor 117, a diode Ds, or a diode Dm, to obtain a terminal voltage Vi and temperature information Tj of the transistor 117 and the diode D.

[0532] In order to apply a constant current Ic to the diode D (Di, Ds, Dm), an off voltage (V0, Vn) is applied to the gate terminal g of the transistor 117. By turning off the transistor 117, the constant current Ic flows through the diode Di etc. Note that the following description will be mainly given using the diode Di as an example. In FIG. 55, similarly to FIG. 54, the V1 voltage can be varied or set in the a direction or the b direction.

[0533] The off voltage applied to the transistor is set to a Vn voltage (a voltage lower than V0) when the transistor 117 is an SiC (silicon carbide) transistor, and is set to 0 V when the transistor is an IGBT. The off voltage can be varied and set in the c direction and the d direction as shown in FIG.

[0534] The semiconductor testing apparatus or semiconductor element testing method of the present invention is configured so that the off-voltage supplied to transistor 117 can be changed according to the type of transistor 117 being tested.

[0535] While the off-voltages (V1 to V0 to Vn) are being applied, a constant current Ic is applied to measure the temperature of the transistor 117 (the inter-terminal voltage Vi is measured). During the period in which the off-voltages are being applied, a constant current Ic is made to flow through the diode Di.

[0536] In the case of the SiC transistor 117, by applying a voltage lower than the V0 voltage to the gate terminal g, the off state of the transistor 117 becomes stable, and the temperature information Tj can be stably measured. In addition, noise is less likely to be introduced when measuring the temperature information Tj, and the measurement accuracy of the temperature information Tj (terminal voltage Vi) is improved.

[0537] When the constant current Ic is made to flow through the diode Di, the switch circuit 122 b and the switch circuit 122 a are turned off, and control and setting are performed so that the current from the power supply device 132 is not applied to the transistor 117 .

[0538] A constant current Ic is applied to the diode Di to obtain a terminal voltage Vi of the diode Di, etc., and an operational amplifier circuit 116 outputs a terminal voltage Vi corresponding to the terminal voltage. The terminal voltage Vi is input to a temperature measurement circuit 115, which determines temperature information Tj corresponding to the temperature of a transistor 117.

[0539] The temperature information Tj is transferred to the controller circuit 111, and the controller circuit 111 controls the test of the transistor 117 of the semiconductor test device, such as continuing, stopping, or changing the conditions of the test of the transistor 117, based on the temperature information Tj.

[0540] It goes without saying that the above matters and contents, in which the V1 voltage of the voltage Vg applied to the gate terminal is changed in the b direction and the c direction, and the V0 voltage is changed in the c direction and the d direction, can also be applied to other embodiments of the present invention.

[0541] 56 is an explanatory diagram of a method for measuring the channel-to-channel voltage of the transistor 117 without using the constant current Ic, in a state where a test current Id is supplied to the transistor 117. The terminal-to-terminal voltage of the transistor 117 due to the test current Id is taken as the voltage Vi, and temperature information Tj is obtained.

[0542] When the evaluation or test target is transistor 117m, switch circuit 124c and switch circuit 124d are turned on to supply test current Id to transistor 117m and obtain inter-channel voltage Vi. When the evaluation or test target is transistor 117s, switch circuit 122b is turned on to supply test current Id to transistor 117s and obtain inter-channel voltage Vi.

[0543] In the power cycle test, when the test current Id is supplied to perform the test, the channel-to-channel voltage Vi changes due to the deterioration, aging, and characteristics of the transistor 117. Measurement of Vi is performed every cycle or every several cycles, similar to the embodiment in which the constant current Ic is applied.

[0544] If the transistor 117 has deteriorated or changed, the change over time can be obtained by measuring or evaluating the change in the channel-to-channel voltage Vi of the transistor 117 while a test current Id is supplied to the transistor 117.

[0545] 56(d) shows that a test current Id is supplied to the transistor 117, and a voltage V2 is applied to the gate terminal g, while measuring a channel-to-channel voltage Vi of the transistor 117. The voltage measurement Vi is performed during at least one of the period from t1 to t2 and the period from t5 to t6.

[0546] 56(e) shows that a test current Id is supplied to the transistor 117 and a voltage V1 is applied to the gate terminal g, while measuring a channel voltage Vi of the transistor 117. The voltage measurement Vi is performed during a period from t3 to t4. In addition, the channel voltage Vi (Vce) of the transistor 117 is measured during periods t1 to t2 and t5 to t6 when the V2 voltage is applied as the gate terminal voltage Vg.

[0547] 56 is an embodiment in which the Vi voltage is measured at one or more points in the periods t1 to t2, t3 to t4, and t5 to t6. The measured or acquired Vi voltage is acquired every cycle or every several cycles, and the characteristics and characteristic changes of the transistor 117 are evaluated and tested based on the change in the Vi voltage.

[0548] 57, a constant current Ic may be supplied during a period from t6 to t7, and the voltage applied to the gate terminal (base terminal) g may be set to the V2 voltage during a period from t5 to t6. The off voltage is set to the V0 voltage or a voltage from V0 to Vn.

[0549] During the period from t4 to t5, a V1 voltage is applied to the g terminal of the transistor 117, and a test current Id is supplied to the transistor 117. The supply of the test current Id is performed at a predetermined cycle. The V1 voltage may be changed or altered every cycle or every several cycles (arrows a and b). By changing or setting the V1 voltage during the period from t4 to t5, the amount of heat generated by the transistor 117 changes, and the inter-channel voltage Vec(Vi) of the transistor 117 changes. In accordance with this change, Tj(Vi) due to the constant current Ic supplied during the period from t5 to t6 changes. By quantifying the rate and amount of change, the deterioration state of the transistor 117 can be quantitatively grasped.

[0550] Fig. 58 is an explanatory diagram of a semiconductor device testing method according to another embodiment of the present invention. As shown in Fig. 58(c), during the period from t2 to t5, the voltage of the g terminal can be changed arbitrarily. Or, this is an embodiment in which it is changed. The voltage applied during the period from t2 to t5 is the voltage applied to the gate terminal g of the transistor 117, which is changed based on the output of the gate driver circuit 113.

[0551] In the embodiment shown in Fig. 58(c), the gate signal voltage Vg of the transistor 117 is changed so that it is V1a voltage at t2 and V1b voltage at t5. The channel-to-channel resistance of the transistor 117 changes depending on the voltage applied to the gate terminal g of the transistor 117, and the heat generation state of the transistor 117 also changes. By changing the heat generation state, various tests can be performed or realized. In addition, since the channel-to-channel voltage Vce(Vi) of the transistor 117 can be changed, various test conditions can be set.

[0552] If the transistor 117 has deteriorated or changed, the change over time can be obtained by measuring or evaluating the change in the channel-to-channel voltage Vi of the transistor 117 while a test current Id is supplied to the transistor 117.

[0553] 58(d) shows that a test current Id is supplied to the transistor 117 and a voltage V2 is applied to the gate terminal g, while measuring a channel-to-channel voltage Vi of the transistor 117. The measurement of the voltage Vi is performed during at least one of the period from t1 to t2 and the period from t5 to t6.

[0554] 58(e) shows the measurement of the channel voltage Vi of the transistor 117 while supplying a test current Id to the transistor 117 and changing the gate terminal g from a voltage V1 to a voltage V2. The voltage measurement Vi is performed during the period from t2 to t5, and the measurement of Vi is performed in the range from t2 to t5.

[0555] As shown in Fig. 59(a), the gate voltage Vg applied to the gate terminal g when the test current Id is supplied or applied to the transistor 117 may be changed periodically. In Fig. 59(a), the voltage V1a is applied in the period A and the period C, and the voltage V1b is applied in the period B. The period A (period C) and the period B are alternately repeated.

[0556] As described above, in the present invention, during the period in which the test current Id is applied, the gate terminal voltage of the transistor 117 can be varied to a plurality of voltages, or the voltage can be changed continuously.

[0557] As shown in Fig. 59(b), the voltage change shown in Fig. 58 may be implemented. In period A and period C, the voltage changes from V1a to V1b, and in period B, the voltage changes from V1b to V1a. Period A (period C) and period B are repeated alternately. As shown in FIG. 59(c), the terminal voltage to the gate terminal g in the periods t1 to t2 and t6 to t7 can also be changed.

[0558] In FIG. 59(c), in period A (period C), the V1b voltage is applied to the g terminal of transistor 117 from period t1 to t2. The V2 voltage is applied to the g terminal of transistor 117 from period t6 to t7. In period B, the V1b voltage is applied to the g terminal of transistor 117 from period t1 to t2. The V1b voltage is also maintained from period t2 to t6. The V2 voltage is applied to the g terminal of transistor 117 from t6 to t7.

[0559] 59(d), in periods A, B, and C, the Vn voltage is applied to the g terminal of transistor 117 from period t1 to t2. The V2 voltage is applied to the g terminal of transistor 117 from period t6 to t7. In period A (period C), the V1a voltage is applied to the g terminal of transistor 117 from period t2 to t6. In period B, the V1b voltage is applied to the g terminal of transistor 117 from period t2 to t6.

[0560] 59, the period for measuring the inter-terminal voltage Vi and for obtaining the temperature information Tj of the characteristic curve (characteristic equation) is the period from t6 to t7. Preferably, measurements are also made during the period from t1 to t2. By comparing the terminal voltage Vi during the period from t1 to t2 with the inter-terminal voltage Vi during the period from t6 to t7, more diverse tests can be performed and the evaluation status of the transistor 117 being tested can be grasped in detail. FIG. 60 is an explanatory diagram of an embodiment in which the transistors 117m and 117 are tested alternately.

[0561] For ease of explanation and understanding, the following description will be given assuming that the test current Id is supplied to the transistor 117m by turning on the switch circuit 122a, and the charge between the channel of the transistor 117m is discharged by turning on the switch circuit 124d. The gate terminal of the transistor 117m is Vgm, and the test current supplied to the transistor 117m is Idm.

[0562] The transistor 117s is described as being supplied with a test current Id by turning on the switch circuit 122b, and discharging the charge between the channel of the transistor 117s by turning on the switch circuit 124c. The gate terminal of the transistor 117s is Vgs, and the test current supplied to the transistor 117s is Ids.

[0563] 60 is a timing chart when the test current Id and the constant current Ic are applied in one cycle ts. The V1 voltage is applied for a period toa, and the V2 voltage is applied for a period tob. After the conduction period of the transistor 117, the V0 voltage is applied to turn off the transistor 117. A power cycle test (load test), avalanche test, etc. are performed with the V1 voltage, V2 voltage, and V0 voltage for one cycle ts.

[0564] The transistors 117m and 117s are alternately turned on. Therefore, the test current Id (Idm or Ids) is alternately applied to the transistors 117m and 117s. Id is supplied from the power supply device 132a.

[0565] As described in FIG. 52, during the period from tb2 before the switch circuit 122a turns on to tb1 after the switch circuit 122a turns on, the switch circuit 124d turns on and the charge between the channel terminals of the transistor 117m is discharged.

[0566] During the period from ta2 before the switch circuit 122a is turned off to ta1 after the switch circuit 122a is turned off, the switch circuit 124d is turned on and the charge between the channel terminals of the transistor 117m is discharged. During the other periods, the switch circuit 124d is maintained in the off state (FIG. 60(d1), FIG. 60(e1)).

[0567] 60(a1), a voltage V1 is applied to the gate terminal gm of the transistor 117m during a period toa, and a voltage V2 is applied to the gate terminal gm of the transistor 117m during a period tob. The period during which the on-voltage is applied to the transistor 117m is ts.

[0568] The time when the transistor 117m changes from the V0 voltage to the V1 voltage may be before the switch circuit 124d changes from OFF to ON. It is preferable to change from the V0 voltage to the V1 voltage after the switch circuit 124d changes from OFF to ON and while the switch circuit 124d is in the ON state. The period during which the test current Idm flows through the transistor 117m is the period during which the switch circuit 122a is in the ON state and the switch circuit 124d is in the OFF state.

[0569] There is no particular restriction on the time when the voltage applied to the gate terminal gm of transistor 117m is changed from the V1 voltage to the V2 voltage, but the change is at least made before the constant current Icm is supplied to transistors 117m, etc. During the period when the V2 voltage is being applied, the constant current Icm is supplied and the inter-terminal voltage Vi of transistor 117m is measured.

[0570] The voltage applied to the gate terminal gm of the transistor 117m is preferably changed from the V2 voltage to the V1 voltage after the switch circuit 124d changes from on to off, preferably after the constant current Icm supplied to the transistor 117m is stopped.

[0571] As described in FIG. 52, during the period from ta2 before the switch circuit 122a is turned off to ta1 after the switch circuit 122a is turned off, the switch circuit 124d is turned on, and the charge between the channel terminals of the transistor 117m is discharged (FIG. 60(d1), FIG. 60(e1)). The transistor 117s is also supplied with a test current Ids in the same manner as the transistor 117m, and a power cycle test or the like is performed.

[0572] The transistors 117m and 117s are alternately turned on. Therefore, the test current Id (Idm or Ids) is alternately applied to the transistors 117m and 117s. Id is supplied from the power supply device 132a. Since the test current Id (Idm, Ids) is not supplied to the transistors 117m and 117s at the same time, a low-capacity power supply device 132 can be used.

[0573] As described in FIG. 52, during the period from tb2 before the switch circuit 122b turns on to tb1 after the switch circuit 122b turns on, the switch circuit 124c turns on and the charge between the channel terminals of the transistor 117s is discharged.

[0574] During the period from ta2 before the switch circuit 122b is turned off to ta1 after the switch circuit 122b is turned off, the switch circuit 124c is turned on and the charge between the channel terminals of the transistor 117s is discharged. During the other periods, the switch circuit 124c is maintained in the off state (FIG. 60(d1), FIG. 60(e1)).

[0575] 60(a1), a V1 voltage is applied to the gate terminal gs of the transistor 117s during a period toa, and a V2 voltage is applied to the gate terminal gs of the transistor 117s during a period tob. The period during which the on-voltage is applied to the transistor 117s is ts.

[0576] The time when the transistor 117s changes the voltage from V0 to V1 may be before the switch circuit 124c changes from OFF to ON. It is preferable to change the voltage from V0 to V1 after the switch circuit 124c changes from OFF to ON and while the switch circuit 124c is in the ON state. The period during which the test current Ids flows through the transistor 117s corresponds to a period during which the switch circuit 122b is in an ON state and the switch circuit 124c is in an OFF state.

[0577] There is no particular restriction on the time when the voltage applied to the gate terminal gs of the transistor 117s is changed from the V1 voltage to the V2 voltage, but the change is at least made before the constant current Ics is supplied to the transistor 117s, etc. During the period in which the V2 voltage is being applied, the constant current Ics is supplied and the inter-terminal voltage Vi of the transistor 117s is measured.

[0578] The voltage applied to the gate terminal gs of the transistor 117s is preferably changed from the V2 voltage to the V1 voltage after the switch circuit 124d changes from on to off, preferably after the constant current Ics supplied to the transistor 117s is stopped.

[0579] As described in FIG. 52, during the period from ta2 before the switch circuit 122b is turned off to ta1 after the switch circuit 122a is turned off, the switch circuit 124c is turned on, and the charge between the channel terminals of the transistor 117s is discharged (FIG. 60(d1), FIG. 60(e1)). FIG. 60 shows an embodiment in which the test method of FIG. 52 is carried out in the ts cycle, but it goes without saying that the same can be applied to FIG. 53.

[0580] In FIG. 52 and the like, the V0 voltage is used as the off voltage, but the V0 voltage is not limited to a single-level potential. For example, there may be a plurality of voltages such as V0a voltage and V0b voltage, and a plurality of off voltages may be used. For example, the off voltage before changing to the V1 voltage may be the V0a voltage for a period of 10 milliseconds or less, and the application period of other off voltages may be the V0b voltage. It is preferable that the potential levels of the V0a and V0b voltages satisfy V0a < V0b. By lowering the V0a voltage, the change rate from the V0a voltage to the V1 voltage increases, and the intermediate state of the on-off operation becomes shorter.

[0581] FIG. 61 is a timing chart for explaining the operation of the semiconductor test apparatus in another embodiment of the present invention. The differences from FIG. 60 are FIGS. 61(e3) and 61(e2).

[0582] In the embodiment of FIG. 60, the switch circuit 124d was turned on as shown in FIG. 60(e1) in response to the Vgm signal of the transistor 117m to discharge the channel voltage of the transistor 117m or the charge between the terminals of the power supply device 132. Also, the switch circuit 124c was turned on as shown in FIG. 60(e2) in response to the Vgs signal of the transistor 117s to discharge the channel voltage of the transistor 117s or the charge between the terminals of the power supply device 132.

[0583] In the embodiment of FIG. 61, the switch circuits 124c and 124d are controlled to be turned on and off as shown in FIG. 61(e3) in common for the Vgm signal of the transistor 117m and the Vgs signal of the transistor 117s. By turning on the switch circuits 124c and 124d, the channel voltage between the transistors 117s and 117m or the charge between the terminals of the power supply device 132 can be discharged.

[0584] 61(e4), the switch circuit 124b is turned on and off in common with the Vgm signal of the transistor 117m and the Vgs signal of the transistor 117s. By turning on the switch circuit 124b, the inter-channel voltages of the transistor 117s and the transistor 117m, or the charges between the terminals of the power supply device 132 can be discharged.

[0585] Fig. 62 is a timing chart of an embodiment in which the transistors 117m and 117s are simultaneously turned on to perform a power cycle test (load test) or the like. The transistors 117s and 117m are connected in series. A common gate voltage is applied to the gate terminal gm of the transistor 117m and the gate terminal gs of the transistor 117s (Fig. 62(a3)).

[0586] The test current Id is supplied by turning on the switch circuit 122b (FIG. 62(d2)). The switch circuit 122a is controlled to be always in the off state. The charge between the channels of the transistors 117s and 117m is discharged by turning on the switch circuit 124b (FIG. 62(e4)) or by simultaneously turning on the switch circuits 124c and 124d. The test current Id (test current Idm, test current Ids) is supplied to the transistor 117m and the transistor 117s during the period toa (FIG. 62(b3)). The constant current Ic (constant current Icm, constant current Ics) is supplied independently to the transistor 117m and the transistor 117s during the period tob (FIG. 62(c3)).

[0587] As shown in Fig. 62(e4), the charge between the channels of the transistors 117m and 117s is discharged by turning on the switch circuit 124b, or by simultaneously turning on the switch circuits 124c and 124d.

[0588] In the embodiments of Figures 1, 2, 8, 21, 26, 30, 40, etc., the semiconductor module 117 is illustrated and described as having two transistors, the upper transistor 117s and the lower transistor 117m, but the present invention is not limited to this. For example, it goes without saying that the embodiments of the present invention can be applied even when only one of the upper transistor 117s or the lower transistor 117m is used. It goes without saying that the embodiments of the present invention can also be applied when the semiconductor module 117 is configured with three or more transistors.

[0589] In the case of a configuration in which the upper transistor 117s is not arranged or implemented as in Figure 26 etc., a pressing tool 501 is used to connect the power supply wiring 212 to which the collector (C) terminal of the upper transistor 117s is connected and the collector (C) terminal of the lower transistor 117m, thereby electrically connecting the power supply wiring 212 and the collector (C) terminal of the lower transistor 117m.

[0590] In the case of a configuration in which the lower transistor 117s is not arranged or implemented as in Figure 26 etc., a pressing tool 501 is used to connect the emitter (E) terminal of the upper transistor 117s and the power supply wiring 212 connected to the emitter (E) terminal of the lower transistor 117m, and the emitter (E) terminal of the upper transistor 117s and the power supply wiring 212 can be electrically connected.

[0591] As described above, when either the lower transistor 117m or the upper transistor 118s is not arranged or mounted, it is possible to test or evaluate one of the transistors by using a pressing tool 510 that shorts the terminals of the corresponding transistor 117 or by connecting them with wiring. For example, in Fig. 30, a configuration in which the transistors 117a, 117c, and 117e are not mounted, and in Fig. 30, a configuration in which the transistors 117b, 117d, and 117f are not mounted are exemplified. The above matters are also applicable when the number of transistors constituting the semiconductor module 117 is three or more. It goes without saying that the above items can be similarly applied to the inspection or test methods for semiconductor elements (electrical elements) in FIGS.

[0592] The semiconductor device (electrical device) testing method described above with reference to Figures 51 to 61 can be applied to the semiconductor device (electrical device) testing apparatus of the present invention described in the embodiments of the present invention. It goes without saying that all or part of the methods can be combined.

[0593] In the embodiment of the present invention, the transistor 117 to be tested is described as an IGBT, but the present invention is not limited to this. For example, as shown in Fig. 62, the transistor 117 may be a two-terminal element such as a diode. In addition, the transistor 117 is not limited to a semiconductor element, and any electric element such as a capacitor or resistor may be used. It goes without saying that the matters or contents described in this specification and drawings can be combined with each other in part or in whole.

[0594] In the above, the present specification has specifically described the present invention based on the embodiment, but it goes without saying that the present invention is not limited thereto and various modifications are possible without departing from the spirit of the present invention. [Industrial Applicability]

[0595] In the present invention, semiconductor elements such as transistors can be mounted on slide plate 505 and fixed in the tank of the testing device. Also, the connections can be easily changed according to the test contents and number of electric elements to be tested. [Explanation of symbols]

[0596] 111 Control circuit (controller) 112 Gate signal control circuit 113 Gate driver circuit 115 Temperature measurement circuit 116 Operational Amplifier (Buffer Amplifier) 117 Electrical elements (transistors) 118 Constant current circuit 122 Switch Circuit 124 Switch Circuit 125 Variable Resistor Circuit 127 Analog-to-Digital (AD) Converter Circuit 128 Digital-to-Analog (DA) Converter Circuit 132 Power supply 134 Heating and cooling plate 137 Short Circuit 201 Switch circuit board 202 Connector 203 Sample connection circuit 204 Conductor plate 205 Fork plug 206 connection pins 208 Connector 209 Device Control Circuit 211 Connection wiring 212 Power wiring 214 Bulkhead 216 Opening 219 Connection bolt 220 Contact part 221 Fixing screw 223 Heat Pipe 226 Element terminal 227 (Cooling) (Heating) Cooling fan 500 Element mounting stand 501 Pressing tool 502 Terminal Board 503 devices 504 Connector stand 505 Slide plate 506 Cam Follower 507 Rail Guide 508 Socket Connector (Male) 509 Socket Connector (Female) 510 Temperature Sensor 511 Wiring Pattern 512 fixing hole 514 Fixed hole 515 rand 516 Thermal grease 517 Conductor Plate Group 518 Toride 519 Control circuit section (board) 520 Holder 522 Heating and Cooling Equipment Department 523 Enclosure (Thermostatic chamber) 524 Processing Circuit 525 Fan 526 Inside the tank 527 Door 528 Fork connector (connecting member) 529 Contact switch (detection switch) 530 Confirmation lamp (confirmation indicator lamp) 531 Fixing hole 532 fixing hole 533 Testing Machinery Department 534 Element insertion part 535 Element connection part 536 Connectors 537 Opening 538 Heat dissipation fin 702 IC fastening hole 704 Insulating plate 705 Shield plate 707 (pin) connector 708 Insulating sheet (insulating film) 709 Conductor Plate 710 screw hole 711 Metal fittings 712 Cable Connector 713 Shaft hole 714 Knurled Nut 717 Pressing tool support (pressing tool fixing support) 721 Contact fittings 722 Connection fittings 723 Set screw 724 connection pins 725 Cable Mounting Screw 726 pin socket 727 Signal Wiring 728 Press Screw 732 Signal Cable 737 Fasteners 738 Connection Detector 751 Frame Border 752 Frame fixing foot 753 Front cover 754 Signal Cable Connector 755 Power cable attachment terminal 756 Fixed plate support 757 Pressure Regulator 758 Pressure Regulator 759 Fixing screw 760 Drawer Pin 761 Fan control unit 762 Operation Panel 763 Control Interface 764 Alarm 781 Connection fitting pin 782 Separation fixing plate 783 Fixing hole 784 Fixed plate pin 791 External connection hole 801 Spacer stand 802 Fixed plate 821 Cable spacer stand

Claims

1. An electrical element testing device to be installed inside a constant temperature chamber, A sliding plate and A frame on which the aforementioned sliding plate is arranged, A fixing device for securing the frame inside the tank, The electrical element arrangement section arranged on the slide plate, A connecting member that connects to the element terminals of the electrical elements arranged in the aforementioned electrical element arrangement section, A power supply device that supplies a test current to the aforementioned electrical element, The power cable is connected to the aforementioned connecting member, passes through the back surface of the slide plate, and connects to the power cable mounting terminal on the front surface of the slide plate. An electrical element testing apparatus characterized in that the test current is supplied to the electrical element via a power cable mounting terminal.

2. An electrical element testing device to be installed inside the chamber of a constant temperature chamber, A sliding plate and A frame on which the aforementioned sliding plate is arranged, A fixing device for securing the frame inside the tank, The electrical element arrangement section arranged on the slide plate, A connecting member that connects to the element terminals of the electrical elements arranged in the aforementioned electrical element arrangement section, The system comprises a power supply device that supplies a test current to the aforementioned electrical element, The connecting member comprises a first connecting fitting having a shaft hole, a second connecting fitting, and a pressing tool attached to the shaft hole. The element terminals of the electrical element are positioned between the first connecting fitting and the second connecting fitting. An electrical element testing apparatus characterized in that the second connecting fitting is pressed by the pressing tool, thereby connecting the element terminal of the electrical element with the connecting member.

3. An electrical element testing device to be installed inside a constant temperature chamber, A sliding plate and A frame on which the aforementioned sliding plate is arranged, A fixing device for securing the frame inside the tank, The electrical element arrangement section arranged on the slide plate, A connecting member that connects to the element terminals of the electrical elements arranged in the aforementioned electrical element arrangement section, A power supply device that supplies a test current to the aforementioned electrical element, A power cable connecting the power supply unit and the connecting member, The system includes a fan that sets the airflow to the aforementioned electrical element, The upper and lower limits of the rate of change in the fan's rotation speed are registered. The rotation speed of the aforementioned fan at the start of the test is obtained, From the fan speed and the upper limit of the rate of change, the upper limit of the fan speed is determined. From the fan speed and the lower limit of the rate of change, the lower limit of the fan speed is determined. An electrical element testing apparatus characterized by monitoring when the fan speed exceeds the upper limit or lower limit of the fan speed.

4. An electrical element testing device to be installed inside a constant temperature chamber, A sliding plate and A frame on which the aforementioned sliding plate is arranged, The electrical element arrangement section arranged on the slide plate, A connecting member that connects to the element terminals of the electrical elements arranged in the aforementioned electrical element arrangement section, A power supply device that supplies a test current to the aforementioned electrical element, The constant temperature bath device comprises a conductive member that connects the inside of the bath to the outside of the bath, An electrical element testing apparatus characterized in that the conductor member inside the tank is connected to the connecting member, the conductor member outside the tank is connected to the power supply device, and the test current is supplied from the conductor member outside the tank.

5. The electrical element testing apparatus according to claim 1, claim 2, claim 3, or claim 4, further comprising a handle for pulling out the slide plate.

6. The electrical element testing apparatus according to claim 1, claim 2, claim 3, or claim 4, further comprising a display that is linked to the position of the slide plate.

7. The electrical element testing apparatus according to claim 1, claim 2, claim 3, or claim 4, characterized in that the supply of the test current is linked to the opening and closing state of the door of the constant temperature chamber device.

8. The electrical element is a semiconductor element having a first element terminal, a second element terminal, and a gate terminal, A first semiconductor element and a second semiconductor element are arranged in the aforementioned electrical element arrangement section. The electrical element testing apparatus according to claim 1, 2, 3, or 4, further comprising a pressing tool for connecting the first element terminal of the first semiconductor element and the second element terminal of the second semiconductor element.

9. The electrical element is a semiconductor element having a first element terminal, a second element terminal, and a gate terminal, A constant current circuit is provided between the first element terminal and the second element terminal to supply a constant current. The electrical element testing apparatus according to claim 1, 2, 3, or 4, further comprising a voltage output circuit that outputs a terminal voltage between the terminals of the first element and the terminals of the second element.

10. The electrical element is a semiconductor element having a first element terminal, a second element terminal, and a gate terminal, The electrical element testing apparatus according to claim 1, 2, 3, or 4, further comprising a gate driver circuit that applies a first on-voltage and a second on-voltage for turning on the semiconductor element, and an off-voltage for turning off the semiconductor element, to the gate terminal.

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