Metal fill process for three-dimensional vertical NAND wordline

Abstract

To provide a method of depositing transition metal such as tungsten on a semiconductor substrate.SOLUTION: A method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor into metal, such as a tungsten-containing precursor into tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 545,405, filed Aug. 14, 2017, and entitled “METAL FILL PROCESS FOR THREE-DIMENSIONAL VERTICAL NAND WORDLINE,” which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present disclosure relates generally to the deposition of transition metals on semiconductor substrates, and more particularly to the deposition of transition metals on semiconductor substrates by conversion of a boron layer formed by a boron-containing precursor. [Background technology]

[0003] The deposition of tungsten and tungsten-containing materials is an essential part of many semiconductor manufacturing processes. Such deposition can be achieved by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), and other deposition techniques known in IC manufacturing technology, such as physical vapor deposition (PVD). Tungsten and tungsten-containing materials, hereinafter referred to as tungsten-based materials or simply tungsten materials, may be used for horizontal interconnects, vias between adjacent metal layers, contacts between a first metal layer and devices on a silicon substrate, and generally within various high aspect ratio features used in IC design.

[0004] In a conventional process for depositing tungsten material, a substrate is heated to a predetermined process temperature in a deposition chamber, and a thin layer of tungsten material is deposited to act as a seed layer or nucleation layer. A bulk layer of tungsten material is then deposited on the nucleation layer. Typically, tungsten material is formed by reducing tungsten hexafluoride (WF6) with hydrogen (H2). Typically, the tungsten material is deposited over the entire exposed surface area of ​​the substrate, which often includes one or more field regions, as well as various IC features. These features may have widely varying aspect ratios, and in some embodiments, one or more or all of the features may have a relatively high aspect ratio. Summary of the Invention

[0005] The present disclosure relates to a method, the method includes providing a gas mixture in a gas supply line, the gas mixture including diborane (B2H6) balanced with hydrogen (H2). The method further includes introducing the gas mixture from the gas supply line into a deposition chamber and to a surface of a semiconductor substrate, the semiconductor substrate including a vertical structure having a plurality of horizontally oriented features, the diborane decomposing to form a boron layer in the horizontally oriented features. The method further includes converting the boron layer to a transition metal layer in the semiconductor substrate.

[0006] In some implementations, the gas mixture includes at least 20% by volume diborane balanced with hydrogen. In some implementations, the gas mixture includes about 20% by volume to about 50% by volume diborane balanced with hydrogen. In some implementations, the transition metal includes molybdenum, ruthenium, cobalt, or tungsten. In some implementations, converting the boron layer to the transition metal layer includes reacting the boron layer with a tungsten-containing precursor to form a tungsten layer. In some implementations, the semiconductor substrate has an opening in a sidewall of the vertical structure and is fluidly accessible from the vertical structure through the opening. In some implementations, the vertical structure is a three-dimensional (3D) vertical NAND structure. In some implementations, the boron layer is conformally deposited in horizontally oriented features of the vertical structure, and the boron layer has at least 90% step coverage.

[0007] The present disclosure also relates to an apparatus, the apparatus including a gas supply line and a deposition chamber coupled to the gas supply line, the deposition chamber configured to process a semiconductor substrate in the deposition chamber, the gas supply line configured to contain a gas mixture of diborane and a hydrogen balance, the semiconductor substrate including a vertical structure having a plurality of horizontally oriented features, the apparatus further including a controller configured to provide instructions, the instructions including the following operations: A gas mixture is introduced from a gas supply line into a deposition chamber and to a surface of a semiconductor substrate, where the diborane decomposes to form a boron layer in the horizontally oriented features, and the boron layer is converted to a transition metal layer in the semiconductor substrate.

[0008] In some implementations, the gas mixture includes at least 20% by volume diborane balanced with hydrogen. In some implementations, the gas mixture includes about 20% by volume to about 50% by volume diborane balanced with hydrogen. In some implementations, the transition metal layer includes molybdenum, ruthenium, cobalt, or tungsten. In some implementations, the system controller configured with instructions to convert the boron layer is configured with instructions to react the boron layer with a transition metal precursor to form the transition metal layer. In some implementations, the semiconductor substrate has an opening in a sidewall of the vertical structure and is fluidly accessible from the vertical structure through the opening. In some implementations, the controller is further configured with instructions to perform an operation of exposing the semiconductor substrate to a reducing gas including silane, disilane, or hydrogen. In some implementations, the controller is further configured with instructions to perform an operation of providing a semiconductor substrate in a deposition chamber.

[0009] These and other embodiments are further described below with reference to the drawings. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 1A shows a cross-section of a vertical feature in a substrate that can be designed to be filled with a tungsten material.

[0011] [Figure 1B] FIG. 1B shows an example of a feature similar to that of FIG. 1A, but with an inwardly recessed profile due to the presence of an underlayer covering the bottom, sidewalls, and opening of the feature.

[0012] [Figure 1C] 1C shows a top plan view of a horizontal feature exhibiting a constriction approximately in the middle of its sidewall. In some embodiments, such a horizontal feature may be what is referred to as a "word line" in a vertically integrated memory structure.

[0013] [Figure 1D] FIG. 1D shows a side view of the same horizontal feature shown in FIG. 1C, but now with an opening into the vertical structure, and thus forming part of the vertical structure.

[0014] [Figure 2A] FIG. 2A shows a cross-sectional side view of a 3D vertical memory NAND (VNAND) structure (formed on a semiconductor substrate) having a VNAND stack (left and right), a central vertical structure, and multiple stacked horizontal features with openings on opposing sidewalls of the central vertical structure.

[0015] [Figure 2B] FIG. 2B shows a top cross-sectional view of the VNAND structure shown in side view in FIG. 2A, the cross-section being taken at the horizontal cross-section indicated by the dashed horizontal line in FIG. 2A.

[0016] [Figure 3A] FIG. 3A shows a vertical cross-section (cut-out) of a VNAND structure similar to that shown in FIG. 2A, but focuses on a single pair of wordlines, and additionally shows a schematic of the tungsten fill process that resulted in the formation of voids in the wordlines.

[0017] [Figure 3B] FIG. 3B shows a horizontal cross section (cut-out) of a VNAND structure similar to that shown in FIG. 2A, and also shows diagrammatically the presence of voids as in FIG. 3A.

[0018] [Figure 3C] FIG. 3C is a top-down cross-sectional view of a single wordline, illustrating how the nearly conformal deposition of tungsten material begins to pinch off inside the illustrated wordline due to the presence of the pillars shown.

[0019] [Figure 4] FIG. 4 is a schematic representation of a feature at various stages of feature fill using boron to tungsten conversion.

[0020] [Diagram 5] FIG. 5 is a graph of diborane concentration as a function of days, with the diborane balanced with nitrogen, hydrogen, or a mixture of hydrogen and nitrogen.

[0021] [Figure 6A] FIG. 6A shows a schematic representation of various tungsten stacks deposited according to different sequences. [Figure 6B] FIG. 6B shows a schematic representation of various tungsten stacks deposited according to different sequences. [Figure 6C] FIG. 6C shows a schematic representation of different tungsten stacks deposited according to different sequences. [Figure 6D] FIG. 6D shows a schematic representation of different tungsten stacks deposited according to different sequences.

[0022] [Figure 7] FIG. 7 is a flow diagram illustrating an exemplary method for depositing a transition metal layer using hydrogen balanced diborane.

[0023] [Figure 8] FIG. 8 is a schematic diagram of an apparatus including a deposition chamber for performing a metal deposition process in accordance with certain implementations.

[0024] [Figure 9] FIG. 9 is a schematic diagram of a multi-station apparatus for performing metal deposition and / or etching operations in accordance with certain implementations.

[0025] [Figure 10] FIG. 10 is a schematic diagram of a multi-station apparatus for performing metal deposition and / or etching operations in accordance with certain implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented concepts. The presented concepts may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the presented concepts. While some concepts will be described in conjunction with specific embodiments, it will be understood that these embodiments are not intended to be limiting.

[0027] In this disclosure, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of the many stages of integrated circuit manufacturing fabricated on the silicon wafer. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the disclosure is implemented on a wafer. However, the disclosure is not so limited. Workpieces may have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosure include various articles such as printed circuit boards.

[0028] 3D vertical NAND structure Despite the frequent use of tungsten material in integrated circuit (IC) design and fabrication, there are difficulties associated with its use. For example, when tungsten material is deposited into small features or features with high aspect ratios, voids may form in the deposited tungsten. A void is simply an area in a structure or feature that remains unfilled after the surrounding areas have been filled. In many cases, void formation occurs due to a disproportionate accumulation of deposited material near the entrance of the feature, resulting in the entrance being blocked and the interior volume of the feature being pinched off, preventing further deposition within the interior volume. Once blocked or pinched off, reactive deposition precursor species have no way into the interior volume, preventing any further deposition within these regions. In other cases, even without pinching off, seams may appear in the deposited tungsten material, as the tungsten material tends to deposit outward from the sidewalls (rather than exhibiting bottom-up filling). Thus, such seams are typically elongated along a significant portion of the central axis of the feature, extending toward the bottom of the feature. Sometimes, the presence of seams can lead to the formation of voids, such as when the seams extend close to the field area after the fill process is completed, and subsequent chemical mechanical planarization opens the seams. In any case, seams and voids can cause high resistance, substrate contamination, loss of material, etc., and otherwise adversely affect the electrical properties of the integrated circuit.

[0029] Aspects of the present disclosure may provide uniform tungsten filling of semiconductor substrate structures and features while minimizing or eliminating the formation of voids and seams. Applications of such uniform tungsten filling include logic and memory contact filling, buried wordline filling of DRAM, vertically integrated memory gate / wordline filling, and 3D integration (TSV). The methods, apparatus, and systems described herein may be used to fill vertical features, such as vias, as well as horizontal features, such as horizontal wordlines in vertical NAND (VNAND) structures, as described in more detail below. The substrate having the structure or feature to be filled may be a 200, 300, or 450 mm semiconductor wafer, or a wafer having a diameter of about 200-300 mm, or about 300-450 mm, or greater than about 450 mm, or any suitable size wafer. Additionally, the methods, apparatus, and systems may be used to fill features on other types of substrates, including panels, display substrates, and the like, with tungsten.

[0030] As discussed above, a significant problem associated with filling semiconductor substrate structures and features with tungsten material is the formation of seams and voids during the tungsten filling process. In particular, structures having features characterized by one or more of narrow and / or reentrant openings, or constrictions, or simply having a relatively high aspect ratio can be problematic. FIG. 1A shows a cross-section of a vertical feature 101 in a substrate 103 that can be designed to be filled with a tungsten material. Such a vertical feature has a feature opening 105 and sidewalls 107. The vertical feature 101 can have an aspect ratio of at least about 2:1, or at least about 4:1, or at least about 6:1, or at least about 10:1, or at least about 20:1, or even higher. The feature opening 105 can have a diameter of about 10 nanometers to 500 nanometers, for example, about 25 to 300 nanometers.

[0031] Similarly, FIG. 1B shows an example of a similar feature 101, but with an inwardly concave profile due to the presence of an underlayer 113 covering the bottom, sidewalls, and opening of the feature 101. An inwardly concave profile is one in which the cross-section narrows somewhere between the feature opening and the bottom or closed end of the feature, thereby creating a "bottleneck" in the profile. In some cases, the inwardly concave profile narrows gradually from the feature opening inward, or the feature may include an overhang at the opening itself. FIG. 1B shows an example of the latter, where again the narrowing is due to the presence of an underlayer 113 that is thicker near the feature opening than at the bottom of the feature or further down the feature sidewall 107, thereby creating an overhang 115. The underlayer 113 may be, for example, a diffusion barrier layer, an adhesion layer, a nucleation layer, or any combination of these, or any other useful or advantageous layer of material.

[0032] In some embodiments, one or more constrictions in the sidewall of the feature may make it difficult to achieve a uniform tungsten fill. FIG. 1C shows a top plan view of an exemplary horizontal feature 121 showing a constriction 109 approximately in the middle of the sidewall 107. In some embodiments, such a horizontal feature may be what is referred to as a "word line" in a vertically integrated memory structure, such as one of the 3D vertical NAND (VNAND) structures described in more detail below. FIG. 1D shows a side view of the same horizontal feature 121 having an opening 105 to, and thus forming part of, the vertical structure 122. Achieving a uniform fill of tungsten in such a structure may be difficult, since for some embodiments, and for some deposition chemistries and processes, a sufficient amount of each species of deposition precursor must travel vertically down to the base of the structure 122 and then horizontally through the horizontal feature 121, particularly through the region of the constriction 109. It should be noted again that Figure 1C presents a top plan view of the horizontal feature 121 and the constriction 109, while Figure 1D presents a side view of the same. Thus, from these views, it is apparent that in this embodiment, the constriction 109 extends horizontally inward and vertically from the sidewall 107 of the feature 121. However, it should be understood that in other embodiments, the constriction in the feature may only exist in one of the two cross-sectional dimensions, and that any type of constriction, whether one or two dimensional, may make uniform tungsten filling more difficult.

[0033] In some embodiments, the structure to be filled on the semiconductor substrate is a vertical structure having a number of horizontal features, the horizontal features having openings in sidewalls of the vertical structure, the openings leading to a number of interior volumes (of the horizontal features), the interior volumes being fluidically accessible from the main vertical structure through the feature openings.

[0034] For example, FIG. 2A shows a cross-sectional side view of a 3D vertical memory NAND (VNAND) structure 200 (formed on a semiconductor substrate 201) having VNAND stacks (left 205 and right 206), a central vertical structure 210, and multiple stacked horizontal features 220 with openings 230 on opposing sidewalls 240 of the central vertical structure 210. Note that FIG. 2A shows two "stacks" of the VNAND structure shown, which together form the "trench-like" central vertical structure 210. However, in certain embodiments, there may be two or more "stacks" arranged in sequence and running parallel to each other in space, with the gap between each pair of adjacent "stacks" forming the central vertical structure 210 as explicitly shown in FIG. 2A. In this embodiment, the horizontal features 220 are actually 3D memory "word lines" and are fluidically accessible from the vertical structures 210 through the openings 230. Although not explicitly shown in the figures, the horizontal features 220 present in both VNAND stacks 205, 206 (i.e., the left VNAND stack 205 and the right VNAND stack 206) shown in FIG. 2A are also accessible from the opposite sides of the VNAND stacks (left and right ends, respectively) via similar vertical structures (not shown, but at the left and right ends) formed by additional VNAND stacks. In other words, each VNAND stack 205, 206 contains a stack of word lines that are fluidly accessible from both sides of the VNAND stack via a central vertical structure 210. In the particular example shown diagrammatically in FIG. 2A, each VNAND stack contains six pairs of stacked word lines, but in other embodiments, the 3D VNAND memory layout may contain 8, or 16, or 32, or 64 pairs of vertically stacked word lines, corresponding to 16, or 32, or 64, or 128 stacked horizontal word line features 220 with openings 230. Furthermore, in principle, any number of wordlines may be stacked vertically within such a VNAND structure, so long as technology is available that satisfactorily achieves (substantially) void-free filling of the vertical features.Thus, for example, a VNAND stack may include 2 to 256 horizontal word line features, or 8 to 128 horizontal word line features, or 16 to 64 horizontal word line features, etc. (with the stated ranges being understood to include the recited endpoints).

[0035] FIG. 2B shows a top cross-sectional view of the same VNAND structure 200 shown in side view in FIG. 2A, with the cross-section taken at horizontal cross-section 260 (i.e., indicated by dashed horizontal line) shown in FIG. 2A. FIG. 2B shows several columns of pillars 250 running vertically from the base of semiconductor substrate 201 to the top of VNAND stack 200 shown in FIG. 2A. In some embodiments, these pillars 250 are formed from polysilicon material and are structurally and functionally important to VNAND structure 200. In some embodiments, such polysilicon pillars may function as gate electrodes for stacked memory cells formed by the word lines. The top view of FIG. 2B shows that pillars 250 form a constriction at opening 230 to word line 220. That is, the pillars 250 inhibit fluidic accessibility to word line 220 from vertical structure 210 through opening 230 (indicated by arrow in FIG. 2B). In some embodiments, the size of the horizontal gap between adjacent polysilicon pillars is about 1-20 nm. This reduced fluid accessibility increases the difficulty of uniformly filling the wordlines 220 with tungsten material.

[0036] The structure of the wordlines 220 and the difficulty in uniformly filling the wordlines 220 with tungsten material due to the presence of the pillars 250 are further illustrated in Figures 3A, 3B, and 3C. Figure 3A shows a vertical cut through the VNAND structure 200 similar to that shown in Figure 2A, but now focusing on a single pair of wordlines 220, and additionally shows a schematic of the tungsten filling process that resulted in the formation of a void 270 in the wordlines 220. Figure 3B also shows the void 270 schematic, but this time by a horizontal cut through the pillars 250, similar to the horizontal cut shown in Figure 2B. Figure 3B shows the accumulation of tungsten material around the pillars 250 forming a constriction, which pinches off the opening 230, such that additional tungsten material cannot be deposited in the area of ​​the void 270. 3A and 3B, it is clear that void-free tungsten fill relies on a sufficient amount of deposited precursor migrating down the vertical structures 210, through the openings 230, past the pillars 250 causing the constriction, and to the furthest end of the wordline 220 before the accumulated tungsten deposition around the pillars 250 pinches off the openings 230 and prevents the precursor from migrating further into the wordline 220. Similarly, FIG. 3C shows a single wordline 220 in cross section from above, illustrating how the generally conformal deposition of tungsten material begins to pinch off the interior of the wordline 220 due to the fact that the large width of the pillars 250 acts to partially block and / or narrow and / or narrow what would otherwise be an open path through the wordline 220. (It should be noted that the example of FIG. 3C can be understood as a 2D rendering of the 3D features of the pillar constriction structure shown in FIG. 3B, and thus shows the constriction as it appears in plan view rather than in cross section.)

[0037] Accordingly, uniform deposition of tungsten-containing materials into constricted regions of semiconductor features can pose significant challenges. Although the above examples relate specifically to the problem of uniformly filing memory wordlines of 3D VNAND memory structures, the methods described herein can be applied to any type of feature in which a relatively constricted path exists from a source of tungsten-containing material to the area of ​​the feature where uniform tungsten deposition is desired.

[0038] One class of techniques for avoiding void formation and achieving uniform tungsten filling of horizontal features involves the combination of tungsten deposition and tungsten etching operations. The general idea is to deposit tungsten until a pinch-off occurs, etch back the pinch-off point to reopen the closed area, and then deposit tungsten again into the previously closed area. In situations where such techniques can be used, a single etching operation interposed between a pair of deposition operations may be sufficient to complete a sufficiently uniform tungsten fill, even within a particular horizontal feature. However, in more challenging situations, additional deposition-etch cycles may be required to adequately fill, depending on the magnitude of the aspect ratio of the structure, the degree of constriction within the horizontal feature to be filled, etc. Additional details regarding the deposition of tungsten using a combination of deposition and etching operations are described in U.S. patent application Ser. No. 14 / 285,505, entitled "METHODS AND APPARATUSES FOR VOID-FREE TUNGSTEN FILL IN THREE-DIMENSIONAL SEMICONDUCTOR FEATURES," filed May 22, 2014, which is incorporated by reference in its entirety for all purposes.

[0039] Boron Transformation In some implementations, tungsten deposition can include conformal boron deposition followed by reduction of a tungsten-containing precursor (such as WF6) with boron to form a layer of tungsten. An example reaction is: WF6(g)+2B(s)→W(s)+BF3(g). Tungsten deposition by boron conversion can occur in forming a tungsten nucleation layer or filling a feature with tungsten. An example of feature filling by boron conversion is shown in FIG. 4. However, it is understood that boron conversion can be useful not only for depositing tungsten for feature filling, but also for depositing tungsten as a nucleation layer and for other purposes.

[0040] FIG. 4 shows a flow diagram illustrating certain operations in such a method for filling a feature by boron conversion. Initially, in operation 410, a thin conformal layer of boron 425 is deposited on titanium nitride layer 413 in feature 401. In operation 420, the thin conformal layer of boron 425 is converted to tungsten layer 427, for example, by the reaction described above. In 430 and 440, the boron deposition and conversion operations are repeated to form another conformal layer of boron 425, which is then converted to tungsten, resulting in the growth of tungsten layer 427. The deposition and conversion reactions can be repeated until the feature is completely filled with tungsten 427. Multiple cycles of thin conformal boron (or another reducing material) and conversion to tungsten can be used to deposit highly conformal, smaller grained, and smoother tungsten, thereby reducing seams that may form using CVD methods that result in large or non-uniform grain growth. In some implementations, each cycle can form a tungsten layer having a thickness of up to about 10 nm. There can be an increase in volume associated with the conversion of boron to tungsten.

[0041] Boron-containing compounds can be used that can decompose or react to form a layer that can reduce a tungsten-containing precursor to form elemental tungsten. Examples include B n Hn+4 , B n H n+6 , B n H n+8 , B n H m where n is an integer from 1 to 10 and m is an integer different from m.

[0042] In some implementations, layer 425 may be any material capable of reducing tungsten precursors, including silicon or silicon-containing materials, phosphorus or phosphorus-containing materials, germanium or germanium-containing materials, and hydrogen. Examples of precursors that can be used to form such layers include SiH4, Si2H6, PH3, SiH2Cl2, and GeH4. Additional examples of the use of boron conversion in tungsten feature filling are described below.

[0043] Additional details regarding the deposition of tungsten using boron-containing compounds are described in U.S. patent application Ser. No. 13 / 851,885, entitled "TUNGSTEN FEATURE FILL," filed Mar. 27, 2013, which is incorporated by reference in its entirety for all purposes.

[0044] Nucleation layer deposition In some implementations, the methods described herein involve depositing a tungsten nucleation layer prior to deposition of the bulk layer. The nucleation layer is typically a thin conformal layer that facilitates subsequent deposition of a bulk tungsten-containing material thereon. According to various implementations, the nucleation layer may be deposited prior to any filling of the feature and / or at a later point during the filling of the feature. For example, in some implementations, the nucleation layer may be deposited following etching of tungsten in the feature.

[0045] In a particular implementation, the nucleation layer is deposited using a pulsed nucleation layer (PNL) technique. In the PNL technique, pulses of a reducing agent, an optional purge gas, and a tungsten-containing precursor are sequentially injected into and purged from a reaction chamber. This process is repeated periodically until a desired thickness is achieved. PNL broadly embodies any cyclic process that sequentially adds reactants to react on a semiconductor substrate, including atomic layer deposition (ALD) techniques. PNL techniques for depositing tungsten nucleation layers are described in U.S. Patent Nos. 6,635,965; 7,005,372; 7,141,494; 7,589,017, 7,772,114, 7,955,972, and 8,058,170, and U.S. Patent Publication No. 2010-0267235, which are incorporated herein by reference in their entirety. The thickness of the nucleation layer may depend on the deposition method of the nucleation layer and the desired quality of the bulk deposition. Generally, the thickness of the nucleation layer is thick enough to support a high quality, uniform bulk deposition. Examples may range from 10 Angstroms to 100 Angstroms.

[0046] Although an example of PNL deposition is described above, the methods described herein are not limited to a particular method of tungsten nucleation layer deposition and include deposition of a bulk tungsten film on a tungsten nucleation layer formed by any method, including PNL, ALD, CVD, and physical vapor deposition (PVD). Furthermore, in certain implementations, bulk tungsten may be directly deposited in a feature without the use of a nucleation layer. For example, in some implementations, the feature surface and / or a previously deposited underlayer supports bulk tungsten deposition. In some implementations, a bulk tungsten deposition process may be performed without the use of a nucleation layer. U.S. Patent Application No. 13 / 560,688, filed July 27, 2012, which is incorporated herein by reference, describes, for example, deposition of a tungsten bulk layer without a nucleation layer.

[0047] In various implementations, deposition of the tungsten nucleation layer may involve exposure to a tungsten-containing precursor, such as tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), and tungsten hexacarbonyl (W(CO)6). In certain implementations, the tungsten-containing precursor is a halogen-containing compound, such as WF6. Organometallic precursors and fluorine-free precursors, such as MDNOW (methylcyclopentadienyl-dicarbonylnitrosyl-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitrosyl-tungsten), may also be used.

[0048] Examples of reducing agents may include boron-containing reducing agents, including diborane (B2H6) and other boranes, silicon-containing reducing agents, including silane (SiH4) and other silanes, hydrazine, and germane. In some implementations, the pulses of the tungsten-containing precursor may alternate with pulses of one or more reducing agents, such as S / W / S / W / B / W, where W represents the tungsten-containing precursor, S represents the silicon-containing precursor, and B represents the boron-containing precursor. In some implementations, a separate reducing agent may not be used, for example, the tungsten-containing precursor may undergo thermal or plasma-assisted decomposition.

[0049] The properties of the PNL tungsten film can be substantially altered by the selection and introduction sequence of the process gas. In particular, it is advantageous to start the PNL tungsten deposition with a single dose of a boron-containing reducing agent (e.g., B2H6) before the first dose of a tungsten-containing gas (e.g., WF6). After the initial dose of B2H6-WF6, the remaining cycles of the PNL tungsten deposition can continue as described above (e.g., alternating SiH4 and WF6 pulses).

[0050] In this technique, diborane (or other boron-containing precursor) reacts on the substrate surface to form a "sacrificial layer" of elemental boron. This sacrificial layer subsequently reacts with a tungsten precursor to form elemental tungsten. The boron deposition process is not a traditional self-limiting ALD-type deposition process (e.g., as opposed to a silane-based reaction). Rather, diborane (or other suitable boron-containing material) thermally decomposes under typical PNL or CVD operating conditions (e.g., 200°C-400°C, 1-300 Torr) to produce a boron film on the dielectric surface. The reaction can proceed as long as the substrate is exposed to the boron reducing agent. However, to ensure that a limited amount of tungsten is actually formed in the subsequent steps, the deposition of diborane is preferably limited to a thickness of about 3-10 angstroms. This may correspond to about 1-3 monolayers of diborane. In the second operation of the process, the elemental boron layer is exposed to a tungsten precursor, which is reduced to elemental tungsten by the boron.

[0051] In some embodiments, the boron operation is carried out at moderate temperatures (e.g., 300°C) to ensure that a sufficient amount of boron is formed on the surface within a reasonable time. With regard to other parameters, the process steps are generally carried out at pressures of about 0.1-300 Torr, with the dose being defined by the flow rate and contact time. In general, the boron-containing reducing agent can be any process-compatible boron compound that can effectively reduce the tungsten precursor to produce a layer of metallic tungsten. Examples of suitable boron-containing reducing agents include hexaborane (B6H 10 ), triborane, and diborane (B2H6).

[0052] Measurements show first-order growth kinetics of boron from B2H6 with an activation energy of about 200 kJ / gmol. Thus, a very thin boron film can be deposited as a sacrificial layer before the first WF6 or other W-containing reagent pulse. The amount of B on the surface is adjusted to provide suitable nucleation sites for WF6 to initiate nucleation and tungsten growth on the entire surface of the wafer. This makes the PNL process highly less sensitive to the variations in the incoming semiconductor wafer substrate. In particular, with a properly optimized B layer from the first B2H6 pulse, it is even possible to nucleate tungsten on the wafer surface with a discontinuous Ti-TiN line barrier film. This is very important for semiconductor contact structures with very high aspect ratios for logic and DRAM devices. The reason is that poor step coverage of Ti and TiN barriers by PVD or CVD often leads to discontinuous films near the bottom of the contact when the aspect ratio of the contact exceeds 10:1 (depth / diameter).

[0053] B2H6 is not without its drawbacks as a reducing agent for PNL tungsten. Because B2H6 is deposited in a thermal CVD process and is not self-limiting, boron deposition from B2H6 can experience step coverage issues. This is typically not seen for features with aspect ratios less than 20:1, but can be problematic for aggressive (DRAM) structures with aspect ratios of 60:1 or greater. SiH4 is self-limiting and can fully saturate any topography given sufficient dose time. Thus, a typical PNL tungsten growth may begin with an initial pulse of B2H6, followed by alternating doses of WF6 and SiH4. The B2H6 dose time may be optimized to provide suitable nucleation sites for subsequent tungsten growth. Boron may also act as a getter to consume excess fluorine produced by the decomposition of WF6. The subsequent doses of WF6 and SiH4 are self-limiting, resulting in uniform and fully conformal tungsten film growth.

[0054] Bulk Deposition In many implementations, tungsten bulk deposition may occur by a CVD process in which a reducing agent and a tungsten-containing precursor are flowed into a deposition chamber to deposit a bulk fill layer in the feature. An inert carrier gas may be used to deliver one or more of the reactant streams, which may or may not be premixed. Unlike PNL or ALD processes, this operation generally involves continuously flowing the reactants until a desired amount is deposited. In certain implementations, the CVD operation may be performed in multiple stages, where multiple periods of continuous and simultaneous reactant flow are separated by periods of diverting one or more reactant flows.

[0055] Various tungsten-containing gases can be used as the tungsten-containing precursor, including but not limited to WF6, WCl6, and W(CO)6. In certain implementations, the tungsten-containing precursor is a halogen-containing compound, such as WF6. In certain implementations, the reducing agent is hydrogen gas, although other reducing agents can be used, including silane (SiH4), disilane (Si2H6), hydrazine (N2H4), diborane (B2H6), and germane (GeH4). In many implementations, hydrogen gas is used as the reducing agent in the CVD process. In some other implementations, a tungsten precursor can be used that can decompose to form a bulk tungsten layer. Bulk deposition can also be performed using other types of processes, including ALD processes.

[0056] Exemplary temperatures can range from 200° C. to 500° C. According to various implementations, any of the CVD W operations described herein can use low temperature CVD W filling, for example, at about 250° C. to 350° C., or at about 300° C.

[0057] According to various implementations, deposition may proceed until a particular feature profile is achieved and / or a particular amount of tungsten is deposited. In some implementations, deposition times and other related parameters may be determined by modeling and / or trial and error. For example, in an early deposition of an inside-out fill process where tungsten can be conformally deposited in a feature until pinch-off, it may be straightforward to determine the thickness of tungsten at which pinch-off is achieved, and the corresponding deposition time, based on the dimensions of the feature. In some implementations, the process chamber may be equipped with various sensors to perform in-situ metrology measurements for endpoint detection of the deposition operation. Examples of in-situ metrology include optical microscopy and X-ray fluorescence (XRF) to determine the thickness of the deposited film.

[0058] It is understood that the tungsten films described herein may contain some amount of other compounds, dopants, and / or impurities such as nitrogen, carbon, oxygen, boron, phosphorus, sulfur, silicon, germanium, etc., depending on the particular precursors and processes used. The tungsten content in the film may range from 20% to 100% (atomic) tungsten. In many implementations, the film is tungsten rich, having at least 50% (atomic) tungsten, or even at least about 60%, 75%, 90%, or 99% (atomic) tungsten. In some implementations, the film may be a mixture of metallic or elemental tungsten (W) and other tungsten-containing compounds, such as tungsten carbide (WC), tungsten nitride (WN), etc.

[0059] CVD and ALD deposition of these materials may include the use of any suitable precursor. For example, CVD and ALD deposition of tungsten nitride may include the use of halogen-containing and halogen-free tungsten-containing and nitrogen-containing compounds, as described further below. CVD and ALD deposition of titanium-containing layers may include the use of titanium-containing precursors, including, for example, tetrakis(dimethylamino)titanium (TDMAT) and titanium chloride (TiCl4), and one or more co-reactants, where appropriate. CVD and ALD deposition of tantalum-containing layers may include the use of precursors such as pentakis-dimethylaminotantalum (PDMAT) and TaF5, and one or more co-reactants, where appropriate. CVD and ALD deposition of cobalt-containing layers may include the use of precursors such as tris(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt, bis(cyclopentadienyl)cobalt, and dicobalt hexacarbonylbutylacetylene, and one or more co-reactants. CVD and ALD deposition of nickel-containing layers can include the use of precursors such as cyclopentadienylallylnickel (CpAllylNi) and MeCp2Ni. Examples of co-reactants can include N2, NH3, N2H4, N2H6, SiH4, Si3H6, B2H6, H2, and AlCl3.

[0060] The distribution of material within a feature may also be characterized by its step coverage. For purposes herein, "step coverage" is defined as the ratio of two thicknesses, i.e., the thickness of the material inside the feature divided by the thickness of the material near the opening. For purposes herein, the term "inside the feature" refers to a middle portion of the feature located near the midpoint of the feature along the feature's axis, e.g., an area about 25%-75%, or in certain embodiments, about 40%-60%, of the distance measured from the opening of the feature along the feature's depth, or an end of the feature located about 75%-95% of the distance measured from the opening of the feature along the feature's depth. The term "near the opening of the feature" or "near the feature opening" refers to the top of the feature located within 25%, or more specifically within 10%, of the edge of the opening, or other element representing the edge of the opening. Step coverage of greater than 100% can be achieved, for example, by filling the feature wider near the center or bottom of the feature than at the feature opening.

[0061] In certain embodiments, the target step coverage of the etched layer is superconformal (greater than 100%), such as at least about 60%, 75%, 100%, or 125%, etc. In certain embodiments, a step coverage of less than about 50%, less than 25%, or even less may be targeted.

[0062] Hydrogen-balanced diborane As previously mentioned, uniformly depositing tungsten within horizontal wordline features of a 3D VNAND structure can pose significant challenges. As the aspect ratio of a 3D VNAND structure increases and the number of stacks of horizontal wordlines increases, precursor gases may need to travel longer distances and narrower paths to areas where uniform tungsten deposition is desired. Difficulties associated with uniform deposition of tungsten in a 3D VNAND structure are discussed in connection with FIGS. 1A-1D, 2A-2B, and 3A-3C.

[0063] The present disclosure relates to the deposition of transition metals, such as tungsten molybdenum, ruthenium, or cobalt, onto horizontally oriented features of a vertical structure of a semiconductor substrate. The semiconductor substrate may include a vertical structure, such as a 3D vertical NAND structure. The semiconductor substrate may further include a plurality of horizontally oriented features, such as wordlines of the 3D vertical NAND structure. The horizontally oriented features may include constrictions. The semiconductor substrate may include a vertical structure, the vertical structure having a plurality of horizontally oriented features with openings in sidewalls of the vertical structure, the features being fluidically accessible from the vertical structure through the openings. An example of a vertical structure having a plurality of horizontally oriented features is shown in Figures 2A-2B.

[0064] The deposition of void-free tungsten fill, or other transition metal fill, depends in part on the transport of a sufficient amount of precursor gas down the vertical structure, through the openings in the sidewalls of the vertical structure, past the pillars that create the constriction, and into the horizontally oriented features. The vertical structure and the horizontally oriented features may have a high aspect ratio. In some implementations, the horizontally oriented features may have a depth on the order of several micrometers. The horizontally oriented features may provide a large surface area where uniform transition metal deposition is desired. Accordingly, it may be very difficult to provide a sufficient amount of precursor gas to travel long distances across narrow barriers to saturate a large surface area of ​​the semiconductor substrate.

[0065] Diborane reacts at the substrate surface to form a "sacrificial layer" of elemental boron, which may subsequently react with the metal precursor to form the metal layer, with elemental boron acting as a reducing agent. Deposition of diborane onto the substrate surface is not a self-limiting process and typically results in poor step coverage of the metal layer on the substrate surface. Poor step coverage can result in non-uniform deposition of the metal layer and voids in the metal fill. In addition, diborane is typically delivered with a nitrogen (N2) balance that limits the diborane concentration. For example, diborane is provided with a nitrogen balance such that the limit of diborane concentration is about 5% or less by volume of diborane. Providing such a limit on diborane concentration may be due, at least in part, to controlling the stability of diborane to limit diborane decomposition. With these limitations in diborane concentration, very high flow rates and / or very long dosing times are required to deliver a sufficient dose to the substrate to cover a large surface area and provide suitable nucleation sites for subsequent metal (e.g., tungsten) growth. Higher gas flows and longer dosing times have a negative impact on gas usage and throughput.

[0066] The present disclosure relates to supplying diborane gas with a balance of diborane and hydrogen (H2) instead of supplying diborane gas with a balance of diborane. A boron-containing gas mixture may be supplied before entering the deposition chamber, the boron-containing gas mixture including diborane and hydrogen. Hydrogen is not pulsed separately from diborane, for example, hydrogen is pulsed as a purge gas following diborane. Hydrogen is also not delivered into the deposition chamber from a separate gas line or separate gas source, for example, hydrogen is delivered with diborane as a carrier gas. Diborane is delivered together with hydrogen as a co-reactant with diborane into the deposition chamber, and diborane is balanced with hydrogen in the gas mixture. In some implementations, diborane is stored with hydrogen in the gas supply before delivery to the deposition chamber.

[0067] A gas mixture of diborane and hydrogen may provide a higher diborane concentration than a gas mixture of diborane and nitrogen. In some implementations, the gas mixture includes at least 20% diborane by volume balanced with hydrogen. In some implementations, the gas mixture includes 20-50% diborane by volume balanced with hydrogen. A higher diborane concentration results in a higher partial pressure dose of diborane delivered to the semiconductor substrate. A higher partial pressure dose of diborane can allow more diborane to reach into the horizontally oriented features of the vertical structure and saturate a larger surface area. For example, a higher partial pressure dose of diborane can facilitate a larger amount of diborane to reach the horizontal wordline features of a 3D vertical NAND structure. This can be done without necessarily increasing the gas flow and dose time.

[0068] Providing hydrogen-balanced diborane stabilizes diborane and limits its decomposition. As diborane decomposes, elemental boron and hydrogen gas are formed: B2H6←→2B(S)+3H2(g). The decomposition of diborane is a reversible reaction, so adding hydrogen slows the decomposition of diborane. Figure 5 shows a graph of diborane concentration over hundreds of days, where diborane is mixed with nitrogen balance, hydrogen balance, or hydrogen and nitrogen balance. As shown in Figure 5, nitrogen-balanced diborane can lead to a decrease in diborane concentration from 5% diborane by volume to 4.5% diborane by volume in about one month, while hydrogen-balanced diborane can maintain the diborane concentration at about 5% diborane by volume for several years.

[0069] Diborane can be pyrolyzed to produce higher boranes. Diborane can dissociate to boranes as shown below, which can act as reactive intermediates that undergo a series of reactions leading to higher boranes and molecular hydrogen. Further steps can yield successively higher boranes. The higher boranes produced by pyrolysis can shorten the hardware life of systems and devices that store diborane. The higher boranes can eventually decompose to form elemental boron and hydrogen. (1) B2H6 ←→ 2BH3 (2) B2H6+BH3←→B3H9 (3) B3H9 ←→ B3H7 + H2 (rate-determining step) (4) BH3+B3H7←→B4H 10 (5) B2H6+B3H7←→B5H 11 +H2 Adding hydrogen to diborane in the gas mixture can slow the thermal decomposition of diborane. Thus, hydrogen-balanced diborane stabilizes the decomposition of diborane. Diborane can be slowed down during storage, delivery, and when adsorbed on a substrate surface.

[0070] The deposition of diborane on a substrate surface is not a self-limiting process. Accordingly, unlike other reducing agents, the decomposition of diborane to elemental boron is not a self-limiting reaction. Instead of being limited to the number of reactive sites on the substrate surface, boron can be continuously formed on the substrate surface by the decomposition of diborane. Typically, boron deposition by the decomposition of diborane results in poor step coverage, in part due to not being a self-limiting process. However, adding hydrogen to balance diborane slows the decomposition, which may improve step coverage by boron deposition.

[0071] By using hydrogen-balanced diborane, a boron layer can be formed on the substrate surface that acts as a reducing agent in converting the metal precursor to metal. This can occur in any part of the sequence of filling the feature with a metal (e.g., tungsten). Thus, diborane can be deposited before, during, or after bulk metal filling of the feature. In some implementations, diborane can be deposited in a "soak" process or PNL process before the bulk metal filling. In some implementations, diborane can be deposited in a soak process or PNL process when the bulk metal filling is partially completed in the bulk metal filling. In some implementations, multiple soak and / or nucleation cycles can be combined before or during the bulk metal filling of the feature. In some implementations, diborane can be deposited in a CVD process with the metal precursor for the bulk metal filling of the feature.

[0072] A "soak" or "initiation soak" process can pretreat the substrate surface by exposing the substrate to a gas, which promotes metal growth without nucleation delay. In some implementations, the soak process can expose the substrate surface to a gas, such as diborane, in its gaseous state for about 1 to about 60 seconds. As an example, the soak process can include a single pulse (and purge) of diborane prior to a pulsed nucleation process. This can reduce or eliminate nucleation delay by establishing a boron layer as a reducing agent on the substrate surface, thereby providing an optimal surface for metal nucleation regardless of any adhesion layer (such as a Ti-TiN layer) applied during substrate pretreatment. It is noted that the soak step can be viewed as an initial cycle, such as a long initial dose of diborane used to improve nucleation density and reduce nucleation delay.

[0073] In a pulsed nucleation process, a PNL technique may be used to deposit a thin conformal metal layer that facilitates subsequent bulk metal deposition. In a pulsed nucleation process, pulses of diborane or silane, optional purge gas, and metal precursor are sequentially injected into and purged from the deposition chamber. This process is repeated until a desired thickness is achieved. In some implementations, an immersion step and a pulsed nucleation step may be combined before or during the bulk metal filling of the feature. The immersion step and the pulsed nucleation step may occur in any sequence and any number of times before or during the bulk metal filling of the feature. In terms of sequences, an immersion process may be followed by a pulsed nucleation process, or a pulsed nucleation process may be followed by an immersion process. Examples of various sequences in depositing tungsten are shown in Figures 6A-6D.

[0074] FIG. 6A shows a schematic diagram of a tungsten stack formed according to a sequence of soak, pulse nucleation, and bulk fill operations. The tungsten stack of FIG. 6A may be formed according to a sequence of operations B / BW / B / W, where B represents the soak step, BW represents the diborane pulse nucleation step, and W represents the bulk tungsten fill step. In FIG. 6A, in an initial soak step, diborane may be deposited to establish a first boron layer 602 that acts as a reducing agent for the tungsten-containing precursor, which may be provided as a reactant in a subsequent step. In a subsequent pulse nucleation step, diborane, an optional purge gas, and a tungsten-containing precursor may be pulsed sequentially to form a tungsten nucleation layer 604. A subsequent soak step may further deposit diborane on top of the tungsten nucleation layer 604. The deposited diborane can establish a second boron layer 606 that acts as a reducing agent for a tungsten-containing precursor that can be supplied as a reactant in a subsequent step. In a subsequent bulk tungsten fill step, CVD techniques can be used to simultaneously and continuously flow the reducing agent and tungsten-containing precursor reactants until a desired amount of tungsten 608 is deposited.

[0075] FIG. 6B shows a schematic diagram of a tungsten stack formed according to another sequence of soaking, pulsed nucleation, and bulk filling operations. The tungsten stack in FIG. 6B may be formed according to a sequence of operations of B / BW / B / SW / W, where SW represents a silane pulsed nucleation step. As in FIG. 6A, the initial soaking step is followed by a pulsed nucleation step using diborane, followed by a soaking step. However, unlike FIG. 6A, FIG. 6B adds a subsequent pulsed nucleation step in which silane, an optional purge gas, and a tungsten-containing precursor are pulsed sequentially to form an intermediate tungsten nucleation layer 610. In the subsequent bulk tungsten filling step, CVD techniques can be used to simultaneously continuously flow the reducing agent and tungsten-containing precursor reactants until a desired amount of tungsten 608 is deposited.

[0076] FIG. 6C shows a schematic diagram of a tungsten stack formed according to another sequence of soak, pulsed nucleation, and bulk fill operations. The tungsten stack of FIG. 6C may be formed according to a SW / B / SW / B / W operation sequence. As in FIG. 6A, an initial soak step is followed by a pulsed nucleation step using diborane, followed by a soak step, followed by a bulk tungsten fill step. However, unlike FIG. 6A, FIG. 6C adds an initial pulsed nucleation step before the initial soak step, in which silane, an optional purge gas, and a tungsten-containing precursor are pulsed sequentially to form an initial tungsten nucleation layer 612.

[0077] FIG. 6D shows a schematic diagram of a tungsten stack formed according to another sequence of soak, pulse nucleation, and bulk fill operations. The tungsten stack of FIG. 6D may be formed according to a BW / W / B / BW / B / W operation sequence. In FIG. 6D, in an initial pulse nucleation step, diborane, an optional purge gas, and a tungsten-containing precursor may be pulsed sequentially to form a first tungsten nucleation layer 614. In a subsequent bulk tungsten fill step, a CVD technique may be used to simultaneously and continuously flow a reactant of a reducing agent and a tungsten-containing precursor until a desired amount of tungsten 616 is formed. The desired amount of tungsten 616 formed during this step may only partially complete the bulk tungsten fill process. In a subsequent soak step, diborane may be deposited to establish a first boron layer 618 that acts as a reducing agent for the tungsten-containing precursor, which may be provided as a reactant in a subsequent step. Such a step may "interrupt" the bulk tungsten filling process. In other words, if the bulk tungsten filling process is not fully completed, diborane may be deposited in a soak step and / or a pulsed nucleation step. In a subsequent pulsed nucleation step, diborane, an optional purge gas, and a tungsten-containing precursor may be pulsed sequentially to form a second tungsten nucleation layer 620. A subsequent soak step may further deposit diborane on the second tungsten nucleation layer 620. The deposited diborane may establish a second boron layer 622 that acts as a reducing agent for the tungsten-containing precursor, which may be provided as a reactant in a subsequent step. In a subsequent bulk tungsten filling step, the reducing agent and the tungsten-containing precursor reactants may be flowed simultaneously and continuously using CVD techniques until a desired amount of tungsten 624 is deposited.

[0078] 7 is a flow diagram illustrating an example method of depositing a transition metal layer using hydrogen-balanced diborane. Process 700 may be performed in a different order or with different, fewer, or additional operations. In some implementations, the blocks of process 700 may be performed using a system controller, as described below. In some implementations, the blocks of process 700 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media.

[0079] Process 700 involves the delivery of diborane to a substrate surface to deposit metal within a plurality of horizontally oriented features within a vertical structure. The diborane is delivered in the form of a gas mixture having diborane balanced with hydrogen. The delivery of diborane and conversion to metal may be a step in a step sequence that deposits metal within the features.

[0080] In block 702 of process 700, a gas mixture is optionally delivered to a gas delivery line, the gas mixture including diborane balanced with hydrogen. Instead of delivering diborane balanced with nitrogen, diborane may be delivered balanced with hydrogen. A nitrogen balance limits the concentration of diborane (e.g., 5% by volume or less), shortens the hardware life and degrades the step coverage at the substrate surface. However, a hydrogen balance increases the concentration of diborane (e.g., 20% by volume or more), extends the hardware life and improves the step coverage at the substrate surface.

[0081] The gas supply line may be coupled to a deposition chamber for depositing the transition metal on the substrate surface. Hydrogen-balanced diborane is supplied from a common source before being delivered into the deposition chamber. In some implementations, the gas mixture is substantially free of nitrogen.

[0082] At block 704 of process 700, a gas mixture is introduced into a deposition chamber from a gas supply line and onto a surface of a semiconductor substrate. The semiconductor substrate includes a vertical structure with a plurality of horizontally oriented features. The diborane decomposes to form a boron layer in the horizontally oriented features. In some implementations, hydrogen-balanced diborane may be flowed with a suitable inert carrier gas, such as hydrogen, nitrogen, or argon.

[0083] In some implementations, the vertical structure includes a 3D vertical NAND structure. In some implementations, the plurality of horizontally oriented features may include horizontal wordline features. The horizontal wordline features may have a high aspect ratio, which may represent the ratio of the depth or length (L) of the wordline feature to the height (h) of the gap of the wordline feature. For a single step contact scheme, the aspect ratio may be calculated as L:2h, while for a dual step contact scheme, the aspect ratio may be calculated as L:h. In some implementations, the horizontal wordline features may have an aspect ratio of at least about 4:1, or at least about 6:1, or at least about 10:1, or at least about 20:1, or at least about 60:1, or even higher. In some implementations, the horizontal wordline features may have a depth on the order of a few micrometers. The horizontal wordline features may include a constriction. In some implementations, the semiconductor substrate may include a vertical structure having a plurality of horizontally oriented features with openings in a sidewall of the vertical structure, the features being fluidically accessible from the vertical structure through the openings. An example of a vertical structure having a plurality of horizontally oriented features is shown in Figures 2A-2B.

[0084] To effectively deposit in the large surface area 3D vertical NAND structures, the diborane dosing concentration can be high. Hydrogen-balanced diborane delivers more diborane dosing without necessarily increasing gas flow and dose time. Thus, sufficient diborane can be deposited throughout the 3D vertical NAND structures and to the furthest extents of the horizontal wordline features. The deposited diborane may undergo thermal decomposition to form a boron layer in the horizontally oriented features, with the boron layer acting as a reducing agent. Due in part to hydrogen slowing down the decomposition of diborane to elemental boron, the boron layer may be conformally deposited in the horizontally oriented features of the vertical structures, with the step coverage of the boron layer being at least 70%, at least 80%, at least 85%, at least 90%, or at least 95%.

[0085] In some implementations, the semiconductor substrate is exposed to a pulse of hydrogen-balanced diborane for a period of time, for example, from about 0.1 seconds to about 10 seconds, in a PNL cycle. The pulse may be optionally followed by a purge with a suitable purge gas, such as hydrogen, nitrogen, or argon. In some implementations, the purge gas may be provided in the background throughout the PNL cycle. The diborane on the semiconductor substrate decomposes to form a boron layer. The semiconductor substrate may then be exposed to a transition metal precursor, such as a tungsten-containing precursor, for a period of time in a PNL cycle. In some implementations, such period of time may be from about 0.1 seconds to about 10 seconds.

[0086] In some implementations, the semiconductor substrate is exposed to a "soak" of hydrogen-balanced diborane for a period of time, for example, from about 1 second to about 60 seconds. The diborane may be in a gaseous state. The pulse may optionally be followed by a purge with a suitable purge gas, such as hydrogen, nitrogen, or argon.

[0087] In block 706 of process 700, the boron layer is converted to a transition metal layer in the semiconductor substrate. For example, the transition metal layer may include molybdenum, ruthenium, cobalt, or tungsten. In some implementations, the semiconductor substrate is exposed to a transition metal precursor, such as a tungsten-containing precursor. In some implementations, the tungsten-containing precursor includes tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), or tungsten hexacarbonyl (W(CO)6). The tungsten-containing precursor may be reduced by the boron layer to form elemental tungsten. In some implementations, the transition metal layer may be conformally deposited in the horizontally oriented features of the vertical structure, and the step coverage of the transition metal layer is at least 85%, at least 90%, or at least 95%.

[0088] In some implementations, the process 700 further includes exposing the semiconductor substrate to a reducing gas, the reducing gas including silane, disilane, or hydrogen. In some implementations, the silane reducing gas may be deposited in a conventional PNL process. The silane reducing gas contacts the substrate for a period of about 0.1 seconds to about 10 seconds and is then purged from the deposition chamber using a purge gas. The silane reducing gas may convert the transition metal precursor to a metal. In some implementations, the silane reducing gas, disilane reducing gas, or hydrogen reducing gas is used in a CVD process for bulk deposition of metals.

[0089] Device The methods presented herein may be implemented in a variety of apparatus available from a variety of vendors. Examples of apparatus that may be suitable include Novellus Concept-1™ ALTUS™, Concept-2 ALTUS™, Concept-2 ALTUS-S™, Concept-3 ALTUS™, and ALTUS Max™ deposition systems, or any of a variety of other commercially available chemical vapor deposition (CVD) tools. FIG. 8 shows a schematic diagram of an apparatus 800 for processing a partially fabricated semiconductor substrate in accordance with certain embodiments. The apparatus 800 includes a chamber 818 having a pedestal 820, a showerhead 814, an in-situ plasma generator 816, and a remote plasma generator 806. The pedestal 820 is configured to support a semiconductor substrate 828. The apparatus 800 also includes a system controller 822 for receiving inputs and / or communicating control signals to various devices.

[0090] A deposition reagent including diborane balanced with hydrogen may be provided from a source 802, which may be a storage tank. In some implementations, the deposition reagent is provided to a remote plasma generator 806. Any suitable remote plasma generator may be used to activate the deposition reagent before it is introduced into the deposition chamber 818. For example, remote plasma generating units such as ASTRON® i Type AX7670, ASTRON® e Type AX7680, ASTRON® ex Type AX7685, ASTRON® hf-s Type AX7645, all available from MKS Instruments, Andover, Massachusetts, may be used. In general, a remote plasma generator unit is typically a self-contained device that uses the provided deposition reagent to generate a free radical-based plasma (which may be weakly ionized to some degree). A remote plasma generator is a high-power RF generator that provides energy to the electrons in the plasma. This energy is then transferred to the neutral reagents, resulting in a temperature of around 20,00 K, causing thermal dissociation of these molecules. The remote plasma generator unit, due to its high RF energy and special channel geometry, can dissociate more than 60% of the incoming reagents, as most of this energy becomes adsorbed by the etchant.

[0091] 8, one or more reagents flow from a remote plasma generator 806 through a connecting line 808 into a deposition chamber 818 where the mixture is distributed through a showerhead 814. In other embodiments, one or more reagents flow directly into the deposition chamber 818, bypassing the remote plasma generator 806 entirely (e.g., the apparatus 800 does not include such a generator 806). Alternatively, one or more reagents do not need to be activated, so that, for example, the remote plasma generator 806 may be turned off while one or more reagents are flowing into the deposition chamber 818. Additionally, in certain embodiments, an inert gas, such as argon, helium, etc., is also provided from a source 803, which may be a storage tank.

[0092] Once the precursor reagents are introduced into the deposition chamber 818, in situ plasma activation can be achieved via an internal plasma generator 816 attached to the showerhead 814 and pedestal 820. In a particular embodiment, the internal plasma generator 816 is a high frequency (HF) RF generator capable of delivering about 0 W to 10,000 W of power at a frequency of about 1 to 100 MHz. In a more particular embodiment, the HF RF generator can deliver about 0 to 5,000 W of power at about 13.56 MHz. In some implementations, the internal plasma generator 816 can generate an in situ plasma to enhance removal of the deposited metal.

[0093] The chamber 818 may include sensors 824 for sensing various process parameters such as the extent of deposition and etching, concentration, pressure, temperature, etc. The sensors 824 may provide information regarding chamber conditions during processing to the system controller 822. Examples of the sensors 824 include mass flow controllers, pressure sensors, thermocouples, etc. The sensors 824 may also include infrared or optical detectors for monitoring the presence of gases in the chamber and controlling measurements. The sensors 824 provide information that may be used to determine the flow rates of reducing agent and tungsten-containing precursor to the processing chamber, as well as the flow rates of plasma species from the remote plasma generator 806 and its precursors to the remote plasma generator 806.

[0094] The deposition and selective removal operations generate various volatile species that are exhausted from the deposition chamber 818. Moreover, the processing is carried out at a certain predetermined pressure level in the chamber 818. Both of these functions are accomplished using a vacuum outlet 826, which may be a vacuum pump.

[0095] In certain embodiments, a system controller 822 is used to control process conditions and parameters during metal deposition and etching operations. The system controller 822 typically includes one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor control boards, etc. Typically, there will be a user interface associated with the system controller 822. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices, e.g., a pointing device, a keyboard, a touch screen, a microphone, etc.

[0096] In certain embodiments, the system controller 822 controls the substrate temperature, chamber pressure, reagent flow rates, power output and operating frequency (or frequency range) of the remote plasma generator 806, power output and operating frequency (or frequency range) of the in situ plasma generator 816, and other process parameters. The system controller 822 executes system control software and instructions to provide the aforementioned control. In some embodiments, other computer programs stored on memory devices associated with the controller may be used.

[0097] The computer program code for controlling the processes in the process sequence can be written in any conventional computer readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. The compiled object code or script is executed by the processor to perform the tasks identified in the program. The system software may be designed or configured in many different ways. For example, subroutines or control objects for various chamber components may be written to control the operation of the chamber components necessary to carry out the described process. Examples of programs or portions of programs for this purpose include substrate temperature control code, chamber pressure control code, reagent flow rate control code, process gas control code, remote plasma generator control code (possibly including power output and operating frequency control code), in situ plasma generator control code (possibly including power output and operating frequency control code), and control code for other process parameters.

[0098] Parameters for controlling the substrate temperature, chamber pressure, reagent flow rates, power output and operating frequency (or frequency range) of the remote plasma generator, power output and operating frequency (or frequency range) of the in situ plasma generator, and other process parameters may be provided by a user in the form of a recipe or may be entered using a user interface.

[0099] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 822. Signals for controlling the process are output to analog and digital output connections of the apparatus 800.

[0100] In some implementations, the system controller 822 is configured with instructions to perform the following operations: introducing a gas mixture from a gas supply line into a deposition chamber and to a surface of a semiconductor substrate, the gas mixture including diborane balanced with hydrogen, the semiconductor substrate including a vertical structure having a plurality of horizontally oriented features, the diborane decomposing to form a boron layer in the horizontally oriented features; and converting the boron layer to a transition metal layer in the semiconductor substrate, hi some implementations, converting the boron layer includes exposing the boron layer to a transition metal precursor.

[0101] FIG. 9 shows an example of a multi-station apparatus 900. The apparatus 900 includes a process chamber 901 and one or more cassettes 903 (e.g., Front Opening Unified Pods (FOUPs)) for holding substrates to be processed as well as substrates that have completed processing. The chamber 901 may have multiple stations, for example, 2 stations, 3 stations, 4 stations, 5 stations, 6 stations, 7 stations, 8 stations, 10 stations, or any other number of stations. The number of stations is typically determined by the complexity of the processing operations and the number of these operations that can be performed in a shared environment. FIG. 9 shows a process chamber 901 that includes six stations, labeled 911-916. All stations in a multi-station apparatus 900 with a single process chamber 901 are exposed to the same pressure environment. However, each station may have a designated reactant distribution system, and local plasma and heating conditions achieved by a dedicated plasma generator and pedestal as shown in FIG. 8.

[0102] Substrates to be processed are loaded from one of the cassettes 903 through the load lock 905 into the station 911. An external robot 907 may be used to transfer the substrates from the cassette 903 into the load lock 905. In the illustrated embodiment, there are two separate load locks 905. These are typically equipped with substrate transfer devices to move substrates from the load lock 905 into the station 911 (once the pressure has equilibrated to a level corresponding to the internal environment of the process chamber 901) and from station 916 back into the load lock 905 for removal from the processing chamber 901. A mechanism 909 is used to transfer substrates between the processing stations 911-916 and to support some substrates during processing, as described below.

[0103] In certain embodiments, one or more stations may be reserved for heating the substrate. Such stations may have heat lamps (not shown) positioned above the substrate and / or a heated pedestal supporting the substrate similar to that shown in FIG. 8. For example, station 911 may be used to receive the substrate from a load lock and preheat the substrate prior to further processing. Other stations may be used for filling high aspect ratio features, including deposition and etch operations.

[0104] After the substrate is heated or otherwise processed in station 911, the substrate is moved sequentially to processing stations 912, 913, 914, 915, and 916, which may or may not be arranged in sequence. The multi-station apparatus 900 is configured such that all stations are exposed to the same pressure environment. In doing so, the substrate may be transferred from station 911 to other stations within the chamber 901 without the need for transfer ports such as load locks.

[0105] In certain embodiments, one or more stations may be used to fill a feature with a tungsten-containing material. For example, station 912 may be used for an initial deposition operation, and station 913 may be used for a corresponding selective removal operation. In embodiments where deposition-removal cycles are repeated, station 914 may be used for another deposition operation, and station 915 may be used for another partial removal operation. Station 916 may be used for a final filling operation. It should be understood that any configuration of station designations for a particular process (heating, filling, and removal) may be used.

[0106] As an alternative to the multi-station apparatus described above, the method may be realized in a single substrate chamber or in a multi-station chamber that processes substrates in a batch mode (i.e., non-sequential) within a single processing station. In this aspect of the invention, the substrate is loaded into the chamber and placed on a pedestal in a single processing station (whether in an apparatus with only one processing station or an apparatus with multiple stations operating in batch mode). The substrate may then be heated and a deposition operation may be performed. Then, the process conditions in the chamber may be adjusted and selective removal of the deposition layer may be performed. This process may continue with one or more deposition-removal cycles and a final fill operation, all in the same station. Alternatively, a single-station apparatus may be used initially to perform only one of the operations in the new method (e.g., deposition, selective removal, final fill) on multiple wafers, and then the substrate may be returned to the same station or moved to a different station (e.g., in a different apparatus) to perform one or more of the remaining operations.

[0107] FIG. 10 is a schematic diagram of a multi-chamber apparatus 1020 that may be used in accordance with certain embodiments. As shown, the apparatus 1020 has three separate chambers 1021, 1023, and 1025. Two pedestals are shown for each of these chambers. It should be understood that the apparatus may have any number of chambers (e.g., 1, 2, 3, 4, 5, 6, etc.), and each chamber may have any number of chambers (e.g., 1, 2, 3, 4, 5, 6, etc.). Each chamber 1021-1025 has its own pressure environment that is not shared between the chambers. Each chamber may include one or more corresponding transfer ports (e.g., load locks). The apparatus may also include a shared substrate handling robot 1027 for transferring substrates between the transfer ports and one or more cassettes 1029.

[0108] As mentioned above, separate chambers may be used for depositing tungsten-containing materials and selectively removing these deposited materials in a subsequent operation. Separating these two operations into different chambers can help substantially improve processing speed by maintaining the same environmental conditions in each chamber. In other words, the chamber does not have to change its environment from the conditions used for deposition to the conditions used for selective removal and back again, which may involve different precursors, different temperatures, pressures, and other process parameters. In certain embodiments, transferring a partially fabricated semiconductor substrate between two or more different chambers is faster than changing the environmental conditions of those chambers.

[0109] In some embodiments, a system controller (which may include one or more physical or logical controllers) controls some or all of the operation of the etch chambers, deposition chambers, and / or multi-module tools including one or more etch modules and / or one or more deposition modules. The system controller may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions that effectuate the appropriate control operations are executed by the processor. The instructions may be stored in a memory device associated with the controller, or the instructions may be provided over a network. In certain embodiments, the system controller executes system control software.

[0110] The system control software may include instructions that control the application timing and / or magnitude of any one or more of the following chamber operating conditions: gas mixture and / or composition, chamber pressure, chamber temperature, wafer temperature, bias applied to the wafer, frequency and power applied to coils or other plasma generating components, wafer position, wafer movement speed, and other parameters of the particular process being performed by the tool. The system control software may be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be written to control the operation of the process tool components necessary to perform the various process tool processes. The system control software may be coded in any suitable computer readable programming language.

[0111] In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller. Instructions for setting process conditions for an etch stage may be included in a corresponding etch recipe stage, for example. In some embodiments, recipe stages may be sequenced such that all instructions for a process stage are executed simultaneously with that process stage. Instructions for setting process conditions for a deposition stage may be included in a corresponding deposition recipe stage.

[0112] In some embodiments, other computer software and / or programs may be used. Examples of programs or portions of programs for this purpose include a substrate positioning program, a process gas composition control program, a pressure control program, a heater control program, and an RF power control program.

[0113] In some cases, the controller controls the gas concentrations, the wafer movement, and / or the power supplied to the coil and / or the electrostatic chuck. In some cases, the controller controls the gas concentrations, the wafer movement, and / or the power supplied to the remote plasma generator.

[0114] The controller may control gas concentrations, for example, by opening and closing associated valves to generate one or more inlet gas flows that provide the required reactants at the appropriate concentrations. Wafer movement may be controlled, for example, by directing a wafer alignment system to move as desired. Power supplied to the coils and / or chuck and / or remote plasma generators may be controlled to provide particular RF power levels. The controller may control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, etc. reach particular thresholds), operation timing (e.g., opening valves at particular times during the process), or based on instructions received from a user.

[0115] Photolithography The apparatus / processes described herein above may be used in conjunction with tools or processes for lithographic patterning, for example for the creation or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, such tools / processes will be used or performed together in a common manufacturing facility. Lithographic patterning of films typically includes some or all of the following operations, each of which is enabled by multiple enabling tools: (1) Applying a photoresist onto a workpiece, i.e., a substrate, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate, oven, or UV curing tool; (3) exposing the photoresist to visible light, UV light, or x-rays using a tool such as a wafer stepper; (4) using a tool such as a wet bench to develop the resist, thereby selectively removing and patterning the resist; (5) transferring the resist pattern to the underlying film or workpiece by using a dry etching tool or a plasma-assisted etching tool; and (6) removing resist using tools such as RF or microwave plasma resist strippers.

[0116] Other embodiments Although the foregoing disclosed processes, methods, systems, apparatus, and compositions have been described in detail in connection with specific embodiments for purposes of clarity and understanding, it will be apparent to those skilled in the art that there are many alternative ways of implementing these processes, methods, systems, apparatus, and compositions that fall within the spirit of the present disclosure. Accordingly, the embodiments described herein should be considered illustrative of the disclosed inventive concepts, and not limiting, and should not be used as an impermissible basis for unnecessarily limiting the scope of any claims ultimately directed to the subject matter of this disclosure.

Claims

1. 1. A method for depositing a transition metal layer, comprising the steps of: A boron-containing precursor and hydrogen (H) are delivered from a common gas supply line to a process chamber having a semiconductor substrate. 2 ), wherein the semiconductor substrate includes one or more vertical structures each having a plurality of horizontally oriented features, the boron-containing precursor reacts with a surface of the semiconductor substrate to form a boron layer in the plurality of horizontally oriented features, and the boron-containing precursor thermally decomposes on the surface of the semiconductor substrate under a pulsed nucleation layer (PNL) process or a chemical vapor deposition (CVD) process to form the boron layer; exposing the semiconductor substrate to a transition metal precursor to convert the boron layer to the transition metal layer in a plurality of horizontally oriented features of the semiconductor substrate; A method comprising:

2. 2. The method of claim 1 , The method, wherein the plurality of horizontally oriented features are wordlines fluidly accessible from the one or more vertical structures through openings in the one or more vertical structures.

3. 2. The method of claim 1 , The method of claim 1, wherein the boron-containing precursor comprises diborane.

4. 4. The method of claim 3, The method of claim 1, wherein the gas mixture comprises at least 20% by volume diborane, balanced with hydrogen.

5. 2. The method of claim 1 , The method of claim 1, wherein the transition metal layer comprises molybdenum, ruthenium, cobalt, or tungsten.

6. 6. The method of claim 5, The method of claim 1, wherein the transition metal layer comprises molybdenum.

7. 2. The method of claim 1 , The gas mixture is essentially nitrogen (N 2 ).

8. 2. The method of claim 1 , The method of claim 1, wherein the boron-containing precursor is stored with the hydrogen prior to delivery to the process chamber.

9. 1. A method for depositing a transition metal on a semiconductor substrate, comprising the steps of: Depositing a first boron layer on the semiconductor substrate, comprising: 2 H 6 ) and hydrogen (H 2 ), wherein the diborane reacts with a surface of the semiconductor substrate to form the first boron layer; and sequentially pulsing diborane and a first transition metal precursor to form a first nucleation layer of the transition metal from the first boron layer on the semiconductor substrate; exposing the semiconductor substrate to diborane to form a second boron layer; sequentially pulsing silane and a second transition metal precursor to form a second nucleation layer of said transition metal; A method comprising:

10. 10. The method of claim 9, the first transition metal precursor and the second transition metal precursor each comprise a tungsten-containing precursor, and the first transition metal layer and the second transition metal layer each comprise tungsten.

11. 10. The method of claim 9, The method of claim 1, wherein the semiconductor substrate includes one or more vertical structures each having a plurality of horizontally oriented features, the plurality of horizontally oriented features being wordlines fluidly accessible from the one or more vertical structures through openings in the one or more vertical structures.

12. 10. The method of claim 9 further comprising: exposing the semiconductor substrate to a reducing agent and a third transition metal precursor to deposit a bulk layer of the transition metal.

13. 1. A method for depositing a transition metal on a semiconductor substrate, comprising the steps of: sequentially pulsing diborane and a first transition metal precursor to deposit a nucleation layer of the transition metal on the semiconductor substrate; exposing the semiconductor substrate to a reducing agent and a second transition metal precursor to form a bulk layer of the transition metal; Depositing a first boron layer on the semiconductor substrate, comprising: 2 H 6 ) and hydrogen (H 2 ), wherein the diborane reacts with a surface of the semiconductor substrate to form the first boron layer; and sequentially pulsing diborane and a third transition metal precursor to form a second nucleation layer of said transition metal; A method comprising:

14. 14. The method of claim 13, The method of claim 1, wherein the first transition metal precursor and the second transition metal precursor each comprise a tungsten-containing precursor and the transition metal comprises tungsten.

15. 14. The method of claim 13, The method of claim 1, wherein the semiconductor substrate includes one or more vertical structures each having a plurality of horizontally oriented features, the plurality of horizontally oriented features being wordlines fluidly accessible from the one or more vertical structures through openings in the one or more vertical structures.

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