Memory system

Abstract

To shorten the time period of data transfer.SOLUTION: A memory system in an embodiment comprises a nonvolatile memory that includes a plurality of memory packages, a plurality of memory dies provided in respective ones of the plurality of memory packages, and a plurality of planes provided in respective ones of the plurality of memory dies and respectively storing data and a memory controller that reads data from the nonvolatile memory based on round-robin processing. The memory controller, when selecting a plane to execute data transfer in the next cycle from among the plurality of planes, selects a plane belonging to a memory package different from a memory package to which the plane under data transfer belongs by the round-robin processing.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The embodiments relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art NAND flash memories capable of storing data in a non-volatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2015 / 0212732 [Patent Document 2] US Patent Application Publication No. 2019 / 0214087 [Patent Document 3] US Patent Application Publication No. 2022 / 0084568 Summary of the Invention [Problem to be solved by the invention]

[0004] Reduce the duration of data transfer. [Means for solving the problem]

[0005] The memory system of the embodiment includes a non-volatile memory including a plurality of memory packages, a plurality of memory dies provided in each of the plurality of memory packages, and a plurality of planes provided in each of the plurality of memory dies, each of which stores data, and a memory controller that reads data from the non-volatile memory based on a round robin process, and when the memory controller selects a plane from the plurality of planes to perform a data transfer in the next cycle, the memory controller selects, by the round robin process, a plane that belongs to a memory package different from the memory package to which the plane currently transferring data belongs. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing a configuration of an information processing system according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing the configuration of a nonvolatile memory in the memory system according to the first embodiment. [Diagram 3] FIG. 2 is a diagram showing the configuration of a memory controller in the memory system according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing the functional configuration of the memory system according to the first embodiment. [Diagram 5] 4 is a flowchart showing the operation of the memory system according to the first embodiment. [Figure 6] 4A to 4C are diagrams for explaining the effects of the memory system according to the first embodiment; [Figure 7] FIG. 13 is a diagram showing the functional configuration of a memory system according to a second embodiment. [Figure 8] 10 is a flowchart showing the operation of the memory system according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A memory system according to an embodiment will be described with reference to FIGS.

[0008] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, elements having the same functions and configurations are given the same reference numerals. Furthermore, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) given reference numerals with distinguishing numbers / letters at the end are not required to be distinguished from each other, descriptions (reference numerals) with the numbers / letters at the end omitted are used.

[0009] (Embodiment) (1) First embodiment (a) Configuration (a-1) Configuration of Information Processing System 1 FIG. 1 is a block diagram showing an example of the configuration of an information processing system 1 according to the present embodiment.

[0010] The information processing system 1 includes a host device HD and a memory system MS.

[0011] The host device HD is an electronic device such as a personal computer, a portable information terminal, or a server.

[0012] The memory system MS is a semiconductor storage device such as a memory card, a solid state drive (SSD), etc. The memory system MS includes a non-volatile memory 10 and a memory controller 20.

[0013] The nonvolatile memory 10 is a memory device that stores data in a nonvolatile manner. In this embodiment, the nonvolatile memory 10 is, for example, a NAND type flash memory. However, the nonvolatile memory 10 may be a NOR type flash memory, a magneto-resistive random access memory (MRAM), a phase change random access memory (PRAM), a resistive random access memory (ReRAM), or a ferroelectric random access memory (FeRAM). The nonvolatile memory 10 includes a plurality of memory packages 100. Each of the plurality of memory packages 100 includes a plurality of memory dies (memory chips) 110. Each of the plurality of memory dies 110 includes a plurality of planes PLN. In this embodiment, storing (writing) data in the nonvolatile memory 10 is also called "nonvolatilization."

[0014] The memory controller 20 is a control device that controls the nonvolatile memory 10. The memory controller 20 is, for example, a semiconductor integrated circuit configured as a SoC (System On a Chip). The memory controller 20 controls the nonvolatile memory 10 based on an instruction (request) received from the host device HD, and executes data read, write, erase, and other operations. The memory controller 20 may collectively manage a plurality of nonvolatile memories 10. The memory controller 20 is connected to the host device HD via a bus B1. The nonvolatile memory 10 is connected to the memory controller 20 via a bus B2. The host device HD and the memory controller 20 may be connected to each other via a network.

[0015] (a-2) Hardware configuration of memory system MS (a-2-1) Hardware configuration of non-volatile memory 10 FIG. 2 is a block diagram showing an example of a hardware configuration of the nonvolatile memory 10 of the present embodiment.

[0016] In a certain memory package 100 of the non-volatile memory 10, each memory die 110 includes, for example, a plurality of planes PLN and a control circuit 130.

[0017] Each of the multiple planes PLN is a circuit that can operate independently and in parallel (simultaneously). A set of the multiple planes PLN is also called a memory core circuit 120.

[0018] The control circuit 130 is a collection of multiple circuits that control the operations of multiple planes PLN.

[0019] Each plane PLN includes a memory cell array 121, a row decoder module 122, and a sense amplifier module 123.

[0020] The memory cell array 121 is a storage circuit including a set of a plurality of memory cells MC. The plurality of memory cells MC may be arranged two-dimensionally or three-dimensionally.

[0021] The row decoder module 122 is a decoder that decodes a row address. Based on the decoded result, the row decoder module 122 selects a row (one block BLK) of the memory cell array 121. The row decoder module 122 transfers a voltage to each of a plurality of wirings (word lines WL and bit lines BL) provided in the selected block BLK.

[0022] The sense amplifier module 123 is a sense circuit that senses data read from a selected block BLK based on the voltage of the bit line BL during a read operation. The sense amplifier module 123 transmits the read data to the memory controller 20 via the control circuit 130 during a read operation. The sense amplifier module 123 can apply a voltage to each bit line BL according to data to be written to the memory cell MC during a write operation.

[0023] The memory cell array 121 includes a plurality of blocks BLK (BLK0 to BLKn-1), where n is a natural number. The blocks BLK are used, for example, as a unit for erasing data. The blocks BLK include a plurality of pages. A page is a unit for reading data. Also, a page is a unit for writing data. A page corresponds to data stored by a plurality of memory cells MC connected to one word line WL, for example. Note that the plurality of memory cells MC connected to one word line WL can store a plurality of pages of data depending on the number of bits of data stored in each memory cell MC.

[0024] The block BLK includes a plurality of memory cells MC, a plurality of bit lines BL, and a plurality of word lines WL. Each memory cell MC stores at least one bit of data in a non-volatile manner. Each memory cell MC is associated with one bit line BL and one word line WL. Each memory cell MC is identified based on an address that identifies the word line WL and an address that identifies the bit line BL.

[0025] The control circuit 130 includes a memory interface (memory I / F) 131, a sequencer 132, and a driver module 133.

[0026] The memory I / F 131 is a hardware interface connected to the memory controller 20 via the bus B2. The memory I / F 131 performs communication between the nonvolatile memory 10 and the memory controller 20 in accordance with an interface standard. The interface standard supported by the memory I / F 131 is, for example, the NAND interface standard. For example, the memory I / F 131 sends a row address to each row decoder module 122. During a read operation, the memory I / F 131 receives read data from each of the sense amplifier modules 123. During a write operation, the memory I / F 131 sends data to a certain sense amplifier module 123.

[0027] The sequencer 132 is a control circuit that controls the overall operation of the memory die 110. The sequencer 132 controls the driver module 133, the multiple row decoder modules 122, the multiple sense amplifier modules 123, etc. based on a command received via the memory I / F 131 to execute a read operation, a write operation, an erase operation, etc.

[0028] The driver module 133 is a circuit that generates voltages used for read operations, write operations, erase operations, etc. The driver module 133 is connected to each of the row decoder modules 122 via a plurality of signal lines. The driver module 133 can change the voltages applied to each of a plurality of signal lines corresponding to a plurality of word lines WL and a plurality of bit lines BL based on an address received via the memory I / F 131.

[0029] In the memory space of the non-volatile memory 10, the identification number (address value) of the memory package 100 corresponds to the upper address hierarchy in the memory space. The identification number (address) of the plane PLN corresponds to the lower address hierarchy in the memory space. The identification number (address) of the memory die 110 corresponds to the middle address hierarchy between the memory package 100 hierarchy and the plane PLN hierarchy in the memory space.

[0030] (a-2-2) Hardware configuration of memory controller 20 FIG. 3 is a block diagram showing an example of a hardware configuration of the memory controller 20 of the present embodiment.

[0031] The memory controller 20 of this embodiment includes a host interface (host I / F) 21, a memory interface (memory I / F) 22, a CPU (Central Processing Unit) 23, an ECC (Error Correction Code) circuit 24, a ROM (Read Only Memory) 25, a RAM (Random Access Memory) 26, and a buffer memory 27.

[0032] The host I / F 21 is a hardware interface connected to the host device HD via the bus B1. The host I / F 21 performs communication between the host device HD and the memory controller 20 in accordance with an interface standard. The interface standards supported by the host I / F 21 include SATA (Serial Advanced Technology Attachment), PCIe TM (PCI Express), etc.

[0033] The memory I / F 22 is a hardware interface connected to the nonvolatile memory 10 via the bus B2. The memory I / F 22 performs communication between the nonvolatile memory 10 and the memory controller 20 in accordance with an interface standard. The interface standard supported by the memory I / F 22 is, for example, the NAND interface standard.

[0034] The CPU 23 is a processor. The CPU 23 controls the overall operation of the memory controller 20. The CPU 23 instructs the nonvolatile memory 10 to write data via the memory I / F 22 in accordance with a write request received via the host I / F 21. The CPU 23 instructs the nonvolatile memory 10 to read data via the memory I / F 22 in accordance with a read request received via the host I / F 21.

[0035] The ECC circuit 24 is a circuit that executes ECC processing. The ECC processing includes encoding and decoding of data. The ECC circuit 24 encodes data to be written to the nonvolatile memory 10. The ECC circuit 24 decodes data read from the nonvolatile memory 10.

[0036] The ROM 25 is a non-volatile memory. For example, the ROM 25 is an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). The ROM 25 stores programs such as firmware. For example, the operation of the memory controller 20 described later is realized by the CPU 23 executing the firmware in the ROM 25.

[0037] The RAM 26 is a volatile memory. For example, the RAM 26 is a dynamic random access memory (DRAM) or a static random access memory (SRAM). The RAM 26 is used as a working area for the CPU 23. The RAM 26 stores a management table such as a look-up table (LUT) that associates logical addresses with physical addresses. The management table is a type of system data of the memory system MS. The LUT may be called an "address conversion table" or a "logical address / physical address conversion table."

[0038] The buffer memory 27 is a volatile memory. The buffer memory 27 is a dynamic random access memory (DRAM) or a static random access memory (SRAM). The buffer memory 27 temporarily stores data received via the host I / F 21 and data received via the memory I / F 22. The buffer memory 27 may be externally connected to the memory controller 20.

[0039] (a-2-3) Functional configuration of the non-volatile memory 10 and the memory controller 20 FIG. 4 is a block diagram showing an example of a functional configuration of the nonvolatile memory 10 and the memory controller 20 in the memory system MS of the present embodiment.

[0040] As described above, the non-volatile memory 10 includes a plurality of memory packages 100. Each of the plurality of memory packages 100 is connected to the memory controller 20 via a channel Ch (Ch0, Ch1, . . . ). A certain number (e.g., two) of the memory packages 100 are connected to one channel Ch. A collection of the plurality of channels Ch is a bus B2.

[0041] Each memory package 100 includes a plurality of memory dies 110 and a NAND control unit 190. One memory package includes, for example, two memory dies 110. However, the number of memory dies 110 included in the memory package 100 may be three or more.

[0042] Each memory die 110 includes a plurality of planes PLN. For example, one memory die 110 includes two planes PLN. However, the number of planes PLN of the memory die 110 may be three or more. Each of the planes PLN executes an operation sequence according to a command independently of each other.

[0043] The NAND control unit 190 is a functional block showing a collection of control circuits 130 of the multiple memory dies 110. The NAND control unit 190 controls various operations of the multiple planes PLN of the memory package 100. In a read operation, the NAND control unit 190 sends data read from the plane PLN to the memory controller 20. In a write operation, the NAND control unit 190 sends data to be written to the non-volatile memory 10 to the plane PLN.

[0044] The memory controller 20 includes a command generation unit 210 and a plurality of channel control units 220 .

[0045] The command generation unit 210 is a functional block that generates commands.

[0046] Each of the channel control units 220 is a functional block that controls a corresponding one of the multiple channels Ch.

[0047] The channel control unit 220 includes a read issuing unit 221 , a read period end detection unit 222 , and a data transfer control unit 223 .

[0048] Based on the command, the read issuing unit 221 issues a read command to each of the memory packages 100 belonging to the channel Ch.

[0049] The read period end detection unit 222 detects a plane PLN whose read period has ended from among a plurality of planes PLN. The read period is a period from the start to the completion of a read operation of the plane PLN. A plane PLN whose read period has ended is a plane PLN in which data transfer is possible in a read operation, or a plane PLN waiting for an instruction for data transfer. For example, the read period end detection unit 222 can monitor the operating state of the memory package 100, the operating state of the memory die 110, and the operating state of the plane PLN via the NAND control unit 190 based on various functions. The read period end detection unit 222 detects a plane PLN whose read period has ended (a plane in which data transfer is possible) based on the monitoring result. For example, the read period end detection unit 222 notifies the hierarchical state storage unit 30 described later of the plane PLN in which the read period has ended.

[0050] The data transfer control unit (also called a data out control unit) 223 controls the order of transfer (output of data) of data read from the plane PLN of each memory package 100 by round robin processing. When selecting a plane PLN for executing data transfer in the next cycle from among a plurality of plane PLNs capable of data transfer, the data transfer control unit 223 preferentially selects, by round robin processing, a plane PLN belonging to a memory package 100 (or memory die 110) different from the memory package 100 (or memory die 110) to which the plane PLN currently being transferred belongs. The data transfer control unit 223 is configured by, for example, software, hardware, or a combination of software and hardware.

[0051] The data transfer control unit 223 includes a hierarchical state storage unit 30 and a hierarchical round robin scheduler 40 .

[0052] The hierarchical state storage unit 30 stores various information related to data transfer in each hierarchical layer, which includes a plurality of memory packages 100, a plurality of memory dies 110, and a plurality of planes PLN. For example, the hierarchical state storage unit 30 stores the end state of the read period of each memory package 100 (whether data transfer is possible, waiting for data transfer), the end state of the read period of each memory die 110, and the end state of the read period of the plane PLN, based on a notification from the read period end detection unit 222. Here, the end state of the read operation indicates a state in which data read from the plane can be transferred to the memory controller 20 depending on whether the read period has ended. The hierarchical state storage unit 30 can also send the stored information to the channel control unit 220 and / or the hierarchical round robin scheduler 40.

[0053] The hierarchical round robin scheduler (also called a round robin control unit) 40 controls the execution timing of various processes for the round robin process, the execution period of various operations, and various settings. For example, the hierarchical round robin scheduler 40 hierarchically searches for memory packages 100 capable of data transfer, memory dies 110 capable of data transfer, and planes PLN capable of data transfer, based on information in the hierarchical state storage unit 30. The hierarchical round robin scheduler 40 detects planes PLN capable of data transfer based on the search results of the round robin process. The hierarchical round robin scheduler 40 selects a plane PLN for executing the data transfer based on the detection results. The hierarchical round robin scheduler 40 controls the data transfer from the selected plane PLN.

[0054] The hierarchical state memory unit 30 includes a register area 300 and a logic operation unit 390 .

[0055] The register area 300 stores information.

[0056] The logical operation unit 390 executes a logical operation (for example, an OR operation) on the values ​​of the registers 322 and 332. The logical operation unit 390 may be provided outside the hierarchical state storage unit 30 as a component of the data transfer control unit 223.

[0057] The register area 300 includes a channel corresponding section 310 .

[0058] The channel corresponding unit 310 is provided for a corresponding channel Ch between the non-volatile memory 10 and the memory controller 20. The channel corresponding unit 310 stores information regarding the data transfer enable state of the multiple memory packages 100 of the corresponding channel Ch in the round robin process.

[0059] The channel corresponding unit 310 includes a register 311 , a plurality of registers 312 , and a plurality of memory package corresponding units 320 .

[0060] The register 311 stores information (e.g., the identification number or address value of the memory package 100) indicating which of the multiple memory packages 100 in the hierarchy of the memory packages 100 of the corresponding channel Ch is the memory package 100 to be monitored in the round robin processing.

[0061] Each of the plurality of registers 312 stores information indicating whether or not the corresponding memory package 100 in the hierarchy of the memory packages 100 has completed the read period (whether or not data transfer is possible).

[0062] For example, when a certain memory package 100 is in a state where data transfer is not possible (when the memory dies 110 of the memory package 100 do not include a plane PLN for which the read period has ended), the register 312 corresponding to the memory package 100 stores a first value (N). The first value is, for example, 1-bit data. The 1-bit data means "0" data or "1" data.

[0063] Also, for example, when a certain memory package 100 is in a state in which data transfer is possible (when at least one memory die 110 of the memory package 100 includes a plane PLN for which the read period has ended), the register 312 corresponding to that memory package 100 stores a second value (Y) different from the first value. The second value is, for example, 1-bit data. The 1-bit data means "0" data or "1" data.

[0064] Furthermore, for example, the value of the register 312 for a certain memory package 100 is determined based on the result of a logical operation of the values ​​of multiple registers 322 for the memory die 110 belonging to that memory package 100. The logical operation performed on the values ​​of the multiple registers 322 is, for example, a logical sum operation (OR operation).

[0065] The multiple memory package corresponding units 320 correspond to the multiple memory packages 100 belonging to the channel Ch, respectively. Each of the multiple memory package corresponding units 320 stores information regarding the data transfer enable state of the multiple memory dies 110 of the corresponding memory package 100 in the round robin process.

[0066] Each memory package corresponding portion 320 includes a register 321 and a plurality of registers 322 .

[0067] The register 321 stores information (e.g., the identification number or address value of the memory die 110) indicating which of the multiple memory dies 110 in the hierarchy of the memory dies 110 of the corresponding memory package 100 is the memory die 110 to be monitored in the round robin process.

[0068] Each of the multiple registers 322 stores information indicating whether or not the corresponding memory die 110 in the hierarchy of the memory die 110 has completed the read period.

[0069] For example, when a certain memory die 110 is in a state in which data transfer is not possible (when the memory die 110 does not include a plane PLN in which the read period has ended), the register 322 corresponding to the memory die 110 stores a third value (N). The third value is, for example, 1-bit data.

[0070] Also, for example, when a certain memory die 110 is in a state where data transfer is possible (when the state includes a plane PLN for which the read period has ended), the register 322 corresponding to the memory die 110 stores a fourth value (Y) different from the third value. The fourth value is, for example, 1-bit data.

[0071] Furthermore, for example, the value of the register 322 for a certain memory die 110 is determined based on the result of a logical operation of the values ​​of multiple registers 332 for the plane PLN belonging to that memory die 110. The logical operation performed on the values ​​of the multiple registers 332 is, for example, a logical sum operation (OR operation).

[0072] Each memory package counterpart 320 includes a number of memory die counterparts 330 .

[0073] The multiple memory die corresponding units 330 correspond to the multiple memory dies 110 belonging to the memory package 100, respectively. Each of the multiple memory die corresponding units 330 stores information regarding the data transfer enable state of the multiple planes PLN of the corresponding memory die 110 in the round robin process.

[0074] Each memory die corresponding portion 330 includes a register 331 and a number of registers 332 .

[0075] The register 331 stores information (e.g., the identification number or address value of the plane PLN) indicating which of multiple plane PLNs in the hierarchy of the plane PLNs of the corresponding memory die 110 is the plane PLN to be monitored in the round robin process.

[0076] Each of the multiple registers 332 stores information indicating whether or not the corresponding plane PLN has finished the read period in the hierarchy of the plane PLN.

[0077] For example, when a certain plane PLN is in a state where data transfer is not possible (when the read period has not yet ended), the register 332 corresponding to that plane PLN stores a fifth value (N). The fifth value is, for example, 1-bit data.

[0078] Also, for example, when a certain plane PLN is in a state where data transfer is possible (when the read period has ended), the register 332 corresponding to that plane PLN stores a sixth value (Y) different from the fifth value. The sixth value is, for example, 1-bit data.

[0079] Furthermore, for example, when the read period (tR) of a certain plane PLN ends, the value of the register 332 corresponding to that plane PLN changes from the fifth value to the sixth value. When the register 332 has the sixth value, the plane PLN corresponding to that register 332 indicates a state waiting for data transfer (a state in which data transfer is possible). When the data transfer of the plane PLN capable of data transfer is completed, the value of the register 332 corresponding to that plane PLN changes from the sixth value to the fifth value.

[0080] (b) Operation FIG. 5 is a flowchart showing the operation of the memory system MS of the first embodiment.

[0081] The memory controller 20 performs a round robin process for multiple data transfers from the non-volatile memory 10 .

[0082] The data transfer control unit 223 of the memory controller 20 hierarchically monitors the memory space of the corresponding memory packages 100 using the hierarchical round robin scheduler 40 based on the information (data) of the hierarchical state memory unit 30 to determine the end state of the read period of the multiple memory packages 100 (whether data transfer is possible or not), the end state of the read period of the multiple memory dies 110, and the end state of the read period of the multiple planes PLN.

[0083] Here, we consider one channel Ch (e.g., channel Ch <0> The round robin processing and data transfer of the channel control unit 220 and the memory package 100 regarding the above will be described below.

[0084] At the start of data transfer or during data transfer from a certain plane PLN, the hierarchical round robin scheduler 40 determines the memory package 100 corresponding to the identification number stored in the register 311 as the target (S1). If the identification number is not stored in the register 311, the hierarchical round robin scheduler 40 determines the memory package 100 corresponding to the identification number stored in the register 311 as the target (S2). <0> The memory package 100 with a certain identification number (ith) belonging to the memory package 100 is determined as the target, where i is an integer equal to or greater than 0. For example, if a data transfer of a certain memory package 100 is in progress, a memory package 100 other than the memory package 100 in progress of the data transfer is determined as the target. If an identification number is not stored in the register 311, the hierarchical round robin scheduler 40 stores the identification number of the target memory package 100 in the register 311.

[0085] The hierarchical round robin scheduler 40 determines whether the target memory package 100 is in a state in which data transfer is possible (S2). Information on whether the target memory package 100 is in a state in which data transfer is possible is stored in the corresponding register 312.

[0086] If the target memory package 100 is not in a state capable of data transfer (S2 NO), the hierarchical round robin scheduler 40 increments (adds 1) or decrements (subtracts 1) the value of the register 311 (S3). As a result, the hierarchical round robin scheduler 40 changes the value of the register 311. Thereafter, the hierarchical round robin scheduler 40 performs the process of S1.

[0087] If the target memory package 100 is in a state where data transfer is possible (S2 YES), the hierarchical round robin scheduler 40 selects, among the multiple memory dies 110 belonging to the target memory package 100, a memory die 110 corresponding to the identification number stored in the register 321 as the target (S4). If no identification number is stored in the register 321, the hierarchical round robin scheduler 40 selects a memory die 110 with a certain identification number (jth), where j is an integer equal to or greater than 0. If no identification number is stored in the register 321, the hierarchical round robin scheduler 40 stores the identification number of the target memory die 110 in the register 321.

[0088] The hierarchical round robin scheduler 40 determines whether the target memory die 110 is in a state in which data transfer is possible (S5). Information on whether the target memory die 110 is in a state in which data transfer is possible is stored in the corresponding register 322.

[0089] If the target memory die 110 is not in a state where data transfer is possible (S5 NO), the hierarchical round robin scheduler 40 increments or decrements the value of the register 321 (S6). As a result, the hierarchical round robin scheduler 40 changes the value of the register 321. Thereafter, the hierarchical round robin scheduler 40 performs the process of S4.

[0090] If the target memory die 110 is in a state where data transfer is possible (S5 YES), the hierarchical round robin scheduler 40 selects the target memory die 110 and then increments or decrements the value of the register 321 (S7). In this manner, the hierarchical round robin scheduler 40 changes the value of the register 321. This makes it possible to prevent memory dies 110 having the same identification number from being selected consecutively even in a situation where multiple read operations are executed consecutively.

[0091] The hierarchical round robin scheduler 40 selects a plane PLN corresponding to the identification information stored in the register 331 as the target among the multiple plane PLNs belonging to the selected memory die 110 (S8). If no identification information is stored in the register 331, the hierarchical round robin scheduler 40 selects a plane PLN having a certain identification number (kth), where k is an integer equal to or greater than 0. If no identification information is stored in the register 331, the hierarchical round robin scheduler 40 stores the identification number of the target plane PLN in the register 331.

[0092] The hierarchical round robin scheduler 40 judges whether the target plane PLN is in a state in which data transfer is possible (S9). Information on whether the target plane PLN is in a state in which data transfer is possible is stored in the corresponding register 332.

[0093] If the target plane PLN is not in a state where data transfer is possible (S9 NO), the hierarchical round robin scheduler 40 increments or decrements the value of the register 331 (S10). As a result, the hierarchical round robin scheduler 40 changes the value of the register 331. Thereafter, the hierarchical round robin scheduler 40 performs the process of S8.

[0094] If the target plane PLN is in a state where data transfer is possible (S9 YES), the hierarchical round robin scheduler 40 determines the target plane PLN as the target plane PLN for data transfer (S11). After determining the target plane PLN for data transfer, the hierarchical round robin scheduler 40 may change the value of the register 331. This makes it possible to prevent plane PLNs having the same identification number from being selected consecutively even in a situation where multiple read operations are executed consecutively.

[0095] The hierarchical round robin scheduler 40 instructs the data transfer control unit 223 to transfer data to the determined target plane PLN of the data transfer (S12).

[0096] When the data transfer is instructed, the data transfer control unit 223 causes the nonvolatile memory 10 to output data of the plane PLN that is the target of the data transfer to the memory controller 20 (S13). The data is output to the memory controller 20 via the NAND control unit 190 and the channel Ch. After the data transfer of the plane PLN that is the target of the data transfer is completed, information indicating a state in which data transfer is not possible is stored in the register 332 corresponding to the plane PLN that is the target of the data transfer.

[0097] After the data transfer of the target plane PLN is completed, the hierarchical round robin scheduler 40 checks whether the transfer of data corresponding to all read commands is completed (S14).

[0098] If data transfer for all read commands has not been completed (S13 NO), the hierarchical round robin scheduler 40 increments or decrements the value of the register 311 (S15). After that, the hierarchical round robin scheduler 40 performs the process of S1.

[0099] If data transfer for all read commands has been completed (S13 YES), the memory controller 20 ends the series of processes shown in FIG. 5 (END).

[0100] 6 is a diagram showing a data transfer process using a round robin process to control the order of data transfer in the memory system MS of this embodiment. In FIG. 6, an example is shown in which two memory packages 100 execute data transfer in parallel. In FIG. 6, "(1), (2), (3),..., (15), (16)" indicate the order of ending the read period.

[0101] By controlling the order of data transfer through round robin processing, data (plurality of data items) is output from each of the plurality of memory packages 100 to the channel Ch (bus B2).

[0102] In this embodiment, at the time when a preceding data transfer of a plane PLN of a certain memory package 100 is completed, a plane PLN of a memory package 100 other than the memory package 100 performing the preceding data transfer is selected from one or more plane PLNs capable of data transfer.

[0103] Therefore, in this embodiment, data transfers of the plane PLN for which the read period tR has ended are executed alternately from two memory packages 100, regardless of the order of ending of the read period tR of the data in each memory package 100. When two consecutive data transfers are executed in different memory packages 100, the data output waiting time tWHR2 does not occur.

[0104] As a result, the memory system MS of this embodiment can suppress the occurrence of the wait time tWHR2 between data transfers.

[0105] Therefore, the memory system MS of this embodiment can shorten the time required to complete a plurality of data transfers.

[0106] When multiple memory dies 110 of one memory package 100 transfer data in parallel by data transfer based on the order set by the round robin process, a plane PLN of a memory die 110 different from the memory die 110 performing the preceding data transfer is selected as the target of the next data transfer. After the preceding data transfer of a certain memory die 110 is completed, the data transfer of the different memory die 110 is performed by the selected plane PLN.

[0107] (c) Effects The memory system MS of the first embodiment searches for the memory packages 100, memory dies 110, and planes PLN that are targets of data transfer following the data transfer of the previous cycle by round robin processing for each memory package 100 and each memory die 110. This allows the memory system MS of the first embodiment to guarantee that the planes PLN that can execute data transfer are selected as targets of data transfer within a certain number of rounds. Therefore, the memory system MS of the first embodiment can guarantee the upper limit of the latency of data transfer.

[0108] (d) Summary When the round robin process hierarchically searches for transferable units of data in the order of memory package 100, memory die 110, and plane PLN, multiple memory packages 100 having different identification numbers and / or memory dies 110 having different identification numbers have a tendency to be selected sequentially (alternately) as targets of data transfer. Therefore, consecutive data transfers from memory packages 100 having the same identification number and / or memory dies 110 having the same identification number can be relatively avoided. As a result, in the memory system MS of the first embodiment, occurrence of a waiting time between multiple data transfers is suppressed. Therefore, the memory system MS of the first embodiment can shorten the time for data transfer. The memory system MS of the first embodiment can make data transfer efficient. The memory system MS of the first embodiment can improve the performance of the memory system.

[0109] (2) Second embodiment (a) Configuration FIG. 7 is a diagram illustrating a schematic configuration of a memory system MS according to the second embodiment.

[0110] In the second embodiment, an index (identification number) Idx is assigned to each of the minimum units of data output. For example, each of the multiple planes PLN included in the non-volatile memory 10 is the minimum unit of data output.

[0111] 7, two memory packages 100 belong to one channel Ch in the non-volatile memory 10. One memory package 100 includes two memory dies 110. One memory die 110 includes two planes PLN.

[0112] In this case, an index Idx is assigned to each of a plurality of planes PLN, which are units of data transfer, as follows:

[0113] An index Idx of "0" is assigned to a plane PLN of "0" that belongs to a memory package 100 with an identification number of "0" and a memory die 110 with an identification number of "0".

[0114] An index Idx of "1" is assigned to a plane PLN of "0" that belongs to a memory package 100 with an identification number of "1" and a memory die 110 with an identification number of "0".

[0115] An index Idx of "2" is assigned to a plane PLN of "0" that belongs to a memory package 100 with an identification number of "0" and a memory die 110 with an identification number of "1."

[0116] An index Idx of "3" is assigned to a plane PLN of "0" that belongs to a memory package 100 with an identification number of "1" and a memory die 110 with an identification number of "1".

[0117] An index Idx of "4" is assigned to a plane PLN of "1" that belongs to the memory package 100 with an identification number of "0" and the memory die 110 with an identification number of "0".

[0118] An index Idx of "5" is assigned to a plane PLN of "1" that belongs to a memory package 100 with an identification number of "1" and a memory die 110 with an identification number of "0".

[0119] An index Idx of "6" is assigned to a plane PLN of "1" that belongs to a memory package 100 with an identification number of "0" and a memory die 110 with an identification number of "1."

[0120] An index Idx of "7" is assigned to a plane PLN of "1" that belongs to a memory package 100 with an identification number of "1" and a memory die 110 with an identification number of "1".

[0121] Each of two adjacent indexes Idx is associated with a memory package 100 having a different identification number.

[0122] For example, the array of multiple indexes Idx is set based on a numerical value in which the plane PLN number is the most significant digit, the memory package 100 number is the least significant digit, and the memory die 110 number is the digit between the plane PLN number digit and the memory package 100 number digit.

[0123] In this way, eight indexes Idx are set for round robin processing of data transfer according to the number of planes PLN in one memory package 100.

[0124] In this embodiment, the data transfer control unit 223 includes a one-dimensional state storage unit 50 and a one-dimensional round robin scheduler 60 .

[0125] The one-dimensional state storage unit 50 includes a register area 500. The register area 500 includes a plurality of registers 501 and 502. The register 501 stores a value (m) of an index Idx of a monitoring target, where m is an integer equal to or greater than 0.

[0126] Each of the registers 502 stores a value indicating whether the plane PLN corresponding to the corresponding index Idx is capable of transferring data. The value of the register 502 is controlled by the read period end detection unit 222, for example.

[0127] The register 502 stores a seventh value (N) when the read period of the plane PLN of the corresponding index Idx has not ended (when data transfer is not possible). The seventh value is 1-bit data ("0" data or "1" data).

[0128] When the read period of the plane PLN of the corresponding index Idx has ended (data transfer is possible, data transfer is on hold), the register 502 stores an eighth value (Y) different from the seventh value. The eighth value is 1-bit data (either "0" data or "1" data).

[0129] The one-dimensional round robin scheduler (round robin control unit) 60 sets the value of the index Idx to be monitored in the register 501.

[0130] The one-dimensional round robin scheduler 60 monitors, based on the values ​​of a plurality of registers 502, whether or not the plane PLN corresponding to the monitored index Idx is capable of data transfer.

[0131] For example, the one-dimensional round robin scheduler 60 can control data transfer from each plane of the non-volatile memory 10 .

[0132] (b) Operation FIG. 8 is a flowchart showing the operation of the memory system MS according to the second embodiment.

[0133] At the timing of starting a data transfer or during data transfer from a certain plane PLN, the one-dimensional round robin scheduler 60 determines the plane PLN of the index Idx corresponding to the identification number stored in the register 501 as the target (S21).

[0134] The one-dimensional round robin scheduler 60 judges whether the target plane PLN is capable of data transfer (S22).

[0135] If the target plane PLN is not available for data transfer (S22 NO), the one-dimensional round robin scheduler 60 changes the value of the register 501 by incrementing or decrementing (S23). After that, the one-dimensional round robin scheduler 60 performs the process of S21.

[0136] If the target plane PLN is available for data transfer (YES in S22), the one-dimensional round robin scheduler 60 determines the target plane PLN as the target plane PLN for data transfer (S24).

[0137] The one-dimensional round robin scheduler 60 instructs the data transfer control unit 223 to transfer the data of the determined target plane PLN for data transfer (S25).

[0138] When the data transfer is instructed, the data transfer control unit 223 causes the nonvolatile memory 10 to output the data of the plane PLN that is the target of the data transfer to the memory controller 20 (S26).

[0139] After the data transfer of the target plane PLN is completed, the one-dimensional round robin scheduler 60 checks whether the data transfer for all read commands is completed (S27).

[0140] If data transfer for all read commands has not been completed (S27 NO), the one-dimensional round robin scheduler 60 changes the value of the register 501 (S28). After that, the one-dimensional round robin scheduler 60 performs the process of S21.

[0141] If data transfer for all read commands has been completed (S27 YES), the memory controller 20 ends the series of processes shown in FIG. 8 (END).

[0142] (c) Summary In the memory system MS of the second embodiment, data transfers of the nonvolatile memory 10 are managed in units of planes PLN to which different indexes Idx are assigned. This allows the memory system MS of the second embodiment to relatively easily control the order of multiple data transfers from the nonvolatile memory 10.

[0143] In the memory system MS of the second embodiment, the multiple planes PLN are searched in a cycle according to the number of indexes Idx. Therefore, in the second embodiment, each of the multiple planes PLN can be reliably selected as a data transfer target. Therefore, the memory system MS of the second embodiment can guarantee an upper limit of the latency of data transfer.

[0144] The memory system MS of the second embodiment can reduce the number of registers 501 that store the identification numbers of the monitored objects by making the search hierarchy one-dimensional through the round robin process. As a result, in the second embodiment, the size of the register area 500 of the state storage unit 50 can be reduced.

[0145] The memory system MS of the second embodiment can obtain substantially the same effects as those of the first embodiment. The memory system MS of the second embodiment can shorten the time for data transfer. The memory system MS of the second embodiment can improve the performance of the memory system.

[0146] (3) Other The embodiments are illustrative and the scope of the invention is not limited thereto. [Explanation of symbols]

[0147] 1. Information processing system HD: Host device MS…Memory system 100…Memory package 110…Memory die PLN…Plane 222...Read period end detection unit 223...Data transfer control unit 30...Hierarchical state memory unit 311, 312, 321, 322, 331, 332… registers 40...Hierarchical round-robin scheduler 50...One-dimensional state memory unit 501, 502... Registers 60...One-dimensional round-robin scheduler

Claims

1. A non-volatile memory including at least a first memory device and a second memory device; a controller electrically connected to the non-volatile memory and configured to communicate with a host and to control an order of transfer of a plurality of data items such that when two or more data items are ready to be transferred from the first memory device and at least one data item is ready to be transferred from the second memory device, the two or more data items are transferred non-contiguous from the first memory device; A memory system comprising:

2. Each of the first and second memory devices is a memory package, a memory die, or a plane of a memory die.

2. The memory system of claim 1.

3. The controller is configured to control an order of transfer of the plurality of data items by instructing the non-volatile memory to transfer the plurality of data items in an order different from an order in which the plurality of data items are ready to be transferred within the non-volatile memory.

2. The memory system of claim 1.

4. The two or more data items ready to be transferred in the first memory device include at least a first data item and a second data item; the at least one data item ready to be transferred in the second memory device includes at least a third data item; The controller: determining that the first and second data items are ready to be transferred from the first memory device and that the third data item is ready to be transferred from the second memory device; directing the non-volatile memory to transfer the first data item from the first memory device; instructing the non-volatile memory to transfer the third data item from the second memory device before instructing the non-volatile memory to transfer the second data item from the first memory device; directing the non-volatile memory to transfer the second data item from the first memory device; The memory system of claim 1 further configured as follows:

5. The first memory device includes a third memory device and a fourth memory device, the second memory device includes a fifth memory device; the first data item is transferred from the third memory device to the first memory device; the third data item is transferred from the fifth memory device to the second memory device; the second data item is transferred from the fourth memory device to the first memory device.

5. The memory system of claim 4.

6. Each of the first and second memory devices is a memory package, and each of the third, fourth, and fifth memory devices is a memory die. Or, each of the first and second memory devices is a memory die, and each of the third, fourth, and fifth memory devices is a plane of a memory die.

6. The memory system of claim 5.

7. The controller: instructing the non-volatile memory to transfer the third data item from the second memory device before instructing the non-volatile memory to transfer the second data item from the first memory device, even if the second data item is ready to be transferred from the first memory device before the third data item is ready to be transferred from the second memory device. The memory system of claim 4 , configured as follows:

8. Further comprising a first register, The controller: storing an identifier of one of the first and second memory devices in the first register; storing an identifier of the second memory device in the first register when any one of the two or more data items is transferred from the first memory device; The memory system of claim 1 further configured as follows:

9. The memory system of claim 8, wherein the controller is configured to determine which of the first and second memory devices is the target of a data transfer based at least on the information stored in the first register.

10. Further comprising a second register, The controller: storing an identifier of the first memory device in the second register when the one of the two or more data items is ready to be transferred from the first memory device; determining a target memory device for the data transfer further based on the information stored in the second register; 10. The memory system of claim 9, further configured as follows:

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