Display

Abstract

To provide a display that has improved the aperture ratio of a display unit with a simple configuration.SOLUTION: A display comprises: a plurality of pixel electrodes respectively connected with a semiconductor device; a plurality of common electrodes respectively arranged opposite to some of the plurality of pixel electrodes; and a plurality of pieces of common wire respectively connected with the plurality of common electrodes. The semiconductor device includes an oxide semiconductor layer having a polycrystalline structure, and at least some of the common wire are formed of the oxide semiconductor layer. The plurality of common electrodes may respectively be arranged over some of the plurality of pixel electrodes.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] Conventionally, a display device with a touch sensor is known in which a touch sensor is arranged over a display section. A touch sensor is a sensor that detects the position of a finger or the like that touches the display section, and there are various types of touch sensors, for example, a resistive film type and a capacitive type. In particular, the capacitive type has an advantage that it is possible to detect touches at multiple points, and is widely used. The capacitive type is further divided into a self-capacitive type and a mutual-capacitive type. In particular, a display device equipped with a self-capacitive type touch sensor has an advantage that the number of electrodes used as a touch sensor is smaller than that of a mutual-capacitive type, and the structure of the entire display device is simplified (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-42184 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a self-capacitance touch sensor, in order to apply a control voltage (e.g., a ground voltage) to a plurality of detection electrodes used for touch detection, each detection electrode needs to be electrically connected by a common wiring. Therefore, a plurality of detection electrodes are arranged in the display section of a display device equipped with a self-capacitance touch sensor, and a plurality of common wirings are arranged to electrically connect these detection electrodes. Such a plurality of common wirings are generally made of a metal material, and may reduce the aperture ratio of the display section (the ratio of the area effective as pixels to the area of ​​the display section).

[0005] An embodiment of the present invention has been made in consideration of the above problems, and has an object to provide a display device having an improved aperture ratio of a display unit with a simple structure. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention comprises a plurality of pixel electrodes each connected to a semiconductor device, a plurality of common electrodes each arranged opposite a portion of the plurality of pixel electrodes, and a plurality of common wirings each connected to the plurality of common electrodes, wherein the semiconductor device includes an oxide semiconductor layer having a polycrystalline structure, and at least a portion of the common wirings is composed of the oxide semiconductor layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view showing a configuration of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a diagram showing a configuration of a pixel circuit in a display device according to an embodiment of the present invention; [Diagram 3] 2 is a plan view showing a configuration of a touch sensor circuit in the display device according to the embodiment of the present invention; [Figure 4] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Diagram 5] 1 is a cross-sectional view showing a configuration of a semiconductor device used in a display device according to an embodiment of the present invention. [Figure 6] 1 is a plan view showing a configuration of a semiconductor device used in a display device according to an embodiment of the present invention; [Figure 7A] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 7B] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 7C] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 8]1 is a band diagram illustrating a band structure of a conductive portion of an oxide semiconductor layer. [Figure 9] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Figure 10] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 13] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 14] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 15] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 17] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 18] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 19] 1 is a cross-sectional view showing a configuration of a semiconductor device used in a display device according to an embodiment of the present invention. [Figure 20] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Figure 21] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 22] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 23]5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device used in a display device according to one embodiment of the present invention. [Figure 24] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Diagram 25] 5 is a sequence diagram showing a manufacturing method of a semiconductor device used in the display device of the embodiment of the present invention. FIG. [Figure 26] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Figure 27] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Figure 28] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Figure 29] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. [Diagram 30] 1 is a diagram showing a configuration of a pixel circuit in a display device according to an embodiment of the present invention; [Diagram 31] 1 is a cross-sectional view showing a structure of a pixel in a display device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In each embodiment, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". Thus, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the order of stacking in a structure in which multiple layers are stacked, and when it is expressed as "a pixel electrode above a transistor", it may be a positional relationship in which the transistor and the pixel electrode do not overlap in a planar view. On the other hand, when it is expressed as "a pixel electrode vertically above a transistor", it means a positional relationship in which the transistor and the pixel electrode overlap in a planar view.

[0010] In each embodiment, multiple elements formed by processing a film such as etching may be described as elements having different functions or roles. These multiple elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer.

[0011] In each embodiment, the term "display device" refers to a device that displays an image using an electro-optical layer. For example, the term display device includes not only a display panel including an electro-optical layer, but also a device in which other optical members (e.g., a polarizing member or a backlight) are attached to the display panel. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. In each embodiment described below, a liquid crystal display device including a liquid crystal layer will be described as an example, but the present invention can also be applied to a display device including the other electro-optical layers described above.

[0012] In each embodiment, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] (First embodiment) [Display device configuration] A display device 100 according to an embodiment of the present invention will be described. In this embodiment, the display device 100 is a liquid crystal display device having a liquid crystal layer as an electro-optical layer. More specifically, the display device 100 is a liquid crystal display device having a touch sensor function. Specifically, the display device 100 has a self-capacitance touch sensor.

[0014] Fig. 1 is a plan view showing a configuration of a display device 100 according to an embodiment of the present invention. As shown in Fig. 1, a display unit 110, a scanning side driving unit 120, and a terminal unit 130 are provided on the front side of a circuit board 100A of the display device 100.

[0015] The circuit board 100A is a substrate in which a plurality of semiconductor devices formed using oxide semiconductors are arranged on a light-transmitting support substrate. In this embodiment, an example in which thin film transistors are arranged as the semiconductor devices is shown, but the present invention is not limited to this example, and other semiconductor devices may be arranged as long as they function as switching elements. The circuit board 100A may also be called an active matrix substrate. A light-transmitting substrate may be used as the support substrate constituting the circuit board 100A. For example, it is preferable to use a glass substrate or a flexible resin substrate as the support substrate.

[0016] The display unit 110 is a part for controlling a plurality of pixels 112 that display an image. Specifically, the display unit 110 includes a plurality of scanning signal lines 114 extending in a D1 direction (row direction) and a plurality of video signal lines 116 extending in a D2 direction (column direction), and has pixels 112 including semiconductor devices such as thin film transistors corresponding to each of the intersections of the plurality of scanning signal lines 114 and the plurality of video signal lines 116. In this embodiment, each pixel 112 is a sub-pixel corresponding to any one of the colors R (red), G (green), and B (blue). Therefore, in reality, the display unit 110 is configured to perform color display with one pixel (main pixel) including three pixels 112 corresponding to each of the colors RGB as a unit.

[0017] Here, a pixel circuit 200 for controlling the emission of each pixel 112 will be described with reference to Fig. 2. For convenience of explanation, a basic configuration using one semiconductor device (thin film transistor) and one storage capacitor will be described as an example, but the configuration of the pixel circuit 200 is not limited to this example.

[0018] Fig. 2 is a diagram showing a configuration of a pixel circuit 200 in a display device 100 according to one embodiment of the present invention. As shown in Fig. 2, the pixel circuit 200 includes a selection transistor 201, a storage capacitor 202, and a liquid crystal element 203. As will be described later, the selection transistor 201 is a thin-film transistor including a channel portion formed of an oxide semiconductor layer.

[0019] The gate of the selection transistor 201 is connected to a scanning signal line 114, and the source of the selection transistor 201 is connected to a video signal line 116. A gradation signal that determines the amount of light transmitted through the liquid crystal element 203 is supplied to the video signal line 116. A scanning signal for selecting a pixel to which a gradation signal is to be written is supplied to the scanning signal line 114. The drain of the selection transistor 201 is connected to a storage capacitor 202 and the liquid crystal element 203. Note that the source and drain of the selection transistor 201 may be switched depending on the magnitude relationship between the voltage applied to the video signal line 116 and the voltage stored in the storage capacitor 202.

[0020] The storage capacitor 202 is a capacitor that stores a voltage input from the video signal line 116 via the selection transistor 201. One electrode of the storage capacitor 202 is connected to the drain of the selection transistor 201, and the other electrode is fixed to the ground potential. However, this is not limited to this example, and the other electrode may be fixed to another potential.

[0021] The liquid crystal element 203 is an electro-optical element having a structure in which a liquid crystal layer is provided between a pair of electrodes. Although the specific structure will be described later, the liquid crystal element 203 of this embodiment includes a pixel electrode connected to the drain of the selection transistor 201 and a common electrode connected to a common wiring 204, and the orientation of the liquid crystal molecules is controlled by an electric field formed between the pixel electrode and the common electrode. In this embodiment, the common electrode connected to the common wiring 204 functions as an electrode that applies a voltage to the liquid crystal layer and also functions as a detection electrode of a touch sensor. This point will be described later.

[0022] The pixel circuit 200 described above is disposed in each pixel 112 of the display device 100. In other words, it can be said that the display unit 110 shown in FIG.

[0023] Returning to FIG. 1, the scanning side driving unit 120 is connected to the scanning signal line 114 and transmits a scanning signal to the scanning signal line 114. Specifically, the scanning signal is provided to the gate of the selection transistor 201 shown in FIG. 2 and is used for switching control of the selection transistor 201. In this embodiment, like the pixel circuits 200 included in the multiple pixels 112, the driving circuit constituting the scanning side driving unit 120 is also formed using thin film transistors, but it is also possible to substitute an IC chip or the like. Note that, in this embodiment, the circuit board 100A includes two scanning side driving units 120, but only one of them may be included.

[0024] The terminal section 130 is a portion for electrically connecting various wirings arranged on the circuit board 100A to the flexible printed circuit board 140. Specifically, the terminal section 130 is an assembly of a plurality of video signal lines 116, wirings (not shown) for supplying control signals to the scanning side driving section 120, and a plurality of terminals connected to a common wiring 204. The terminal section 130 is arranged on the outside of the display section 110. Video signals and control signals supplied from the outside are supplied to the display section 110 and the scanning side driving section 120, respectively, via the terminal section 130. In addition, the touch sensor function of the display device 100 is realized by processing a detection signal outputted to the outside via the common wiring 204.

[0025] A flexible printed circuit board 140 is connected to the terminal unit 130. The flexible printed circuit board 140 is an interface board for connecting the circuit board 100A to an external control circuit (not shown). In this embodiment, a display control circuit 150 is mounted on the flexible printed circuit board 140. The display control circuit 150 is a signal processing circuit that performs signal processing of a video signal supplied to the display unit 110 and various control signals supplied to the scanning side driver 120.

[0026] In this embodiment, the display control circuit 150 also functions as a touch sensor circuit that detects a touch position based on a detection signal acquired via the common wiring 204. However, this is not limiting, and the function related to display control and the function related to the touch sensor may be provided separately in separate control circuits. In this embodiment, the display control circuit 150 is mounted on the flexible printed circuit board 140 in the form of an IC chip.

[0027] The flexible printed circuit board 140 is a circuit board in which wiring is printed on a flexible substrate made of a resin material, and therefore can be bent. In this embodiment, the flexible printed circuit board 140 can be bent along the dashed dotted line 142 so that the flexible printed circuit board 140 and the back side of the circuit board 100A (the side on which the display unit 110 and the like are not formed) overlap with each other.

[0028] Next, the touch sensor will be described. The display device 100 of this embodiment is equipped with a self-capacitance touch sensor. However, the touch sensor type is not limited to the self-capacitance type. The present invention can be applied to any display device as long as the display unit has wiring for supplying signals to detection electrodes constituting the touch sensor, or wiring for outputting signals from the detection electrodes.

[0029] 3 is a plan view showing a configuration of the touch sensor circuit 115 in the display device 100 of one embodiment of the present invention. The touch sensor circuit 115 is provided on the circuit board 100A, and is arranged in substantially the same region as the display unit 110. The touch sensor circuit 115 includes a plurality of common electrodes 205 arranged in the D1 direction (row direction) and the D2 direction (column direction), and a plurality of common wirings 204 electrically connected to the plurality of common electrodes 205, respectively. The plurality of common wirings 204 are connected to the terminal unit 130.

[0030] 3, in this embodiment, a plurality of common wirings 204a-204c are connected to a plurality of common electrodes 205a-205c arranged in the D2 direction. That is, when m common electrodes 205 are arranged in the D2 direction, the number of common wirings 204 corresponding to one row of common electrodes 205 is m. When the number of common electrodes 205 arranged in the D1 direction is n, a total of n×m common wirings 204 are arranged.

[0031] The common wiring 204 is used to apply a predetermined voltage (for example, a ground voltage) to the common electrode 205 and to read a detection signal indicating a touch position from the common electrode 205. That is, in this embodiment, the common electrode 205 is used as an electrode for applying a voltage to the liquid crystal layer during the display period and is also used as a detection electrode of the touch sensor during the sensing period. A method for detecting a touch position in a self-capacitance touch sensor is well known, and therefore a description thereof will be omitted here.

[0032] One common electrode 205 shown in Fig. 3 is disposed across the pixel circuits 200 of the multiple pixels 112. Although details will be described later, each pixel circuit 200 is provided with a common electrode for applying a voltage to the liquid crystal layer. In other words, one common electrode 205 shown in Fig. 3 can be said to be an assembly of each common electrode included in the multiple pixel circuits 200. Each common wiring 204 is electrically connected to one common electrode 205, i.e., to multiple common electrodes included in each of the multiple pixel circuits 200.

[0033] 4 is a cross-sectional view showing a structure of a pixel 112 in a display device 100 according to an embodiment of the present invention. As shown in FIG. 4, a selection transistor 201 is provided on a substrate 500. The substrate 500 is a light-transmitting substrate, and may be, for example, a glass substrate or a resin substrate. The base layer 520 is composed of a silicon oxide layer, a silicon nitride layer, or a laminated film of a silicon oxide layer and a silicon nitride layer. The base layer 520 has a role of preventing the intrusion of impurities and the like from the substrate 500.

[0034] The selection transistor 201 of this embodiment includes an oxide semiconductor layer 544 made of an oxide semiconductor having a polycrystalline structure. As the oxide semiconductor, for example, a metal oxide containing two or more metals including indium (In) is used. In general, an oxide semiconductor has light-transmitting properties and is transparent to visible light. The oxide semiconductor layer 544 includes a channel portion 403a and a conductive portion 403b. The channel portion 403a functions as a channel of the selection transistor 201. The conductive portion 403b functions as a source or drain of the selection transistor 201. A detailed structure of the selection transistor 201 will be described later.

[0035] As shown in FIG. 4, the common wiring 204 shown in FIG. 3 is made of the same layer as the oxide semiconductor layer 544 constituting the selection transistor 201. That is, in this embodiment, the oxide semiconductor layer 544 and the common wiring 204 are elements derived from the same oxide semiconductor layer and made of the same layer structure and the same material. Although details will be described later, the common wiring 204 is formed at the same time as the conductive part 403b of the oxide semiconductor layer 544. As will be described later, the conductive part 403b is a part of the oxide semiconductor layer 544 that is made conductive in the process of adding impurities. The common wiring 204 is made of an oxide semiconductor layer that is made conductive through the same process as the conductive part 403b. This point will be described later together with the manufacturing method of the selection transistor 201.

[0036] A planarization layer 610 made of a resin material is provided on the selection transistor 201 and the common wiring 204. The planarization layer 610 has a role of planarizing undulations on the substrate 500 caused by the formation of the selection transistor 201. A pixel electrode 620 is provided on the planarization layer 610. The pixel electrode 620 is made of a transparent conductive film containing a metal oxide such as ITO. The pixel electrode 620 is connected to the selection transistor 201 via a contact hole provided in the planarization layer 610.

[0037] An insulating layer 630 is provided on the pixel electrode 620. The insulating layer 630 is composed of a silicon oxide layer, a silicon nitride layer, or a laminated structure thereof. A common electrode 205 is provided on the insulating layer 630 so as to overlap a part of the pixel electrode 620. The common electrode 205 is composed of a transparent conductive film containing a metal oxide such as ITO, similar to the pixel electrode 620. The common electrode 205 is connected to the common wiring 204 through contact holes provided in the planarization layer 610 and the insulating layer 630. As described with reference to FIG. 3, the common electrode 205 functions as a detection electrode of the touch sensor by inputting and outputting a signal through the common wiring 204 during the sensing period.

[0038] In this embodiment, the common electrode 205 has a comb-like pattern shape. For example, the common electrode 205 has a pattern shape in which a linear electrode extending in the D1 direction in FIG. 1 is connected to a plurality of linear electrodes extending in the D2 direction. In the example shown in FIG. 4, three electrode patterns are shown overlapping the pixel electrode 620, which correspond to cross sections of a plurality of linear electrodes extending in the D2 direction and are electrically connected to each other. That is, although they are shown separately in FIG. 4, all of the common electrodes 205 are electrically connected to the common wiring 204.

[0039] In this embodiment, a FFS (Fringe Field Switching) method is adopted in which a fringe field is formed between the pixel electrode 620 and the common electrode 205 to align the liquid crystal molecules of the liquid crystal layer 650. The FFS method is a well-known driving method for liquid crystal display devices, and therefore a description thereof will be omitted here. When forming the fringe field, a predetermined voltage (e.g., a ground voltage) is applied to the common electrode 205. That is, the strength of the fringe field is controlled by the voltage applied to the pixel electrode 620. In this way, the common electrode 205 is held at a constant voltage via the common wiring 204 during the display period, and functions as an electrode for applying a voltage to the liquid crystal layer.

[0040] In this embodiment, an example of the FFS method of forming a fringe electric field between the pixel electrode 620 and the common electrode 205 has been described, but the present invention is not limited to this example, and for example, an IPS (In-Plane Switching) method may be adopted. In this case, both the pixel electrode and the common electrode are configured in a comb-like pattern, and the comb portions of the pixel electrode and the common electrode are arranged to face each other. In the case of the IPS method, a horizontal electric field is formed by the pixel electrode and the common electrode facing each other in the horizontal direction, and the orientation of the liquid crystal molecules is controlled by the horizontal electric field.

[0041] A substrate 700 and a color filter 710 are provided on the pixel electrode 620 and the common electrode 205 via a liquid crystal layer 650. In this embodiment, the substrate 700 and the color filter 710 are collectively referred to as a counter substrate 700A. The liquid crystal layer 650 is disposed between the circuit substrate 100A and the counter substrate 700A, which are bonded together by a sealant (not shown). Although not shown in FIG. 4, an alignment film is provided on the surfaces of the circuit substrate 100A and the counter substrate 700A that contact the liquid crystal layer 650. In this embodiment, only the color filter 710 is shown on the substrate 700, but a light-shielding film (so-called black matrix) may be provided as necessary.

[0042] As described above, in this embodiment, each pixel 112 has the common electrode 205 arranged so as to overlap the pixel electrode 620, and the common electrode 205 is electrically connected to the common wiring 204. In this case, the common wiring 204 is made of an oxide semiconductor layer 544 that functions as an active layer (a semiconductor layer including a channel portion 403a) of a semiconductor device (here, a selection transistor 201) arranged in each pixel 112. Note that the common wiring 204 does not need to be made of the oxide semiconductor layer 544 in its entirety, and at least a part of it may be made of the oxide semiconductor layer 544.

[0043] The oxide semiconductor layer 544 used in the selection transistor 201 of this embodiment has a polycrystalline structure and is extremely excellent in crystallinity. In addition, the conductive portion 403b of this embodiment, which is obtained by imparting conductivity to the oxide semiconductor layer 544, has a feature that its resistance is significantly lower than that of conventional conductive portions. Specifically, the sheet resistance of the conductive portion 403b is 1000 Ω / sq. or less (preferably 500 Ω / sq. or less), and it is sufficiently usable as wiring. In the display device 100 of this embodiment, focusing on such physical properties of the oxide semiconductor layer 544, the common wiring 204 used as the touch sensor circuit 115 is formed of the same layer as the oxide semiconductor layer 544.

[0044] According to this embodiment, the common wiring 204 for the touch sensor, which has been a factor in reducing the aperture ratio of the display unit 110 in the conventional technology, can be made of a light-transmitting material (specifically, an oxide semiconductor layer 544 made of a metal oxide). Moreover, since the common wiring 204 can be made of the same layer as the oxide semiconductor layer 544 used in the selection transistor 201, it is possible to improve the aperture ratio of the display unit of the display device 100 with a simple structure.

[0045] The structure of the display unit 110 described above is realized by reducing the resistance of the oxide semiconductor layer to a level where it can be used as wiring. Specifically, it is realized by reducing the resistance of the conductive part 403b of the selection transistor 201, which is a semiconductor device using an oxide semiconductor. Therefore, the configuration and manufacturing method of the semiconductor device (selection transistor 201 in FIG. 4) used in this embodiment will be described below.

[0046] [Configuration of semiconductor device] Fig. 5 is a cross-sectional view showing the configuration of a semiconductor device 10 used in a display device 100 according to one embodiment of the present invention. Fig. 6 is a plan view showing the configuration of a semiconductor device 10 used in a display device 100 according to one embodiment of the present invention. Fig. 10 corresponds to a cross-sectional view taken along the dashed dotted line shown in Fig. 11. Note that, although shown with slightly different dimensions for ease of explanation, the semiconductor device 10 shown in Fig. 5 and the selection transistor 201 shown in Fig. 4 have basically the same structure.

[0047] 5, the semiconductor device 10 is provided above a substrate 500. The semiconductor device 10 includes a base layer 520, an oxide semiconductor layer 544, a gate insulating layer 550, a gate electrode 564, an insulating layer 570, an insulating layer 580, a source electrode 591, and a drain electrode 593.

[0048] The base layer 520 is provided on the substrate 500. The oxide semiconductor layer 544 is provided on the base layer 520. The oxide semiconductor layer 544 is in contact with the base layer 520. Of the main surfaces of the oxide semiconductor layer 544, a surface in contact with the gate insulating layer 550 is called an upper surface, and a surface in contact with the base layer 520 is called a lower surface. A surface between the upper surface and the lower surface is called a side surface. The base layer 520 functions as a barrier film that blocks impurities diffusing from the substrate 500 toward the oxide semiconductor layer 544.

[0049] The oxide semiconductor layer 544 has light transmitting properties. The oxide semiconductor layer 544 is divided into a source region 544S, a drain region 544D, and a channel region 544CH. The channel region 544CH is a region of the oxide semiconductor layer 544 vertically below the gate electrode 564. The source region 544S is a region of the oxide semiconductor layer 544 that does not overlap with the gate electrode 564 and is closer to the source electrode 591 than the channel region 544CH. The drain region 544D is a region of the oxide semiconductor layer 544 that does not overlap with the gate electrode 564 and is closer to the drain electrode 593 than the channel region 544CH. The channel region 544CH corresponds to the channel portion 403a shown in FIG. 4, and the source region 544S and the drain region 544D correspond to the conductive portion 403b shown in FIG. 4.

[0050] The gate electrode 564 is made of a metal layer and faces the oxide semiconductor layer 544. The gate insulating layer 550 is provided between the oxide semiconductor layer 544 and the gate electrode 564. The gate insulating layer 550 is in contact with the oxide semiconductor layer 544. The insulating layer 570 and the insulating layer 580 are provided on the gate insulating layer 550 and the gate electrode 564, respectively. The insulating layer 570 and the insulating layer 580 are provided with contact holes 571 and 573 that reach the oxide semiconductor layer 544. The source electrode 591 is in contact with the source region 544S through the contact hole 571. The drain electrode 593 is in contact with the drain region 544D through the contact hole 573.

[0051] The oxide semiconductor layer 544 has a polycrystalline structure including a plurality of crystal grains. Although details will be described later, the oxide semiconductor layer 544 having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. In the following description, an oxide semiconductor having a polycrystalline structure itself may be referred to as Poly-OS.

[0052] In this embodiment, the oxide semiconductor layer 544 contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. Metal elements other than indium include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides. However, the present invention is not limited to this example, and the oxide semiconductor layer 544 may contain metal elements other than the above.

[0053] The source region 544S and the drain region 544D may contain elements other than the above metal elements. As will be described in detail later, the source region 544S and the drain region 544D have a lower resistivity than the channel region 544CH. Such a decrease in resistivity is achieved by adding an element such as argon (Ar), phosphorus (P), or boron (B) (hereinafter referred to as an "impurity element") to the oxide semiconductor layer 544.

[0054] The concentration of impurity elements contained in the source region 544S and the drain region 544D is 1×10 18 cm -3 More than 1×10 21 cm -3 The source region 544S and the drain region 544D are preferably 1×10 18 cm -3 More than 1×10 21 cm -3When the impurity element is contained in the source region 544S and the drain region 544D, it is presumed that the impurity element is intentionally added by ion implantation or ion doping. 18 cm -3 Impurity elements other than argon (Ar), phosphorus (P), or boron (B) may be contained in the channel region 544CH at a concentration of less than 1×10. Note that if an impurity element is contained in the channel region 544CH, it will affect the characteristics of the semiconductor device 10. Therefore, the concentration of the impurity element contained in the channel region 544CH is set to 1×10 18 cm -3 Less than (more preferably 1 × 10 16 cm -3 It is preferable that

[0055] The gate electrode 564 functions as a top gate of the semiconductor device 10. The gate insulating layer 550 functions as a gate insulating layer for the top gate and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layer 570 and the insulating layer 580 insulate the gate electrode 564 from the source electrode 591 and the gate electrode 564 from the drain electrode 593, respectively. This makes it possible to reduce parasitic capacitances generated between the gate electrode 564 and the source electrode 591 and between the gate electrode 564 and the drain electrode 593.

[0056] 6, the gate wiring 565 extends in a first direction (direction D1). A part of the gate wiring 565 branches out toward a second direction (direction D2) and overlaps with the oxide semiconductor layer 544. The part of the gate wiring 565 that overlaps with the oxide semiconductor layer 544 functions as a gate electrode 564. The length of a region where the oxide semiconductor layer 544 and the gate electrode 564 overlap (i.e., a channel region 544CH) in the first direction (direction D1) is the channel length (L), and the length in the second direction (direction D2) is the channel width (W).

[0057] [Crystal structure of oxide semiconductor layer] In this embodiment, the oxide semiconductor layer 544 and the common wiring 204 contain Poly-OS. In the following description, the oxide semiconductor layer 544 is taken as an example, but the same description can be applied to the common wiring 204 that is formed of the same layer as the oxide semiconductor layer 544.

[0058] The crystal grains contained in the Poly-OS observed from the top surface of the oxide semiconductor layer 544 (or from the thickness direction of the oxide semiconductor layer 544) have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained by, for example, cross-sectional SEM observation, cross-sectional TEM observation, or an electron backscattered diffraction (EBSD) method.

[0059] In the Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of the Poly-OS can be identified by electron beam diffraction, XRD, or the like. That is, the crystal structure of the oxide semiconductor layer 544 can be identified by electron beam diffraction, XRD, or the like.

[0060] The oxide semiconductor layer 544 preferably has a cubic crystal structure. A cubic crystal structure has high symmetry, and even if oxygen defects are generated in the oxide semiconductor layer 544, structural relaxation is unlikely to occur and the crystal structure is stable. As described above, the oxide semiconductor layer 544 contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. By increasing the ratio of indium element, the crystal structure of each of the multiple crystal grains can be controlled, and the oxide semiconductor layer 544 having a cubic crystal structure can be formed.

[0061] As shown in FIG. 5, the oxide semiconductor layer 544 includes a channel portion 403a (see FIG. 4) corresponding to the channel region 544CH, and a conductive portion 403b (see FIG. 4) corresponding to the source region 544S and the drain region 544D. In the oxide semiconductor layer 544, the channel portion 403a has a first crystal structure, and the conductive portion 403b has a second crystal structure. The conductive portion 403b has a higher electrical conductivity than the channel portion 403a, but the second crystal structure is the same as the first crystal structure. Here, the two crystal structures being the same means that the crystal systems are the same. For example, when the crystal structure of the oxide semiconductor layer 544 is a cubic crystal, the first crystal structure of the channel portion 403a and the crystal structure of the conductive portion 403b are both cubic crystals and are the same. The first crystal structure and the second crystal structure can be identified using, for example, a microelectron beam diffraction method or the like.

[0062] In addition, in a given crystal orientation, the d-spacing value of the first crystal structure and the d-spacing value of the second crystal structure are substantially the same. Here, "substantially the same" refers to one d-spacing value being 0.95 to 1.05 times the other d-spacing value. Alternatively, this refers to the two diffraction patterns being almost identical in a microelectron beam diffraction method.

[0063] There may be no crystal grain boundary between the channel portion 403a and the conductive portion 403b. Also, the channel portion 403a and the conductive portion 403b may be included in one crystal grain. In other words, the change from the channel portion 403a to the conductive portion 403b may be a continuous change in crystal structure.

[0064] 7A to 7C are schematic diagrams illustrating a bonding state of Poly-OS included in the conductive portion 403b of the oxide semiconductor layer 544. 7A to 7C show Poly-OS including indium atoms (In atoms) and metal atoms (M atoms) different from In atoms.

[0065] In the Poly-OS shown in FIG. 7A, each of the In atom and the metal atom M is bonded to an oxygen atom (O atom). In the crystal structure of the Poly-OS shown in FIG. 7A, in the conductive portion 403b, in order to increase the electrical conductivity compared to the channel portion 403a, the bond between the In atom and the O atom (or the metal atom M and the O atom) is cut, and oxygen defects resulting from the removal of the O atom are generated (see FIG. 7B). Since the Poly-OS contains crystal grains with a large crystal grain size, the long-range order is easily maintained. Therefore, even if oxygen defects are generated, structural relaxation is unlikely to occur, and the positions of the In atom and the metal atom M are hardly changed. In the state shown in FIG. 7B, if hydrogen is present, the dangling bond of the In atom in the oxygen defect and the dangling bond of the metal atom M are bonded to the hydrogen atom (H atom) and stabilized (see FIG. 7C). Since the H atom in the oxygen defect functions as a donor, the carrier concentration of the conductive portion 403b increases.

[0066] 7C, in Poly-OS, even if an H atom is bonded in an oxygen defect, the positions of the In atom and the metal atom M hardly change. Therefore, the second crystal structure of the conductive portion 403b does not change from the crystal structure of Poly-OS without oxygen defects. That is, the second crystal structure of the conductive portion 403b is the same as the first crystal structure of the channel portion 403a.

[0067] FIG. 8 is a band diagram illustrating the band structure of the conductive portion 403b of the oxide semiconductor layer 544. In FIG.

[0068] As shown in FIG. 8, the poly-OS of the conductive portion 403b has a band gap E g The energy level includes a first energy level 1010 and a second energy level 1020. In addition, the energy level E C The first energy level 1010 includes a tail level 1030 adjacent to each of the first and second energy levels. gThe first energy level 1010 is a deep trap level present in the conduction band and is due to oxygen vacancies. The second energy level 1020 is a donor level present near the bottom of the conduction band and is due to hydrogen atoms bonded in the oxygen vacancies. The tail level 1030 is due to a disorder of the long-range order.

[0069] Although the Poly-OS in the conductive portion 403b contains oxygen defects, it has a crystalline structure and maintains long-range order. In addition, in the Poly-OS in the conductive portion 403b, hydrogen atoms can be bonded within the oxygen defects without causing structural disorder. Therefore, the DOS of the second energy level 1020 can be increased while suppressing the DOS of the tail level 1030. Therefore, the DOS of the second energy level 1020 is larger than the DOS of the tail level 1030 near the bottom of the conduction band, and the DOS of the second energy level 1020 is larger than the DOS of the energy level E C That is, the Fermi level E F is the energy level E at the bottom of the conduction band C , and the Poly-OS in the conductive portion 403b has metallic properties.

[0070] As described above, the Poly-OS in the conductive portion 403b has metallic properties, unlike conventional oxide semiconductors. Therefore, the conductive portion 403b can have a sufficiently low resistance by generating oxygen defects. The sheet resistance of the conductive portion 403b is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq.

[0071] In this manner, in this embodiment, since it is possible to sufficiently reduce the resistance of the source region 544S and the drain region 544D (i.e., the conductive portion 403b) of the oxide semiconductor layer 544, the conductive portion 403b can be used as wiring. The common wiring 204 shown in FIGS. 3 and 4 utilizes such a feature of the oxide semiconductor layer 544.

[0072] In this embodiment, a light-shielding layer may be provided between the substrate 500 and the oxide semiconductor layer 544. By providing the light-shielding layer in a region overlapping with the channel region 544CH, it is possible to suppress a characteristic change of the semiconductor device 10 caused by irradiation of the channel region 544CH with light. In this case, the light-shielding layer may be used as a gate electrode to give the semiconductor device 10 a dual-gate structure.

[0073] [Method of manufacturing semiconductor device] A method for manufacturing the semiconductor device 10 used in the display device 100 of one embodiment of the present invention will be described with reference to Fig. 9 to Fig. 18. Fig. 9 is a sequence diagram showing a method for manufacturing the semiconductor device 10 used in the display device 100 of one embodiment of the present invention. Figs. 10 to 18 are cross-sectional views showing a method for manufacturing the semiconductor device 10 used in the display device 100 of one embodiment of the present invention.

[0074] First, as shown in FIGS. 9 and 10, an underlayer 520 is formed on a substrate 500 (step S1001).

[0075] A rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used as the substrate 500. When the substrate 500 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used as the substrate 500. When a substrate containing a resin is used as the substrate 500, an impurity element may be introduced into the resin in order to improve the heat resistance of the substrate 500.

[0076] The underlayer 520 is formed by a chemical vapor deposition (CVD) method or a sputtering method. A general insulating material is used as the underlayer 520. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlOx ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), and aluminum nitride (AlN x ) and other inorganic insulating materials are used.

[0077] The above SiO x N y and AlO x N y is a silicon and aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0078] The underlayer 520 is formed in a single layer structure or a laminated structure. When the underlayer 520 is formed in a laminated structure, it is preferable that the insulating material containing nitrogen and the insulating material containing oxygen are formed in this order from the substrate 500. By using the insulating material containing nitrogen, for example, it is possible to block impurities diffusing from the substrate 500 side toward the oxide semiconductor layer 544. In addition, by using the insulating material containing oxygen, it is possible to release oxygen by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the insulating material containing oxygen releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 500. In this embodiment, for example, silicon nitride is used as the insulating material containing nitrogen. For example, silicon oxide is used as the insulating material containing oxygen.

[0079] 9 and 11, an oxide semiconductor layer 540 is formed on the underlayer 520 (step S1002). The oxide semiconductor layer 540 is formed by sputtering or atomic layer deposition (ALD). The oxide semiconductor layer 540 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm.

[0080] A metal oxide having semiconductor properties can be used as the oxide semiconductor layer 540. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 540. The ratio of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or lanthanoids is used as the oxide semiconductor layer 540. Elements other than the above may be used as the oxide semiconductor layer 540. In this embodiment, a metal oxide (IGO-based oxide semiconductor) containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 540.

[0081] When the oxide semiconductor layer 540 is crystallized by OS annealing (step S1004) described later, the oxide semiconductor layer 540 after deposition and before OS annealing is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the oxide semiconductor layer 540 is preferably formed under conditions that prevent the oxide semiconductor layer 540 immediately after deposition from crystallizing as much as possible. For example, when the oxide semiconductor layer 540 is formed by a sputtering method, conditions that prevent the oxide semiconductor layer 540 from crystallizing can be realized by controlling the temperature of the object on which the oxide semiconductor layer 540 is to be formed (the substrate 500 and a structure formed thereon).

[0082] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object increases with the film formation process. If the temperature of the target object increases during the film formation process, the oxide semiconductor layer 540 contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing is inhibited. In order to control the temperature of the target object as described above, for example, the target object can be cooled while the film is formed. For example, the target object can be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer 540 while cooling the target object, the oxide semiconductor layer 540 having a small amount of crystalline components immediately after the film formation can be formed.

[0083] Next, as shown in FIGS. 9 and 12, a pattern of the oxide semiconductor layer 540 is formed by photolithography (step S1003). Although not shown, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. Either wet etching or dry etching may be used when etching the oxide semiconductor layer 540. In the case of wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0084] The oxide semiconductor layer 540 is preferably patterned before the OS annealing performed in step S1004. If the oxide semiconductor layer 540 is crystallized by the OS annealing, it tends to be difficult to etch. Even if the oxide semiconductor layer 540 is damaged by etching, the damage can be repaired by the OS annealing.

[0085] After the oxide semiconductor layer 540 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (step S1004). In the OS annealing, the oxide semiconductor layer 540 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. By performing the OS annealing, the oxide semiconductor layer 540 is crystallized, and an oxide semiconductor layer 544 having a polycrystalline structure is formed.

[0086] In manufacturing the display device 100 of this embodiment, a wiring pattern made of an oxide semiconductor layer to be used as the common wiring 204 is formed at the same time as forming the oxide semiconductor layer 544 of the selection transistor 201. Therefore, the wiring pattern formed in this process has the same crystal structure as the oxide semiconductor layer 544.

[0087] Next, as shown in FIGS. 9 and 13, a gate insulating layer 550 is formed on the oxide semiconductor layer 544 (Step S1005).

[0088] The description of the base layer 520 may be referred to for the method of forming the gate insulating layer 550 and the insulating material thereof. In this embodiment, the thickness of the gate insulating layer 550 is, for example, not less than 50 nm and not more than 150 nm, but is not limited to this example.

[0089] It is preferable to use an insulating material containing oxygen for the gate insulating layer 550. It is also preferable to use an insulating layer with few defects for the gate insulating layer 550. For example, when the oxygen composition ratio in the gate insulating layer 550 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 550 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 550 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x), the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 550 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the insulating layer 580. For example, the gate insulating layer 550 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0090] In order to form an insulating layer with few defects as the gate insulating layer 550, the gate insulating layer 550 may be formed at a film formation temperature of 350° C. or higher. In addition, after forming the gate insulating layer 550, a process of implanting oxygen into a part of the gate insulating layer 550 may be performed. In this embodiment, in order to form an insulating layer with few defects as the gate insulating layer 550, a silicon oxide layer is formed at a film formation temperature of 350° C. or higher.

[0091] Next, as shown in FIGS. 9 and 13, a metal oxide layer 555 containing aluminum as a main component is formed on the gate insulating layer 550 (step S1006).

[0092] The metal oxide layer 555 is formed by a sputtering method. By forming the metal oxide layer 555, oxygen is implanted into the gate insulating layer 550. The metal oxide layer mainly composed of aluminum is, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. "Aluminum-based metal oxide layer" means that the ratio of aluminum contained in metal oxide layer 555 is 1% or more of the entire metal oxide layer 555. The ratio of aluminum contained in metal oxide layer 555 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 555. The above ratio may be a mass ratio or a weight ratio.

[0093] The thickness of the metal oxide layer 555 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 555. Aluminum oxide has high barrier properties against gas. In this embodiment, aluminum oxide used as the metal oxide layer 555 suppresses outward diffusion of oxygen implanted into the gate insulating layer 550 during deposition of the metal oxide layer 555.

[0094] For example, when the metal oxide layer 555 is formed by a sputtering method, the process gas used in the sputtering remains in the film of the metal oxide layer 555. For example, when Ar is used as the process gas for the sputtering, Ar may remain in the film of the metal oxide layer 555. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 555.

[0095] A gate insulating layer 550 is formed on the oxide semiconductor layer 544, and a metal oxide layer 555 is formed on the gate insulating layer 550. In this state, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 544 (step S1007).

[0096] During the process from when the oxide semiconductor layer 544 is formed until when the gate insulating layer 550 is formed on the oxide semiconductor layer 544, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 544. By the above-mentioned oxidation annealing, oxygen released from the base layer 520 is supplied to the upper surface and side surfaces of the oxide semiconductor layer 544, and the oxygen defects inside the oxide semiconductor layer 544 are repaired.

[0097] In the above-mentioned oxidation annealing, oxygen implanted into the gate insulating layer 550 is blocked by the metal oxide layer 555, and thus is prevented from being released into the atmosphere. Therefore, oxygen is efficiently supplied to the oxide semiconductor layer 544 by the oxidation annealing performed in step S1007, and oxygen defects in the oxide semiconductor layer 544 are repaired.

[0098] Next, as shown in FIG. 9 and FIG. 14, after the oxidation annealing, the metal oxide layer 555 is etched (removed) (step S1008). Either wet etching or dry etching may be used for etching the metal oxide layer 555. As an etchant for the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By this etching, the metal oxide layer 555 formed on the entire surface of the gate insulating layer 550 is removed. In other words, the removal of the metal oxide layer 555 is performed without using a mask. In further other words, by the etching performed in step S1008, all of the metal oxide layer 555 in the region overlapping with the oxide semiconductor layer 544 formed in a certain pattern is removed at least in a plan view.

[0099] 9 and 15, a gate electrode 564 is formed on the gate insulating layer 550 (step S1009). The gate electrode 564 is formed by patterning a metal layer formed by sputtering or atomic layer deposition. As described above, the gate electrode 564 is formed so as to be in contact with the gate insulating layer 550 exposed by removing the metal oxide layer 555.

[0100] A common metal material is used as the material of the gate electrode 564. Examples of the metal material that can be used include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The gate electrode 564 may be made of the above materials in a single layer structure or a multilayer structure.

[0101] 9 and 16, with the gate electrode 564 formed, a source region 544S and a drain region 544D of the oxide semiconductor layer 544 are formed (step S1010). Specifically, an impurity element is implanted into the oxide semiconductor layer 544 through the gate insulating layer 550 by ion implantation or ion doping using the gate electrode 564 as a mask. In step S1010, an impurity element such as argon (Ar), phosphorus (P), or boron (B) is implanted into a part of the oxide semiconductor layer 544 that is not covered with the gate electrode 564.

[0102] The region of the oxide semiconductor layer 544 into which the impurity element is implanted has a low resistance to such an extent that the region can function as a conductive layer due to the formation of oxygen vacancies. That is, as a result of implanting the impurity element into the oxide semiconductor layer 544 in step S1010, a conductive portion 403b (a source region 544S and a drain region 544D) is formed in the region not covered with the gate electrode 564. On the other hand, a channel portion 403a (a channel region 544CH) is formed in the region of the oxide semiconductor layer 544 covered with the gate electrode 564. Since the gate electrode 564 functions as a mask, the impurity element is not implanted into the channel portion 403a.

[0103] In manufacturing the display device 100 of this embodiment, impurities are injected into the oxide semiconductor layer 544 and at the same time, impurities are also injected into the wiring pattern made of the oxide semiconductor layer (the wiring pattern formed simultaneously with the oxide semiconductor layer 544 in FIG. 12). This impurity injection causes the wiring pattern to become an oxide semiconductor layer having the same sheet resistance or electrical conductivity as the conductive portion 403b. That is, the common wiring 204 is formed by the process shown in FIG.

[0104] In addition, in this embodiment, since impurity elements are implanted into the oxide semiconductor layer 544 through the gate insulating layer 550, impurity elements such as argon (Ar), phosphorus (P), and boron (B) are contained not only in the source region 544S and the drain region 544D but also in the gate insulating layer 550.

[0105] Next, as shown in FIGS. 9 and 17, insulating layers 570 and 580 are formed as interlayer films on the gate insulating layer 550 and the gate electrode 564 (step S1011).

[0106] The description of the base layer 520 may be referred to for the film formation method and insulating material of the insulating layers 570 and 580. The film thickness of the insulating layer 570 is 50 nm or more and 500 nm or less. The film thickness of the insulating layer 580 is 50 nm or more and 500 nm or less. In this embodiment, for example, a silicon nitride layer is formed as the insulating layer 570, and a silicon oxide layer is formed as the insulating layer 580.

[0107] 9 and 18, contact holes 571 and 573 are formed in the gate insulating layer 550 and the insulating layers 570 and 580 (step S1012). The source region 544S is exposed through the contact hole 571, and the drain region 544D is exposed through the contact hole 573. After the source region 544S and the drain region 544D are exposed through the contact holes 571 and 573, the source electrode 591 and the drain electrode 593 shown in FIG. 5 are formed (step S1013). Through the above processes, the semiconductor device 10 shown in FIG. 5 is completed.

[0108] The source electrode 591 and the drain electrode 593 are formed by, for example, a sputtering method. The source electrode 591 and the drain electrode 593 can be formed by using a general metal material. As the metal material, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. The source electrode 591 and the drain electrode 593 may have a single-layer structure or a multilayer structure.

[0109] In the semiconductor device 10 manufactured by the above manufacturing method, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the field effect mobility means the field effect mobility in the saturation region of the semiconductor device 10, and refers to the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the voltage (Vg) supplied to the gate electrode minus the threshold voltage (Vth) of the semiconductor device 10 (Vg-Vth).

[0110] In the semiconductor device 10 of this embodiment, the resistance value of the conductive portion 403b constituting the source region 544S and the drain region 544D is sufficiently low. Therefore, it is possible to use an oxide semiconductor layer formed of the same layer as the conductive portion 403b as wiring (specifically, the common wiring 204). Since the oxide semiconductor has light-transmitting properties, if it is possible to use the oxide semiconductor as a wiring material as in this embodiment, it is very advantageous in improving the aperture ratio of the display unit 110 in the display device 100.

[0111] Second Embodiment In this embodiment, a semiconductor device 10a having a different configuration from the semiconductor device 10 shown in the first embodiment will be described.

[0112] The configuration of the semiconductor device 10a according to this embodiment is similar to that of the semiconductor device 10 of the first embodiment, but differs from the semiconductor device 10 of the first embodiment in that a metal oxide layer 530 is provided between the base layer 520 and the oxide semiconductor layer 544. In the following description, the description of the same configuration as in the first embodiment will be omitted, and the differences from the first embodiment will be mainly described.

[0113] 19 is a cross-sectional view showing a configuration of a semiconductor device 10a used in a display device 100 according to one embodiment of the present invention. As shown in FIG. 19, the semiconductor device 10a includes a base layer 520, a metal oxide layer 530, an oxide semiconductor layer 544, a gate insulating layer 550, a gate electrode 564, an insulating layer 570, an insulating layer 580, a source electrode 591, and a drain electrode 593.

[0114] The metal oxide layer 530 is provided on the base layer 520. The metal oxide layer 530 is in contact with the base layer 520. The oxide semiconductor layer 544 is provided on the metal oxide layer 530. A lower surface of the oxide semiconductor layer 544 is in contact with the metal oxide layer 530. In this embodiment, an end of the metal oxide layer 530 and an end of the oxide semiconductor layer 544 approximately coincide with each other.

[0115] The metal oxide layer 530 is a layer containing a metal oxide mainly composed of aluminum, similar to the metal oxide layer 555 (see FIG. 13), and has a function as a gas barrier film that blocks gases such as oxygen and hydrogen. The metal oxide layer 530 can be made of the same material as the metal oxide layer 555, but may also be made of a different material.

[0116] 6, the planar shape of the semiconductor device 10a is not shown. However, in the planar view, the planar pattern of the metal oxide layer 530 is substantially the same as the planar pattern of the oxide semiconductor layer 544. With reference to FIG. 19, the lower surface of the oxide semiconductor layer 544 is covered with the metal oxide layer 530. In particular, in this embodiment, the entire lower surface of the oxide semiconductor layer 544 is covered with the metal oxide layer 530.

[0117] A high-mobility semiconductor device 10a can be realized by setting the ratio of indium to 50% or more in the oxide semiconductor layer 544. On the other hand, in such an oxide semiconductor layer 544, oxygen contained in the oxide semiconductor layer 544 is easily reduced, and oxygen defects are easily formed in the oxide semiconductor layer 544.

[0118] In a top-gate structure such as the semiconductor device 10a, hydrogen is released from a layer (for example, the underlayer 520) provided closer to the substrate 500 than the oxide semiconductor layer 544 during a heat treatment process in the manufacturing process. When hydrogen released from a lower layer reaches the oxide semiconductor layer 544, oxygen defects may occur in the oxide semiconductor layer 544. The occurrence of oxygen defects is more noticeable as the pattern size of the oxide semiconductor layer 544 becomes larger. In order to suppress the occurrence of such oxygen defects, it is preferable to suppress the arrival of hydrogen at the lower surface of the oxide semiconductor layer 544.

[0119] The upper surface of the oxide semiconductor layer 544 is affected by a process (for example, a patterning process or an etching process) performed after the oxide semiconductor layer 544 is formed. On the other hand, the lower surface of the oxide semiconductor layer 544 is not affected as described above. Therefore, the number of oxygen defects formed on the upper surface of the oxide semiconductor layer 544 is greater than the number of oxygen defects formed on the lower surface of the oxide semiconductor layer 544. That is, the oxygen defects in the oxide semiconductor layer 544 are not uniformly distributed in the film thickness direction of the oxide semiconductor layer 544 but are non-uniformly distributed in the film thickness direction of the oxide semiconductor layer 544. Specifically, the number of oxygen defects in the oxide semiconductor layer 544 is smaller on the lower surface side of the oxide semiconductor layer 544 and is more on the upper surface side of the oxide semiconductor layer 544.

[0120] When an amount of oxygen necessary to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer 544 in which oxygen defects are distributed as described above is uniformly supplied to the oxide semiconductor layer 544, an excess of oxygen is supplied to the lower surface side of the oxide semiconductor layer 544. As a result, a defect level different from the oxygen defects is formed on the lower surface side due to the excess oxygen, which may cause a phenomenon such as a characteristic fluctuation in a reliability test or a decrease in field-effect mobility. Therefore, in order to suppress such a phenomenon, it is desirable to supply oxygen to the upper surface side of the oxide semiconductor layer 544 while suppressing the supply of oxygen to the lower surface side of the oxide semiconductor layer 544.

[0121] As described above, in the configuration and manufacturing method of the first embodiment, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a risk that the characteristics may vary due to the reliability test. In other words, it can be said that there is a trade-off between the initial characteristics and the reliability test. However, according to the present embodiment, by disposing the metal oxide layer 530 on the lower surface of the oxide semiconductor layer 544, it is possible to obtain good initial characteristics and reliability tests for the semiconductor device 10a.

[0122] A method for manufacturing the semiconductor device 10a used in the display device 100 of one embodiment of the present invention will be described with reference to Fig. 20 to Fig. 23. Fig. 20 is a sequence diagram showing a method for manufacturing the semiconductor device 10a used in the display device 100 of one embodiment of the present invention. Figs. 21 to 23 are cross-sectional views showing a method for manufacturing the semiconductor device 10a used in the display device 100 of one embodiment of the present invention.

[0123] 20, an underlayer 520 is formed on a substrate 500 (step S2001). For step S2001, refer to the description of step S1001 shown in FIGS. 9 and 10. In this embodiment, silicon nitride and silicon oxide are used as materials for the underlayer 520. Silicon oxide is preferable in terms of reducing oxygen defects in the oxide semiconductor layer 544 because it releases oxygen by heat treatment.

[0124] 20 and 21, a metal oxide layer 530 and an oxide semiconductor layer 540 are formed on an underlayer 520 (step S2002). The metal oxide layer 530 and the oxide semiconductor layer 540 are formed by a sputtering method or an atomic layer deposition method (ALD).

[0125] For the material of the metal oxide layer 530, the description of the material of the metal oxide layer 555 shown in FIG. 13 may be referred to. The film thickness of the metal oxide layer 530 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 530. Aluminum oxide has high barrier properties against gas. In this embodiment, aluminum oxide used as the metal oxide layer 530 blocks hydrogen and oxygen released from the underlayer 520 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 540.

[0126] The oxide semiconductor layer 540 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 540. The oxide semiconductor layer 540 is amorphous before OS annealing performed in step S2004 described later.

[0127] When the oxide semiconductor layer 540 is crystallized by OS annealing described later, the oxide semiconductor layer 540 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after deposition and before OS annealing. For a deposition method for making the oxide semiconductor layer 540 amorphous after deposition, the description of step S1002 in FIG. 9 may be referred to.

[0128] Next, as shown in FIG. 20 and FIG. 22, a pattern of the oxide semiconductor layer 540 is formed (step S2003). Although not shown, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. The oxide semiconductor layer 540 may be etched by either wet etching or dry etching. The wet etching can be performed using an acidic etchant. As the acidic etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0129] 20 , after the oxide semiconductor layer 540 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (step S2004). In this embodiment, the oxide semiconductor layer 540 is crystallized by the OS annealing. The crystallized oxide semiconductor layer is referred to as an oxide semiconductor layer 544.

[0130] Next, as shown in FIG. 20 and FIG. 23, a pattern of the metal oxide layer 530 is formed (step S2005). The metal oxide layer 530 is etched using the crystallized oxide semiconductor layer 544 as a mask. Either wet etching or dry etching may be used for etching the metal oxide layer 530. As an etchant for wet etching, for example, diluted hydrofluoric acid (DHF) is used. The crystallized oxide semiconductor layer 544 has etching resistance to diluted hydrofluoric acid compared to the amorphous oxide semiconductor layer 540. Therefore, the metal oxide layer 530 can be etched in a self-aligned manner using the oxide semiconductor layer 544 as a mask. This makes it possible to omit a photolithography process.

[0131] The process shown in step S2006 to step S2014 in Fig. 20 is similar to step S1005 to step S1013 in Fig. 9, and therefore the following description will be omitted. By going through step S2006 to step S2014, the semiconductor device 10a shown in Fig. 19 can be formed.

[0132] In the semiconductor device 10a manufactured by the above manufacturing method, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 50 cm 2 / Vs or more, 55cm 2 / Vs or more, or 60cm 2 In this embodiment, the field effect mobility is defined in the same manner as in the first embodiment.

[0133] Third embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the second embodiment will be described. The structure of the semiconductor device of this embodiment is the same as the semiconductor device 10a described in the second embodiment in appearance, so in the following description, it will be referred to as the semiconductor device 10a. In this embodiment, the description will focus on the points that are different from the second embodiment.

[0134] Fig. 24 is a sequence diagram showing a method for manufacturing a semiconductor device 10a used in a display device 100 according to an embodiment of the present invention. As shown in Fig. 24, in this embodiment, two steps, step S2007 and step S2009 shown in Fig. 20, are omitted. That is, in this embodiment, after the gate insulating layer 550 is formed, oxidation annealing (step S2008) is performed in this state. By the oxidation annealing, oxygen released from the gate insulating layer 550 is supplied to the oxide semiconductor layer 540, and oxygen defects contained in the oxide semiconductor layer 540 are repaired. The role of the metal oxide layer 530 in this case is the same as in the second embodiment, and therefore will not be described here.

[0135] In the semiconductor device 10a manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the field effect mobility is defined in the same manner as in the first embodiment.

[0136] Fourth embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the first embodiment will be described. Since the structure of the semiconductor device of this embodiment is identical in appearance to the semiconductor device 10 described in the first embodiment, the semiconductor device will be referred to as the semiconductor device 10 in the following description. In this embodiment, the description will focus on the differences from the first embodiment.

[0137] Fig. 25 is a sequence diagram showing a manufacturing method of the semiconductor device 10 used in the display device 100 of one embodiment of the present invention. As shown in Fig. 25, in this embodiment, two processes, step S1006 and step S1008 shown in Fig. 9, are omitted. That is, in this embodiment, after the gate insulating layer 550 is formed, oxidation annealing (step S1007) is performed in this state. By the oxidation annealing, oxygen released from the gate insulating layer 550 is supplied to the oxide semiconductor layer 544, and oxygen defects contained in the oxide semiconductor layer 544 are repaired.

[0138] Fifth embodiment In the first embodiment, an example in which the common electrode 205 is disposed on the pixel electrode 620 has been described, but in this embodiment, the positional relationship between the pixel electrode 620 and the common electrode 205 may be reversed. That is, the pixel electrode 620 may be disposed on the common electrode 205. In this embodiment, configurations different from those in the first embodiment will be described, and the same configurations will be illustrated using the same reference numerals, and description thereof will be omitted.

[0139] Fig. 26 is a cross-sectional view showing the structure of a pixel 112 in a display device 100 according to one embodiment of the present invention. As shown in Fig. 26, in this embodiment, a common electrode 205 is provided on a planarizing layer 610. Moreover, a pixel electrode 620 is disposed on the common electrode 205 via an insulating layer 630. Even in this embodiment, the alignment of liquid crystal molecules in a liquid crystal layer 650 is controlled by a fringe electric field formed between the pixel electrode 620 and the common electrode 205.

[0140] Sixth embodiment In the first embodiment, an example in which the selection transistor 201 has a top gate structure has been described, but the structure of the selection transistor 201 is not limited to the top gate structure. In the present embodiment, an example in which the selection transistor arranged in the pixel 112 has a dual gate structure will be described. In the present embodiment, configurations different from those in the first embodiment will be described, and the same configurations will be illustrated with the same reference numerals and descriptions thereof will be omitted.

[0141] 27 is a cross-sectional view showing a structure of a pixel 112 in a display device 100 according to one embodiment of the present invention. As shown in FIG. 27, in this embodiment, a gate electrode 525 is provided on a base layer 520. The gate electrode 525 functions as a bottom gate in the selection transistor 201b according to this embodiment. The material constituting the gate electrode 525 may be the same as or different from the material constituting the gate electrode 564. However, it is preferable that the material of the gate electrode 525 is a material that can withstand the temperature of the process for crystallizing the oxide semiconductor layer 544 (S1004: OS annealing shown in FIG. 9).

[0142] A gate insulating layer 527 is provided on the gate electrode 525. The gate electrode 525 and the oxide semiconductor layer 544 face each other with the gate insulating layer 527 interposed therebetween. The gate insulating layer 527 can be made of the same material as the gate insulating layer 550. In this embodiment, a silicon oxide layer is used as the gate insulating layer 527.

[0143] When the selection transistor 201a has a dual gate structure as in this embodiment, the gate electrode 525 functions as a light-shielding film. That is, the gate electrode 525 has a function of blocking light directed from the substrate 500 side toward the channel portion 403a of the oxide semiconductor layer 544. Therefore, the selection transistor 201a of this embodiment has an advantage of having a lower off-current than the selection transistor 201 of the first embodiment. In addition, since a gate voltage is applied to the channel portion 403a of the oxide semiconductor layer 544 from above and below, an increase in on-current is expected.

[0144] Seventh embodiment In the first embodiment, an example in which the selection transistor 201 has a top gate structure has been described, but in this embodiment, an example in which the selection transistor arranged in the pixel 112 has a bottom gate structure will be described. In this embodiment, configurations different from those in the first embodiment will be described, and the same configurations will be illustrated with the same reference numerals and descriptions thereof will be omitted.

[0145] Fig. 28 is a cross-sectional view showing a structure of a pixel 112 in a display device 100 of one embodiment of the present invention. As shown in Fig. 28, in the selection transistor 201b of this embodiment, a gate electrode 525 and a gate insulating layer 527 are provided on a base layer 520. The gate electrode 525 and the gate insulating layer 527 are as described in the sixth embodiment (see Fig. 27).

[0146] An oxide semiconductor layer 544a is provided on the gate insulating layer 527. A source electrode 591a and a drain electrode 593a are arranged on the oxide semiconductor layer 544 at positions corresponding to the source region 544S and the drain region 544D, respectively. A region of the oxide semiconductor layer 544a where the source electrode 591a and the drain electrode 593a are not arranged functions as a channel region 544CH. In the selection transistor 201b of this embodiment, the source electrode 591a and the drain electrode 593a are arranged so as to be in direct contact with the oxide semiconductor layer 544a.

[0147] Insulating layers 570 and 580 are disposed on the source electrode 591a and the drain electrode 593a. In this embodiment, the insulating layer 580 and the insulating layer 570 are disposed in this order from the bottom up, which is the opposite of the first embodiment. That is, the insulating layer 580 made of silicon oxide is in contact with the channel region 544CH of the oxide semiconductor layer 544a. With this structure, when a heat treatment similar to the oxidation annealing (S1007) shown in FIG. 9 is performed, oxygen is supplied from the insulating layer 580 to the channel region 544CH of the oxide semiconductor layer 544a, and oxygen defects inside the channel region 544CH can be repaired.

[0148] The oxide semiconductor layer 544a of this embodiment has a polycrystalline structure similar to that of the first embodiment, since the oxide semiconductor layer 544a is subjected to a heat treatment similar to the OS annealing (S1004) shown in Fig. 9. However, the source region 544S and the drain region 544D can have low resistance due to oxygen vacancies formed in the oxide semiconductor layer 544a when the source electrode 591a and the drain electrode 593a are formed.

[0149] The common wiring 204a is formed in the same layer as the oxide semiconductor layer 544a, but is formed in the same process as the channel region 544CH. Therefore, it is desirable to add a separate process for reducing the resistance of the common wiring 204a. In the example shown in FIG. 28, after forming a wiring pattern made of an oxide semiconductor layer used as the common wiring 204a, impurities are added to the wiring pattern by ion implantation or the like. Therefore, the common wiring 204a has the same electrical conductivity as the conductive portion 403b in the oxide semiconductor layer 544 of the first embodiment.

[0150] Fig. 29 is a cross-sectional view showing a structure of a pixel 112 in a display device 100 according to one embodiment of the present invention. Specifically, Fig. 29 shows an example in which the resistance of a common line 204b is reduced by intentionally introducing hydrogen thereinto.

[0151] In the example shown in FIG. 29, after forming an insulating layer 580 made of silicon oxide, an opening 582 is provided in the insulating layer 580 so that a wiring pattern (not shown) made of an oxide semiconductor layer is exposed. When an insulating layer 570 made of silicon nitride is formed after the opening 582 is formed, the above-mentioned wiring pattern is covered with the insulating layer 570. When a heat treatment process is performed while the wiring pattern made of an oxide semiconductor layer and the insulating layer 570 are in contact with each other, hydrogen contained in the silicon nitride diffuses into the oxide semiconductor layer. The hydrogen diffused into the oxide semiconductor layer combines with oxygen vacancies and functions as a donor, so that the resistance of the oxide semiconductor layer is reduced.

[0152] 29, the insulating layer 570 made of silicon nitride is brought into contact with the wiring pattern used as the common wiring 204b, and hydrogen is intentionally introduced into the oxide semiconductor layer. The introduction of hydrogen sufficiently reduces the resistance of the wiring pattern made of the oxide semiconductor layer, so that the oxide semiconductor layer made of the same layer as the oxide semiconductor layer 544a can be used as the common wiring 204b.

[0153] Eighth embodiment In the first embodiment, a liquid crystal display device is taken as an example of the display device 100, but in this embodiment, an example in which the present invention is applied to an organic EL display device is described. In this embodiment, configurations different from those in the first embodiment are described, and the same configurations are illustrated with the same reference numerals, and description thereof will be omitted.

[0154] Fig. 30 is a diagram showing a configuration of a pixel circuit 300 in a display device according to one embodiment of the present invention. The pixel circuit 300 is a circuit for controlling light emission of each pixel 112 (see Fig. 1). In the example shown in Fig. 30, for convenience of explanation, a basic configuration using two semiconductor devices is illustrated, but the present invention is not limited to this example.

[0155] 30, a pixel circuit 300 of the present embodiment includes a driving transistor 301, a selection transistor 302, a storage capacitor 303, and a light-emitting element 304. The driving transistor 301 and the selection transistor 302 are configured of a semiconductor device using an oxide semiconductor layer (specifically, a thin film transistor).

[0156] The source of the driving transistor 301 is connected to an anode power line 311, and the drain of the driving transistor 301 is connected to one end (anode) of the light-emitting element 304. The other end (cathode) of the light-emitting element 304 is connected to a common wiring 312. That is, in this embodiment, the common wiring 312 functions as a cathode power line during the display period, and functions as a wiring for extracting a detection signal of the touch sensor during the sensing period. In this embodiment, a power supply voltage higher than that of the common wiring 312 is applied to the anode power line 311.

[0157] The gate of the selection transistor 302 is connected to a scanning signal line 313, and the source of the selection transistor 302 is connected to a video signal line 314. The drain of the selection transistor 302 is connected to the gate of the drive transistor 301. Note that the source and drain of the selection transistor 302 may be switched depending on the relationship between the voltage applied to the video signal line 314 and the voltage stored in the storage capacitor 303.

[0158] The storage capacitor 303 is connected to the gate and drain of the drive transistor 301 and the drain of the selection transistor 302. A gradation signal that determines the light emission intensity of the light emitting element 304 is supplied to the video signal line 314. A scanning signal for selecting a pixel to which the gradation signal is to be written is supplied to the scanning signal line 313.

[0159] In the pixel circuit 300 described above, a gray scale signal (gray scale voltage) input from a video signal line 314 via a selection transistor 302 is held in a holding capacitance 303. During a display period (light emitting period), a current according to the voltage held in the holding capacitance 303 flows from an anode power line 311 to a light emitting element 304 via a drive transistor 301. In this embodiment, the light emitting element 304 is an organic EL element. The light emitting element 304 emits light with a luminance according to the amount of current flowing between an anode electrode and a cathode electrode.

[0160] Fig. 31 is a cross-sectional view showing the structure of a pixel 112 in a display device of one embodiment of the present invention. As shown in Fig. 31, a driving transistor 301 is disposed on a substrate 500 on which an underlayer 520 is provided. The driving transistor 301 of this embodiment includes an oxide semiconductor layer 544 having a polycrystalline structure. The basic structure of the driving transistor 301 of this embodiment is similar to the structure of the selection transistor 201 of the first embodiment, and therefore a detailed description thereof will be omitted.

[0161] A common wiring 312 made of the same layer as the oxide semiconductor layer 544 of the driving transistor 301 is provided on the base layer 520. The common wiring 312 is made of an oxide semiconductor layer having the same electrical conductivity or sheet resistance as the conductive portion 403b of the oxide semiconductor layer 544.

[0162] The driving transistor 301 is provided with a pixel electrode 620 that functions as an anode electrode of the light emitting element 304. In this embodiment, the pixel electrode 620 has a structure in which a transparent conductive film such as ITO and a metal layer such as silver are laminated. In this embodiment, when the pixel electrode 620 is formed, a connection electrode 622 is formed. That is, the connection electrode 622 is composed of the same layer as the pixel electrode 620. The connection electrode 622 is connected to the common wiring 312 via contact holes provided in the gate insulating layer 527, the insulating layer 570, the insulating layer 580, and the planarization layer 610.

[0163] The end of the pixel electrode 620 is covered with a resin layer 810 called a bank or rib. An opening 815 provided in the resin layer 810 exposes a part of the surface of the pixel electrode 620. The outline of the surface of the pixel electrode 620 exposed by the opening 815 defines the light-emitting region of the light-emitting element 304. A light-emitting layer 820 and a common electrode 830 are provided inside the opening 815. The common electrode 830 functions as a cathode electrode of the light-emitting element 304 and is disposed across a plurality of pixels 112. On the other hand, the pixel electrode 620 and the light-emitting layer 820 are provided individually for each pixel 112. The light-emitting layer 820 is made of a different material depending on the display color of the pixel. Although only the light-emitting layer 820 is illustrated in FIG. 31, in addition to the light-emitting layer 820, functional layers such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer may be provided.

[0164] 30, the common electrode 830 is connected to the common wiring 312. In this embodiment, as shown in Fig. 31, the common electrode 830 is connected to the common wiring 312 via a connection electrode 622. A contact hole 816 for connecting the connection electrode 622 and the common electrode 830 may be formed at the same time as the opening 815 is formed in the resin layer 810.

[0165] A sealing layer 840 is provided on the light emitting element 304. The sealing layer 840 may be made of a resin material, or may be made of a combination of a resin material and an inorganic material. The sealing layer 840 of this embodiment has a three-layer structure in which a resin layer is sandwiched between silicon nitride layers. A protective substrate 850 is provided on the sealing layer 840. The protective substrate 850 is a light-transmitting substrate such as a glass substrate, and also functions as a touch surface of the touch sensor.

[0166] The common electrode 830 of this embodiment functions as a cathode electrode of the light-emitting element 304 during the display period, and functions as a detection electrode for extracting a detection signal of the touch sensor during the sensing period. The supply of a voltage to be applied to the common electrode 830 and the output of a detection signal from the common electrode 830 are performed via a common wiring 312. In this embodiment, the common wiring 312 is formed in the same layer as the oxide semiconductor layer 544 that functions as the active layer of the drive transistor 301. That is, since the common wiring 312 for the touch sensor can be formed of a material having translucency (oxide semiconductor layer), it is possible to improve the effective light-emitting area (area that effectively functions as a light-emitting area) in the display unit of the display device with a simple structure.

[0167] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions, based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0168] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0169] 10, 10a...semiconductor device, 100...display device, 100...display device, 100A...circuit board, 110...display section, 112...pixel, 114...scanning signal line, 115...touch sensor circuit, 116...video signal line, 120...scanning side drive section, 130...terminal section, 140...flexible printed circuit board, 150...display control circuit, 200...pixel circuit, 201, 201a, 201b...selection transistor, 202...storage capacitance, 203...liquid crystal element 204, 204a to 204c...common wiring, 205, 205a to 205c...common electrode, 300...pixel circuit, 301...driving transistor, 302...selection transistor, 303...storage capacitance, 304...light emitting element, 311...anode power line, 312...common wiring (cathode power line), 313...scanning signal line, 314...video signal line, 403a...channel portion, 403b...conductive portion, 500...substrate, 520...underlying layer, 525...gate electrode electrode, 527...gate insulating layer, 530...metal oxide layer, 540, 544, 544a...oxide semiconductor layer, 544CH...channel region, 544D...drain region, 544S...source region, 550...gate insulating layer, 555...metal oxide layer, 564...gate electrode, 565...gate wiring, 570...insulating layer, 571, 573...contact hole, 580...insulating layer, 582...opening, 591, 591a...source electrode, 593, 593 a...drain electrode, 610...planarization layer, 620...pixel electrode, 622...connection electrode, 630...insulating layer, 650...liquid crystal layer, 700...substrate, 700A...opposite substrate, 710...color filter, 810...resin layer, 815...opening, 816...contact hole, 820...light-emitting layer, 830...common electrode, 840...sealing layer, 850...protective substrate, 1010...first energy level, 1020...second energy level, 1030...tail level

Claims

1. a plurality of pixel electrodes each connected to the semiconductor device; a plurality of common electrodes each disposed opposite a part of the plurality of pixel electrodes; a plurality of common wirings respectively connected to the plurality of common electrodes; Equipped with the semiconductor device includes an oxide semiconductor layer having a polycrystalline structure, At least a part of the common wiring is made of the oxide semiconductor layer.

2. The display device according to claim 1 , wherein each of the plurality of common electrodes is disposed across a portion of the plurality of pixel electrodes.

3. the common electrode and the pixel electrode are superposed with an insulating layer interposed therebetween, The display device according to claim 1 , wherein a liquid crystal layer is disposed on the pixel electrodes and the common electrode.

4. The display device according to claim 3 , wherein the pixel electrode or the common electrode has a comb-like pattern.

5. a light-emitting layer is disposed on the pixel electrode; The display device according to claim 1 , wherein the common electrode is disposed on the light-emitting layer.

6. The display device according to claim 1 , wherein the plurality of common electrodes function as detection electrodes of a touch sensor.

7. the semiconductor device is a thin film transistor including a channel portion and a conductive portion formed of the oxide semiconductor layer, The display device according to claim 1 , wherein at least a portion of the common wiring is formed in the same layer as the conductive portion.

8. The display device according to claim 7 , wherein the thin film transistor is a transistor having a top gate structure or a dual gate structure.

9. The display device according to claim 8 , wherein the conductive portion does not overlap with a top gate of the thin film transistor.

10. 8. The display device according to claim 7, wherein the sheet resistance of the conductive portion is 500 Ω / sq. or less.

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