Semiconductor device and control system

Abstract

To provide a semiconductor device that enables shortening of the time between a detection of an abnormality and a stop of the drive of an inverter drive element, and a control system using the same.SOLUTION: Drive circuits 22u, 22v, 22w, 24u, 24v, 24w drive high-side MOS transistors 30uu, 30du, 30uv and low-side MOS transistors 30dv, 30uw, 30dw according to commands received from a microcontroller 10. Overcurrent detection units 26u, 26v, 26w determine abnormalities in the overcurrents flowing to the high-side MOS transistors and the low-side MOS transistors. Gates 21u, 21v, 21w, 23u, 23v, 23w stop the drive by the drive circuits regardless of a command from the microcontroller if the overcurrent detection units determine that there is an abnormality.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a control system using the semiconductor device. [Background technology]

[0002] Conventionally, a vehicle drive device that drives an inverter has been proposed (see, for example, Patent Document 1). This vehicle drive device includes a voltmeter, a no-energization determiner that determines the no-energization state of the inverter, and an ammeter that detects the current applied to the motor from each phase arm of the inverter, and transmits these signals and a signal from the no-energization determiner to a motor control device. The motor control device determines an abnormality based on these signals and controls the drive of the inverter.

[0003] Additionally, the applicant of the present application has previously proposed a control system similar to that described in Patent Document 1. The control system provided by the applicant of the present application includes a microcomputer, and the semiconductor device body is configured separately from the microcomputer, and the semiconductor device body drives an inverter driving element according to commands received from the microcomputer.

[0004] Conventionally, when an abnormality occurs due to an overcurrent, the semiconductor device body detects the current and then notifies the microcomputer of the abnormality via communication. When the microcomputer receives the abnormality notification, it outputs a drive signal to stop driving to the inverter drive element via the semiconductor device body. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-278790 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the control system described in the Background section, the period from when the semiconductor device detects an abnormality to when the inverter drive element actually stops driving becomes long. This increases the risk of the inverter drive element breaking down. In order to prevent this breakdown, it is necessary to increase the tolerance, which requires the inverter drive element to be large in size, which increases the mounting area, which is undesirable.

[0007] An object of the present disclosure is to provide a semiconductor device that can shorten the time from detection of an abnormality to stopping the driving of an inverter drive element, and a control system that uses this semiconductor device. [Means for solving the problem]

[0008] The invention of claim 1 is directed to a semiconductor device that includes a microcomputer and a semiconductor device body separate from the microcomputer, and that constitutes a control system in which the semiconductor device body drives an inverter drive element according to commands received from the microcomputer. A drive circuit drives the inverter drive element according to commands received from the microcomputer. An abnormality determination unit determines an abnormality in an overcurrent flowing through the inverter drive element. A stop unit stops driving by the drive circuit regardless of commands from the microcomputer when the abnormality determination unit determines that there is an abnormality.

[0009] According to the invention described in claim 1, the stop unit stops the drive by the drive circuit regardless of the command from the microcomputer. Therefore, if the abnormality determination unit determines that there is an abnormality of an overcurrent, the drive by the drive circuit can be immediately stopped regardless of whether there is a command from the microcomputer. As a result, the time from the detection of the abnormality to the stop of the drive of the inverter drive element can be shortened as much as possible. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is an electrical configuration diagram illustrating a control system according to a first embodiment. [Diagram 2] An explanatory diagram showing the structure of an electric power steering system. [Diagram 3] A flowchart outlining the operation flow. [Figure 4] A time chart showing the changes in each signal from when an abnormality is detected until the drive of the inverter drive element is stopped. [Diagram 5] FIG. 1 is a schematic diagram showing an electrical configuration of a comparative example. [Figure 6] FIG. 11 is an electrical configuration diagram illustrating a control system according to a second embodiment. [Figure 7] A time chart showing the changes in each signal from when an abnormality is detected until the drive of the inverter drive element is stopped. [Figure 8] FIG. 1 is an explanatory diagram showing a modification of the timing of stopping the drive signal output of the microcomputer. [Figure 9] FIG. 2 is an explanatory diagram showing a modified example of the timing of stopping the drive signal output of the microcomputer. [Figure 10] FIG. 13 is an electrical configuration diagram illustrating a control system according to a third embodiment. [Figure 11] FIG. 13 is an electrical configuration diagram illustrating a control system according to a fourth embodiment. [Figure 12] FIG. 13 is an electrical configuration diagram illustrating a control system according to a fifth embodiment. [Figure 13] FIG. 13 is an electrical configuration diagram illustrating a control system according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, several embodiments of a semiconductor device and a control system will be described with reference to the drawings. In the embodiments described below, the same or similar components in each embodiment will be denoted by the same or similar reference numerals, and the description thereof may be omitted.

[0012] (First embodiment) A first embodiment will be described with reference to Fig. 1 to Fig. 5. Fig. 2 illustrates an example of an entire control system 1. The control system 1 is configured with an electric power steering system 50. The electric power steering system 50 provides a steering assist torque to a steering shaft 52 for assisting the steering torque generated by the steering of a steering wheel 51 by a driver. Fig. 2 shows a schematic structure of the pinion assist type electric power steering system 50.

[0013] A steering shaft 52 is connected to the handle 51. A torque sensor 53 for detecting steering torque is attached to the steering shaft 52. A pinion gear 57 is provided at the tip of the steering shaft 52, and the pinion gear 57 meshes with a rack shaft 58.

[0014] A pair of wheels 59R, 59L are rotatably connected to both ends of the rack shaft 58 via tie rods or the like. When the steering shaft 52 rotates, the rotation is converted into linear motion of the rack shaft 58 by the pinion gear 57. As a result, the pair of wheels 59R, 59L are steered to an angle corresponding to the displacement of the linear motion of the rack shaft 58.

[0015] The electric power steering system 50 includes a motor drive device 54, a steering assist motor 55, and a reduction gear 56. The motor drive device 54 is connected to a battery 60 serving as a DC power source, and drives the steering assist motor 55 using the power of the battery 60. The steering assist motor 55 in this embodiment is configured by a three-phase AC brushless motor. Hereinafter, the steering assist motor 55 will be abbreviated as "motor 55." The motor 55 generates a steering assist torque. The reduction gear 56 reduces the speed of rotation of the motor 55 and transmits it to the steering shaft 52.

[0016] The electric power steering system 50 performs current control based on the steering torque signal detected by the torque sensor 53, controls the drive torque of the motor 55, and assists the driver's steering according to the driving situation. The electric power steering system 50 can be configured as a more fuel-efficient system than a hydraulic power steering system. This system is also called an EPS system. EPS is an abbreviation for Electric Power Steering.

[0017] 1, the motor drive device 54 includes a microcomputer 10, an ASIC 20, an inverter 30, a backflow prevention transistor 41, and a relay 42. The inverter 30 is a three-phase AC inverter, and converts a power supply voltage VB of a DC battery 60 into AC power and supplies it to a motor 55.

[0018] The inverter 30 is configured by connecting inverter driving elements, which are N-channel type high-side MOS transistors 30uu, 30uv, and 30uw and N-channel type low-side MOS transistors 30du, 30dv, and 30dw, in a bridge configuration.

[0019] The shunt resistor Ru is connected in series to the high-side MOS transistor 30uu and the low-side MOS transistor 30du. The shunt resistor Rv is connected in series to the high-side MOS transistor 30uv and the low-side MOS transistor 30dv. The shunt resistor Rw is connected in series to the high-side MOS transistor 30uw and the low-side MOS transistor 30dw.

[0020] The backflow prevention transistor 41 is connected between the supply terminal of the power supply voltage VB of the battery 60 and the inverter 30, and unidirectionally conducts the power supply voltage VB to the inverter 30, thereby preventing backflow to the battery 60. The relay transistors 42u, 42v, and 42w are composed of N-channel MOS transistors that unidirectionally conduct the power supply voltage VB to the motor 55. In this embodiment, the shunt resistors Ru, Rv, and Rw are provided in each of the UVW phases, but this is not limited to this. For example, the shunt resistors Ru, Rv, and Rw of the UVW phases may be configured as one, and the current may be detected by the one shunt resistor. In this case, the backflow prevention transistor 41 may be connected to the current path from the one shunt resistor to the ground node.

[0021] The relay 42 is composed of relay transistors 42u, 42v, and 42w. The drain-source of the relay transistor 42u is connected between the motor 55 and a common connection point of the high-side MOS transistor 30uu and the low-side MOS transistor 30du. The drain-source of the relay transistor 42v is connected between the motor 55 and a common connection point of the high-side MOS transistor 30uv and the low-side MOS transistor 30dv.

[0022] The drain-source of the relay transistor 42w is connected between the common connection point of the high-side MOS transistor 30uw and the low-side MOS transistor 30dw and the motor 55. The gates of these relay transistors 42u, 42v, 42w are connected to the microcomputer 10, and are on / off controlled by the control logics 11u, 11v, 11w of the microcomputer 10, respectively.

[0023] <Explanation of the configuration of Microcontroller 10> The microcomputer 10 is a microcontroller / microcomputer including control logics 11u, 11v, and 11w connected to each other and a communication unit 19 connected to the control logics 11u, 11v, and 11w. The control logics 11u, 11v, and 11w are configured to be capable of switching between enabling and disabling the supply of current from the inverter 30 to the motor 55 by controlling the gates of the relay transistors 42u, 42v, and 42w to be on or off.

[0024] The control logic 11u, 11v, and 11w output high-side drive signals through terminals HIU, HIV, and HIW of the ASIC 20. The control logic 11u, 11v, and 11w output low-side drive signals through terminals LOU, LOV, and LOW of the ASIC 20. The drive signals are PWM-modulated pulse signals, and are commands from the microcontroller 10 to the ASIC 20.

[0025] The microcomputer 10 has a functional block serving as a cause determination unit 11a. Although the cause determination unit 11a is configured in the control logic 11u in FIG. 1, the present invention is not limited to this. When the cause determination unit 11a receives a notification of an abnormality detection from the communication unit 29 via the communication unit 19, the cause determination unit 11a determines the cause of the abnormality.

[0026] The cause determination unit 11a is a block that determines whether an overcurrent abnormality has occurred in any of the UVW phases as the cause of the abnormality, or whether any other abnormality has occurred, based on a notification of abnormality detection from the ASIC 20. The control logics 11u, 11v, and 11w output or stop a drive signal to the ASIC 20 based on the cause of the abnormality determined by the cause determination unit 11a.

[0027] The communication unit 19 is connected to the communication unit 29 of the ASIC 20. When the overcurrent detection units 26u, 26v, and 26w of the ASIC 20 determine that an overcurrent abnormality exists, the communication unit 19 receives an abnormality detection from the communication unit 29 of the ASIC 20. The control logics 11u, 11v, and 11w are connected to the communication unit 19, and output or stop a drive signal to the ASIC 20 based on whether or not the communication unit 19 has received an abnormality detection.

[0028] <Description of the Configuration of ASIC20> ASIC20 includes gate 21u, 21v, 21w, 23u, 23v, 23w, drive circuits 22u, 22v, 22w, 24u, 24v, 24w, and current amplifiers 25u, 25v, 25w. Further, ASIC20 includes overcurrent detection units 26u, 26v, 26w, drive unit 27a, buffer 27b, and communication unit 29. When an activation signal that permits driving is notified from the communication unit 19 of the microcomputer 10 to the communication unit 29, the drive unit 27a and the buffer 27b of ASIC20 turn on the reverse current prevention transistor 41 and turn on the power supply to the inverter 30.

[0029] The common connection point of the high-side MOS transistor 30uu and the low-side MOS transistor 30du is connected to the terminal MTU of ASIC20. The common connection point of the high-side MOS transistor 30uv and the low-side MOS transistor 30dv is connected to the terminal MTV of ASIC20. The common connection point of the high-side MOS transistor 30uw and the low-side MOS transistor 30dw is connected to the terminal MTW of ASIC20. The terminals MTU, MTV, and MTW are connected to voltage dividing resistors during an appropriate period and can measure the voltage, but are not related to the features of the present application, so the illustration is omitted.

[0030] The current amplifier 25u detects the current flowing through the high-side MOS transistor 30uu and the low-side MOS transistor 30du by amplifying and detecting the voltage between the terminals of the shunt resistor Ru. The current amplifier 25u outputs to the control logic 11u of the microcomputer 10 through the terminal IOU and also outputs to the overcurrent detection unit 26u.

[0031] The current amplifier 25v detects the current flowing through the high-side MOS transistor 30uv and the low-side MOS transistor 30dv by amplifying and detecting the voltage between the terminals of the shunt resistor Rv. The current amplifier 25v outputs to the control logic 11v of the microcomputer 10 through the terminal IOV and also outputs to the overcurrent detection unit 26v.

[0032] The current amplifier 25w detects the current flowing through the high-side MOS transistor 30uw and the low-side MOS transistor 30dw by amplifying and detecting the voltage between the terminals of the shunt resistor Rw. The current amplifier 25w outputs the current to the control logic 11w of the microcomputer 10 through the terminal IOW and also to the overcurrent detection unit 26w.

[0033] The overcurrent detection units 26u, 26v, 26w are provided as an abnormality determination unit that receives the detection results of the current amplifiers 25u, 25v, 25w, detects whether an overcurrent is occurring, and determines whether an overcurrent is abnormal. The overcurrent detection units 26u, 26v, 26w are composed of a comparator that compares the detection results of the current amplifiers 25u, 25v, 25w with a first abnormality determination threshold Ita for abnormality determination, and a counter that counts the number of times the threshold is reached. The overcurrent detection units 26u, 26v, 26w determine an overcurrent abnormality when the count number reaches a predetermined number.

[0034] Here, a form in which the first abnormality determination threshold value Ita for each of the UV and W phases is set to the same value will be described, but the present invention is not limited to this. The first abnormality determination threshold value Ita for each of the UV and W phases may be set to different values.

[0035] When the overcurrent detection units 26u, 26v, and 26w determine that an overcurrent abnormality has occurred, they notify the communication unit 29 and output a low level indicating that an abnormality has been detected to the gates 21u, 21v, 21w, 23u, 23v, and 23w. The communication unit 29 is used as a notification unit that notifies the communication unit 19 of the microcomputer 10 that an overcurrent abnormality has been determined when an overcurrent abnormality has been determined by any of the overcurrent detection units 26u, 26v, and 26w.

[0036] Each of the gates 21u, 21v, 21w, 23u, 23v, and 23w is composed of an AND gate. <High side drive explanation> The gates 21u, 21v, 21w respectively receive drive signals for the high-side MOS transistors 30uu, 30uv, 30uw from the control logics 11u, 11v, 11w, and also receive outputs from the overcurrent detectors 26u, 26v, 26w.

[0037] The gates 21u, 21v, and 21w are configured as stopping units that stop the output of the drive signals input from the control logics 11u, 11v, and 11w when the overcurrent detection units 26u, 26v, and 26w respectively determine that an overcurrent abnormality exists.

[0038] The gates 21u, 21v, and 21w receive drive signals from the control logics 11u, 11v, and 11w, respectively. The gates 21u, 21v, and 21w output the drive signals to the drive circuits 22u, 22v, and 22w, on the condition that the overcurrent detection units 26u, 26v, and 26w have not determined that there is an overcurrent abnormality.

[0039] The drive circuits 22u, 22v, 22w are configured with buffers that shape the waveforms of the outputs of the gates 21u, 21v, 21w, and are connected to the gates of the high-side MOS transistors 30uu, 30uv, 30uw, respectively. When the drive circuits 22u, 22v, 22w receive drive signals from the gates 21u, 21v, 21w, they output the drive signals to the gates of the high-side MOS transistors 30uu, 30uv, 30uw.

[0040] <Explanation of low side drive> The gates 23u, 23v, 23w respectively receive drive signals for the low-side MOS transistors 30du, 30dv, 30dw from the control logics 11u, 11v, 11w, and also receive outputs from the overcurrent detectors 26u, 26v, 26w.

[0041] The gates 23u, 23v, 23w are configured as stopping units that stop the output of the drive signals input from the control logics 11u, 11v, 11w when the overcurrent detection units 26u, 26v, 26w determine that an overcurrent abnormality exists.

[0042] The gates 23u, 23v, and 23w also receive drive signals from the control logics 11u, 11v, and 11w, respectively. The gates 23u, 23v, and 23w output the received drive signals to the drive circuits 24u, 24v, and 24w, on the condition that the overcurrent detection units 26u, 26v, and 26w have not determined that there is an overcurrent abnormality.

[0043] The drive circuits 24u, 24v, 24w are also configured with buffers that shape the waveforms of the outputs of the gates 23u, 23v, 23w, and are connected to the gates of the low-side MOS transistors 30du, 30dv, 30dw, respectively. When the drive circuits 24u, 24v, 24w receive drive signals from the drive circuits 22u, 22v, 22w, they output the drive signals to the gates of the low-side MOS transistors 30du, 30dv, 30dw.

[0044] Next, the process for determining an overcurrent abnormality will be described with reference to Figures 3 and 4. Normally, when driving the motor 55, the microcomputer 10 outputs a drive signal to the ASIC 20 using control logics 11u, 11v, and 11w. The ASIC 20 drives the inverter 30 in S1 of Figure 3 using the input drive signal to rotate the motor 55. While the motor 55 is being rotated, the current amplifiers 25u, 25v, and 25w of the ASIC 20 detect the voltage between the terminals of the resistors Ru, Rv, and Rw to detect the current of the inverter 30 in S2.

[0045] <Notification of overcurrent abnormalities via communication> 4 shows the current detection result of the inverter 30 for one phase (for example, the U phase) and the communication timing between the microcomputer 10 and the ASIC 20. In the following example, the determination of an overcurrent abnormality by the overcurrent detection unit 26u for the U phase will be described, but the determination of an overcurrent abnormality is performed in the same manner for the other phases.

[0046] The communication unit 29 executes communication processing with the communication unit 19 at a predetermined cycle T0, and periodically transmits the presence or absence of an abnormality (see the communication signals at timings ta1 and ta2 in Fig. 4). The overcurrent detection unit 26u detects whether the current of the inverter 30 has reached the first abnormality determination threshold Ita when some abnormality occurs, and determines the presence or absence of an overcurrent abnormality.

[0047] 4, the overcurrent detection unit 26u detects the current of the inverter 30 in a pulsed manner. Normally, unless some abnormality occurs, the amplitude of the detected current of the inverter 30 is less than the first abnormality determination threshold Ita. In this case, the overcurrent detection unit 26u continues to clear the count related to the overcurrent abnormality.

[0048] For example, consider a case where an abnormality occurs due to some influence and the amplitude of the detected current of the inverter 30 reaches the first abnormality determination threshold Ita at timing t0 in Fig. 4. In this case, the overcurrent detection unit 26u counts the number of times the first abnormality determination threshold Ita is reached using a counter, and determines whether the count result reaches a predetermined number of times.

[0049] The overcurrent detection unit 26u determines that there is an overcurrent abnormality at timing t1 when the count result reaches a predetermined number of times (four times in the example of FIG. 4). If the first abnormality determination threshold Ita is not reached even once as a result of periodically counting from timing t0, the overcurrent detection unit 26u clears the count result of the counter and repeats the count from the beginning. This is to prevent erroneous detection due to the influence of current noise as much as possible.

[0050] Overcurrent detection processing is also carried out for the V phase and the W phase. For example, when the overcurrent detection unit 26u for the U-phase inverter determines that there is an overcurrent abnormality, it transmits to the communication unit 29 that there is an overcurrent abnormality. When the overcurrent detection unit 26u determines an overcurrent abnormality at timing t1, at the next communication timing ta2 when communicating regularly, the communication unit 29 can notify the microcontroller 10 that there is an overcurrent abnormality by communicating with the communication unit 19. In this case, the ASIC 20 will notify the microcontroller 10 that an overcurrent abnormality has occurred with a delay of period T1 from timing t1.

[0051] After that, when the microcontroller 10 receives, via the communication signal from the communication unit 19, that there is an overcurrent abnormality at timing t2, it notifies the control logics 11u, 11v, 11v of all phases of the content. After receiving the notification, the control logic 11u stops outputting the drive signal after timing t3. Refer to the waveforms of terminals HIU and LOU in FIG. 4. Similarly, the control logics 11v and 11v also stop outputting the drive signal after timing t3 after receiving the notification. Refer to the waveforms of terminals HIV, HIW, LOV, and LOW in FIG. 4.

[0052] <Processing at the time of a single overcurrent abnormality by the ASIC 20> Normally, by communicating between the microcontroller 10 and the ASIC 20 as described above, the determination of overcurrent abnormality is executed, and the microcontroller 10 mainly stops outputting the drive signal. In this embodiment, in addition to this, the ASIC 20 independently stops outputting the drive signal.

[0053] In FIG. 3, the microcontroller 10 and the ASIC 20 drive the inverter 30 at S1 and detect the current of the motor 55 at S2, and at S3, the overcurrent detection units 26u, 26v, 26w determine overcurrent abnormalities.

[0054] For example, when the overcurrent detection unit 26u determines that there is an overcurrent abnormality in S3, regardless of a command from the microcontroller 10, the gates 21u, 21v of the ASIC 20 cut off the drive signal received from the control logic 11u, thereby stopping driving by the drive circuits 22u, 24u.

[0055] That is, in Fig. 4, the overcurrent detection unit 26u can immediately cut off the output of the drive signal at timing t1 when it determines that an overcurrent has occurred, thereby stopping the drive. See the waveforms of the terminals HGU and LGU in Fig. 4. As a result, the drive of the inverter 30 can be stopped (S4 in Fig. 3). This makes it possible to minimize the time from when the abnormality is detected until the drive of the U-phase high-side MOS transistor 30uu and low-side MOS transistor 30du is stopped.

[0056] Thereafter, as described above, the ASIC 20 notifies the microcomputer 10 of the result of the determination that there is an overcurrent abnormality, and the control logics 11u, 11v, and 11w of the microcomputer 10 stop outputting the original drive signals. At this time, if the communication unit 19 receives a notification that an abnormality has occurred in even one of the UVW phases, the control logics 11u, 11v, and 11w of all phases stop outputting drive signals. As a result, the drive of the inverter 30 can be stopped by the dual system monitoring function, improving robustness.

[0057] On the other hand, the overcurrent detection units 26u, 26v, and 26w of the ASIC 20 for the UV and W phases each individually count the number of times the first anomaly determination threshold Ita is reached. When the count result of each of the overcurrent detection units 26u, 26v, and 26w reaches a predetermined number of times, the overcurrent detection units 26u, 26v, and 26w notify the communication unit 29 that an overcurrent anomaly has been determined. The communication unit 29 notifies the microcomputer 10 via the communication unit 9. Therefore, the microcomputer 10 can receive through the communication unit 29 which of the UV and W phases has an overcurrent anomaly.

[0058] When the microcomputer 10 receives the abnormality detection through the communication unit 19, the cause determination unit 11a determines the cause of the abnormality in S5. The microcomputer 10 can determine which of the UVW phases has an abnormality from the abnormality detection received from the communication unit 19.

[0059] When the microcomputer 10 determines that only one of the UVW phases, for example the U phase, is overcurrent when the cause determination unit 11a determines the cause of the abnormality, it stops only the phase in which the abnormality was detected, and continues driving only with the remaining two phases in S6 of Fig. 3. If only one phase is short-circuited when the microcomputer 10 drives the three-phase inverter 30, the connection part of the motor 55 of the short-circuited phase is connected to the midpoint of the power supply voltage VB, and the motor 55 can be controlled by the remaining two phases. This allows the motor 55 to continue driving while stopping driving only the phase in which the abnormality occurred.

[0060] On the other hand, when the microcomputer 10 determines that there is an abnormality of overcurrent in two or more of the UVW phases, the control logics 11u, 11v, and 11w stop outputting all drive signals. This makes it possible to stop the inverter 30 in S7 in Fig. 3, and to stop driving the motor 55 even if an abnormality occurs. The microcomputer 10 may disable the supply of current from the inverter 30 to the motor 55 by controlling the gates of the relay transistors 42u, 42v, and 42w to be OFF.

[0061] <Explanation of Comparative Example> The problems, technical significance, and effects of this embodiment will be described below. FIG. 5 shows the configurations of the microcomputer 110 and the ASIC 120 of the comparative example. As shown in the ASIC 120 of FIG. 5, for example, consider a system in which an overcurrent detection unit 26z mounted on the ASIC 120 detects the drain-source voltage of the backflow prevention transistor 41 to determine whether an overcurrent abnormality has occurred. When the overcurrent detection unit 26z determines that an overcurrent abnormality has occurred, the communication unit 29 of the ASIC 120 notifies the communication unit 19 of the microcomputer 110, and the control unit 111 of the microcomputer 110 stops outputting the drive signal. When an overcurrent abnormality is detected in this manner, it takes a lot of time for communication processing between the communication units 29 and 19.

[0062] <Summary of this embodiment> According to this embodiment, when the U-phase overcurrent detection unit 26u determines that there is an abnormality, the gates 21u and 23u of the ASIC 20 can stop the drive circuits 22u and 24u regardless of the command from the microcomputer 10. Therefore, when the overcurrent detection units 26u, 26v, and 26w determine that there is an abnormality in the overcurrent, they can immediately stop driving even without a command from the microcomputer 10. This makes it possible to minimize the time until the high-side MOS transistor 30uu and the low-side MOS transistor 30du of the U-phase are stopped driving. The same effect is achieved for the V-phase and W-phase.

[0063] According to this embodiment, by making the most of the functions of the overcurrent detection units 26u, 26v, and 26w mounted on the ASIC 20, it is possible to minimize the time from the detection of an abnormality to the stopping of the inverter 30 of the phase in which the abnormality has occurred while minimizing additional functions. As a result, it is possible to reduce the possibility of the inverter driving element being destroyed by the high-side MOS transistors 30uu, 30uv, and 30uw or the low-side MOS transistors 30du, 30dv, and 30dw. Alternatively, it is possible to reduce the element tolerance of the inverter driving element and reduce the size of the element.

[0064] Second embodiment The second embodiment will be described with reference to Fig. 6 to Fig. 9. As shown in Fig. 6, a control system 201 of the present embodiment includes a motor drive device 254 instead of the motor drive device 54. The motor drive device 254 includes a microcomputer 210, which includes overcurrent detection units 12u, 12v, and 12w in addition to a communication unit 19 and control logics 11u, 11v, and 11w.

[0065] The microcomputer 210 includes overcurrent detection units 12u, 12v, and 12w for determining an abnormality of an overcurrent in each of the UV and W phases. The overcurrent detection units 12u, 12v, and 12w are configured as independent abnormality determination units. The overcurrent detection unit 12u determines an abnormality of an overcurrent flowing through the high-side MOS transistor 30uu and the low-side MOS transistor 30du independently of a notification operation from the communication unit 29 by the ASIC 20.

[0066] The overcurrent detection unit 12v independently determines an abnormality in an overcurrent flowing through the high-side MOS transistor 30uv and the low-side MOS transistor 30dv, regardless of a notification operation from the communication unit 29 by the ASIC 20. The overcurrent detection unit 12w independently determines an abnormality in an overcurrent flowing through the high-side MOS transistor 30uw and the low-side MOS transistor 30dw, regardless of a notification operation from the communication unit 29 by the ASIC 20.

[0067] The overcurrent detection units 12u, 12v, and 12w determine an overcurrent abnormality by comparing the detected currents by the current amplifiers 25u, 25v, and 25w, which are transmitted from the ASIC 20 via the terminals IOU, IOV, and IOW, respectively, with a predetermined second abnormality determination threshold Itm.

[0068] Here, a form in which the second abnormality determination thresholds Itm for the UVW phases are set to the same value will be described, but the present invention is not limited to this. The second abnormality determination thresholds Itm for the UVW phases may be set to different values.

[0069] As described in the first embodiment, the overcurrent detection units 26u, 26v, and 26w of the ASIC 20 determine an overcurrent abnormality by comparing the currents detected by the current amplifiers 25u, 25v, and 25w with a predetermined first abnormality determination threshold Ita. In this embodiment, the first abnormality determination threshold Ita of the overcurrent detection units 26u, 26v, and 26w of the ASIC 20 is set to be lower than the second abnormality determination threshold Itb of the overcurrent detection units 12u, 12v, and 12w of the microcomputer 210. The other configurations are similar to those of the first embodiment, and therefore description of the other configurations will be omitted.

[0070] Variations in the operation when determining an abnormality due to an overcurrent will be described with reference to Fig. 7 to Fig. 9. Fig. 7 shows waveforms of each part when an abnormality occurs and the amplitude of the detected current of the motor 55 changes to be equal to or greater than the first abnormality determination threshold Ita and less than the second abnormality determination threshold Itm. In this case, the processing is the same as that in Fig. 4 used in the description of the first embodiment.

[0071] The control logics 11u, 11v, and 11w stop outputting the drive signals from timing t3 onward after receiving the notification from the communication unit 19. See the waveforms of the terminals HIU, HIV, HIW, LOU, LOV, and LOW in FIG.

[0072] During an abnormality, the amplitude of the detection current of the inverter 30 may fluctuate significantly. Fig. 8 shows signal waveforms of each component in a case where the amplitude of the detection current of the inverter 30 is equal to or greater than the first abnormality determination threshold Ita and less than the second abnormality determination threshold Itm around timing t0 when the abnormality first occurs, but the amplitude then gradually changes significantly.

[0073] The microcomputer 210 counts the number of times that the current amplitude of the inverter 30 reaches the second abnormality determination threshold Itm by the overcurrent detection unit 12u. In the example of Fig. 8, the overcurrent detection unit 12u continues counting from timing t0a, and determines that there is an overcurrent abnormality around timing t3a when the count result reaches a predetermined number of times (four times in the example of Fig. 8).

[0074] The control logic 11u stops the output of the drive signal at timing t3a when the overcurrent detection unit 12u determines that there is an overcurrent abnormality. See the waveforms of terminals HIU and LOU in Figure 8. The control logic 11u notifies the control logics 11v and 11w that there is an overcurrent abnormality, so that the control logics 11v and 11w can stop the output of the drive signal at timing t3a. See the waveforms of terminals HIV, LOV, HIW, and LOW in Figure 8.

[0075] This allows the microcomputer 210 to stop outputting the drive signal earlier than the output stop timing t3 of the drive signal received from the ASIC 20 by communication. Moreover, the ASIC 20 can stop outputting the drive signal at timing t1 earlier than the output stop timing t3a of the drive signal from the microcomputer 210. See the waveforms of the terminals HGU and LGU in Figure 8.

[0076] FIG. 9 shows waveforms of various parts when the amplitude of the detected current of the motor 55 changes significantly from about timing t0 when the abnormality first occurs so as to reach the second abnormality determination threshold value Itm.

[0077] The microcomputer 210 counts the number of times that the current amplitude of the motor 55 reaches the second abnormality determination threshold Itm by the overcurrent detection unit 12u. In the example of Fig. 9, the overcurrent detection unit 12u continues counting from timing t0, and determines that there is an overcurrent abnormality around timing t1 when the count result reaches a predetermined number of times (four times in the example of Fig. 8).

[0078] The control logic 11u stops the output of the drive signal at timing t1 when the overcurrent detection unit 12u determines that there is an overcurrent abnormality. See the waveforms of terminals HIU and LOU in Figure 9. The control logic 11u notifies the control logics 11v and 11w that there is an overcurrent abnormality, so that the control logics 11v and 11w can stop the output of the drive signal at timing t1. See the waveforms of terminals HIV, LOV, HIW, and LOW in Figure 9.

[0079] This allows the microcomputer 210 to stop outputting the drive signal earlier than the timing t3 at which the drive signal is to be stopped by communication received from the ASIC 20. Moreover, the ASIC 20 can stop outputting the drive signal at the timing t1 that is the same as the timing at which the microcomputer 210 stops outputting the drive signal. See the waveforms at terminals HGU and LGU in Figure 9.

[0080] As described above, according to this embodiment, the first abnormality determination threshold Ita of the overcurrent detection units 26u, 26v, and 26w of the ASIC 20 is set to be lower than the second abnormality determination threshold Itm of the overcurrent detection units 12u, 12v, and 12w of the microcomputer 210. Therefore, even if the amplitude of the current of the motor 55 fluctuates greatly, the microcomputer 210 can stop the output of the drive signal at timing t3a or t1 that is earlier than or equal to the output stop timing t3 of the drive signal received by communication from the ASIC 20.

[0081] Third embodiment The third embodiment will be described with reference to Fig. 10. As shown in Fig. 10, a control system 301 of this embodiment includes a motor drive device 354 instead of the motor drive device 54. The motor drive device 354 includes a microcomputer 310 and an ASIC 320. The ASIC 320 represents a semiconductor device or a semiconductor device body. The microcomputer 310 includes control logics 311u, 311v, and 311w.

[0082] The control logics 311u, 311v, and 311w of the microcomputer 310 output the high-side drive signal and the low-side drive signal together in one line. The ASIC 320 has terminals HLIU, HLIV, and HLIW for inputting the drive signals output together from the microcomputer 310. The ASIC 320 has drive circuits 22u, 22v, 22w, 24u, 24v, and 24w, and has NOT gates 24ui, 24vi, and 24wi in front of the drive circuits 24u, 24v, and 24w.

[0083] The input nodes of the NOT gates 24ui, 24vi, and 24wi are commonly connected to the input nodes of the drive circuits 22u, 22v, and 22w. This common connection point is connected to the terminals HLIU, HLIV, and HLIW, respectively.

[0084] When the drive signals output by the control logics 311u, 311v, and 311w are input to the terminals HLIU, HLIV, and HLIW, respectively, they are converted into complementary drive signals by the NOT gates 24ui, 24vi, and 24wi.

[0085] The drive circuits 22u, 22v, 22w and the drive circuits 24u, 24v, 24w apply complementary drive signals between the gates and sources of the high-side MOS transistors 30uu, 30uv, 30uw and between the gates and sources of the low-side MOS transistors 30du, 30dv, 30dw, respectively. Even when such a circuit configuration of the ASIC 320 is applied, the inverter 30 can be driven and controlled in a similar manner. The other configurations are the same as those in the first embodiment, and therefore illustration and description of the other configurations are omitted.

[0086] According to this embodiment, the ASIC 320 receives the drive signal input from the microcomputer 310 as a command, and generates drive signals for driving the high-side MOS transistors 30uu, 30uv, and 30uw and the low-side MOS transistors 30du, 30dv, and 30dw based on the command of the drive signal. At this time, the ASIC 320 internally separates one drive signal output by the microcomputer 310 for each of the UV and W phases into drive signals for the high side and low side. Even with this configuration, the inverter 30 and the motor 55 can be driven in the same way as in the above embodiment.

[0087] (Fourth embodiment) The fourth embodiment will be described with reference to Fig. 11. In the above-mentioned first to third embodiments, the drive signals of the high-side MOS transistors 30uu, 30uv, and 30uw and the low-side MOS transistors 30du, 30dv, and 30dw are received, and the drive signals are waveform-shaped and output, but the present invention is not limited to this. It may be configured as in the control system 401 in Fig. 11.

[0088] 11, a control system 401 of this embodiment includes a motor drive device 454 instead of the motor drive device 54. The motor drive device 454 includes a microcomputer 410 and an ASIC 420. The ASIC 420 indicates a semiconductor device, which corresponds to the semiconductor device body.

[0089] The microcomputer 410 includes a control logic 11 and a communication unit 19. The microcomputer 410 outputs a communication signal in a predetermined format as a command to the ASIC 420 via the communication unit 19. The ASIC 420 includes a communication unit 29, signal generation units 28u, 28v, and 28w, and drive circuits 22u, 22v, 22w, 24u, 24v, and 24w. The communication unit 19 of the microcomputer 410 and the communication unit 29 of the ASIC 420 are capable of data communication and transmit and receive communication signals.

[0090] When the signal generating units 28u, 28v, and 28w of the ASIC 420 receive a communication signal as a command from the microcomputer 410 via the communication unit 29, they convert the communication signal into a drive signal. The signal generating units 28u, 28v, and 28w generate drive signals complementary to each other and output them to the drive circuits 22u, 22v, and 22w and the drive circuits 24u, 24v, and 24w.

[0091] The drive circuits 22u, 22v, 22w and the drive circuits 24u, 24v, 24w apply complementary drive signals between the gates and sources of the high-side MOS transistors 30uu, 30uv, 30uw and between the gates and sources of the low-side MOS transistors 30du, 30dv, 30dw. With this configuration, the inverter 30 and the motor 55 can be driven in the same manner as in the above embodiment.

[0092] Fifth embodiment The fifth embodiment will be described with reference to Fig. 12. As shown in Fig. 12, a control system 501 of this embodiment includes a motor drive device 554 instead of the motor drive device 54. The motor drive device 554 includes a microcomputer 10 and an ASIC 520. Here, the configuration of the U phase will be described, and since the configurations of the V phase and W phase are similar to the configuration of the U phase, illustrations and descriptions thereof will be omitted. The ASIC 520 indicates a semiconductor device, equivalent to the semiconductor device main body.

[0093] The ASIC 520 includes an overcurrent detection unit 526u in the U phase as an abnormality determination unit. The overcurrent detection unit 526u includes a voltage detection unit that detects the differential voltage between the drain and source of the high-side MOS transistor 30uu, and a counter that counts the number of times that the differential voltage reaches a predetermined voltage threshold, and determines whether an abnormality has occurred based on whether the count number has reached a predetermined number. With this configuration, the same effects as those of the above-described embodiment can be achieved.

[0094] Sixth embodiment The sixth embodiment will be described with reference to Fig. 13. As shown in Fig. 13, a control system 601 of this embodiment includes a motor drive device 654 instead of the motor drive device 54. The motor drive device 654 includes a microcomputer 10 and an ASIC 620. Here, the configuration of the U phase will be described, and since the configurations of the V phase and W phase are similar to the configuration of the U phase, illustrations and descriptions thereof will be omitted. The ASIC 620 indicates a semiconductor device, equivalent to the semiconductor device main body.

[0095] The motor drive device 654 includes an ASIC 620. The ASIC 620 includes an overcurrent detection unit 626u in the U phase as an abnormality determination unit. The overcurrent detection unit 626u includes a voltage detection unit that detects the differential voltage between the drain and source of the low-side MOS transistor 30du, and a counter that counts the number of times that the differential voltage reaches a predetermined voltage threshold, and determines whether an abnormality has occurred based on whether the count has reached a predetermined number. With this configuration, the same effects as those of the above-described embodiment can be achieved.

[0096] (Other embodiments) The present invention is not limited to the above-described embodiment, and the following modifications and extensions are possible. In the above embodiment, the pinion-assist type electric power steering system 50 has been described, but the present invention is not limited to this. For example, the present invention may be applied to a rack-assist type electric power steering system or a column-assist type electric power steering system. Although the present invention is applied to a three-phase inverter 30, the present invention may be applied to an inverter having a predetermined phase that is greater than three phases.

[0097] The microcomputer 10 and the techniques described herein may be implemented by a special-purpose computer provided by configuring a processor and memory programmed to perform one or more functions embodied in a computer program, or the microcomputer 10 and the techniques described herein may be implemented by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits.

[0098] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0099] In the drawings, 1, 201, 301, 401, 501, and 601 indicate control systems, 10, 210, and 310 indicate microcontrollers, 11a indicates a cause determination unit, 12u, 12v, and 12w indicate overcurrent detection units (individual abnormality determination units), 20, 320, 420, 520, and 620 indicate ASICs (semiconductor device, semiconductor device body), 21u, 21v, 21w, 23u, 23v, and 23w indicate gates (stopping units), 22u, 22v, 22w, 24u, 24v, and 24w indicate drive circuits, 26u, 26v, and 26w indicate overcurrent detection units (abnormality determination units), 29 indicates a communication unit (notification unit), and 30uu, 30du, 30uv, 30dv, 30uw, and 30dw indicate MOS transistors (inverter driving elements).

Claims

1. A semiconductor device constituting a control system including a microcomputer (10, 210, 310) and a semiconductor device body (20, 320, 420, 520, 620) separate from the microcomputer, the semiconductor device body driving inverter driving elements (30uu, 30du, 30uv, 30dv, 30uw, 30dw) in accordance with a command received from the microcomputer, a drive circuit (22u, 22v, 22w, 24u, 24v, 24w) that drives the inverter drive elements in accordance with a command received from the microcomputer; an abnormality determination unit (26u, 26v, 26w) that determines an abnormality in an overcurrent flowing through the inverter drive element; a stop unit (21u, 21v, 21w, 23u, 23v, 23w) that stops driving by the drive circuit when the abnormality determination unit determines that there is an abnormality, regardless of a command from the microcomputer; The microcomputer is configured to include an independent abnormality determination unit (12u, 12v, 12w) that determines an abnormality of an overcurrent flowing through the inverter drive element independently of a notification operation from a notification unit of the semiconductor device main body (20), and to output a command to the semiconductor device main body to stop the drive circuit when the independent abnormality determination unit determines an abnormality of an overcurrent, the abnormality determination unit of the semiconductor device body determines an abnormality due to an overcurrent by comparing a predetermined first abnormality determination threshold with a current flowing through the inverter drive element; The single abnormality determination unit of the microcomputer determines an abnormality due to an overcurrent by comparing a predetermined second abnormality determination threshold value with a current flowing through the inverter drive element, The first abnormality determination threshold of the semiconductor device body is set to be lower than the second abnormality determination threshold of the microcomputer.

2. 2. The semiconductor device according to claim 1, further comprising a notification section (29) for notifying the microcomputer of the detection of an abnormality when the abnormality determination section determines that an overcurrent abnormality exists.

3. The semiconductor device body includes:

3. The semiconductor device according to claim 1, further comprising: a drive signal or a communication signal received from the microcomputer as the command; and a drive signal for driving the inverter drive element based on the command.

4. The inverter driving element is an element that configures an inverter (30) by bridge-connecting high-side MOS transistors (30uu, 30uv, 30uw) and low-side MOS transistors (30du, 30dv, 30dw), The abnormality determination unit detects a differential voltage between terminals of a shunt resistor (R) connected in series to the inverter drive element, between the drain and source of the high-side MOS transistor, or between the drain and source of the low-side MOS transistor to determine an abnormality.

3. The semiconductor device according to claim 1.

5. A semiconductor device comprising a microcomputer (10, 210, 310) and a semiconductor device body (20, 320, 420, 520, 620) separate from the microcomputer, the semiconductor device body forming a control system for driving inverter driving elements (30uu, 30du, 30uv, 30dv, 30uw, 30dw) in accordance with a command received from the microcomputer, wherein a drive circuit (22u, 22v) drives the inverter driving elements in accordance with a command received from the microcomputer. , 22w, 24u, 24v, 24w), an abnormality determination unit (26u, 26v, 26w) that determines an abnormality in an overcurrent flowing through the inverter drive element, a stop unit (21u, 21v, 21w, 23u, 23v, 23w) that stops driving by the drive circuit regardless of a command from the microcomputer when the abnormality determination unit determines that there is an abnormality, and a notification unit (29) that notifies the microcomputer that an abnormality has been detected when the abnormality determination unit determines that there is an abnormality in an overcurrent. a microcomputer that transmits a command to the semiconductor device body to stop a drive circuit when an abnormality detection is received from the notification unit; the inverter driving element is bridge-connected to drive a motor having three or more predetermined phases; The microcomputer includes a cause determination unit (11a) that determines a cause of an abnormality when it receives a notification of abnormality detection in one or more of the predetermined phases from the notification unit, When the cause determination unit determines that an overcurrent is occurring in only one of the specified phases when determining the cause of the abnormality, the control system stops only the phase in which an abnormality is detected among the bridge-connected inverter drive elements and continues to drive only the remaining phases.

6. 3. The semiconductor device according to claim 1, which is applied to an electric power steering system.

7. 6. The control system according to claim 5, which is applied to an electric power steering system.

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