Wiring circuit board, electrical element mounting substrate, wiring circuit board manufacturing method, and electrical element mounting substrate manufacturing method

Abstract

To provide a wiring circuit board with which mounting of electrical elements is made easy, and that makes it possible to reduce the impedance of wiring and secure the heat dissipation of the electrical elements.SOLUTION: A wiring circuit board 100 has a first plane 101 and a second plane 102 facing mutually opposite directions in a thickness direction DT. The wiring circuit board 100 includes a plurality of laminated insulating layers (10, 20, 30), a plurality of conductive layers (11, 21, 31) formed on one of the insulating layers, and a plurality of terminals T1, T2. The plurality of terminals T1 are formed on the first plane 101, and the plurality of terminals T2 are formed on the second plane 102. The first conductive layer 11 is formed on the first insulating layer 10 among the plurality of insulating layers (10, 20, 30). The sum total of the thickness of the first insulating layer 10 and the thickness of the first conductive layer 11 is 30 μm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wired circuit board including a plurality of insulating layers and a plurality of conductor layers, a board mounted with electric components, a method for manufacturing a wired circuit board, and a method for manufacturing a board mounted with electric components. [Background technology]

[0002] For example, a rewiring substrate may be inserted between a semiconductor chip and a rigid printed circuit board. The rewiring substrate serves to convert the pitch between the fine pattern of the semiconductor chip and the coarse pattern of the package substrate. The rewiring substrate is also called an interposer substrate.

[0003] The semiconductor device described in Patent Document 1 includes a wiring circuit layer. The wiring circuit layer functions as a rewiring layer. The wiring circuit layer includes an insulating layer and a conductor layer. The conductor layer is formed inside the insulating layer. One conductive path extends from the conductor layer to one main surface, and the other conductive path extends from the conductor layer to the other main surface. One connecting conductor portion exposed at one main surface is provided at the tip of one conductive path, and the other connecting conductor portion exposed at the other main surface is provided at the tip of the other conductive path.

[0004] The rewiring board includes, for example, a conductor layer forming wiring, such as the wiring circuit layer described in Patent Document 1. The rewiring board may have a multi-layer structure in which a plurality of conductor layers forming wiring are laminated together with a plurality of insulating layers. Conventionally, such a rewiring board has a thickness of about several hundred μm. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2010-232524 A [Patent Document 2] JP 2020-123599 A Summary of the Invention [Problem to be solved by the invention]

[0006] When the rewiring board includes wiring, there is a demand for the rewiring board to be made thinner in order to reduce the impedance of the wiring and to improve the heat dissipation of the semiconductor chip mounted on the rewiring board.

[0007] On the other hand, a semiconductor module has been proposed that is configured so that a semiconductor chip can be electrically connected to other semiconductor chips or electrical elements such as a wiring circuit board, etc. The semiconductor module described in Patent Document 2 has a circuit configuration similar to the above-mentioned rewiring board, and is fabricated as follows.

[0008] First, a plurality of sets of semiconductor chips are mounted on a support substrate via an adhesive. Next, a sealing resin portion is formed on the adhesive so as to cover the plurality of sets of semiconductor chips. Thereafter, the adhesive and the support substrate are removed from the sealing resin portion while the plurality of sets of semiconductor chips are covered with the sealing resin portion. In this state, a plurality of insulating films and a plurality of wirings (rewirings) are formed and stacked on the surface of the sealing resin portion where one surface of the semiconductor chips is exposed.

[0009] In the above semiconductor module, the thickness of the layers of the insulating films and the rewirings formed on one surface of the semiconductor chip can be made relatively small. However, in order to manufacture the semiconductor module, a dedicated device is required to accurately position the sets of semiconductor chips on the support substrate and fix them with sealing resin. In addition, a complex wiring design is required that takes into account the positional relationship between the sets of semiconductor chips. Furthermore, when the insulating films and the rewirings are directly formed on the sets of semiconductor chips, a processing environment that does not adversely affect the semiconductor chips is required. Therefore, as described above, forming the insulating films and the rewirings on one surface of the semiconductor chip fixed by the sealing resin portion is more difficult than mounting the semiconductor chip on a rewiring substrate.

[0010] An object of the present invention is to provide a wired circuit board, an electrical element mounting board, a manufacturing method for a wired circuit board, and a manufacturing method for an electrical element mounting board, which are capable of easily mounting electrical elements and capable of reducing the impedance of the wiring and ensuring the heat dissipation of the electrical elements. [Means for solving the problem]

[0011] A wired circuit board according to one aspect of the present invention has a first surface and a second surface facing in opposite directions in a thickness direction, and includes a plurality of insulating layers including a first insulating layer that are stacked in the thickness direction, a plurality of conductor layers formed on any one of the plurality of insulating layers, and a first connected portion and a second connected portion configured to be connectable to a connection terminal of an electrical element, wherein the first connected portion is formed on the first surface so as to be electrically connected to the plurality of conductor layers and exposed in the direction in which the first surface faces, and the second connected portion is formed on the second surface so as to be electrically connected to the plurality of conductor layers and exposed in the direction in which the second surface faces, and the plurality of conductor layers include a first conductor layer formed on the first insulating layer, and a sum of a thickness of a portion of the first insulating layer where the first conductor layer is formed and a thickness of the first conductor layer is 30 μm or less.

[0012] An electrical element mounting board according to another aspect of the present invention comprises the above-mentioned wired circuit board, an electrical element having a connection terminal and mounted on the first surface of the wired circuit board, and a joining member joining the connection terminal of the electrical element to the first connected portion or the second connected portion of the wired circuit board, wherein the electrical element further has an opposing surface that faces the wired circuit board when mounted on the wired circuit board, and a columnar joint formed so as to protrude a certain length from the opposing surface, and the connection terminal is constituted by a tip portion of the columnar joint.

[0013] According to yet another aspect of the present invention, there is provided a method for manufacturing a wired circuit board having a first surface and a second surface facing in opposite directions in a thickness direction, the method comprising the steps of: forming a plurality of insulating layers including a first insulating layer and stacked in the thickness direction; forming a plurality of conductor layers on any one of the plurality of insulating layers; forming a first connected portion on the first surface to which a connection terminal of an electrical element can be connected, the first connected portion being electrically connected to the plurality of conductor layers and exposed in the direction in which the first surface faces; and forming the second connected portion on the second surface to which a connection terminal of an electrical element can be connected, the second connected portion being electrically connected to the plurality of conductor layers and exposed in the direction in which the second surface faces, the plurality of conductor layers including a first conductor layer formed on the first insulating layer, and a sum of a thickness of a portion of the first insulating layer where the first conductor layer is formed and a thickness of the first conductor layer is 30 μm or less.

[0014] A method for manufacturing an electrical component mounting board according to yet another aspect of the present invention includes the steps of: producing the wired circuit board by the above-described manufacturing method; and mounting an electrical component having a connection terminal on the first surface of the wired circuit board produced by the manufacturing method, the mounting step including using a bonding member to bond the connection terminal of the electrical component to the first connected portion of the wired circuit board, the electrical component having an opposing surface that faces the wired circuit board when mounted on the wired circuit board and a columnar joint formed to protrude a certain length from the opposing surface, and the connection terminal is constituted by a tip of the columnar joint. Effect of the Invention

[0015] According to the present invention, it is possible to facilitate the mounting of electrical elements, reduce the impedance of wiring, and ensure the heat dissipation of the electrical elements. [Brief description of the drawings]

[0016] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a rewiring substrate according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a schematic plan view of the rewiring substrate of FIG. [Diagram 3] 2 is a schematic bottom view of the rewiring substrate of FIG. 1. [Figure 4] FIG. 2 is a schematic side view showing an example of a roll-to-roll apparatus used in the manufacturing process of a rewiring substrate. [Diagram 5] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 6] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 7] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 8] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 9] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 10] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 11] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 12] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 13] 2A to 2C are schematic cross-sectional views for explaining an example of a method for manufacturing the rewiring board of FIG. 1. [Figure 14] 10 is a schematic cross-sectional view of a rewiring board showing an example of a state in which an etching liquid has entered inside a first conductor layer. FIG. [Figure 15] 11A to 11C are schematic cross-sectional views for explaining a method for manufacturing a rewiring substrate according to a first modified example. [Figure 16] 11A to 11C are schematic cross-sectional views for explaining a method for manufacturing a rewiring substrate according to a first modified example. [Figure 17] 11A to 11C are schematic cross-sectional views for explaining a method for manufacturing a rewiring substrate according to a first modified example. [Figure 18]11A to 11C are schematic cross-sectional views for explaining a method for manufacturing a rewiring substrate according to a first modified example. [Figure 19] 11A to 11C are schematic cross-sectional views for explaining a method for manufacturing a rewiring substrate according to a first modified example. [Figure 20] 13A to 13C are views for explaining a method for manufacturing a rewiring substrate according to a second modified example. [Figure 21] 13A to 13C are views for explaining a method for manufacturing a rewiring substrate according to a second modified example. [Figure 22] 13A to 13C are views for explaining a method for manufacturing a rewiring substrate according to a second modified example. [Diagram 23] 13A to 13C are views for explaining a method for manufacturing a rewiring substrate according to a second modified example. [Figure 24] FIG. 11 is a schematic cross-sectional view showing a configuration of a rewiring substrate according to another embodiment. [Diagram 25] FIG. 13 is a diagram showing the results of an impedance test on a rewiring board. [Figure 26] 1 is a schematic cross-sectional view showing the structure of a mobile terminal used in a simulation for evaluating the heat dissipation performance of a semiconductor element. [Figure 27] FIG. 11 is a diagram showing the results of a plurality of simulations for evaluating the heat dissipation performance of a semiconductor element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, a wired circuit board, an electric element mounting board, a manufacturing method of a wired circuit board, and a manufacturing method of an electric element mounting board according to an embodiment of the present invention will be described with reference to the drawings. As an example of a wired circuit board, a rewired board will be described. The rewired board is disposed between an electronic component such as a semiconductor element and another wired circuit board such as a rigid printed wiring circuit board (hereinafter abbreviated as a rigid board), and serves to convert the pitch between the fine pattern of the electronic component and the coarse pattern of the other wired circuit board. The rewired board is also called an interposer board.

[0018] 1. Basic structure of rewiring board FIG. 1 is a schematic cross-sectional view showing a configuration of a rewiring substrate according to an embodiment of the present invention. FIG. 2 is a schematic plan view of the rewiring substrate 100 of FIG. 1. FIG. 3 is a schematic bottom view of the rewiring substrate 100 of FIG. 1. FIG. 1 shows a cross section taken along line AA in FIG. 2 and FIG. 3. As shown in FIG. 1, the rewiring substrate 100 has a first surface (upper surface in this example) 101 and a second surface (lower surface in this example) 102 which face in opposite directions in the thickness direction DT of the rewiring substrate 100. In FIG. 1, the thickness direction DT of the rewiring substrate 100 is indicated by an arrow pointing from bottom to top.

[0019] The rewiring substrate 100 is disposed between the semiconductor element 200 and the rigid substrate 300 in the thickness direction DT. A plurality of terminal portions T1 are formed on the first surface 101. The semiconductor element 200 is mounted on the first surface 101 of the rewiring substrate 100, thereby forming a semiconductor element mounting substrate 400.

[0020] The semiconductor element 200 has an opposing surface 211 that faces the rewiring substrate 100 when mounted on the rewiring substrate 100. The semiconductor element 200 also has a plurality of columnar joints 220 formed to protrude from the opposing surface 211 by a certain length. Each columnar joint 220 is formed of a metal material containing copper, for example, and has a cross section perpendicular to the axial direction of the columnar joint 220 that is circular, as shown in the balloon in FIG. 1. The diameter of the cross section of the columnar joint 220 is 20 μm or more and 40 μm or less. The length (height) of the columnar joint 220 in the axial direction is 20 μm or more and 40 μm or less. The tip of the columnar joint 220 constitutes a connection terminal of the semiconductor element 200, and is joined to the terminal portion T1 of the rewiring substrate 100 that is previously associated with the columnar joint 220 via solder S. The cross section of the columnar joint 220 may have a shape other than a circle, such as an ellipse or a polygon.

[0021] In the semiconductor element mounting board 400, an underfill 290 is filled between the opposing surface 211 of the semiconductor element 200 and the first surface 101 of the rewiring board 100. The underfill 290 is formed of, for example, an epoxy resin. A lid member (not shown) that covers the semiconductor element 200 may be provided on the first surface 101 of the rewiring board 100. In Figs. 1 to 3, the semiconductor element 200 is indicated by a dashed line.

[0022] A plurality of terminal portions T2 are formed on the second surface 102 of the rewiring substrate 100. The rigid substrate 300 has a plurality of electrode pads 301 as a plurality of connection terminals of the rigid substrate 300. Each electrode pad 301 has a circular shape in a plan view. The diameter of the electrode pad 301 is 50 μm or more and 400 μm or less. The electrode pad 301 may have a shape other than a circle, such as an elliptical shape or a polygonal shape. The electrode pad 301 is bonded to the terminal portion T2 of the rewiring substrate 100 to which it is previously associated via solder S. In FIGS. 1 to 3, the rigid substrate 300 is indicated by a two-dot chain line.

[0023] The rewiring substrate 100 generally has a configuration in which a plurality of conductor layers are formed inside a plurality of (four in this example) insulating layers arranged in a stacked manner. In the following description, when distinguishing between the four insulating layers constituting the rewiring substrate 100 in FIG. 1, the insulating layers are referred to as a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, and a fourth insulating layer 40, respectively. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 are arranged in this order in the thickness direction DT of the rewiring substrate 100.

[0024] Each of the four insulating layers (10, 20, 30, 40) is formed of a photosensitive material. Specific examples of the photosensitive material used for the four insulating layers (10, 20, 30, 40) include photosensitive polyimide. Note that the insulating layers (10, 20, 30, 40) may be formed of other photosensitive resins (acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, polyvinyl chloride resin, or other photosensitive resins) instead of photosensitive polyimide. The thickness of each of the insulating layers (10, 20, 30, 40) is greater than 0 μm and less than 30 μm. Furthermore, the thickness of each of the insulating layers (10, 20, 30, 40) is preferably greater than 3 μm and less than 15 μm.

[0025] The multiple conductor layers include multiple first conductor layers 11, multiple second conductor layers 21, and multiple third conductor layers 31. The multiple first conductor layers 11 basically include via portions 11a and wiring portions 11b. Note that some of the multiple first conductor layers 11 may be composed of only wiring portions 11b.

[0026] The via portion 11a is a portion of the first conductor layer 11 that is formed inside a through hole h11 (FIG. 6) described later in the first insulating layer 10. The wiring portion 11b is a portion that is formed in a predetermined pattern on one surface (upper surface) of the first insulating layer 10. In the rewiring substrate 100 of FIG. 1, the other surface (lower surface) of the first insulating layer 10 constitutes a second surface 102 of the rewiring substrate 100.

[0027] The bottom of the via portion 11a is located on the second surface 102. The above-mentioned terminal portion T2 is formed at the bottom of the via portion 11a of the first conductor layer 11 so as to be exposed in the direction in which the second surface 102 faces. Each terminal portion T2 may be formed at the bottom of the via portion 11a, or may be formed by performing a surface treatment on the bottom of the via portion 11a. For example, each terminal portion T2 may be formed by growing a plating layer of a metal having excellent corrosion resistance, such as gold, on the bottom of the via portion 11a. Alternatively, each terminal portion T2 may be formed by forming an organic film, such as a water-soluble preflux, on the bottom of the via portion 11a.

[0028] The second conductor layers 21 have the same configuration as the first conductor layers 11, and basically include a via portion 21a and a wiring portion 21b. Note that some of the second conductor layers 21 may be composed of only the wiring portion 21b.

[0029] The via portion 21a is a portion formed inside a through hole h21 (FIG. 8) described later in the second insulating layer 20. The wiring portion 21b is a portion formed in a predetermined pattern on one surface (upper surface) of the second insulating layer 20. At least one wiring portion 21b among the multiple wiring portions 21b is connected to the first conductor layer 11 through the via portion 21a.

[0030] The third conductor layers 31 have the same configuration as the first conductor layers 11, and basically include a via portion 31a and a wiring portion 31b. Note that some of the third conductor layers 31 may be composed of only the wiring portion 31b.

[0031] The via portion 31a is a portion formed inside a through hole h31 (FIG. 10) described later of the third insulating layer 30. The wiring portion 31b is a portion formed in a predetermined pattern on one surface (upper surface) of the third insulating layer 30. At least one of the multiple wiring portions 31b is connected to the second conductor layer 21 through the via portion 31a.

[0032] The fourth insulating layer 40 functions as a cover insulating layer for protecting the third conductor layer 31 formed on the third insulating layer 30, and one surface (upper surface) is exposed to the outside of the rewiring substrate 100. This one surface of the fourth insulating layer 40 constitutes the first surface 101 of the rewiring substrate 100.

[0033] The above-mentioned multiple terminal portions T1 are formed in parts of the wiring portion 31b of the third conductor layer 31. The fourth insulating layer 40 has openings for exposing the terminal portions T1 formed in parts of the third conductor layer 31 in the direction in which the first surface 101 faces.

[0034] Each terminal portion T1 may be configured from a part of the third conductor layer 31, or may be formed by performing a surface treatment on the part of the third conductor layer 31. For example, each terminal portion T1 may be formed by growing a plating layer of a metal having excellent corrosion resistance, such as gold, on a part of the third conductor layer 31. Alternatively, each terminal portion T1 may be formed by forming an organic film, such as a water-soluble preflux, on a part of the third conductor layer 31.

[0035] Each of the conductor layers (11, 21, 31) is formed by growing a plating layer on a seed layer by electrolytic plating. A specific example of this formation method will be described later. The seed layer forming the conductor layer is made of, for example, a chromium thin film and a copper thin film. Alternatively, the seed layer is made of a titanium thin film and a copper thin film. Alternatively, the seed layer is made of a copper thin film. On the other hand, the plating layer is formed of a metal or an alloy containing one or more of copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, and the like. In this embodiment, the plating layer is copper. The thickness of each of the wiring parts 11b, 21b, 31b of the multiple conductor layers (11, 21, 31) is greater than 0 μm and smaller than 30 μm. Also, it is preferable that the thickness of each of the wiring parts 11b, 21b, 31b is greater than 3 μm and smaller than 15 μm.

[0036] In the rewiring board 100 according to the present embodiment, the sum of the thickness of each of the insulating layers (10, 20, 30) excluding the fourth insulating layer 40 and the thickness of the wiring portions 11b, 21b, 31b of the conductor layers (11, 21, 31) formed on the insulating layers is 30 μm or less. As a result, the rewiring board 100 according to the present embodiment is made thinner than the thickness (about several hundred μm) of a conventional general rewiring board.

[0037] Assume that the thickness of each of the insulating layers (10, 20, 30, 40) is within the above-mentioned preferred range (3 μm or more and 15 μm or less) and the thickness of each of the wiring parts 11b, 21b, 31b is within the above-mentioned preferred range (3 μm or more and 15 μm or less). In this case, the sum of the thickness of the first insulating layer 10 and the thickness of the wiring part 11b of the first conductor layer 11 formed on the first insulating layer 10 is 6 μm or more and 30 μm or less (see arrow t11 in FIG. 1). In addition, the sum of the thickness of the second insulating layer 20 and the thickness of the wiring part 21b of the second conductor layer 21 formed on the second insulating layer 20 is 6 μm or more and 30 μm or less (see arrow t12 in FIG. 1). Furthermore, the sum of the thickness of the third insulating layer 30 and the thickness of the wiring portion 31b of the third conductor layer 31 formed on the third insulating layer 30 is 6 μm or more and 30 μm or less (see arrow t13 in FIG. 1). As a result, in the rewiring board 100 in FIG. 1, the minimum thickness of each layer (10, 11, 20, 21, 30, 31, 40) is 21 μm when the thickness is within the preferred range.

[0038] 2, each of the terminal parts T1 has a circular shape corresponding to the cross-sectional shape of the columnar joint 220 of the semiconductor element 200 in a plan view, and the diameter of the circular shape is 20 μm or more and 40 μm or less. When the cross-sectional shape of the columnar joint 220 is a shape other than a circle, it is preferable that the terminal part T1 has basically the same shape as the cross-sectional shape of the columnar joint 220.

[0039] 3, each of the multiple terminal portions T2 has a circular shape corresponding to the shape of the electrode pad 301 of the rigid substrate 300 in a plan view, and the diameter of the circular shape is 50 μm or more and 400 μm or less. When the shape of the electrode pad 301 is other than a circular shape, it is preferable that the terminal portion T2 has basically the same shape as the shape of the electrode pad 301.

[0040] In the present embodiment, the number of the plurality of terminal portions T1 located on the first surface 101 of the rewiring substrate 100 is equal to the number of the plurality of terminal portions T2 located on the second surface 102 of the rewiring substrate 100, but the present invention is not limited to this. The number of the plurality of terminal portions T1 located on the first surface 101 of the rewiring substrate 100 does not have to be equal to the number of the plurality of terminal portions T2 located on the second surface 102 of the rewiring substrate 100.

[0041] 2. Manufacturing method of rewiring substrate 100 In this embodiment, the rewiring substrate 100 is manufactured by, for example, a roll-to-roll method. Fig. 4 is a schematic side view showing an example of a roll-to-roll apparatus 500 used in the manufacturing process of the rewiring substrate 100.

[0042] 4, the roll-to-roll apparatus 500 includes an unwinding section 501, a winding section 502, and a plurality of processing sections 510, 520, .... First, a roll (unwinding roll) R1 around which a long metal support 1 is wound is prepared and set in the unwinding section 501 of the roll-to-roll apparatus 500.

[0043] The metal support 1 is made of stainless steel. Instead of stainless steel, the metal support 1 may be made of copper, a copper alloy, aluminum, titanium, or an alloy containing iron and nickel. Examples of the alloy containing iron and nickel include Invar, 42 alloy, 45 permalloy, and copper.

[0044] The metal support 1 is unwound from a prepared unwinding roll R1. The unwound metal support 1 is taken up by another roll (take-up roll) R2 set in a winding section 502, as indicated by the dotted arrow in FIG.

[0045] In the roll-to-roll apparatus 500, a plurality of processing sections 510, 520, ... are arranged between two rolls (R1, R2) in the moving direction of the metal support 1. The plurality of processing sections 510, 520, ... sequentially form a plurality of insulating layers (10, 20, 30, 40) of Fig. 1 and a plurality of conductor layers (11, 21, 31) of Fig. 1 in each region of the long metal support 1 moving between the two rolls (R1, R2). As a result, a plurality of rewiring substrates 100 are formed on the metal support 1 taken up by the take-up roll R2.

[0046] The method for manufacturing the rewiring substrate 100 will now be described in detail.

[0047] Figures 5 to 13 are schematic cross-sectional views for explaining an example of a manufacturing method of the rewiring substrate 100 in Figure 1. The schematic cross-sectional views shown in Figures 5 to 13 correspond to the schematic cross-sectional view of the rewiring substrate 100 in Figure 1. In each of Figures 5 to 13, the thickness direction DT in Figure 1 is shown.

[0048] As described above, a payout roll R1 (FIG. 4) around which the metal support 1 is wound is prepared, and the metal support 1 is paid out from the payout roll R1. FIG 5 shows a cross section of a portion of the paid-out metal support 1. The metal support 1 has an upper surface 1a and a lower surface 1b that face in opposite directions in the thickness direction DT.

[0049] Next, a photosensitive polyimide precursor is applied onto the upper surface 1a of the metal support 1. The applied photosensitive polyimide precursor is exposed to light and developed. As a result, a first insulating layer 10 (FIG. 6) is formed on the metal support 1. The formed first insulating layer 10 is cured. Then, as shown in FIG. 6, a plurality of through holes h11 are formed in a plurality of predetermined portions of the first insulating layer 10 by, for example, laser processing or etching. The plurality of through holes h11 expose a portion of the upper surface 1a of the metal support 1 above the metal support 1.

[0050] The multiple through holes h11 may be formed by exposing a precursor of a photosensitive polyimide applied onto the metal support 1 in a predetermined pattern when the first insulating layer 10 is formed. That is, the multiple through holes h11 may be formed simultaneously with the formation of the first insulating layer 10 on the metal support 1.

[0051] Next, a seed layer SL (FIG. 7) is formed by, for example, sputtering on the portions of the metal support 1 exposed inside the multiple through holes h11, the inner circumferential surfaces of the multiple through holes h11, and the first insulating layer 10. Note that the seed layer SL may be formed by, for example, electroless plating instead of sputtering.

[0052] Thereafter, a plating resist layer having a predetermined pattern is formed on the seed layer SL, and a plating layer PL (FIG. 7) is formed by electrolytic plating on the portion of the seed layer SL exposed through the opening of the plating resist layer. The plating resist layer is then removed by etching. Furthermore, the portion of the seed layer SL on which the plating layer PL is not formed is removed by etching. Thereby, as shown in FIG. 7, one or more first conductor layers 11 having via portions 11a in the through holes h11 and wiring portions 11b on the first insulating layer 10 are formed. Furthermore, one or more first conductor layers 11 having wiring portions 11b on the first insulating layer 10 are formed.

[0053] Next, a precursor of photosensitive polyimide is newly applied onto the first insulating layer 10 so as to cover the wiring parts 11b of the plurality of first conductor layers 11. A second insulating layer 20 (FIG. 8) is formed on the first insulating layer 10 in the same procedure as that for forming the first insulating layer 10. The formed second insulating layer 20 is cured. Then, as shown in FIG. 8, a plurality of through holes h21 are formed in a plurality of predetermined portions of the second insulating layer 20, for example, by laser processing or etching. The plurality of through holes h21 expose a portion of the plurality of first conductor layers 11 above the second insulating layer 20. Here, the formation of the plurality of through holes h21 may be performed simultaneously with the formation of the second insulating layer 20 on the first insulating layer 10 by using a photosensitive polyimide exposure technique (gradation exposure) as in the example of the plurality of through holes h11.

[0054] Next, a seed layer SL is formed on the portions of the first conductor layer 11 exposed inside the through holes h21, the inner circumferential surfaces of the through holes h21, and the second insulating layer 20 in the same manner as when the first conductor layer 11 was formed. A plating resist layer of a predetermined pattern is formed on the seed layer SL, and a plating layer PL is formed by electrolytic plating on the portions of the seed layer SL exposed through the openings of the plating resist layer. In addition, the plating resist layer is removed by etching. Furthermore, the portions of the seed layer SL on which the plating layer PL is not formed are removed by etching. Thereby, as shown in FIG. 9, one or more second conductor layers 21 having a via portion 21a in the through hole h21 and a wiring portion 21b on the second insulating layer 20 are formed. In addition, one or more second conductor layers 21 having a wiring portion 21b on the second insulating layer 20 are formed.

[0055] Next, a precursor of photosensitive polyimide is newly applied onto the second insulating layer 20 so as to cover the wiring parts 21b of the plurality of second conductor layers 21. A third insulating layer 30 (FIG. 10) is formed on the second insulating layer 20 in the same procedure as that for forming the first insulating layer 10. The formed third insulating layer 30 is cured. Then, as shown in FIG. 10, a plurality of through holes h31 are formed in a plurality of predetermined portions of the third insulating layer 30 by, for example, laser processing or etching. The plurality of through holes h31 expose a portion of the plurality of second conductor layers 21 above the third insulating layer 30. Here, the formation of the plurality of through holes h31 may be performed simultaneously with the formation of the third insulating layer 30 on the second insulating layer 20 by using a photosensitive polyimide exposure technique, as in the example of the plurality of through holes h11.

[0056] Next, a seed layer SL is formed on the portions of the second conductor layer 21 exposed inside the through holes h31, the inner circumferential surfaces of the through holes h31, and the third insulating layer 30 in the same manner as when the first conductor layer 11 is formed. A plating resist layer of a predetermined pattern is formed on the seed layer SL, and a plating layer PL is formed by electrolytic plating on the portions of the seed layer SL exposed through the openings of the plating resist layer. In addition, the plating resist layer is removed by etching. Furthermore, the portions of the seed layer SL on which the plating layer PL is not formed are removed by etching. Thereby, as shown in FIG. 11, one or more third conductor layers 31 having a via portion 31a in the through hole h31 and a wiring portion 31b on the third insulating layer 30 are formed. In addition, one or more third conductor layers 31 having a wiring portion 31b on the third insulating layer 30 are formed.

[0057] Next, a precursor of photosensitive polyimide is newly applied onto the third insulating layer 30 so as to cover the wiring parts 31b of the plurality of third conductor layers 31. A fourth insulating layer 40 (FIG. 12) is formed on the third insulating layer 30 in the same procedure as that for forming the first insulating layer 10. The formed fourth insulating layer 40 is cured. Then, as shown in FIG. 12, a plurality of through holes h41 are formed in a plurality of predetermined portions of the fourth insulating layer 40 by, for example, laser processing or etching. The plurality of through holes h41 expose a portion of the plurality of third conductor layers 31 above the fourth insulating layer 40. Here, the formation of the plurality of through holes h41 may be performed simultaneously with the formation of the fourth insulating layer 40 on the third insulating layer 30 by using a photosensitive polyimide exposure technique, as in the example of the plurality of through holes h11.

[0058] Completion of the formation of the fourth insulating layer 40 completes the basic structure of the rewiring substrate 100 of FIG. 1 on the upper surface 1a of the metal support 1. In the roll-to-roll apparatus 500 of FIG. 4, the metal support 1 of FIG. 12 on which the multiple insulating layers (10, 20, 30, 40) and the multiple conductor layers (11, 21, 31) are formed is wound up by the winding roll R2. The metal support 1 (laminate of the metal support 1 and the rewiring substrate 100) wound up by the winding roll R2 is set, for example, as a payout roll in another roll-to-roll apparatus. Subsequent processing is performed on the laminate paid out from the set payout roll.

[0059] Next, before mounting the semiconductor element 200 on the rewiring substrate 100, as shown in FIG. 13, the metal support 1 is removed from the first insulating layer 10 of the rewiring substrate 100 by wet etching.

[0060] Thereafter, as shown by dotted lines in FIG. 13, the portions of the plurality of third conductor layers 31 exposed on the first surface 101 of the rewiring substrate 100 are subjected to surface treatment (plating, etc.) as necessary, to form the plurality of terminal portions T1 in FIG. 1. Furthermore, the portions of the plurality of first conductor layers 11 exposed on the second surface 102 of the rewiring substrate 100 are subjected to surface treatment (plating, etc.) as necessary, to form the plurality of terminal portions T2 in FIG. 1. As described above, the terminal portion T1 may be formed of a part of the third conductor layer 31. Furthermore, the terminal portion T2 may be formed of a part of the first conductor layer 11. In these cases, the above-mentioned surface treatment is not necessary for the exposed portions of the third conductor layer 31 and the exposed portions of the first conductor layer 11.

[0061] 1 is completed by mounting a semiconductor element 200 on the fabricated rewiring board 100. The semiconductor element mounting board 400 is connected onto a rigid board 300.

[0062] 3. First Modification of the Method for Manufacturing the Rewiring Substrate 100 5 to 13 is referred to as a method for manufacturing the rewiring substrate 100 according to the basic example. In the method for manufacturing the rewiring substrate 100 according to the basic example, if there is a missing portion or a thin portion in the seed layer SL of the first conductor layer 11 that contacts the metal support 1, there is a possibility that the etching liquid will enter the inside of the first conductor layer 11 during wet etching of the metal support 1.

[0063] FIG. 14 is a schematic cross-sectional view of the rewiring substrate 100 showing an example of a state in which an etching solution has penetrated into the first conductor layer 11. As shown by the hollow arrow in FIG. 14, if an etching solution penetrates into the first conductor layer 11 during wet etching of the metal support 1, a void may be formed in the through hole h11 of the first insulating layer 10 after the metal support 1 is removed. In the rewiring substrate 100, the presence of such a void reduces the reliability of the rewiring substrate 100. In consideration of this point, the rewiring substrate 100 may be manufactured according to the following first modified example.

[0064] Hereinafter, the method for manufacturing the rewiring substrate 100 according to the first modified example will be described with respect to the differences from the method for manufacturing the rewiring substrate 100 according to the basic example. Figures 15 to 19 are schematic cross-sectional views for explaining the method for manufacturing the rewiring substrate 100 according to the first modified example. The schematic cross-sectional views shown in Figures 15 to 19 correspond to the schematic cross-sectional view of the rewiring substrate 100 in Figure 1. In each of Figures 15 to 19, the thickness direction DT in Figure 1 is shown.

[0065] In the manufacturing method of the rewiring substrate 100 according to the first modification, first, a first insulating layer 10 is formed on the upper surface 1a of the metal support 1, similarly to the manufacturing method of the rewiring substrate 100 according to the basic example. After or during the formation of the first insulating layer 10, a plurality of vertical holes v11 are formed in the first insulating layer 10 instead of the plurality of through holes h11 (FIG. 6). More specifically, as shown in FIG. 15, in the first modification, the vertical holes v11 are formed in each of a plurality of predetermined portions of the first insulating layer 10 so that the bottoms of the vertical holes are located at a certain distance from the metal support 1 in the thickness direction DT. The vertical holes v11 are formed, similarly to the example of the through holes h11 in FIG. 6, by using any of the methods such as laser processing, etching, or exposure technology (gradation exposure) of photosensitive polyimide.

[0066] Next, a seed layer SL is formed on the bottoms of the vertical holes v11, the inner peripheral surfaces of the vertical holes v11, and the first insulating layer 10. A plating resist layer of a predetermined pattern is formed on the seed layer SL, and a plating layer PL is formed by electrolytic plating on the portion of the seed layer SL exposed through the opening of the plating resist layer. The plating resist layer is also removed by etching. Furthermore, the portion of the seed layer SL on which the plating layer PL is not formed is also removed by etching. Thereby, as shown in FIG. 16, one or more first conductor layers 11 having a via portion 11a in the vertical hole v11 and a wiring portion 11b on the first insulating layer 10 are formed. Furthermore, one or more first conductor layers 11 having a wiring portion 11b on the first insulating layer 10 are formed.

[0067] Thereafter, similarly to the above-described basic example, a plurality of insulating layers (20, 30, 40) and a plurality of conductor layers (21, 31) are formed on the first insulating layer 10. In this state, as shown in FIG. 17, a part of the first insulating layer 10 exists between a portion of the seed layer SL located at the lower end of the first conductor layer 11 and the upper surface 1a of the metal support 1.

[0068] Next, before mounting the semiconductor element 200 on the rewiring substrate 100, as shown in FIG. 18, the metal support 1 is removed from the first insulating layer 10 of the rewiring substrate 100 by wet etching.

[0069] Here, the portion of the first insulating layer 10 located between the seed layer SL of the first conductor layer 11 and the metal support 1 is formed of photosensitive polyimide. Therefore, during the above-mentioned wet etching, the portion of the first insulating layer 10 located between the seed layer SL of the first conductor layer 11 and the metal support 1 functions as an etching stop layer for the etching solution of the metal support 1.

[0070] As a result, when the metal support 1 is removed, the etching solution for the metal support 1 does not come into contact with the seed layer SL located at the bottom of the vertical hole v11 of the first insulating layer 10. Therefore, the seed layer SL and the plating layer PL formed inside the vertical hole v11 of the first insulating layer 10 are not dissolved by the etching solution for the metal support 1. As a result, the generation of voids in the vertical hole v11 of the first insulating layer 10 after the metal support 1 is removed is prevented.

[0071] As described above, after the metal support 1 is removed from the first insulating layer 10, a region of a certain thickness (see the dotted line portion in FIG. 18) is removed from the lower end of the first insulating layer 10 by, for example, etching, in order to expose a part of the first conductor layer 11 below the first insulating layer 10. The etching solution used here is an etching solution for dissolving the first insulating layer 10, i.e., the photosensitive polyimide. Therefore, the first conductor layer 11 does not dissolve when the first insulating layer 10 is etched.

[0072] By partially etching the first conductor layer 11, the portions of the first conductor layer 11 located at the bottoms of the vertical holes v11 are exposed on the lower surface of the first insulating layer 10. This completes the rewiring substrate 100 as shown in Fig. 19. According to the method for manufacturing the rewiring substrate 100 of the first modified example, dissolution of the first conductor layer 11 caused by etching the metal support 1 is prevented, and therefore the reliability of the manufactured rewiring substrate 100 is improved.

[0073] 4. Second Modification of the Method for Manufacturing the Rewiring Substrate 100 According to the manufacturing method of the rewiring substrate 100 according to the basic example and the first modified example, the rewiring substrate 100 is manufactured in a state in which the metal support 1 is completely removed from the first insulating layer 10. As a result, the rewiring substrate 100 is made thin and has sufficient flexibility.

[0074] On the other hand, when mounting the semiconductor element 200 on the rewiring substrate 100, from the viewpoint of ease of handling, it is preferable that the rewiring substrate 100 has a certain degree of rigidity. In consideration of this point, the rewiring substrate 100 may be manufactured according to the following second modified example.

[0075] Hereinafter, the method for manufacturing the rewiring substrate 100 according to the second modified example will be described with reference to the differences from the method for manufacturing the rewiring substrate 100 according to the basic example. Figures 20 to 23 are diagrams for explaining the method for manufacturing the rewiring substrate 100 according to the second modified example.

[0076] When manufacturing the rewiring substrates 100 according to the basic example, the first modified example, and the second modified example, a plurality of rewiring substrates 100 are formed on one common metal support 1. A plan view showing a portion of the metal support 1 prepared in the manufacturing method of the rewiring substrate 100 is shown in FIG.

[0077] As shown in FIG. 20, a region for forming the rewiring substrate 100 is predefined in the metal support 1. Hereinafter, the portion of the metal support 1 in the predefined region where the rewiring substrate 100 is to be formed is referred to as a first portion p1. Also, the portion of the metal support 1 other than the first portion p1 is referred to as a second portion p2. In the example of FIG. 20, the first portions p1 are arranged in two rows at intervals along the direction in which the metal support 1 extends. Meanwhile, the second portion p2 spreads in a lattice shape between the first portions p1 and surrounds the first portions p1. As a result, the second portion p2 is adjacent to each of the first portions p1.

[0078] Using the metal support 1 of Fig. 20, the steps (steps shown in Figs. 5 to 12) of forming a plurality of insulating layers (10, 20, 30, 40) and a plurality of conductor layers (11, 21, 31) on the metal support 1 of the basic example are carried out. At this time, the insulating layers (10, 20, 30, 40) are sequentially stacked on the metal support 1 so as to be continuously overlapped from the first portion p1 to the second portion p2. As a result, a plurality of rewiring substrates 100 are formed on the plurality of first portions p1 of the metal support 1, respectively, as shown in Fig. 21.

[0079] Next, in the method for manufacturing the rewiring substrate 100 according to the second modification, only the first portions p1 of the metal support 1 that contact the first insulating layer 10 of the rewiring substrate 100 are removed by wet etching. In this case, the second portion p2 of the metal support 1 functions as a frame. As a result, each rewiring substrate 100 is indirectly supported by the second portion p2 of the metal support 1 via the outer edge portions of the insulating layers (10, 20, 30, 40).

[0080] In this state, as shown in the schematic cross-sectional view of Fig. 22, surface treatment is performed as necessary on the exposed portions of the plurality of first conductor layers 11 and the exposed portions of the plurality of third conductor layers 31 to form a plurality of terminal portions T1, T2. In Fig. 22 and the following Fig. 23, an opening formed in the metal support 1 by wet etching the first portion p1 is indicated by the symbol op.

[0081] 23, the semiconductor element 200 is mounted on the rewiring substrate 100 while the rewiring substrate 100 is supported by the second portion p2 of the metal support 1. This completes the semiconductor element mounting substrate 400. During this mounting, the rewiring substrate 100 is supported by the second portion p2 of the metal support 1, which improves the ease of handling of the rewiring substrate 100 and stabilizes the mounting operation. As a result, the reliability of the semiconductor element mounting substrate 400 is improved.

[0082] 23, as indicated by thick two-dot chain lines, the outer edge portions of the insulating layers (10, 20, 30, 40) are cut from the portions of the insulating layers (10, 20, 30, 40) located on the second portion p2 of the metal support 1. This makes it possible to separate the metal support 1 from the rewiring substrate 100 without using any chemicals that adversely affect the semiconductor element 200, such as an etching solution.

[0083] 5.Effects (a) In the above-described rewiring substrate 100, the tips of the plurality of columnar joints 220 of the semiconductor element 200 can be connected to the plurality of terminal portions T1 on the first surface 101. This makes it easy to mount the semiconductor element 200 on the rewiring substrate 100. In addition, the plurality of electrode pads 301 of the rigid substrate 300 can be easily connected to the plurality of terminal portions T2 on the second surface 102.

[0084] In the rewiring substrate 100, the sum of the thickness of the insulating layer (10, 20, 30) and the thickness of the wiring portion (11b, 21b, 31b) of the plurality of conductor layers (11, 21, 31) is 30 μm or less. Therefore, the overall thickness of the rewiring substrate 100 can be made smaller than when the sum of these thicknesses is greater than 30 μm. In other words, the rewiring substrate 100 can be made thinner.

[0085] As a result, the semiconductor element mounting board 400 including the rewiring board 100 and the semiconductor element 200 can be easily manufactured. In addition, the impedance of the wiring formed by the wiring parts (11b, 21b, 31b) of the conductor layers (11, 21, 31) on the insulating layers (10, 20, 30) can be reduced. Furthermore, high heat dissipation properties can be ensured for the semiconductor element 200 mounted on the rewiring board 100.

[0086] (b) Each of the four insulating layers (10, 20, 30, 40) is formed of photosensitive polyimide. In addition, when forming the insulating layers, a precursor of the photosensitive polyimide is applied onto the metal support 1 or the other insulating layers (20, 30, 40), and the applied precursor is exposed and developed. Therefore, by selectively exposing the precursor, the insulating layer can be easily patterned. Therefore, when forming through holes or the like in each insulating layer (10, 20, 30, 40), the process of removing residues required in laser processing or the like is not required, and the number of processes required for manufacturing the rewiring substrate 100 can be reduced. Note that the same effect can be obtained even when a photosensitive material other than photosensitive polyimide is used for each insulating layer (10, 20, 30, 40).

[0087] (c) According to the manufacturing method of the semiconductor element mounting substrate 400 of the above embodiment, the rewiring substrate 100 is manufactured on the metal support 1 having higher rigidity than resin or the like. This prevents the intermediate body of the rewiring substrate 100 from being excessively deformed during the manufacturing of the rewiring substrate 100. This improves the reliability of the manufacturing of the rewiring substrate 100.

[0088] Moreover, according to the above manufacturing method, the metal support 1 is removed from the rewiring substrate 100 by wet etching before the step of mounting the semiconductor element 200 on the rewiring substrate 100. In this case, when removing the metal support 1 from the rewiring substrate 100, it is not necessary to place the semiconductor element 200 near the rewiring substrate 100 and the metal support 1. Therefore, the semiconductor element 200 is prevented from being damaged or contaminated due to the operation of removing the metal support 1 from the rewiring substrate 100. As a result, it is possible to manufacture a semiconductor element mounting substrate 400 having high reliability.

[0089] (d) According to the above-described method for manufacturing the rewiring substrate 100, the rewiring substrate 100 in which a large number of conductor layers are laminated can be manufactured by simply repeating the steps of forming the insulating layers and conductor layers.

[0090] (e) In manufacturing the rewiring substrate 100 according to the above embodiment, a roll-to-roll apparatus 500 is used to fabricate the rewiring substrate 100 on the metal support 1. This allows multiple processes to be performed continuously on multiple regions on the metal support 1 moving between the pay-out roll R1 and the take-up roll R2. This improves the efficiency of fabricating the rewiring substrate 100.

[0091] 6. Other embodiments (a) The rewiring substrate 100 in the above embodiment basically has a configuration in which a plurality of insulating layers (10, 20, 30, 40) and a plurality of conductor layers (11, 21, 31) are stacked together, and does not include a metal support 1, but the present invention is not limited to this.

[0092] The rewiring substrate may include a metal support. Fig. 24 is a schematic cross-sectional view showing the configuration of a rewiring substrate according to another embodiment. The plan view and bottom view of the rewiring substrate of this example are the same as the plan view and bottom view of the rewiring substrate 100 according to the above embodiment (see Figs. 2 and 3). In Fig. 24, as in the example of Fig. 1, the thickness direction DT of the rewiring substrate 100 is indicated by an arrow.

[0093] As shown in Fig. 24, the rewiring substrate 100 according to another embodiment mainly includes a metal support 110, a plurality of (four in this example) insulating layers, and a plurality of (three in this example) conductor layers. In the following description, when distinguishing between the four insulating layers constituting the rewiring substrate 100 in Fig. 24, the insulating layers are referred to as a first insulating layer 50, a second insulating layer 60, a third insulating layer 70, and a fourth insulating layer 80, respectively. These insulating layers (50, 60, 70, 80) are formed of the same material as the insulating layers (10, 20, 30, 40) in Fig. 1 according to the above embodiment.

[0094] The first insulating layer 50, the second insulating layer 60, the metal support 110, the third insulating layer 70, and the fourth insulating layer 80 are arranged in this order in the thickness direction DT of the rewiring substrate 100. The metal support 110 is made of stainless steel. Instead of stainless steel, the metal support 110 may be made of copper, a copper alloy, aluminum, titanium, or an alloy containing iron and nickel. Examples of the alloy containing iron and nickel include Invar, 42 alloy, 45 permalloy, and copal. When Invar is used for the metal support 110, it becomes possible to adjust the linear expansion coefficient of the metal support 110 in response to the change in the nickel (Ni) composition in Invar. In this case, it becomes possible to suppress the occurrence of warping in each layer constituting the rewiring substrate 100.

[0095] The thermal conductivity of the metal support 110 is 10 W / mK or more and 250 W / mK or less. The linear expansion coefficient of the metal support 110 at 25° C. or more and 200° C. or less is 0 ppm / K or more and 25 ppm / K or less. The thickness of the metal support 110 is 15 μm or more and 60 μm or less.

[0096] 24, one surface of the metal support 110 facing the semiconductor element 200 (surface facing upward in FIG. 24) is referred to as the upper surface 110a, and the other surface of the metal support 110 facing the rigid substrate 300 (surface facing downward in FIG. 24) is referred to as the lower surface 110b. The metal support 110 has a plurality of through holes h111 (two in this example) formed therein, extending from the upper surface 110a to the lower surface 110b.

[0097] A coating layer 120 is formed on the outer surface of the metal support 110. More specifically, the coating layer 120 is formed on the metal support 110 so as to cover the entire upper surface 110a, the lower surface 110b, and the inner circumferential surface of each through hole h111. The coating layer 120 is formed of, for example, photosensitive polyimide. The coating layer 120 has a thickness of 0.1 μm or more and 20 μm or less. The coating layer 120 may be formed of other resins such as acrylic resin, polyethernitrile resin, polyethersulfone resin, epoxy resin, polyethylene terephthalate resin, polyethylene naphthalate resin, or polyvinyl chloride resin. In addition, inorganic insulating materials or organic insulating materials can be used as the material of the coating layer 120 instead of the above-mentioned resins. Specifically, silicon carbide, silicon dioxide, aluminum nitride, aluminum oxide, or the like can be used as the material of the coating layer 120.

[0098] A plurality of first conductor layers 111 are formed on a portion of the outer surface of the metal support 110 via the above-mentioned covering layer 120. Each of the plurality of first conductor layers 111 includes a via portion 111a and wiring portions 111b and 111c.

[0099] The via portion 111a is a portion of the first conductor layer 111 formed inside the through hole h111 of the metal support 110. The wiring portion 111b is a portion formed in a predetermined pattern on the lower surface 110b of the metal support 110. The wiring portion 111c is a portion formed in a predetermined pattern on the upper surface 110a of the metal support 110. The thickness of each of the wiring portions 111b, 111c is greater than 0 μm and less than 30 μm. Furthermore, the thickness of each of the wiring portions 111b, 111c is preferably greater than 3 μm and less than 15 μm.

[0100] The second insulating layer 60 is formed on the lower surface 110b of the metal support 110 via the covering layer 120 so as to cover the wiring portion 111b of the first conductor layer 111 from below. A plurality of through holes (two in this example) extending in the thickness direction DT are formed in the second insulating layer 60. The upper ends of the plurality of through holes are located on the wiring portion 111b of the first conductor layer 111.

[0101] A plurality of second conductor layers 61 are formed on a portion of the second insulating layer 60. Each of the plurality of second conductor layers 61 includes a via portion 61a and a wiring portion 61b. The via portion 61a is a portion of the second conductor layer 61 formed inside a through hole of the second insulating layer 60. The wiring portion 61b is a portion of the second conductor layer 61 formed in a predetermined pattern on one surface (the lower surface in this example) of the second insulating layer 60. Note that some of the plurality of second conductor layers 61 may be composed of only the wiring portion 61b. The thickness of each of the wiring portions 61b is greater than 0 μm and less than 30 μm. In addition, the thickness of each of the wiring portions 61b is preferably greater than 3 μm and less than 15 μm.

[0102] The first insulating layer 50 functions as a cover insulating layer for protecting the second conductor layer 61 formed on the second insulating layer 60, and one surface (lower surface) is exposed to the outside of the rewiring substrate 100. This one surface of the first insulating layer 50 constitutes the second surface 102 of the rewiring substrate 100.

[0103] A plurality of terminal portions T2 are formed in a portion of the wiring portion 61b of the second conductor layer 61. The first insulating layer 50 has openings for exposing the plurality of terminal portions T2 in the direction in which the second surface 102 faces. Each terminal portion T2 may be configured from that portion of the second conductor layer 61, or may be formed by subjecting that portion of the second conductor layer 61 to a surface treatment.

[0104] The third insulating layer 70 is formed on the upper surface 110a of the metal support 110 via the covering layer 120 so as to cover the wiring portion 111c of the first conductor layer 111 from above. A plurality of (two in this example) through holes extending in the thickness direction DT are formed in the third insulating layer 70. The lower ends of the plurality of through holes are located on the wiring portion 111c of the first conductor layer 111.

[0105] A plurality of third conductor layers 71 are formed on a portion of the third insulating layer 70. Each of the plurality of third conductor layers 71 includes a via portion 71a and a wiring portion 71b. The via portion 71a is a portion of the third conductor layer 71 formed inside a through hole of the third insulating layer 70. The wiring portion 71b is a portion of the third conductor layer 71 formed in a predetermined pattern on one surface (the upper surface in this example) of the third insulating layer 70. Note that some of the plurality of third conductor layers 71 may be composed of only the wiring portion 71b. The thickness of each of the wiring portions 71b is greater than 0 μm and less than 30 μm. In addition, it is preferable that the thickness of each of the wiring portions 71b is greater than 3 μm and less than 15 μm.

[0106] The fourth insulating layer 80 functions as a cover insulating layer for protecting the third conductor layer 71 formed on the third insulating layer 70, and one surface (upper surface) is exposed to the outside of the rewiring substrate 100. This one surface of the fourth insulating layer 80 constitutes the first surface 101 of the rewiring substrate 100.

[0107] A plurality of terminal portions T1 are formed in a part of the wiring portion 71b of the third conductor layer 71. The fourth insulating layer 80 has openings for exposing the plurality of terminal portions T1 in the direction in which the first surface 101 faces. Each terminal portion T1 may be configured from the part of the third conductor layer 71, or may be formed by performing a surface treatment on the part of the third conductor layer 71.

[0108] In the rewiring board 100 in Fig. 24, the sum of the thickness of each of the insulating layers (60, 70) excluding the first insulating layer 50 and the fourth insulating layer 80 and the thickness of the wiring portions 61b, 71b of the conductor layers (61, 71) formed on the insulating layers is 30 µm or less. As a result, the rewiring board 100 in Fig. 24 is also thinner than the thickness (about several hundred µm) of a conventional general rewiring board.

[0109] Assume that the thickness of each of the insulating layers (60, 70) is within the above-mentioned preferred range (3 μm or more and 15 μm or less) and the thickness of each of the wiring portions 61b, 71b is within the above-mentioned preferred range (3 μm or more and 15 μm or less). In this case, the sum of the thickness of the second insulating layer 60 and the thickness of the wiring portion 61b of the second conductor layer 61 formed on the second insulating layer 60 is 6 μm or more and 30 μm or less (see arrow t21 in FIG. 24). In addition, the sum of the thickness of the third insulating layer 70 and the thickness of the wiring portion 71b of the third insulating layer 70 formed on the third insulating layer 70 is 6 μm or more and 30 μm or less (see arrow t22 in FIG. 24).

[0110] The rewiring substrate 100 of Fig. 24 having the above configuration is generally fabricated as follows. First, a metal support 110 is prepared, and a plurality of through holes h111 are formed in a predetermined portion of the metal support 110. In addition, a coating layer 120 is formed over the entire outer surface of the metal support 110. After that, a first conductor layer 111 is formed on a predetermined portion of the outer surface of the metal support 110 via the coating layer 120.

[0111] Next, a laminated structure including a second insulating layer 60, a second conductor layer 61, and a first insulating layer 50 is formed on the lower surface 110b of the metal support 110. Also, a laminated structure including a third insulating layer 70, a third conductor layer 71, and a fourth insulating layer 80 is formed on the upper surface 110a of the metal support 110. The formation of these laminated structures is performed in a similar procedure to the process of forming the multiple insulating layers (10, 20, 30, 40) and conductor layers (11, 21, 31) in the manufacturing process of the rewiring substrate 100 according to the above embodiment.

[0112] In the rewiring board 100 of this example, the multiple insulating layers (50, 60, 70, 80) and the multiple conductor layers (111, 61, 71) are reinforced by the highly rigid metal support 110. Therefore, the reliability of the rewiring board 100 is improved.

[0113] Moreover, the metal support 110 has a higher thermal conductivity than the multiple insulating layers (50, 60, 70, 80). Therefore, when the semiconductor element 200 is mounted on the rewiring substrate 100, the metal support 110 easily receives heat generated by the semiconductor element 200. Therefore, the metal support 110 functions as a heat dissipation member for the semiconductor element 200.

[0114] As described above, the thermal conductivity of the metal support 110 is not less than 10 W / mK and not more than 250 W / mK. In this case, the metal support 110 effectively functions as a heat dissipation member for the semiconductor element 200 mounted on the rewiring substrate 100.

[0115] Moreover, the linear expansion coefficient of metal support 110 at temperatures from 25° C. to 200° C. is 0 ppm / K to 25 ppm / K. In this case, metal support 110 is prevented from being significantly deformed in accordance with changes in temperature of rewiring substrate 100. This improves the reliability of rewiring substrate 100.

[0116] (b) In the rewiring substrate 100 according to the above embodiment, the sum of the thickness of each of the multiple insulating layers and the thickness of the wiring portion of the conductor layer formed on the insulating layer is 30 μm or less, but the present invention is not limited to this.

[0117] In the rewiring substrate 100, the sum of the thickness of at least one of the insulating layers and the thickness of the wiring portion of the conductor layer formed on the insulating layer may be 30 μm or less. In this case, the rewiring substrate 100 can be made thinner than when the sum of the thickness of each of the insulating layers and the thickness of the wiring portion of the conductor layer formed on the insulating layer is greater than 30 μm.

[0118] (c) In the above embodiment, the rewiring substrate 100 in Fig. 1, which does not include the metal support 1, has a configuration in which three conductor layers (11, 21, 31) are formed on three insulating layers (10, 20, 30), respectively, but the present invention is not limited to this. The rewiring substrate 100 may have a configuration in which four conductor layers are formed on four insulating layers, respectively, or a configuration in which five or more conductor layers are formed on five or more insulating layers, respectively.

[0119] (d) In the above embodiment, the rewiring substrate 100 is manufactured by a roll-to-roll process, but the present invention is not limited to this. The rewiring substrate 100 may be manufactured by a process other than the roll-to-roll process. For example, the rewiring substrate 100 may be manufactured by a sheet-by-sheet process in which processes are sequentially performed on a single sheet.

[0120] (e) The above-described embodiment is an example of applying the present invention to a rewiring board, but the present invention is not limited to this and may be applied to other wired circuit boards in which a plurality of insulating layers and a plurality of conductor layers are stacked.

[0121] 7. Correspondence between each component of the claims and each part of the embodiment Below, examples of the correspondence between each component of the claims and each element of the embodiment will be described, but the present invention is not limited to the following examples. Various other elements having the configuration or function described in the claims can also be used as each component of the claims.

[0122] In the above-described embodiments, rewiring substrate 100 is an example of a wiring circuit board and a rewiring substrate, first surface 101 is an example of a first surface, second surface 102 is an example of a second surface, thickness direction DT is an example of a thickness direction, any one of the multiple insulating layers (10, 20, 30, 60, 70) is an example of a first insulating layer, and multiple insulating layers (10, 20, 30, 40, 50, 60, 70, 80) are an example of multiple insulating layers.

[0123] In addition, the multiple conductor layers (11, 21, 31, 61, 71) are examples of multiple conductor layers, the semiconductor element 200 and the rigid substrate 300 are examples of electrical elements, the tips of the multiple columnar joints 220 of the semiconductor element 200 and the multiple electrode pads 301 of the rigid substrate 300 are examples of connection terminals, the terminal portion T1 of the rewiring substrate 100 is an example of a first connected portion, the terminal portion T2 of the rewiring substrate 100 is an example of a second connected portion, and any of the multiple conductor layers (11, 21, 31, 61, 71) is an example of a first conductor layer.

[0124] In addition, the semiconductor element 200 is an example of a first electrical element, the rigid substrate 300 is an example of a second electrical element, the second insulating layer 20 is an example of a second insulating layer, the third insulating layer 30 is an example of a third insulating layer, the second conductor layer 21 is an example of a second conductor layer, the third conductor layer 31 is an example of a third conductor layer, the multiple insulating layers (10, 20, 30, 60, 70) are an example of multiple base insulating layers, and the multiple insulating layers (40, 50, 80) are an example of a cover insulating layer.

[0125] In addition, the metal support 1 is an example of a metal support, any of the multiple insulating layers (60, 70) is an example of a second insulating layer, any of the multiple conductor layers (61, 71) is an example of a second conductor layer, the solder S is an example of a joining member, the opposing surface 211 is an example of an opposing surface, the columnar joint 220 is an example of a columnar joint, and the semiconductor element mounting board 400 is an example of an electrical component mounting board.

[0126] 8. Examples and Comparative Examples (a) Regarding wiring impedance The inventors conducted the following test (hereinafter referred to as an impedance test) to confirm whether the impedance of the wiring formed inside the rewiring substrate 100 is reduced by making the rewiring substrate 100 thinner than conventional rewiring substrates.

[0127] First, the inventors produced a rewiring board 100 having basically the same configuration as the rewiring board 100 of FIG. 1 as Example 1. In the rewiring board 100 of Example 1, a plurality of insulating layers (10, 20, 30, 40) were produced from photosensitive polyimide. The thickness of each insulating layer was 5 μm. Furthermore, the dielectric constant of each insulating layer was 3.3, and the dielectric tangent of each insulating layer was 0.007. Furthermore, in the rewiring board 100 of Example 1, each of the plurality of conductor layers (11, 21, 31) was formed from copper. The thickness of each conductor layer was 5 μm.

[0128] The present inventors also fabricated a rewiring board as Comparative Example 1, which has the same configuration as the rewiring board 100 of Example 1, except for the thickness and material of each part. In the rewiring board of Comparative Example 1, a plurality of insulating layers were fabricated using a material (MEGTRON GX R-1515A manufactured by Panasonic Corporation) different from the photosensitive polyimide of Example 1. The thickness of each insulating layer was 30 μm. In addition, the dielectric constant of each insulating layer was 4.7, and the dielectric tangent of each insulating layer was 0.011. Furthermore, in the rewiring board of Comparative Example 1, each of the plurality of conductor layers was formed of copper. The thickness of each conductor layer was 15 μm.

[0129] Thereafter, the inventors measured the impedance of the wiring of the uppermost conductor layer (the wiring located closest to the semiconductor element 200 in the semiconductor element mounting substrate 400) for the rewiring substrate 100 of Example 1 and the rewiring substrate of Comparative Example 1. The impedance measured here is called the upper impedance.

[0130] The inventors also measured the impedance of the wiring of the bottom conductor layer (the wiring located farthest from the semiconductor element 200 in the semiconductor element mounting substrate 400) for the rewiring substrate 100 of Example 1 and the rewiring substrate of Comparative Example 1. The impedance measured here is called the bottom impedance.

[0131] FIG. 25 is a diagram showing the impedance test results for the rewiring substrate 100. In FIG. 25, the impedance test results are shown in a graph. In the graph of FIG. 25, the vertical axis represents the magnitude of the impedance of the wiring, and the horizontal axis represents the frequency. Moreover, the upper impedance of the rewiring substrate 100 of Example 1 is shown by a thick dotted line, and the lower impedance of the rewiring substrate 100 of Example 1 is shown by a thick solid line. Furthermore, the upper impedance of the rewiring substrate 100 of Comparative Example 1 is shown by a dotted line, and the lower impedance of the rewiring substrate 100 of Comparative Example 1 is shown by a solid line.

[0132] According to the impedance test results in FIG. 25, it was confirmed that the impedance of the top and bottom wirings of Example 1 was lower than the impedance of the top and bottom wirings of Comparative Example 1 over a wide frequency band.

[0133] (b) Regarding heat dissipation of electrical elements mounted on the rewiring board The inventors performed the following simulation to confirm the extent to which the heat dissipation of the semiconductor element 200 mounted on the rewiring substrate 100 can be improved by making the rewiring substrate 100 thinner than conventional rewiring substrates.

[0134] First, the inventors assumed a rewiring board model having the configuration of FIG. 1 and having a thickness of the rewiring board 100 (the distance between the first surface 101 and the second surface 102 in the thickness direction DT) of 40 μm as Example 11. The inventors also assumed a rewiring board model having the configuration of FIG. 24 and having a thickness of the rewiring board 100 (the distance between the first surface 101 and the second surface 102 in the thickness direction DT) of 65 μm as Example 12. Furthermore, the inventors assumed a rewiring board model having the configuration of FIG. 1 except that the thickness is 150 μm, that is, a rewiring board model in which the sum of the thickness of each of the multiple insulating layers (10, 20, 30) and the thickness of the conductor layer (11, 21, 31) formed on the insulating layer is greater than 30 μm as Comparative Example 11.

[0135] Then, when these rewiring board models were mounted on a mobile terminal, it was confirmed how the temperature in the vicinity of the rewiring board model would change. Fig. 26 is a schematic cross-sectional view showing the structure of a mobile terminal used in a simulation for evaluating the heat dissipation performance of the semiconductor element 200.

[0136] As shown in FIG. 26, the mobile terminal 900 has a configuration in which a rigid substrate 300A and a plurality of kinds of components 901 such as a battery are housed inside a casing 910. As shown in a partially enlarged view in a balloon in FIG. 26, a rewiring substrate 100 is connected to the rigid substrate 300A via a bonding member 390. A semiconductor element 200 is mounted on the rewiring substrate 100. The rewiring substrate 100 and the semiconductor element 200 constitute a semiconductor element mounting substrate 400. The bonding member 390 includes solder. The semiconductor element mounting substrate 400 is covered with a sealing resin 490. A heat dissipation countermeasure member 491 is further attached to the sealing resin 490. The heat dissipation countermeasure member 491 is in contact with some of the plurality of kinds of components 901 housed inside the casing 910.

[0137] In the following description, a predetermined point located at the connection portion between rigid board 300A and semiconductor element mounting board 400 is referred to as attention point tp. Assuming that mobile terminal 900 in Fig. 26 is equipped with semiconductor element mounting board 400 including the rewiring board model of Example 11, the temperature change of attention point tp during a certain period after a specific program is started in mobile terminal 900 is calculated by simulation.

[0138] In addition, assuming that the mobile terminal 900 in Figure 26 is equipped with a semiconductor element mounting board 400 including the rewiring board model of Example 12, the temperature change of the target point tp during a certain period of time after a specific program is started on the mobile terminal 900 is calculated by simulation.

[0139] Furthermore, assuming that the mobile terminal 900 in Figure 26 is equipped with a semiconductor element mounting substrate 400 including the rewiring substrate model of Comparative Example 11, the temperature change of the target point tp during a certain period of time after a specific program is started on the mobile terminal 900 is calculated by simulation.

[0140] Fig. 27 is a diagram showing a number of simulation results for evaluating the heat dissipation performance of the semiconductor device 200. In Fig. 27, a number of simulation results are shown in a graph. In the graph of Fig. 27, the vertical axis represents the temperature at the point of interest tp in Fig. 26, and the horizontal axis represents time. Point 0 on the horizontal axis is the start time of a specific program.

[0141] The simulation results corresponding to the rewiring substrate model of Example 11 are shown by black circles and solid lines. The simulation results corresponding to the rewiring substrate model of Comparative Example 11 are shown by triangles and dotted lines. The simulation results corresponding to the rewiring substrate model of Example 12 were almost identical to the simulation results corresponding to the rewiring substrate model of Example 11 to such an extent that the difference could not be shown on the graph of FIG. 27. Therefore, the simulation results corresponding to the rewiring substrate model of Example 12 are omitted from the illustration.

[0142] According to the simulation results corresponding to the rewiring board models of Examples 11 and 12, the temperature of the attention point tp reaches 50° C. after 160 seconds have elapsed since the specific program was started. In contrast, according to the simulation results corresponding to the rewiring board model of Comparative Example 11, the temperature of the attention point tp reaches 50° C. after 140 seconds have elapsed since the specific program was started.

[0143] As a result, it was confirmed that the temperature of the attention point tp is less likely to rise in the semiconductor element mounting board 400 including the rewiring board model of Examples 11 and 12 compared to the semiconductor element mounting board 400 including the rewiring board model of Comparative Example 11. That is, it was confirmed that the heat dissipation performance of the semiconductor element 200 is improved in the semiconductor element mounting board 400 including the rewiring board model of Examples 11 and 12 compared to the semiconductor element mounting board 400 including the rewiring board model of Comparative Example 11.

[0144] 9. Summary of the embodiment (1) The printed circuit board according to paragraph 1 is A wired circuit board having a first surface and a second surface facing in opposite directions in a thickness direction, A plurality of insulating layers including a first insulating layer, which are stacked in the thickness direction; a plurality of conductor layers formed on any one of the plurality of insulating layers; a first connected portion and a second connected portion configured to be connectable to a connection terminal of an electrical element; the first connected portion is formed on the first surface so as to be electrically connected to the plurality of conductor layers and exposed in a direction toward which the first surface faces; the second connected portion is formed on the second surface so as to be electrically connected to the plurality of conductor layers and exposed in a direction toward the second surface; the plurality of conductor layers includes a first conductor layer formed on the first insulating layer; The sum of the thickness of the portion of the first insulating layer where the first conductor layer is formed and the thickness of the first conductor layer is 30 μm or less.

[0145] In the wired circuit board, a connection terminal of the electrical element can be connected to a first connected portion on the first surface, and a connection terminal of the electrical element can be connected to a second connected portion on the second surface, making it easy to mount the electrical element on the wired circuit board.

[0146] Furthermore, according to the above configuration, the overall thickness of the wired circuit board can be made smaller than when the sum of the thickness of the portion of the first insulating layer where the first conductor layer is formed and the thickness of the first conductor layer is greater than 30 μm, thereby realizing a thinner wired circuit board.

[0147] As a result, it becomes easier to manufacture a wired circuit board and an electrical component mounting board including electrical components, while reducing the impedance of the wiring formed by the first conductor layer and ensuring high heat dissipation for the mounted electrical components.

[0148] (2) In the printed circuit board according to the first aspect, the electrical element includes a first electrical element and a second electrical element that are separated from each other; The printed circuit board may be a rewiring board used to electrically connect the first electrical element and the second electrical element.

[0149] Each of the first and second electric elements is, for example, an electronic component such as a semiconductor element or a rigid printed wiring circuit board, and has a plurality of connection terminals. According to the above configuration, the wiring circuit board serves as a rewiring board and converts the pitch between the plurality of connection terminals of the first electric element and the pitch between the plurality of connection terminals of the second electric element.

[0150] (Item 3) In the wired circuit board according to item 1 or 2, the plurality of insulating layers includes a second insulating layer and a third insulating layer; the plurality of conductor layers include a second conductor layer formed on the second insulating layer and a third conductor layer formed on the third insulating layer; the sum of a thickness of the portion of the second insulating layer on which the second conductor layer is formed and a thickness of the second conductor layer is 30 μm or less; The sum of a thickness of the portion of the third insulating layer on which the third conductor layer is formed and a thickness of the third conductor layer may be 30 μm or less.

[0151] In this case, the thickness of the printed circuit board having a configuration in which three or more insulating layers are laminated can be reduced.

[0152] (Item 4) In the wired circuit board according to any one of items 1 to 3, The plurality of insulating layers include a plurality of base insulating layers arranged in a stacked manner, the plurality of conductor layers are formed on the plurality of base insulating layers, respectively; The sum of the thickness of each of the plurality of insulating base layers and the thickness of the conductor layer formed on the insulating base layer may be 30 μm or less.

[0153] In this case, the printed circuit board can be made even thinner.

[0154] (5) In the printed circuit board according to the fourth aspect, The plurality of insulating layers includes a cover insulating layer formed on the plurality of base insulating layers arranged in a stacked manner, The insulating cover layer may have a thickness of 3 μm or more and 15 μm or less.

[0155] In this case, the printed circuit board can be made even thinner.

[0156] (Item 6) In the wired circuit board according to any one of items 1 to 5, The thickness of each of the plurality of insulating layers is 3 μm or more and 15 μm or less, The thickness of each of the plurality of conductor layers may be not less than 3 μm and not more than 15 μm.

[0157] In this case, the printed circuit board can be made even thinner.

[0158] (Item 7) In the wired circuit board according to any one of items 1 to 6, The insulating layers may be made of a photosensitive material.

[0159] In this case, the insulating layers can be easily patterned by selectively exposing the photosensitive material that constitutes each insulating layer to light, which eliminates the need for a process for removing residues that is required in laser processing or the like when forming through holes or the like in each insulating layer, thereby reducing the number of processes required for manufacturing the wired circuit board.

[0160] (Item 8) In the wired circuit board according to item 1 or 2, The semiconductor device may further include a metal support for supporting the plurality of insulating layers and the plurality of conductor layers.

[0161] In this case, the insulating layers and the conductor layers are reinforced by the metal support having high rigidity, thereby improving the reliability of the wired circuit board.

[0162] In addition, the metal support has a higher thermal conductivity than the insulating layer, and therefore, when an electrical component is mounted on the wiring circuit board, the metal support is more likely to receive heat generated by the electrical component, and therefore functions as a heat dissipation member for the electrical component.

[0163] (Item 9) In the printed circuit board according to item 8, the plurality of insulating layers includes a second insulating layer; the plurality of conductor layers includes a second conductor layer formed on the second insulating layer; The metal support may be located between the first insulating layer and the first conductor layer and the second insulating layer and the second conductor layer in the thickness direction.

[0164] In this case, the insulating layers and the conductor layers are reinforced by the metal support, thereby improving the reliability of the printed circuit board.

[0165] (Item 10) In the wired circuit board according to item 8 or 9, The thermal conductivity of the metal support may be 10 W / mK or more and 250 W / mK or less.

[0166] In this case, the metal support effectively functions as a heat dissipation member for the electrical elements mounted on the printed circuit board.

[0167] (Item 11) In the wired circuit board according to any one of items 8 to 10, The metal support may have a linear expansion coefficient of 0 ppm / K or more and 25 ppm / K or less at 25° C. or more and 200° C. or less.

[0168] In this case, the metal support is prevented from being significantly deformed due to changes in temperature of the printed circuit board, thereby improving the reliability of the printed circuit board.

[0169] (Item 12) In the wired circuit board according to any one of items 8 to 11, The metal support may be formed from any of stainless steel, copper, copper alloys, aluminum, titanium, or alloys containing iron and nickel.

[0170] Thereby, the insulating layers and the conductive layers are supported by a metal support formed from either stainless steel, copper, a copper alloy, aluminum, titanium, or an alloy containing iron and nickel.

[0171] (Clause 13) The electrical component mounting board according to Clause 13 is A wired circuit board according to any one of items 1 to 12, an electrical element having a connection terminal and mounted on the first surface of the printed circuit board; a joining member that joins the connection terminal of the electric element to the first connected portion or the second connected portion of the wired circuit board, The electrical element comprises: an opposing surface that faces the wired circuit board when mounted on the wired circuit board; Further, the columnar joint is formed so as to protrude from the opposing surface by a certain length, The connection terminal is formed at the tip of the columnar joint.

[0172] When the electric element mounting board is manufactured, the opposing surface of the electric element can be arranged to face the first surface of the wiring circuit board, and the connection terminal of the electric element can be connected to the first connected portion of the wiring circuit board. Alternatively, the opposing surface of the electric element can be arranged to face the second surface of the wiring circuit board, and the connection terminal of the electric element can be connected to the second connected portion of the wiring circuit board. In this case, since the connection terminal of the electric element is formed at the tip of the columnar joint, the connection work is easier than when the connection terminal is formed on a flat surface. In addition, the reliability of the connection using the joint member is improved.

[0173] Furthermore, an electric component mounting board includes the above-mentioned wired circuit board. As a result, the electric component mounting board can be easily manufactured, and the impedance of the wiring formed by the first conductor layer can be reduced and the heat dissipation of the mounted electric components can be ensured.

[0174] (14) In the electrical component mounting board according to the 13th aspect, The bonding material may include solder, in which case a highly reliable electrical component mounting board can be produced using a general-purpose bonding material.

[0175] (Item 15) A method for producing a printed circuit board according to item 15 includes the steps of: A method for manufacturing a wired circuit board having a first surface and a second surface facing in opposite directions in a thickness direction, comprising: forming a plurality of insulating layers including a first insulating layer, the insulating layers being stacked in the thickness direction; forming a plurality of conductor layers on any one of the plurality of insulating layers; forming a first connected portion on the first surface to which a connection terminal of an electrical element can be connected, the first connected portion being electrically connected to the plurality of conductor layers and exposed in a direction in which the first surface faces; forming the second connected portion on the second surface, the second connected portion being electrically connected to the plurality of conductor layers and exposed in a direction in which the second surface faces, and to which a connection terminal of an electrical element can be connected; the plurality of conductor layers includes a first conductor layer formed on the first insulating layer; The sum of the thickness of the portion of the first insulating layer where the first conductor layer is formed and the thickness of the first conductor layer is 30 μm or less.

[0176] In the wired circuit board produced by the above manufacturing method, a connection terminal of an electrical element can be connected to a first connected portion on a first surface. Also, a connection terminal of an electrical element can be connected to a second connected portion on a second surface. Therefore, it is easy to mount an electrical element on the wired circuit board.

[0177] Furthermore, according to the above configuration, the overall thickness of the wired circuit board can be made smaller than when the sum of the thickness of the portion of the first insulating layer where the first conductor layer is formed and the thickness of the first conductor layer is greater than 30 μm, thereby realizing a thinner wired circuit board.

[0178] As a result, it becomes easier to manufacture a wired circuit board and an electrical component mounting board including electrical components, while reducing the impedance of the wiring formed by the first conductor layer and ensuring the heat dissipation of the mounted electrical components.

[0179] (Item 16) In the method for producing a printed circuit board according to item 15, The insulating layers may be made of a photosensitive material.

[0180] In this case, the insulating layers can be easily patterned by selectively exposing the photosensitive material that constitutes each insulating layer to light, which eliminates the need for a process for removing residues that is required in laser processing or the like when forming through holes or the like in each insulating layer, thereby reducing the number of processes required for manufacturing the wired circuit board.

[0181] (Item 17) A method for manufacturing an electrical component mounting board according to item 17 includes the steps of: A step of producing the printed circuit board by the manufacturing method according to item 15 or 16; and mounting an electrical element having a connection terminal on the first surface of the wired circuit board produced by the manufacturing method. The mounting step includes: using a joining member to join the connection terminal of the electrical element and the first connected portion of the wired circuit board; The electrical element comprises: an opposing surface that faces the wired circuit board when mounted on the wired circuit board; A columnar joint formed to protrude a certain length from the opposing surface, The connection terminal is formed at the tip of the columnar joint.

[0182] When the electric element mounting board is manufactured, the opposing surface of the electric element can be arranged to face the first surface of the wiring circuit board, and the connection terminal of the electric element can be connected to the first connected portion of the wiring circuit board. Alternatively, the opposing surface of the electric element can be arranged to face the second surface of the wiring circuit board, and the connection terminal of the electric element can be connected to the second connected portion of the wiring circuit board. In this case, since the connection terminal of the electric element is formed at the tip of the columnar joint, the connection work is easier than when the connection terminal is formed on a flat surface. In addition, the reliability of the connection using the joint member is improved.

[0183] Furthermore, an electric component mounting board includes the above-mentioned wired circuit board. As a result, the electric component mounting board can be easily manufactured, and the impedance of the wiring formed by the first conductor layer can be reduced and the heat dissipation of the mounted electric components can be ensured. [Explanation of symbols]

[0184] 1...metal support, 1a...upper surface, 1b...lower surface, 10,50...first insulating layer, 11,111...first conductor layer, 11a,21a,31a,61a,71a,111a...via portion, 11b,21b,31b,61b,71b,111b,111c...wiring portion, 20,60...second insulating layer, 21,61...second conductor layer, 30,70...third insulating layer, 31,71...third conductor layer, 40,80...fourth insulating layer, 100...rewiring board, 101...first surface, 102...second surface, 110...metal support, 110a...upper surface, 110b...lower surface, 120...coating layer, 200...semiconductor element, 211...opposing surface, 220...columnar joint , 290, ... underfill, 300, 300A ... rigid substrate, 301 ... electrode pad, 390 ... bonding member, 400 ... semiconductor element mounting substrate, 490 ... sealing resin, 491 ... heat dissipation countermeasure member, 500 ... roll-to-roll device, 501 ... unwinding section, 502 ... winding section, 510, 520 ... processing section, 900 ... mobile terminal, 901 ... component, DT ... thickness direction, PL ... plating layer, R1 ... unwinding roll, R2 ... winding roll, S ... solder, SL ... seed layer, T1, T2 ... terminal section, h11, h21, h31, h41, h111 ... through hole, p1 ... first part, p2 ... second part, tp ... attention point, v11 ... vertical hole

Claims

1. A printed circuit board having a first surface and a second surface facing in opposite directions in a thickness direction, a plurality of insulating layers including a first insulating layer, stacked in the thickness direction; a plurality of conductor layers formed on any one of the plurality of insulating layers; a first connected portion and a second connected portion configured to be connectable to a connection terminal of an electrical element; the first connected portion is electrically connected to the plurality of conductor layers and is formed on the first surface so as to be exposed in a direction in which the first surface faces; the second connected portion is electrically connected to the plurality of conductor layers and is formed on the second surface so as to be exposed in a direction toward the second surface; the plurality of conductor layers includes a first conductor layer formed on the first insulating layer; a total thickness of the portion of the first insulating layer where the first conductor layer is formed and the thickness of the first conductor layer is 30 μm or less;

2. the electrical element includes a first electrical element and a second electrical element that are separated from each other; 2. The printed circuit board according to claim 1, wherein the printed circuit board is a rewiring board used to electrically connect the first electrical element and the second electrical element.

3. the plurality of insulating layers include a second insulating layer and a third insulating layer; the plurality of conductor layers include a second conductor layer formed on the second insulating layer and a third conductor layer formed on the third insulating layer; the sum of the thickness of the portion of the second insulating layer where the second conductor layer is formed and the thickness of the second conductor layer is 30 μm or less; 3. The printed circuit board according to claim 1, wherein the sum of the thickness of the portion of said third insulating layer where said third conductor layer is formed and the thickness of said third conductor layer is 30 [mu]m or less.

4. the plurality of insulating layers include a plurality of base insulating layers arranged in a stack; the plurality of conductor layers are formed on the plurality of insulating base layers, respectively; 3. The wired circuit board according to claim 1, wherein the sum of the thickness of each of said insulating base layers and the thickness of the conductor layer formed on said insulating base layer is 30 [mu]m or less.

5. the plurality of insulating layers includes an insulating cover layer formed on the plurality of insulating base layers arranged in a stacked manner; 5. The printed circuit board according to claim 4, wherein the insulating cover layer has a thickness of 3 [mu]m or more and 15 [mu]m or less.

6. the thickness of each of the plurality of insulating layers is 3 μm or more and 15 μm or less; 3. The printed circuit board according to claim 1, wherein each of said plurality of conductor layers has a thickness of 3 [mu]m or more and 15 [mu]m or less.

7. 3. The printed circuit board according to claim 1, wherein said plurality of insulating layers are made of a photosensitive material.

8. The printed circuit board according to claim 1 , further comprising a metal support for supporting said insulating layers and said conductive layers.

9. the plurality of insulating layers includes a second insulating layer; the plurality of conductor layers includes a second conductor layer formed on the second insulating layer; 9. The printed circuit board according to claim 8, wherein the metal support is located between the first insulating layer and the first conductor layer and the second insulating layer and the second conductor layer in the thickness direction.

10. 9. The printed circuit board according to claim 8, wherein the thermal conductivity of the metal support is 10 W / mK or more and 250 W / mK or less.

11. 9. The wired circuit board according to claim 8, wherein the metal support has a linear expansion coefficient of 0 ppm / K or more and 25 ppm / K or less at 25°C or more and 200°C or less.

12. 9. The printed circuit board according to claim 8, wherein said metal support is formed from any one of stainless steel, copper, a copper alloy, aluminum, titanium, and an alloy containing iron and nickel.

13. The wired circuit board according to claim 1 or 2; an electrical element having a connection terminal and mounted on the first surface of the printed circuit board; a joining member that joins the connection terminal of the electrical element to the first connected portion or the second connected portion of the wired circuit board, The electrical element is an opposing surface that faces the printed circuit board when mounted on the printed circuit board; Further, a columnar joint portion formed to protrude from the opposing surface by a certain length, The connection terminal is formed at the tip of the columnar joint.

14. The electrical component mounting board according to claim 13 , wherein the joining member includes solder.

15. A method for manufacturing a wired circuit board having a first surface and a second surface facing in opposite directions in a thickness direction, comprising: forming a plurality of insulating layers including a first insulating layer, the insulating layers being stacked in the thickness direction; forming a plurality of conductor layers on any one of the plurality of insulating layers; forming a first connection portion on the first surface, the first connection portion being electrically connected to the plurality of conductor layers and being exposed in a direction in which the first surface faces, and to which a connection terminal of an electrical element can be connected; forming the second connected portion on the second surface, the second connected portion being electrically connected to the plurality of conductor layers and being exposed in the direction in which the second surface faces, and to which a connection terminal of an electrical element can be connected; the plurality of conductor layers includes a first conductor layer formed on the first insulating layer; a total thickness of the portion of the first insulating layer where the first conductor layer is formed and the thickness of the first conductor layer is 30 μm or less;

16. The method for manufacturing a printed circuit board according to claim 15, wherein the plurality of insulating layers are made of a photosensitive material.

17. a step of producing the printed circuit board by the manufacturing method according to claim 15; and mounting an electrical element having a connection terminal on the first surface of the wired circuit board produced by the manufacturing method. The mounting step includes: using a joining member to join the connection terminal of the electrical element and the first connected portion of the wired circuit board; The electrical element is an opposing surface that faces the printed circuit board when mounted on the printed circuit board; A columnar joint portion formed to protrude a certain length from the opposing surface, The method for manufacturing an electrical component mounting board, wherein the connection terminal is formed from a tip end of the columnar joint.

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