Display device and electronic apparatus

Abstract

To provide a display device and an electronic apparatus capable of suppressing a decline in display quality.SOLUTION: The display device comprises: a scan line; a first data line and a second data line; a first transistor circuit; a second transistor circuit; a first light-emitting element including a first pixel electrode; and a second light-emitting element including a second pixel electrode. The first transistor circuit has a first driving transistor and a first selection transistor. The second transistor circuit has a second driving transistor and a second selection transistor. The first pixel electrode and the second pixel electrode are arranged in a second direction, and the first transistor circuit and the second transistor circuit are arranged in a first direction. A gate included in the first selection transistor and a gate included in the second selection transistor are electrically connected to the scan line.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a display device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art There are known display devices such as liquid crystal display devices and organic electroluminescence display devices. One example of such a device is an organic EL display device described in Patent Document 1.

[0003] In the organic EL display device of Patent Document 1, a plurality of sub-pixels are grouped together to form one rectangular pixel, and the pixels are arranged in a matrix. Each sub-pixel is provided at an intersection of a data line extending in the column direction and a scanning line extending in the row direction. An anode electrode of a light-emitting element, a switching transistor, and a driving transistor are provided in the region of each sub-pixel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-75868 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the display device of Patent Document 1, when the number of sub-pixels is increased to achieve higher resolution, the number of sub-pixels corresponding to one scanning line increases. This reduces one horizontal scanning period. As a result, there is a problem that the display quality is degraded. Furthermore, as the driving frame rate increases, this problem becomes more pronounced. [Means for solving the problem]

[0006] In order to achieve the above object, a display device according to a preferred embodiment of the present invention includes a scanning line extending in a first direction, a first data line and a second data line extending in a second direction intersecting the first direction and aligned in the first direction, a first transistor circuit, a second transistor circuit, a first light-emitting element including a first pixel electrode, and a second light-emitting element including a second pixel electrode, the first transistor circuit including a first drive transistor supplying a first drive current to the first pixel electrode based on a potential corresponding to a first video signal from the first data line, and a first selection transistor electrically connecting the first data line and the first drive transistor. the second transistor circuit has a second drive transistor that supplies to the second pixel electrode a second drive current based on a potential corresponding to a second video signal from the second data line, and a second selection transistor that electrically connects the second data line and the second drive transistor, the first pixel electrode and the second pixel electrode are aligned in the second direction, the first transistor circuit and the second transistor circuit are aligned in the first direction, and a gate of the first selection transistor and a gate of the second selection transistor are electrically connected to the scanning line. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a display device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram illustrating the display device of FIG. [Diagram 3] FIG. 2 is a diagram showing any two pixels among the plurality of pixels in FIG. [Figure 4] FIG. 4 is a layout diagram of six transistor circuits corresponding to the six display pixels shown in FIG. 3. [Diagram 5] FIG. 5 is a diagram showing the six transistor circuits of FIG. [Figure 6] FIG. 11 is a diagram showing one pixel according to the second embodiment. [Figure 7] FIG. 7 is a layout diagram of four transistor circuits corresponding to the four display pixels of FIG. 6. [Figure 8]FIG. 13 is a diagram showing one pixel according to the third embodiment. [Figure 9] FIG. 9 is a layout diagram of two transistor circuits corresponding to the two display pixels of FIG. 8. [Figure 10] FIG. 1 is a perspective view showing the appearance of a head mounted display as an electronic device equipped with a display device. [Figure 11] FIG. 11 is a diagram showing an optical configuration of the head mounted display shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual ones, and some parts are shown diagrammatically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0009] A. First embodiment 1. Basic configuration of display device 1 FIG. 1 is a diagram showing a display device 1 according to a first embodiment. The display device 1 shown in FIG. 1 is, for example, a microdisplay that displays an image in a head mounted display. The display device 1 is, for example, an organic EL device including an OLED. OLED is an abbreviation for Organic Light Emitting Diode. EL is an abbreviation for Electroluminescence. In this embodiment, the display device 1 is capable of displaying a full-color image. The image includes an image that displays only text information. The display device 1 may also be a device that is capable of displaying only a single color.

[0010] The display device 1 has a display panel 10 that displays an image, and is housed in a frame-shaped case 71 that opens at the display panel 10. One end of an FPC board 72 is connected to the display device 1. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 72 is provided with a plurality of terminals 73 for connecting to a host device (not shown). When the plurality of terminals 73 are connected to the host device, various signals are supplied to the display device 1 from the host device via the FPC board 72.

[0011] 2. Configuration of Display Device 1 2 is a diagram showing a schematic diagram of the display device 1 of FIG. 1. For convenience of explanation, the following description will be given using the X direction and the Y direction as appropriate. An axis along the X direction and an axis along the Y direction are perpendicular to each other. The X direction is the "first direction" and the "row direction", and the Y direction is the "second direction" and the "column direction".

[0012] 2, the display device 1 includes a display panel 10, a control circuit 130, a scanning line driving circuit 110, and a data line driving circuit 120. The display panel 10, the control circuit 130, the scanning line driving circuit 110, and the data line driving circuit 120 are formed on a semiconductor substrate such as a silicon substrate.

[0013] The display panel 10 is provided with m scanning lines 11 extending in the X direction and n data lines 12 extending in the Y direction. A plurality of display pixels P0 are provided corresponding to intersections of the plurality of scanning lines 11 and the plurality of data lines 12. Note that, for example, a pixel P that expresses one dot of a color image is configured for every three display pixels P0 aligned in the X direction. In this embodiment, the pixels P are arranged in a so-called RGB stripe arrangement. Further, each display pixel P0 is provided with a pixel electrode 151 of a light-emitting element 15 described later.

[0014] The control circuit 130 controls the display of an image. Digital video data Video output from a host device (not shown) is supplied to the control circuit 130 shown in FIG. 2 in synchronization with a synchronization signal Sync. The control circuit 130 controls each part of the display device 1 based on the video data Video and the synchronization signal Sync. The video data Video specifies the gradation level of the display pixel P0 in the image to be displayed, for example, in 8 bits. The synchronization signal Sync is a signal including a vertical synchronization signal that instructs the start of vertical scanning of the video data Video, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal.

[0015] The control circuit 130 generates a control signal Ctr1 based on the synchronization signal Sync and supplies the control signal Ctr1 to the scanning line driving circuit 110, and also generates a control signal Ctr2 based on the synchronization signal Sync and supplies the control signal Ctr2 to the data line driving circuit 120. Each of the control signals Ctr1 and Ctr2 includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.

[0016] Furthermore, the control circuit 130 generates video data Vid based on the video data Video, and supplies the video data Vid to the data line driving circuit 120. The luminance characteristics of the gradation level indicated by the video data Vid and the light-emitting element 15 described below may not match. Therefore, in order to cause the light-emitting element 15 to emit light at a luminance corresponding to the gradation level indicated by the video data Video, the control circuit 130 generates video data Vid by changing the 8 bits of the video data Video to 10 bits, for example.

[0017] The control circuit 130 receives power from a power supply circuit (not shown), and supplies a power supply potential to the scanning line driving circuit 110, the data line driving circuit 120, and a plurality of transistor circuits 20 (described later) included in the display panel 10.

[0018] The scanning line driving circuit 110 generates a scanning signal Gwr based on a control signal Ctr1. The scanning signal Gwr is a signal for selecting and scanning the m rows of scanning lines 11 in sequence for every predetermined number of rows in each frame period V. The scanning line driving circuit 110 sequentially and exclusively selects one or more scanning lines 11 from the m rows of scanning lines 11 for each horizontal scanning period H included in each frame period V, and selects a display pixel P0 to which a video signal Vd is written from among the multiple display pixels P0. In FIG. 2, the scanning signals Gwr supplied to the 1st, 2nd, 3rd, ..., mth rows of scanning lines 11 are denoted as Gwr_1, Gwr_2, Gwr_3, ..., Gwr_m.

[0019] The frame period V mentioned above refers to a period required for the display device 1 to display one frame of an image. For example, the length of the frame period V is 1 / 60 seconds when the driving frame rate is 60 Hz. One frame period V includes a horizontal scanning period H and a light emission period corresponding to each row. The light emission period is a period during which the light emitting element 15 emits light. One horizontal scanning period H is a period required for horizontal scanning of one row. One horizontal scanning period H includes a write period during which the video signal Vd is written to the display pixel P0. The number of selected scanning lines 11 in one horizontal scanning period H is not limited to one row, and may be two or more rows.

[0020] The data line driving circuit 120 supplies a video signal Vd to a transistor circuit 20 (to be described later) corresponding to a display pixel P0 provided in a row selected by the scanning line driving circuit 110. In addition, in Fig. 2, the video signals Vd supplied to the data lines 12 in the 1st, 2nd, 3rd, ..., nth rows are represented as Vd_1, Vd_2, Vd_3, ..., Vd_n.

[0021] 3. Arrangement of display pixel P0 Fig. 3 is a diagram showing two arbitrary pixels P among the plurality of pixels P in Fig. 1. Fig. 3 shows two arbitrary pixels P among the plurality of pixels P. One pixel P is a first pixel P1, and the other pixel P is a second pixel P2. The second pixel P2 is provided in the Y direction with respect to the first pixel P1.

[0022] Each of the first pixel P1 and the second pixel P2 has three display pixels P0. Specifically, the first pixel P1 has a first display pixel Pa, a third display pixel Pc, and a fifth display pixel Pe. The first display pixel Pa, the third display pixel Pc, and the fifth display pixel Pe are aligned in the X direction. The second pixel P2 has a second display pixel Pb, a fourth display pixel Pd, and a sixth display pixel Pf. The second display pixel Pb, the fourth display pixel Pd, and the sixth display pixel Pf are aligned in the X direction. The first display pixel Pa and the second display pixel Pb emit light in, for example, a red wavelength region. The third display pixel Pc and the fourth display pixel Pd emit light in, for example, a green wavelength region. The fifth display pixel Pe and the sixth display pixel Pf emit light in, for example, a blue wavelength region.

[0023] Each display pixel P0 is provided with a pixel electrode 151. Just as the plurality of display pixels P0 are arranged in a matrix, the plurality of pixel electrodes 151 are also arranged in a matrix. Although not shown, each display pixel P0 is provided with a light-emitting region having substantially the same planar area and substantially the same shape in a plan view as the pixel electrode 151. Light is emitted from the light-emitting region.

[0024] The first display pixel Pa is provided with a first pixel electrode 151a. The third display pixel Pc is provided with a third pixel electrode 151c. The fifth display pixel Pe is provided with a fifth pixel electrode 151e. The second display pixel Pb is provided with a second pixel electrode 151b. The fourth display pixel Pd is provided with a fourth pixel electrode 151d. The fifth display pixel Pe is provided with a fifth pixel electrode 151e. The sixth display pixel Pf is provided with a sixth pixel electrode 151f.

[0025] The third pixel electrode 151c is provided in the X direction with respect to the first pixel electrode 151a. The fifth pixel electrode 151e is provided in the X direction with respect to the third pixel electrode 151c. The second pixel electrode 151b is provided in the Y direction with respect to the first pixel electrode 151a. The fourth pixel electrode 151d is provided in the Y direction with respect to the third pixel electrode 151c, and is provided in the X direction with respect to the second pixel electrode 151b. The sixth pixel electrode 151f is provided in the Y direction with respect to the fifth pixel electrode 151e, and is provided in the X direction with respect to the fourth pixel electrode 151d.

[0026] 4. Layout of transistor circuit 20 Fig. 4 is a layout diagram of six transistor circuits 20 corresponding to the six display pixels P0 shown in Fig. 3. In Fig. 4, the six transistor circuits 20 are a first transistor circuit 20a, a second transistor circuit 20b, a third transistor circuit 20c, a fourth transistor circuit 20d, a fifth transistor circuit 20e, and a sixth transistor circuit 20f.

[0027] The first transistor circuit 20a corresponds to the first display pixel Pa. The second transistor circuit 20b corresponds to the second display pixel Pb. The third transistor circuit 20c corresponds to the third display pixel Pc. The fourth transistor circuit 20d corresponds to the fourth display pixel Pd. The fifth transistor circuit 20e corresponds to the fifth display pixel Pe. The sixth transistor circuit 20f corresponds to the sixth display pixel Pf.

[0028] The first transistor circuit 20a, the second transistor circuit 20b, the third transistor circuit 20c, the fourth transistor circuit 20d, the fifth transistor circuit 20e, and the sixth transistor circuit 20f are arranged in this order in the X direction.

[0029] Although not shown in detail, the first transistor circuit 20a and the second transistor circuit 20b overlap the first display pixel Pa and the second display pixel Pb in a plan view. This arrangement prevents the electrical connection path between the first transistor circuit 20a and the first pixel electrode 151a from becoming excessively long and complicated. The same applies to the second transistor circuit 20b. A plan view refers to a view from a direction perpendicular to both the X direction and the Y direction.

[0030] Similarly, although not shown in detail, the third transistor circuit 20c and the fourth transistor circuit 20d overlap the third display pixel Pc and the fourth display pixel Pd in ​​a plan view. This arrangement prevents the electrical connection path between the third transistor circuit 20c and the third pixel electrode 151c from becoming excessively long and complicated. The same applies to the fourth transistor circuit 20d. The fifth transistor circuit 20e and the sixth transistor circuit 20f overlap the fifth display pixel Pe and the sixth display pixel Pf in a plan view. This arrangement prevents the electrical connection path between the fifth transistor circuit 20e and the fifth pixel electrode 151e from becoming excessively long and complicated. The same applies to the sixth transistor circuit 20f.

[0031] 5. Configuration of transistor circuit 20 Fig. 5 is a diagram showing the six transistor circuits 20 of Fig. 4. As shown in Fig. 5, the first transistor circuit 20a includes a first light emitting element 15a, a first driving transistor 16a, a first selection transistor 17a, and a first capacitance element 18a.

[0032] The first light emitting element 15a includes a first pixel electrode 151a, a common electrode 152, and a light emitting layer 153. The common electrode 152 is common to the first to sixth light emitting elements 15a to 15f. The light emitting layer 153 is common to the first to sixth light emitting elements 15a to 15f, but may be individual.

[0033] The first light-emitting element 15a is disposed on a path connecting the first constant potential wiring 13p and the second constant potential wiring 14p. A high-side potential Vel is supplied to the first constant potential wiring 13p from a power supply circuit (not shown). A low-side potential Vct is supplied to the second constant potential wiring 14p from the power supply circuit. The first light-emitting element 15a is, for example, an OLED. The light-emitting layer 153 includes a light-emitting material and is interposed between the first pixel electrode 151a and the common electrode 152. The first pixel electrode 151a functions as an anode electrode, and the common electrode 152 functions as a cathode electrode. In the first light-emitting element 15a, holes supplied from the first pixel electrode 151a and electrons supplied from the common electrode 152 are recombined in the light-emitting layer 153. The recombination causes the light-emitting layer 153 to emit light.

[0034] The first driving transistor 16a supplies the first pixel electrode 151a with a first driving current Ida based on a potential corresponding to a first video signal Vda supplied from a first data line 12a of the n data lines 12. The first driving transistor 16a is arranged in series with the first light-emitting element 15a. One of the source and the drain of the first driving transistor 16a is electrically connected to the first constant potential wiring 13p, and the other is electrically connected to the first pixel electrode 151a.

[0035] The first selection transistor 17a electrically connects the first data line 12a and the first drive transistor 16a. Specifically, the first selection transistor 17a functions as a switch that controls the conduction and non-conduction between the first data line 12a and the gate of the first drive transistor 16a. One of the source and the drain of the first selection transistor 17a is electrically connected to the first data line 12a, and the other is electrically connected to the gate of the first drive transistor 16a. The gate of the first selection transistor 17a is electrically connected to any one of the m scanning lines 11, i.e., a scanning line 11p.

[0036] The second to sixth transistor circuits 20b to 20f will be described below, but descriptions of the same points as those of the first transistor circuit 20a will be omitted as appropriate.

[0037] The second transistor circuit 20b has a second light emitting element 15b, a second driving transistor 16b, a second selection transistor 17b, and a second capacitance element 18b. The second light emitting element 15b includes a second pixel electrode 151b, a common electrode 152, and a light emitting layer 153. The second driving transistor 16b supplies a second driving current Idb based on a potential corresponding to a second video signal Vdb supplied from a second data line 12b to the second pixel electrode 151b. The second selection transistor 17b electrically connects the second data line 12b of the n data lines 12 to the second driving transistor 16b. The gate of the second selection transistor 17b is electrically connected to the scanning line 11p.

[0038] The third transistor circuit 20c has a third light emitting element 15c, a third driving transistor 16c, a third selection transistor 17c, and a third capacitance element 18c. The third light emitting element 15c includes a third pixel electrode 151c, a common electrode 152, and a light emitting layer 153. The third driving transistor 16c supplies a third driving current Idc based on a potential corresponding to a third video signal Vdc supplied from a third data line 12c to the third pixel electrode 151c. The third selection transistor 17c electrically connects the third data line 12c of the n data lines 12 to the third driving transistor 16c. The gate of the third selection transistor 17c is electrically connected to the scanning line 11p.

[0039] The fourth transistor circuit 20d has a fourth light emitting element 15d, a fourth driving transistor 16d, a fourth selection transistor 17d, and a fourth capacitance element 18d. The fourth light emitting element 15d includes a fourth pixel electrode 151d, a common electrode 152, and a light emitting layer 153. The fourth driving transistor 16d supplies a fourth driving current Idd to the fourth pixel electrode 151d based on a potential corresponding to a fourth video signal Vdd supplied from the fourth data line 12d. The fourth selection transistor 17d electrically connects the fourth data line 12d of the n data lines 12 to the fourth driving transistor 16d. The gate of the fourth selection transistor 17d is electrically connected to the scanning line 11p.

[0040] The fifth transistor circuit 20e has a fifth light emitting element 15e, a fifth driving transistor 16e, a fifth selection transistor 17e, and a fifth capacitance element 18e. The fifth light emitting element 15e includes a fifth pixel electrode 151e, a common electrode 152, and a light emitting layer 153. The fifth driving transistor 16e supplies a fifth driving current Ide based on a potential corresponding to a fifth video signal Vde supplied from a fifth data line 12e to the fifth pixel electrode 151e. The fifth selection transistor 17e electrically connects a fifth data line 12e of the n data lines 12 to the fifth driving transistor 16e. The gate of the fifth selection transistor 17e is electrically connected to the scanning line 11p.

[0041] The sixth transistor circuit 20f has a sixth light emitting element 15f, a sixth driving transistor 16f, a sixth selection transistor 17f, and a sixth capacitance element 18f. The sixth light emitting element 15f includes a sixth pixel electrode 151f, a common electrode 152, and a light emitting layer 153. The sixth driving transistor 16f supplies a sixth driving current Idf based on a potential corresponding to a sixth video signal Vdf supplied from a sixth data line 12f to the sixth pixel electrode 151f. The sixth selection transistor 17f electrically connects a sixth data line 12f of the n data lines 12 to the sixth driving transistor 16f. The gate of the sixth selection transistor 17f is electrically connected to the scanning line 11p.

[0042] Note that the configuration of the transistor circuit 20 shown in Fig. 5 is just an example, and the transistor circuit 20 may have a configuration other than that shown in Fig. 5. For example, the first transistor circuit 20a may further include another transistor that controls conduction between the first pixel electrode 151a and the first driving transistor 16a.

[0043] As described above, the first pixel electrode 151a and the second pixel electrode 151b shown in FIG. 3 are aligned in the Y direction. On the other hand, the first transistor circuit 20a and the second transistor circuit 20b shown in FIG. 4 are aligned in the X direction. Therefore, the arrangement direction of the first transistor circuit 20a and the second transistor circuit 20b intersects with the arrangement direction of the first pixel electrode 151a and the second pixel electrode 151b. The gate of the first selection transistor 17a and the gate of the second selection transistor 17b shown in FIG. 5 are electrically connected to the same scanning line 11p. Note that one of the source or drain of the first selection transistor 17a and one of the source or drain of the second selection transistor 17b are electrically connected to different data lines 12.

[0044] Conventionally, the transistor circuits 20 are arranged in a matrix, similar to the arrangement of the pixel electrodes 151. Therefore, conventionally, when the first pixel electrode 151a and the second pixel electrode 151b are arranged in the Y direction, the first transistor circuit 20a and the second transistor circuit 20b are arranged in the Y direction. Therefore, the first transistor circuit 20a and the second transistor circuit 20b are electrically connected to different scanning lines 11. Conventionally, therefore, two scanning lines 11 are required to control the ON / OFF of the first selection transistor 17a and the second selection transistor 17b.

[0045] In contrast, in this embodiment, the first pixel electrode 151a and the second pixel electrode 151b are aligned in the Y direction, whereas the first transistor circuit 20a and the second transistor circuit 20b are aligned in the X direction. Therefore, the gate of the first selection transistor 17a and the gate of the second selection transistor 17b are electrically connected to the same scanning line 11p. Therefore, the scanning line 11p that controls the ON / OFF of the first selection transistor 17a and the second selection transistor 17b is common. Therefore, the scanning line 11, which is conventionally required to have two, is sufficient in this embodiment with one scanning line 11p. That is, the number of scanning lines 11 can be reduced to half compared to the conventional configuration. Therefore, one horizontal scanning period H can be twice as long as the conventional one horizontal scanning period H. Therefore, it is possible to suppress the deterioration of display quality caused by the shortening of one horizontal scanning period H. In particular, even if the driving frame rate is increased, it is possible to ensure one horizontal scanning period H that is sufficient to maintain display quality.

[0046] 3, the third pixel electrode 151c is provided in the X direction with respect to the first pixel electrode 151a. The fourth pixel electrode 151d is provided in the X direction with respect to the second pixel electrode 151b, and is provided in the Y direction with respect to the third pixel electrode 151c. The fifth pixel electrode 151e is provided in the X direction with respect to the third pixel electrode 151c. The sixth pixel electrode 151f is provided in the X direction with respect to the fourth pixel electrode 151d, and is provided in the Y direction with respect to the fifth pixel electrode 151e. Therefore, the first to sixth pixel electrodes 151a to 151f are arranged in two rows and three columns.

[0047] As shown in FIG. 4, the third transistor circuit 20c, the fourth transistor circuit 20d, the fifth transistor circuit 20e, and the sixth transistor circuit 20f are arranged in the X direction, which is the same as the direction in which the scanning line 11p extends. Therefore, the first to sixth transistor circuits 20a to 29f are arranged in one row and six columns. The gate of the third selection transistor 17c, the gate of the fourth selection transistor 17d, the gate of the fifth selection transistor 17e, and the gate of the sixth selection transistor 17f are electrically connected to the scanning line 11p. Therefore, the gates of the first to sixth selection transistors 17a to 17f are electrically connected to the scanning line 11p. Therefore, the scanning line 11p that controls the ON / OFF of the first to sixth selection transistors 17a to 17f of the first to sixth transistor circuits 20a to 20f is common. Either the source or the drain of each of the first to sixth selection transistors 17a to 17f is electrically connected to different data lines 12.

[0048] According to this embodiment, six display pixels P0 are arranged in two rows and three columns, while six transistor circuits 20 are arranged in one row and six columns. Therefore, the number of transistor circuits 20 arranged in the column direction can be halved compared to the number of pixel electrodes 151 arranged in the column direction. In other words, the number of transistor circuits 20 arranged in the column direction can be halved compared to the number of display pixels P0 arranged. Therefore, as described above, one horizontal scanning period H can be secured to be twice as long as the conventional one horizontal scanning period H. Therefore, deterioration of display quality can be suppressed.

[0049] The first pixel electrode 151a, the third pixel electrode 151c, and the fifth pixel electrode 151e constitute a first pixel P1 that constitutes one dot of color display. The second pixel electrode 151b, the fourth pixel electrode 151d, and the sixth pixel electrode 151f constitute a second pixel P2 that constitutes another dot of color display. Thus, the transistor circuits 20 of two pixels P arranged in a column direction are arranged in a row direction. The gates of the transistor circuits 20 of two pixels P arranged in a column direction are electrically connected to one scanning line 11p. With this configuration, regardless of the arrangement direction of the pixels P, as described above, the number of transistor circuits 20 arranged in the column direction can be halved compared to the number of pixel electrodes 151 arranged in the column direction. Therefore, as described above, one horizontal scanning period H can be secured to be twice as long as the conventional one horizontal scanning period H. This makes it possible to suppress a decrease in display quality.

[0050] B. Second embodiment A second embodiment will be described. In the following examples, elements having the same functions as those in the first embodiment will be designated by the same reference numerals as those in the first embodiment, and detailed descriptions thereof will be omitted as appropriate.

[0051] In this embodiment, the combination of display pixels P0 included in one pixel P is different from that in the first embodiment. The display pixels P0 in this embodiment are arranged in a so-called Bayer array.

[0052] Fig. 6 is a diagram showing one pixel P in the second embodiment. Note that Fig. 6 shows an arbitrary pixel PA among the multiple pixels P.

[0053] As shown in Fig. 6, the pixel PA has four display pixels P0. Specifically, the pixel P3 has a first display pixel PaA, a second display pixel PbA, a third display pixel PcA, and a fourth display pixel PdA. For example, the first display pixel PaA emits light in a red wavelength range. The second display pixel PbA emits light in a green wavelength range. The third display pixel PcA emits light in a green wavelength range. The fourth display pixel PdA emits light in a blue wavelength range.

[0054] The first display pixel PaA is provided with a first pixel electrode 151a. The second display pixel PbA is provided with a second pixel electrode 151b. The third display pixel PcA is provided with a third pixel electrode 151c. The fourth display pixel PdA is provided with a fourth pixel electrode 151d.

[0055] The second pixel electrode 151b is provided in the X direction with respect to the first pixel electrode 151a. The third display pixel PcA is provided in the Y direction with respect to the first pixel electrode 151a. The fourth pixel electrode 151d is provided in the X direction with respect to the third display pixel PcA, and in the Y direction with respect to the second pixel electrode 151b.

[0056] Fig. 7 is a layout diagram of four transistor circuits 20 corresponding to the four display pixels P0 shown in Fig. 6. Fig. 7 illustrates a first transistor circuit 20a, a second transistor circuit 20b, a third transistor circuit 20c, and a fourth transistor circuit 20d as the four transistor circuits 20. The first transistor circuit 20a corresponds to the first display pixel PaA. The second transistor circuit 20b corresponds to the second display pixel PbA. The third transistor circuit 20c corresponds to the third display pixel PcA. The fourth transistor circuit 20d corresponds to the fourth display pixel PdA.

[0057] The first transistor circuit 20a, the second transistor circuit 20b, the third transistor circuit 20c, and the fourth transistor circuit 20d are arranged in this order in the X direction.

[0058] Although not shown in detail, the first transistor circuit 20a and the second transistor circuit 20b overlap the first display pixel PaA and the second display pixel PbA in a planar view. This arrangement prevents the electrical connection path between the first transistor circuit 20a and the first pixel electrode 151a from becoming excessively long and complicated. The same applies to the second transistor circuit 20b. Although not shown in detail, the third transistor circuit 20c and the fourth transistor circuit 20d overlap the third display pixel PcA and the fourth display pixel PdA in a planar view. This arrangement prevents the electrical connection path between the third transistor circuit 20c and the third pixel electrode 151c from becoming excessively long and complicated. The same applies to the fourth transistor circuit 20d.

[0059] In this embodiment, four display pixels P0 are arranged in two rows and two columns, while four transistor circuits 20 are arranged in one row and four columns. In addition, the gate of the first selection transistor 17a, the gate of the second selection transistor 17b, the gate of the third selection transistor 17c, and the gate of the fourth selection transistor 17d are electrically connected to the same scanning line 11p.

[0060] According to this embodiment, as in the first embodiment, the number of transistor circuits 20 arranged in the column direction can be halved compared to the number of pixel electrodes 151 arranged in the column direction. That is, the number of transistor circuits 20 arranged in the column direction can be halved compared to the number of display pixels P0 arranged in the column direction. Specifically, the number of transistor circuits 20 arranged in the row direction is doubled compared to the number of display pixels P0 arranged in the row direction. According to the configuration of this embodiment, one horizontal scanning period H can be secured to be twice as long as one horizontal scanning period H of the related art. Therefore, it is possible to suppress a deterioration in display quality caused by a shortened one horizontal scanning period H.

[0061] In this embodiment, the first pixel electrode 151a, the second pixel electrode 151b, the third pixel electrode 151c, and the fourth pixel electrode 151d constitute one pixel P that constitutes one dot of color display. Therefore, the first to fourth transistor circuits 20a to 20d corresponding to one pixel P are arranged in one row, and the gates of the first to fourth transistor circuits 20a to 20d are electrically connected to the scanning line 11p. Even when the four display pixels P0 of one pixel P are arranged in two rows and two columns as in this embodiment, the number of transistor circuits 20 arranged in the column direction can be reduced to half the number of pixel electrodes 151 arranged in the column direction. Therefore, as described above, one horizontal scanning period H can be secured to be twice as long as the conventional one horizontal scanning period H. Therefore, the deterioration of the display quality can be suppressed.

[0062] C. Third embodiment A third embodiment will be described. In the following examples, elements having the same functions as those in the first embodiment will be designated by the same reference numerals as those in the first embodiment, and detailed descriptions thereof will be omitted as appropriate.

[0063] In this embodiment, the combination of display pixels P0 included in one pixel P is different from that in the first embodiment. In this embodiment, for example, a monochrome display is performed.

[0064] Fig. 8 is a diagram showing one pixel P of the third embodiment. Fig. 8 shows an arbitrary pixel PB among the multiple pixels P. As shown in Fig. 8, the pixel PB has two display pixels P0. Specifically, the pixel PB has a first display pixel PaB and a second display pixel PbB. For example, the first display pixel PaA and the second display pixel PbB emit light in the same color wavelength range.

[0065] The first display pixel PaB is provided with a first pixel electrode 151a. The second display pixel PbB is provided with a second pixel electrode 151b. The second pixel electrode 151b is provided in the Y direction with respect to the first pixel electrode 151a.

[0066] Fig. 9 is a layout diagram of two transistor circuits 20 corresponding to the two display pixels P0 shown in Fig. 8. Fig. 9 illustrates a first transistor circuit 20a and a second transistor circuit 20b as the two transistor circuits 20. The first transistor circuit 20a corresponds to the first display pixel PaB. The second transistor circuit 20b corresponds to the second display pixel PbB.

[0067] The first transistor circuit 20a and the second transistor circuit 20b are arranged in this order in the X direction. Although not shown in detail, the first transistor circuit 20a and the second transistor circuit 20b overlap the first display pixel PaB and the second display pixel PbB in a plan view. This arrangement prevents the electrical connection path between the first transistor circuit 20a and the first pixel electrode 151a from becoming excessively long and complicated. Similarly, it prevents the electrical connection path between the second transistor circuit 20b and the second pixel electrode 151b from becoming excessively long and complicated.

[0068] In this embodiment, similarly to the first embodiment, the arrangement direction of the first transistor circuit 20a and the second transistor circuit 20b intersects with the arrangement direction of the first pixel electrode 151a and the second pixel electrode 151b. In this embodiment, the two display pixels P0 are arranged in two rows and one column, whereas the two transistor circuits 20 are arranged in one row and two columns. The gate of the first selection transistor 17a and the gate of the second selection transistor 17b are electrically connected to the same scanning line 11p.

[0069] According to this embodiment, similarly to the first embodiment, the number of transistor circuits 20 arranged in the column direction can be halved compared to the number of pixel electrodes 151 arranged in the column direction. That is, the number of transistor circuits 20 arranged can be halved compared to the number of display pixels P0 arranged. According to the configuration of this embodiment, one horizontal scanning period H can be secured to be twice as long as one horizontal scanning period H of the related art. Therefore, it is possible to suppress a deterioration in display quality caused by a shortened one horizontal scanning period H.

[0070] In this embodiment, the first pixel electrode 151a and the second pixel electrode 151b constitute one pixel P that constitutes one dot of color display. Even if two display pixels P0 of one pixel P are arranged in two rows and one column, the gates of two transistor circuits 20 corresponding to the two display pixels P0 are electrically connected to one scanning line 11p. With this configuration, as described above, the number of rows can be halved. Therefore, as described above, one horizontal scanning period H can be secured to be twice as long as the conventional one horizontal scanning period H. This makes it possible to suppress a decrease in display quality.

[0071] D. Variations The above-described embodiment may be modified in various ways. Specific modified aspects that may be applied to the above-described embodiment are illustrated below. Two or more aspects selected from the following examples may be combined as appropriate to the extent that they are not mutually inconsistent.

[0072] The arrangement of the display pixels P0 in the above-described embodiment is merely an example, and other arrangements may be used, such as a so-called PenTile arrangement.

[0073] In the above embodiment, two transistor circuits 20 overlap two display pixels P0 in a plan view. However, three or more transistor circuits 20 may overlap three or more display pixels P0 in a plan view. In this case, three or more transistor circuits 20 corresponding to three or more display pixels P0 arranged in the Y direction are arranged in the X direction. In this case, the gates of the selection transistors 17 of the three transistor circuits 20 are electrically connected to the same scanning line 11p. With this configuration, the number of transistor circuits 20 can be reduced to one-third or less of the number of display pixels P0. With this configuration, one horizontal scanning period H can be secured to be three times or more longer than the conventional one horizontal scanning period H.

[0074] However, the optimal configuration is one in which two transistor circuits 20 overlap two display pixels P0 in a plan view, and the gates of the selection transistors 17 of the two transistor circuits 20 corresponding to the two display pixels P0 are electrically connected to the same scanning line 11p. This prevents the number of wirings of the data line 12 from becoming excessively dense, and also makes it possible to suppress a decrease in display quality caused by a shortened horizontal scanning period H.

[0075] In the above embodiment, the light-emitting element 15 is an OLED. However, for example, the light-emitting element 15 may be an LED, a mini LED, a micro LED, etc. LED is an abbreviation of light-emitting diode.

[0076] E.Electronic equipment The display device 1 according to each of the above-described embodiments or modifications can be applied to various electronic devices. The display device 1 according to the above-described embodiments is particularly suitable for electronic devices that are required to display high-definition images of 2K2K or more and are also required to be compact.

[0077] Fig. 10 is a perspective view showing the appearance of a head mounted display 300 as an electronic device. Fig. 11 is a diagram showing the optical configuration of the head mounted display 300 shown in Fig. 10. In Fig. 11, the display device 1 for the left eye is referred to as a display device 1L, and the display device 1 for the right eye is referred to as a display device 1R.

[0078] As shown in Fig. 10, the head mounted display 300 includes temples 310, a bridge 320, a projection optical system 301L, a projection optical system 301R, and a control unit 350. Also, as shown in Fig. 11, the head mounted display 300 includes two display devices 1. The control unit 350 includes, for example, a processor and a memory, and controls the operations of the two display devices 1.

[0079] The image light LL formed by the display device 1L is emitted to the projection optical system 301L. The projection optical system 301L includes an optical lens 302L and a half mirror 303L. The image light LL is emitted toward the half mirror 303L through the optical lens 302L. A part of the image light LL is reflected by the half mirror 303L and projected onto the pupil EY of the wearer of the head mounted display 300. A part of the image light LL passes through the half mirror 303L. Similarly, the image light LR formed by the display device 1R is emitted to the projection optical system 301R. The projection optical system 301R includes an optical lens 302R and a half mirror 303R. The image light LR is emitted toward the half mirror 303L through the optical lens 302R. A part of the image light LR is reflected by the half mirror 303R and projected onto the pupil EY of the wearer of the head mounted display 300. A part of the image light LR passes through the half mirror 303R.

[0080] A person wearing the head mounted display 300 can view the image formed by the image lights LL and LR while viewing an outside world image.

[0081] The head mounted display 300 includes the above-mentioned display device 1 and a control unit 350. The display device 1 can suppress deterioration of display quality. Therefore, by including the display device 1 in the head mounted display 300, deterioration of the display quality of the head mounted display 300 can be suppressed.

[0082] In addition, examples of electronic devices to which the display device 1 is applied include electronic devices that are placed close to the eyes, such as a digital scope, digital binoculars, digital still cameras, and video cameras, in addition to the head mounted display 300. Furthermore, the display device 1 can be applied as a display unit provided in electronic devices such as displays of mobile phones, smartphones, smart watches, personal digital assistants (PDAs), car navigation devices, and in-vehicle instrument panels. The display device 1 can also be applied to a light bulb of a projection projector.

[0083] Although the present invention has been described above based on the illustrated embodiment and modified examples, the present invention is not limited to these. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-mentioned embodiment, and any configuration can be added. [Explanation of symbols]

[0084] 1...display device, 1H...one horizontal scanning period, 1L...display device, 1R...display device, 10...display panel, 11...scanning line, 11p...scanning line, 12...data line, 12a...first data line, 12b...second data line, 12c...third data line, 12d...fourth data line, 12e...fifth data line, 12f...sixth data line, 13p...first constant potential wiring, 14p...second constant potential wiring, 15...light-emitting element, 15a...first light-emitting element, 15b...second light-emitting element, 15c...third light-emitting element, 15d...fourth light-emitting element, 15e...fifth light-emitting element, 15f...sixth light-emitting element, 16a...first driving transistor, 16b ...second drive transistor, 16c...third drive transistor, 16d...fourth drive transistor, 16e...fifth drive transistor, 16f...sixth drive transistor, 17...first selection transistor, 17a...first selection transistor, 17b...second selection transistor, 17c...third selection transistor, 17d...fourth selection transistor, 17e...fifth selection transistor, 17f...sixth selection transistor, 18a...first capacitance element, 18b...second capacitance element, 18c...third capacitance element, 18d...fourth capacitance element, 18e...fifth capacitance element, 18f...sixth Capacitor element, 20... transistor circuit, 20a... first transistor circuit, 20b... second transistor circuit, 20c... third transistor circuit, 20d... fourth transistor circuit, 20e... fifth transistor circuit, 20f... sixth transistor circuit, 71... case, 72... FPC board, 73... terminal, 110... scanning line driving circuit, 120... data line driving circuit, 130... control circuit, 151... pixel electrode, 151a... first pixel electrode, 151b... second pixel electrode, 151c... third pixel electrode, 151d... fourth pixel electrode, 151e... fifth pixel electrode, 151f... sixth pixel electrode Electrode, 152... common electrode, 153... light emitting layer, 300... head mounted display, 301L... projection optical system, 301R... projection optical system, 302L... optical lens, 302R... optical lens, 303L... half mirror, 303R... half mirror, 310... temple, 320... bridge, 350... control unit, Ctr1... control signal, Ctr2... control signal, EY... pupil, Gwr... scanning signal, Ida... first drive current, Idb... second drive current, Idc... third drive current, Idd... fourth drive current, Ide... fifth drive current, Idf... sixth drive current, LL... image light, LR... image light, P... pixel,P0...display pixel, P1...first pixel, P2...second pixel, P3...pixel, PA...pixel, PB...pixel, Pa...first display pixel, PaA...first display pixel, PaB...first display pixel, Pb...second display pixel, PbA...second display pixel, PbB...second display pixel, Pc...third display pixel, PcA...third display pixel, Pd...fourth display pixel, PdA...fourth display pixel, Pe...fifth display pixel, Pf...sixth display pixel, Vct...power supply potential, Vd...video signal, Vda...first video signal, Vdb...second video signal, Vdc...third video signal, Vdd...fourth video signal, Vde...fifth video signal, Vdf...sixth video signal, Vel...power supply potential, Vid...video data, Video...video data.

Claims

1. a scanning line extending in a first direction; a first data line and a second data line extending in a second direction intersecting the first direction and aligned in the first direction; a first transistor circuit; a second transistor circuit; and a first light emitting element including a first pixel electrode; a second light-emitting element including a second pixel electrode, the first transistor circuit includes a first drive transistor that supplies a first drive current to the first pixel electrode based on a potential corresponding to a first video signal from the first data line, and a first selection transistor that electrically connects the first data line and the first drive transistor; the second transistor circuit includes a second driving transistor that supplies a second driving current to the second pixel electrode based on a potential corresponding to a second video signal from the second data line, and a second selection transistor that electrically connects the second data line and the second driving transistor; the first pixel electrode and the second pixel electrode are aligned in the second direction, the first transistor circuit and the second transistor circuit are aligned in the first direction, a gate of the first selection transistor and a gate of the second selection transistor are electrically connected to the scanning line; A display device characterized by:

2. a third data line and a fourth data line extending in the second direction and aligned in the first direction; a third transistor circuit; and a fourth transistor circuit; and a third light emitting element including a third pixel electrode; a fourth light-emitting element including a fourth pixel electrode, the third transistor circuit includes a third driving transistor that supplies a third driving current to the third pixel electrode based on a potential corresponding to a third video signal from the third data line, and a third selection transistor that electrically connects the third data line and the third driving transistor; the fourth transistor circuit includes a fourth drive transistor that supplies a fourth drive current to the fourth pixel electrode based on a potential corresponding to a fourth video signal from the fourth data line, and a fourth selection transistor that electrically connects the fourth data line and the fourth drive transistor; the third pixel electrode is provided in the first direction relative to the first pixel electrode, the fourth pixel electrode is provided in the first direction relative to the second pixel electrode and in the second direction relative to the third pixel electrode; the third transistor circuit and the fourth transistor circuit are aligned in the first direction, a gate of the third selection transistor and a gate of the fourth selection transistor are electrically connected to the scanning line; The display device according to claim 1 .

3. a fifth data line and a sixth data line extending in the second direction and aligned in the first direction; a fifth transistor circuit; and a sixth transistor circuit; and a fifth light-emitting element including a fifth pixel electrode; a sixth light-emitting element including a sixth pixel electrode, the fifth transistor circuit includes a fifth drive transistor that supplies a fifth drive current to the fifth pixel electrode based on a potential corresponding to a fifth video signal from the fifth data line, and a fifth selection transistor that electrically connects the fifth data line and the fifth drive transistor; the sixth transistor circuit includes a sixth drive transistor that supplies a sixth drive current to the sixth pixel electrode based on a potential corresponding to a sixth video signal from the sixth data line, and a sixth selection transistor that electrically connects the sixth data line and the sixth drive transistor; the fifth pixel electrode is provided in the first direction relative to the third pixel electrode, the sixth pixel electrode is provided in the first direction relative to the fourth pixel electrode and in the second direction relative to the fifth pixel electrode; the fifth transistor circuit and the sixth transistor circuit are aligned in the first direction, a gate of the fifth selection transistor and a gate of the sixth selection transistor are electrically connected to the scanning line; the first pixel electrode, the third pixel electrode, and the fifth pixel electrode are provided in a first pixel that constitutes one dot for color display; the second pixel electrode, the fourth pixel electrode, and the sixth pixel electrode are provided in a second pixel constituting another dot of a color display; The display device according to claim 2 .

4. the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode are provided in one pixel that constitutes one dot for color display; The display device according to claim 2 .

5. The display device according to claim 1 ; and a control unit that controls the operation of the display device.

Images