Drive circuit for electro-optic device, electro-optic device and electronic device

Abstract

To suppress display unevenness caused by parasitic capacitance on data lines.SOLUTION: In a first operation, a tournament circuit 82 selects one of data lines 14 in response to selection signals Sel_1a, Sel_1b, and Sel2 to Sel7, to output a voltage of the selected data line 14 to a test output terminal via an amplifier. In a second operation, a selection circuit 821 of a first tier of the tournament circuit 82 is turned off between all the data lines 14 and an input terminal of a selection circuit 822 of a second tier.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a driving circuit for an electro-optical device, an electro-optical device, and an electronic apparatus. [Background technology]

[0002] For example, electro-optical devices that use light-emitting elements such as OLEDs to display various images are known. OLED stands for Organic Light Emitting Diode. In electro-optical devices, pixel circuits including transistors for passing current to the light-emitting elements are provided for each pixel of the display image. The transistors supply current to the light-emitting elements according to the luminance level. This causes the light-emitting elements to emit light with a luminance according to the current.

[0003] In the electro-optical device, a voltage corresponding to the luminance is applied to the gate node of the transistor via a data line. More specifically, data specifying the luminance is converted to an analog voltage by a DA conversion circuit, and the converted voltage is applied to the gate node of the transistor via the data line. As such a DA conversion circuit, for example, a technology has been proposed in which a pair of a switch and a capacitance element is provided corresponding to each bit, and the charging and discharging of the charge accumulated in the capacitance element according to each bit is controlled by the switch, and output to a data line (see, for example, Patent Document 1). Also, it is common that an inspection circuit for inspecting the voltage of the data line outputted to the data line is provided together with the scanning line driving circuit and the DA conversion circuit (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2000-341125 A [Patent Document 2] JP 2005-227505 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the technique described in Patent Document 1 has a problem in that if the parasitic capacitance of each data line differs from one data line to another, the voltage output to the data line also differs, causing display unevenness. [Means for solving the problem]

[0006] In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure includes a first conversion circuit that converts first gradation data into an analog signal and supplies it to a first data line, a second conversion circuit that converts second gradation data into an analog signal and supplies it to a second data line, a third conversion circuit that converts third gradation data into an analog signal and supplies it to a third data line, a fourth conversion circuit that converts fourth gradation data into an analog signal and supplies it to a fourth data line, a tournament circuit including a first selection circuit, a second selection circuit, and a third selection circuit, and a test output terminal, and in a first operation, the first selection circuit selects the first data line or the second data line and supplies an electric signal to one input terminal of the third selection circuit. the second selection circuit selects the third data line or the fourth data line and electrically connects it to the other input terminal of the third selection circuit; the third selection circuit selects the one input terminal or the other input terminal and, when a predetermined condition is satisfied, outputs the tournament circuit; a voltage based on the selection of the tournament circuit appears at the test output terminal; in a second operation, the first selection circuit electrically disconnects both the first data line and the second data line from one input terminal of the third selection circuit, and the second selection circuit electrically disconnects both the third data line and the fourth data line from the other input terminal of the third selection circuit. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view of an electro-optical device according to a first embodiment. [Diagram 2]FIG. 2 is a block diagram showing an electrical configuration of the electro-optical device. [Diagram 3] FIG. 4 is a diagram showing an equivalent circuit of a display region in an electro-optical device. [Figure 4] FIG. 2 is a diagram illustrating a pixel circuit of the electro-optical device. [Diagram 5] FIG. 2 is a diagram illustrating an equivalent circuit of a DA conversion circuit in an electro-optical device. [Figure 6] FIG. 4 is a diagram illustrating an initialization circuit of the electro-optical device. [Figure 7] FIG. 4 is a diagram showing an inspection circuit of the electro-optical device. [Figure 8] FIG. 13 is a diagram showing a tournament circuit in a test circuit. [Figure 9] FIG. 13 is a diagram showing a first stage selection circuit in a tournament circuit. [Figure 10] FIG. 13 is a diagram showing a non-first stage selection circuit in a tournament circuit. [Figure 11] 4 is a timing chart showing a display operation in the electro-optical device. [Figure 12] FIG. 13 is a diagram showing an example of a display screen of an electro-optical device according to a comparative example. [Figure 13] FIG. 11 is a diagram showing an inspection circuit of the electro-optical device according to the second embodiment. [Figure 14] FIG. 1 is a perspective view showing a head mounted display using an electro-optical device. [Figure 15] FIG. 2 is a diagram showing an optical configuration of a head mounted display. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, electro-optical devices according to embodiments will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are attached, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0009] 1 is a perspective view showing an electro-optical device 10 according to an embodiment. The electro-optical device 10 is a micro display panel that displays an image in, for example, a head mounted display. The electro-optical device 10 includes pixel circuits including light emitting elements, a drive circuit that drives the pixel circuits, an inspection circuit, and the like. The pixel circuits, the drive circuit, and the inspection circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0010] The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194. In the figure, the X direction indicates the extension direction of the scanning lines in the electro-optical device 10, and the Y direction indicates the extension direction of the data lines. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of light emitted from the light-emitting element.

[0011] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device 10, and FIG. 3 is a diagram showing the arrangement of pixel circuits in the display area of ​​the electro-optical device 10. As shown in FIG. As shown in FIG. 2, the electro-optical device 10 is roughly divided into a control circuit 20, a data signal output circuit 40, an initialization circuit 60, an inspection circuit 80, a display area 100, and a scanning line driving circuit 120. In the display area 100, for example, 1080 rows of scanning lines 12 are arranged along the X direction in the figure, and 5856 (=1952×3) columns of data lines 14 are arranged along the Y direction and are electrically insulated from each other.

[0012] The pixel circuits 110R, 110G, and 110B are provided corresponding to the scanning lines 12 arranged in 1080 rows and the data lines 14 arranged in 5856 columns as follows. In detail, the red pixel circuit 110R is provided corresponding to the intersection of the i-th row scanning line 12 and the (3j-2)-th column data line 14. The green pixel circuit 110G is provided corresponding to the intersection of the i-th row scanning line 12 and the (3j-1)-th column data line 14. The blue pixel circuit 110B is provided corresponding to the intersection of the i-th row scanning line 12 and the (3j)-th column data line 14. Note that i is an integer between 1 and 1080, and is used to generally describe the scanning lines 12. Also, j is an integer between 1 and 1952, and is used to generally describe the array of color pixels and the data lines 14.

[0013] The pixel circuit 110R includes a light-emitting element that emits light containing a red component, the pixel circuit 110G includes a light-emitting element that emits light containing a green component, and the pixel circuit 110B includes a light-emitting element that emits light containing a blue component. A single color is expressed by additive color mixing of light emitted from the pixel circuits 110R, 110G, and 110B that are adjacent to each other and belong to the same row. Therefore, in this embodiment, in terms of color pixels, an image is displayed in a matrix arrangement of 1080 rows and 1952 columns.

[0014] Strictly speaking, pixel circuits 110R, 110G, and 110B should be called sub-pixel circuits because they represent the red, green, and blue components, respectively, of one color pixel. However, for the sake of convenience, they will be called pixel circuits in this description. Furthermore, since the electrical circuit configurations of the pixel circuits 110R, 110G, and 110B are the same, when a general description is given without specifying a color, the pixel circuit will simply be denoted by the reference numeral 110.

[0015] The control circuit 20 controls each unit based on the video data Vid and the synchronization signal Sync supplied from the host device. The video data Vid specifies the gradation level of each of the color pixels arranged in a 1080×1952 matrix, for example, with 8 bits for each of R, G, and B. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

[0016] The brightness characteristic indicated by the grayscale level in the video data Vid supplied from the host device does not necessarily match the luminance characteristic of the OLED included in the pixel circuit 110. Therefore, in order to cause the OLED to emit light at a brightness corresponding to the grayscale level specified by the video data Vid, the control circuit 20 up-converts the 8 bits of the video data Vid to, for example, 10 bits in this embodiment and outputs it as video data Vdata. Therefore, the 10-bit video data Vdata becomes data corresponding to the grayscale level specified by the video data Vid.

[0017] For the up-conversion, a look-up table is used that stores in advance the correspondence between the 8 bits of the input video data Vid and the 10 bits of the output video data Vdata. The control circuit 20 also generates various control signals to control each unit, which will be described in detail later.

[0018] The scanning line driving circuit 120 is a circuit for outputting various signals to drive the pixel circuits 110 arranged in 1080 rows and 5856 columns, row by row, under the control of the control circuit 20. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(1079), / Gwr(1080) to the scanning lines 12 in the 1st, 2nd, 3rd, ..., 1079th, and 1080th rows in order. In general, the scanning signal supplied to the scanning line 12 in the i-th row is represented as / Gwr(i). The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(1080), which will be described in detail later.

[0019] The data signal output circuit 40 includes DA conversion circuits 41 provided in one-to-one correspondence with the data lines 14. The DA conversion circuits 41 output data signals to pixel circuits 110 located in a row selected by the scanning line driving circuit 120. Specifically, the DA conversion circuit 41 converts 10-bit video data Vdata into an analog data signal and outputs it to the data signal output line 14c. The initialization circuit 60 includes switch circuits 61 provided in one-to-one correspondence with the data lines 14. The switch circuits 61 initialize the data lines 14, the data signal output lines 14c, the OLED, etc. before a data signal is output. The DA conversion circuit 41 and the switch circuit 61 will be described in detail later.

[0020] The inspection inspection circuit 80 is a circuit for inspecting the data signals output to the 5856 data lines 14. Details of the inspection circuit 80 will be described later, but in an inspection operation, the inspection circuit 80 inputs a signal for identifying the data line 14 to be inspected among the 5856 columns, and outputs the voltage of the data signal applied to the data line 14 to be inspected. In this embodiment, the inspection operation is performed, for example, in a wafer state before dicing, rather than in the state shown in Fig. 1. Therefore, the data line 14 to be inspected is instructed by a tester external to the electro-optical device 10 via a test pad provided on the semiconductor substrate. Meanwhile, the voltage of the data signal applied to the data line 14 to be inspected is output via the test output terminal and the probe of the tester.

[0021] 4 is a circuit diagram showing an arbitrary pixel circuit 110 located in the i-th row. The pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitance element 140. The transistors 121 to 124 are, for example, MOS type. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. Moreover, in addition to the scanning signal / Gwr(i), control signals / Gel(i) and / Gcmp(i) are supplied from the scanning line driving circuit 120 to the pixel circuits 110 in the i-th row.

[0022] Control signal / Gel(i) is a generalized representation of control signals / Gel(1), / Gel(2), ..., / Gel(1079), / Gel(1080) that are supplied in order corresponding to rows 1, 2, ..., 1079, and 1080. Similarly, control signal / Gcmp(i) is a generalized representation of control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(1079), / Gcmp(1080) that are supplied in order corresponding to rows 1, 2, ..., 1079, and 1080.

[0023] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically transparent. When a current flows from the anode to the cathode in the OLED 130, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby generating white light.

[0024] The generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light emission side from the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter, and is then visually recognized by the observer. Note that the optical resonator and the color filter are omitted in the figure. In addition, when the electro-optical device 10 simply displays a monochromatic image of light and dark, the color filter is omitted.

[0025] In the i-th row pixel circuit 110, a gate node g of a transistor 121 is electrically connected to a drain node of a transistor 122. A source node s of the transistor 121 is electrically connected to a power supply line 116 to which a potential Vel is supplied, and a drain node d of the transistor 121 is electrically connected to a source node of a transistor 123 and a source node of a transistor 124. In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate via different wiring layers and contact holes even if the elements are not directly connected to each other.

[0026] One end of the capacitance element 140 is electrically connected to the gate node g of the transistor 121, and the other end is electrically connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. The other end of the capacitance element 140 may be electrically connected to a power supply line of another potential other than the power supply line 116 as long as the potential is kept substantially constant.

[0027] In this embodiment, for example, a so-called MOS capacitance formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate node layer (upper electrode) of a transistor is used as the capacitance element 140. Note that, as the capacitance element 140, a parasitic capacitance of the gate node g of the transistor 121 may be used, or a so-called metal capacitance formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used.

[0028] In the pixel circuit 110 in the i-th row, the gate node of the transistor 122 is electrically connected to the scanning line 12 in the i-th row, and the source node of the transistor 122 is electrically connected to the data line 14 corresponding to the pixel circuit 110. In the pixel circuit 110 in the i-th row, a control signal / Gcmp(i) is supplied to the gate node of the transistor 123, and the drain node of the transistor 123 is electrically connected to the data line 14 corresponding to the pixel circuit 110. In the pixel circuit 110 in row i, a control signal / Gel(i) is supplied to the gate node of the transistor 124, and the drain node of the transistor 124 is electrically connected to the pixel electrode 131 which is the anode of the OLED 130.

[0029] In the transistors 122, 123, and 124, when the direction of current flow is reversed, the source node and the drain node are switched, but in this description, the source node and the drain node are as described above.

[0030] FIG. 5 is a diagram showing the DA conversion circuits 41 for any one column in the data signal output circuit 40. As shown in FIG. The DA conversion circuit 41 is a pixel circuit 110 located at the intersection of the selected scanning line 12 and the data line 14 of the column corresponding to the DA conversion circuit 41, and 10 bits of video data Vdata corresponding to the pixel circuit 110 are supplied to the DA conversion circuit 41 during an output period (write period) described later. Specifically, for example, the DA conversion circuit 41 in the (3j-2)th column is supplied with 10 bits of video data Vdata which is the R component of the color pixel in the i-th row (3j) column during the write period of the horizontal scanning period of the i-th row. For convenience, of the 10 bits of the video data Vdata supplied during the output period, the least significant bit is designated as D0, and the subsequent bits from the second most significant bit to the most significant bit are designated as D1 to D9 in order. Outside the output period, the bits D0 to D9 are set to L level. In this description, the L level is the potential Gnd, and the H level is, for example, the potential Vel.

[0031] The DA conversion circuit 41 is supplied with a control signal Rst from the control circuit 20, and the potentials Vrst, VL, VPL, and VPH are supplied from a power supply circuit (not shown). The control signal Rst is common across the DA conversion circuits 41 in each column, and the potentials Vrst, VL, VPL, and VPH are also common across the DA conversion circuits 41 in each column. Although the potentials are divided into VPL and VPH, in the embodiment, for convenience, it will be described with VPL = VPH. Also, the potentials VL, VPL, and VPH have the relationship VL < VPL = VPH.

[0032] The DA conversion circuit 41 includes capacitor elements C0 to C9, Cser, a switch Rsw, and selection circuits 410 to 419. The capacitor elements C0 to C9 and the selection circuits 410 to 419 are paired as follows so as to correspond to each bit. Specifically, the selection circuit 410 and the capacitor element C0 are paired corresponding to bit D0, the selection circuit 411 and the capacitor element C1 are paired corresponding to bit D1, and similarly, the selection circuit 419 and the capacitor element C9 are paired corresponding to bit D9.

[0033] The selection circuits 410 to 414 corresponding to the lower bits are single-pole double-throw switches that select the potential VL if the corresponding bit is at the L level corresponding to "0" and select the potential VPL if the corresponding bit is at the H level corresponding to "1", and supply the selected potential to one end of the corresponding capacitor element. Also, the selection circuits 415 to 419 corresponding to the upper bits are single-pole double-throw switches that select the potential VL if the corresponding bit is at the L level corresponding to "0" and select the potential VPH if the corresponding bit is at the H level corresponding to "1", and supply the selected potential to one end of the corresponding capacitor element.

[0034] For example, the selection circuit 410 corresponding to bit D0 selects the potential VPL if bit D0 is "1" (H level), and selects the potential VL if bit D0 is "0" (L level), and supplies the selected potential to one end of the capacitance element C0. Also, for example, the selection circuit 416 corresponding to bit D6 selects the potential VPH if bit D6 is "1" (H level), and selects the potential VL if bit D6 is "0" (L level), and supplies the selected potential to one end of the capacitance element C6.

[0035] In this embodiment, the capacitance values ​​of the capacitance elements C0 to C9 are set to the following ratios: In detail, if the capacitance value of the capacitance element C0 is "1", the capacitance values ​​of the capacitance elements C2, C3, C4, C5, C6, C7, C8, and C9 are "2", "4", "8", "16", "1", "2", "4", "8", and "16", in that order.

[0036] The weights of bits D0 to D9, when considered as a total of 10 bits, are "1", "2", "4", "8", "16", "32", "64", "128", "256", and "512", respectively. For this reason, the capacitance values ​​of capacitive elements C0 to C9 do not correspond to the weights. However, if bits D0 to D9 are divided into lower bits D0 to D4 and upper bits D5 to D9, and bit D5 of bits D5 to D9 is considered the least significant bit with a weight of "1", the weights of bits D5 to D9 become "1", "2", "4", "8", and "16", respectively.

[0037] Also, the capacitance value of the capacitance element Cser is "1" in this embodiment. Note that a certain degree of error is permissible for the capacitance values ​​of the capacitance elements C0 to C9 and Cser as long as the linearity of the output voltage, which will be described later, is maintained. In this embodiment, since a MOS capacitance is used as the capacitance element 140 in the pixel circuit 110, it is preferable to use a MOS capacitance for the capacitance elements C0 to C9 and Cser as well. Note that a metal capacitance may be used for the capacitance elements C0 to C9 and Cser.

[0038] Among the capacitive elements C0 to C9, the other ends of the capacitive elements C0 to C4 corresponding to the lower 5 bits are electrically connected to one end of the capacitive element Cser. For convenience, the connection line between the other ends of the capacitive elements C0 to C4 and one end of the capacitive element Cser is referred to as a relay line 14b. Among the capacitive elements C0 to C9, the other ends of the capacitive elements C5 to C9 corresponding to the upper five bits are electrically connected to a data signal output line 14c which is an output end of the DA conversion circuit 41 and the other end of the capacitive element Cser.

[0039] The switch Rsw is turned on or off in accordance with the control signal Rst between the power supply line at the potential Vrst and the relay line 14b. In detail, the switch Rsw is turned on when the control signal Rst is at H level, and turned off when the control signal Rst is at L level. In this description, the "on state" of a switch, transistor, or transmission gate means that both ends of the switch, between the source node and the drain node of a transistor, or both ends of a transmission gate are electrically closed and in a low impedance state. The "off state" refers to a state in which both ends of the switch, between the source node and the drain node, or both ends of the transmission gate are electrically open and in a high impedance state.

[0040] 5, the DA conversion circuit 41 for one arbitrary column has been described, but the DA conversion circuits 41 corresponding to other columns have the same configuration. Fig. 5 shows only the electrical configuration, and does not show the actual positions and arrangement of the elements that make up the DA conversion circuit 41. Furthermore, when describing the DA conversion circuit 41 corresponding to a certain specific data line 14, the integer j may be used, as with the data line 14.

[0041] The operation of the DA conversion circuit 41 is divided into a reset period and an output period. The reset period of the DA conversion circuit 41 corresponds to the period from an initialization period (A1) to a compensation period (B) in the operation period of the electro-optical device 10, which will be described later, and the output period of the DA conversion circuit 41 corresponds to a writing period (C) in the operation period of the electro-optical device 10. In the DA conversion circuit 41, in the reset period, the switch Rsw is in an on state, and the bits D0 to D9 are "0" except during the write period, so that the selection circuits 410 to 419 select the potential VL. Also, in the reset period, the data signal output line 14c, which is the output terminal, is at the potential Vini, as described later. Therefore, charges according to the capacitance values ​​are accumulated in the capacitance elements C0 to C9.

[0042] During the output period in the DA conversion circuit 41, the selection circuits 410-414 select the potential VL if the corresponding bit is "0", and select the potential VPL if the corresponding bit is "1". Also, during the output period, the selection circuits 415-419 select the potential VL if the corresponding bit is "0", and select the potential VPH if the corresponding bit is "1". Therefore, at the end of the output period, the selection circuits 410-419 select the potential VL or VPL / VPH in accordance with the bits D0-D9 in order.

[0043] That is, during the output period, the voltage at one end of the capacitance elements C0 to C9 is either changed (increased) or maintained according to the bits D0 to D9. Therefore, at the other end of the capacitance elements C0 to C9 whose voltage at one end has changed, the accumulated charge is discharged, and the voltage at the other end of the capacitance elements C0 to C9 rises from the voltage at the end of the reset period by an amount corresponding to the capacitance value.

[0044] The other ends of the capacitive elements C5-C9 corresponding to the higher bits increase the voltage of the data signal output line 14c according to the capacitance value. On the other hand, the other ends of the capacitive elements C0-C4 corresponding to the lower bits are connected to the data signal output line 14c via the capacitive element Cser, so that the voltage change of the relay line 14b, which is the other end of the capacitive elements C0-C4, is compressed at a ratio determined by the capacitive elements C0-C4 and Cser, causing a change in the voltage of the data signal output line 14c. If this ratio is expressed as the compression ratio k, this compression ratio k is expressed by the following equation (1). k=Cser / (Cser+C0+C1+C2+C3+C4)…(1) In this embodiment, the compression ratio k is 1 / 32 (=1 / (1+1+2+4+8+16)).

[0045] 5, a circuit including the capacitive elements C5 to C9 and the selection circuits 515 to 519 is referred to as an up-conversion circuit Upb. The up-conversion circuit Upb outputs voltages corresponding to the bits D5 to D9 to the data signal output line 14c. Similarly, a circuit including the capacitive elements C0-C4 and the selection circuits 510-514 is referred to as a lower-order conversion circuit Lwb. The lower-order conversion circuit Lwb outputs voltages corresponding to the bits D0-D4 to the relay line 14b. However, the voltage change of the relay line 14b is compressed to 1 / 32 of the compression ratio k, and is output to the data signal output line 14c. Therefore, even if bits D0 to D4 are in the same order as bits D5 to D9, the voltage change on the data signal output line 14c caused by the lower conversion circuit Lwb will be 1 / 32 of the voltage change on the data signal output line 14c caused by the upper conversion circuit Upb. Therefore, the DA conversion circuit 41 changes the voltage of the data signal output line 14c from the voltage (potential Vini) at the end of the reset period by a voltage according to the weights of the bits D0 to D9 during the output period.

[0046] 6 is a diagram showing three columns of switch circuits 61 in the initialization circuit 60. The three columns are referred to as column (3j-2), column (3j-1), and column (3j). The switch circuit 61 in each column is an assembly of p-type transistors 611 and 614, an n-type transistor 612, and a transmission gate 613. The transistors 611, 612, and 614 and the transistors constituting the transmission gate 613 are of a MOS type similar to the transistors 121 to 124 in the pixel circuit 110.

[0047] For example, focusing on column (3j-2), a control signal / Drst is supplied to the gate node of transistor 611 in switch circuit 61 of that column. The control signal / Drst is supplied in common to each column by control circuit 20. A source node of transistor 611 is electrically connected to a power supply line of potential Vel, and a drain node of transistor 611 is electrically connected to data line 14 of the (3j-2)th column.

[0048] A control signal Grst is supplied to the gate node of the transistor 612 in the switch circuit 61 in the (3j-2)th column. The control signal Grst is supplied in common to each column by the control circuit 20. The source node of the transistor 612 is grounded to a potential Gnd that is a reference for zero voltage, and the drain node of the transistor 612 is electrically connected to the data line 14 in the (3j-2)th column.

[0049] The transmission gate 613 in the switch circuit 61 in the (3j-2)th column is provided between the data signal output line 14c in the (3j-2)th column and the data line 14 in the (3j-2)th column, and is turned on or off according to the control signals Gop and / Gop. The logical levels of the control signals Gop and / Gop are mutually exclusive, and are supplied in common to each column by the control circuit 20. If the control signal Gop is at H level and the control signal / Gop is at L level, the transmission gate 613 is turned on, and if the control signal Gop is at L level and the control signal / Gop is at H level, the transmission gate 613 is turned off.

[0050] A control signal / Gini is supplied to the gate node of the transistor 614 in the switch circuit 61 in the (3j-2)th column. The control signal / Gini is supplied commonly to each column by the control circuit 20. A source node of the transistor 614 is electrically connected to a power supply line of a potential Vini, and a drain node of the transistor 614 is electrically connected to the data signal output line 14c in the (3j-2)th column. The potential Vini is set to be lower than the potential (Vel-Vth) of the gate node g when the voltage between the gate node g and the source node s of the transistor 121 in the pixel circuit 110 is the threshold voltage Vth of the transistor 121.

[0051] FIG. 7 is a diagram showing the test circuit 80. As shown in FIG. In this embodiment, the 5856 data lines 14 are grouped into groups of 122 columns. Each group is provided with a set of a tournament circuit 82, an amplifier 84, and a test output terminal 88 corresponding thereto.

[0052] Each tournament circuit 82 selects one of the 122 data lines 14 in accordance with a selection signal. Note that the circuit configuration that supplies the selection signal is omitted from the drawing.

[0053] The amplifier 84 amplifies the signal of the data line 14 selected by the tournament circuit 82. Since the output impedance of the data line 14 is high, the voltage of the data line 14 fluctuates greatly even when a small load is connected. For this reason, the signal output from the data line 14 is current-amplified by the amplifier 84 with a voltage gain of "1", that is, the output impedance of the data line 14 is converted to a low impedance and output. The signal current-amplified by the amplifier 84 is output to a test output terminal 88. There are 48 sets (=5856÷122) of such tournament circuits 82, amplifiers 84, and test output terminals 88.

[0054] The 48 sets of tournament circuits 82, amplifiers 84, and test output terminals 88 are arranged along the X direction. Therefore, when describing a specific set of tournament circuits 82, amplifiers 84, or test output terminals 88, they will be referred to by their number counting from the left.

[0055] 8 is a diagram showing one tournament circuit 82 in the inspection circuit 80. The tournament circuit 82 includes selection circuits 821-827 that select the data lines 14 in a tournament format. Note that selection in a tournament format refers to sequentially selecting one of two inputs in a hierarchical manner, and finally selecting one input. In this embodiment, in the tournament circuit 82, the selection between two alternatives is performed hierarchically seven times. That is, the selection in the first hierarchical level is performed by 64 selection circuits 821, the selection in the second hierarchical level is performed by 32 selection circuits 822, the selection in the third hierarchical level is performed by 16 selection circuits 823, and similarly, the selection in the seventh hierarchical level is performed by one selection circuit 827. In other words, each of the selection circuits 821 to 827 has two input terminals, and among these, the output terminals of the selection circuits 821 to 826 are electrically connected to one of the two input terminals in the selection circuit in the next higher hierarchical level, and the output terminal of the selection circuit 827 is electrically connected to the input terminal of the amplifier 84.

[0056] Each of the 64 selection circuits 821 selects one of the input terminals or deselects both input terminals depending on the logic levels of a selection signal Sel_1a supplied via wiring S1a and a selection signal Sel_1b supplied via wiring S1b. Of the 64 selection circuits 821, one input terminal of 61 selection circuits 821 is electrically connected to the odd-numbered data lines 14 of two adjacent columns of data lines 14, and the other input terminal is electrically connected to the even-numbered data lines 14. The input terminals of the remaining three selection circuits 821 out of the 64 are not connected to the data lines 14, as indicated by x marks in the figure.

[0057] Each of the 32 selection circuits 822 selects one of the input terminals according to the logic level of the selection signal Sel_2 supplied via the wiring S2. Similarly, each of the 16 selection circuits 823 selects one of the input terminals according to the logic level of the selection signal Sel_3 supplied via the wiring S3, each of the 8 selection circuits 824 selects one of the input terminals according to the logic level of the selection signal Sel_4 supplied via the wiring S4, each of the 4 selection circuits 825 selects one of the input terminals according to the logic level of the selection signal Sel_5 supplied via the wiring S5, each of the 2 selection circuits 826 selects one of the input terminals according to the logic level of the selection signal Sel_6 supplied via the wiring S6, and one selection circuit 827 selects one of the input terminals according to the logic level of the selection signal Sel_7 supplied via the wiring S7.

[0058] The selection signals Sel_1a, Sel_1b, and Sel_2 to Sel_7 are supplied not only to the one tournament circuit 82 of interest, but also to the other 47 tournament circuits 82 in common. 8, only the selection signals Sel_1a and Sel_1b are supplied to the selection circuit 821, but in reality, as shown in the following Fig. 9, the selection circuit 821 is supplied with a selection signal / Sel_1a obtained by inverting the logical level of the selection signal Sel_1a, and a selection signal / Sel_1b obtained by inverting the logical level of the selection signal Sel_1b. Similarly, the selection circuits 822 to 827 are also supplied with the selection signals / Sel_2 to / Sel_7 in order. The selection signals / Sel_2 to / Sel_7 are signals obtained by inverting the logical levels of the selection signals Sel_2 to Sel_7.

[0059] Furthermore, in one tournament circuit 82, 64 selection circuits 821 are arranged along the X direction. For this reason, when describing a specific selection circuit 821, it will be referred to by its number counting from the left. Similarly, the selection circuits 822 to 826 are arranged in the X direction in each layer. For this reason, when the selection circuits 822 to 826 are specifically described, they will be referred to by their number counting from the left.

[0060] FIG. 9 is a diagram showing the configuration of any one of the 64 selection circuits 821 in the first layer that is connected to the data line 14. In FIG. Selection signals Sel_1a, / Sel_1a, Sel_1b, and / Sel_1b are supplied in this order via wirings S1a, / S1a, S1b, and / S1b to the selection circuit 821. The selection signal / Sel_1a is a signal obtained by inverting the logical level of the selection signal Sel_1a by a NOT circuit Inv_1a, and the selection signal / Sel_1b is a signal obtained by inverting the logical level of the selection signal Sel_1b by a NOT circuit Inv_1b.

[0061] The selection circuit 821 has transmission gates Swa and Swb. An input terminal of the transmission gate Swa is electrically connected to an odd-numbered data line 14 among two adjacent columns of data lines 14, and an input terminal of the transmission gate Swb is electrically connected to an even-numbered data line 14 among the two columns. The output terminal of the transmission gate Swa and the output terminal of the transmission gate Swb are commonly connected, and this connection terminal is electrically connected to one of the two input terminals of the selection circuit 822 in the second layer. Of the 64 selection circuits 821, the three selection circuits 821 that are not connected to the data lines 14 have the same configuration as the other selection circuits 821, except that the input terminal of the transmission gate Swa and the input terminal of the transmission gate Swb are not connected to the data lines 14.

[0062] FIG. 10 is a diagram showing the configuration of any one of the 32 selection circuits 822 in the second layer. Selection signals Sel_2 and / Sel_2 are supplied in this order via lines S2 and / S2 to the selection circuit 822. The selection signal / Sel_2 is a signal obtained by inverting the logical level of the selection signal Se2 by a NOT circuit Inv_1a.

[0063] The selection circuit 822 has transmission gates Swc and Swd. An input terminal of the transmission gate Swc is electrically connected to an output terminal of the odd-numbered selection circuit 821 in two adjacent columns, and an input terminal of the transmission gate Swd is electrically connected to an output terminal of the even-numbered selection circuit 821 in two adjacent columns. The output terminal of the transmission gate Swc and the output terminal of the transmission gate Swd are commonly connected, and this connection terminal is electrically connected to one of the two input terminals of the selection circuit 823 in the third layer.

[0064] The 16 selection circuits 823 in the third hierarchy, the eight selection circuits 824 in the fourth hierarchy, the four selection circuits 825 in the fifth hierarchy, the two selection circuits 826 in the sixth hierarchy, and the one selection circuit 827 in the seventh hierarchy have the same configuration as selection circuit 822, except that the selection signals are different.

[0065] In addition, except when a tester is connected in the inspection operation to inspect the data signal output to the data line 14, the lines S1a and S1b are fixed to the L level and the lines / S1a and / S1b are fixed to the H level by a configuration not shown in the figure. In addition, except when the data signal output to the data line 14 is inspected, the lines S2 to S7 are fixed to the L or H level.

[0066] The operation of the electro-optical device 10 is divided into an inspection operation for inspecting the voltages output to the 5856 data lines 14, and a display operation for displaying an image specified by the image data Vin. For convenience of explanation, the inspection operation will be described first.

[0067] In the testing operation of the electro-optical device 10, selection signals Sel_1a, Sel1b, Sel2 to Sel_7 are supplied in accordance with instructions from a tester. Furthermore, a probe is brought into contact with each of the 48 test output terminals 88, and the voltage output from the test output terminals 88 via the probe is measured by the tester.

[0068] In the inspection operation, the control circuit 20 causes the DA conversion circuit 41 of each column to operate during a reset period and then to operate during an output period. Specifically, the control circuit 20 sets the control signal Rst to H level to turn on the switch Rsw, sets Gop to L level (the control signal / Gop to H level) to turn off the transmission gate 613, and sets all bits D0 to D9 to "0" to cause the selection circuits 410 to 419 to select the potential VL (reset period). After this, the control circuit 20 sets the control signal Rst to an L level to turn off the switch Rsw, sets the control signal Gop to an H level (the control signal / Gop to an L level) to turn on the transmission gate 613, and supplies a predetermined value (for example, all "1") as bits D0 to D9 (output period). As a result, voltages corresponding to the predetermined values ​​indicated by the bits D0 to D9 are output to the data lines 14 of the 5856 columns.

[0069] On the other hand, the tester designates one column of data lines 14 to be inspected out of the 122 columns. Selection signals Sel_1a, Sel1b, and Sel2 to Sel_7 for selecting the designated one column of data lines 14 are generated, and the one column of data lines 14 is selected by the selection signals Sel_1a, Sel1b, and Sel2 to Sel_7. The voltage of the selected data line 14 is amplified by an amplifier 84 and output from a test output terminal 88. Therefore, the tester checks whether the voltage output from the selected data line 14 is within a voltage range corresponding to a predetermined value. The tester performs such a check while sequentially specifying the 122 data lines 14 and for each of the voltages output from the 48 test output terminals 88, thereby checking the voltages output to the 5,856 data lines 14.

[0070] Next, the display operation of the electro-optical device 10 will be described.

[0071] FIG. 11 is a timing chart for explaining the display operation. In the display operation, since the tester is not connected, the lines S1_a and S1_b are always at the L level, and the lines / S1_a and / S1_b are always at the H level.

[0072] In the electro-optical device 10, in a display operation, the 1080 scanning lines 12 are scanned one by one in the order of lines 1, 2, . . . , 1079th, and 1080th during one frame (V) period. In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by the video data Vid. If the length of the period of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Also, the horizontal scanning period (H) is the time interval during which the 1st to 1080th scanning lines 12 are scanned in sequence.

[0073] In the display operation of the electro-optical device 10, one horizontal scanning period (H) is mainly divided into three periods: an initialization period (A), a compensation period (B), and a writing period (C). The initialization period (A) is divided into three initialization periods (A1), (A2), and (A3). In addition to the above three periods, the operation of the pixel circuit 110 further includes a light emission period (D).

[0074] The operation during the horizontal scanning period (H) will be described by taking the i-th row as an example. Also, the pixel circuits 110 will be described by taking the pixel circuits 110 in any one column in the i-th row as an example.

[0075] In the initialization period (A1) of the i-th row, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, and the control signal / Gel(i) is at H level. Therefore, in the i-th row pixel circuit 110, the transistor 122 is in the ON state, the transistor 123 is in the OFF state, and the transistor 124 is in the OFF state.

[0076] In addition, in the initialization period (A1), the control signal / Drst is at L level, the control signal Grst is at L level, the control signal Gop is at L level (the control signal / Gop is at H level), and the control signal / Gini is at L level. Therefore, in the initialization period (A1), the transistor 611 is in the ON state, the transistor 612 is in the OFF state, the transmission gate 613 is in the OFF state, and the transistor 614 is in the ON state.

[0077] Therefore, the data signal output line 14c has a potential Vini, and the data line 14 has a potential Vel. Since the transistor 122 in the pixel circuit 110 in the i-th row is in an on state, the gate node g of the transistor 121 in that pixel circuit has a potential Vel, and the source node and the drain node of that transistor 121 are forcibly turned off.

[0078] In the DA conversion circuit 41, in the initialization period (A1), the control signal Grst is at H level, so that the switch Rsw is turned on, and the data signal output line 14c is set to the potential Vini due to the on state of the transistor 614. Since the bits D0 to D9 are "0", each of the selection circuits 410 to 419 selects the potential VL, and thus, charges according to the capacitance values ​​are stored in the capacitance elements C0 to C9.

[0079] In the initialization period (A2) of the i-th row, the scanning signal / Gwr(i) changes to H level, the control signal / Gcmp(i) changes to L level, and the control signal / Gel(i) changes to L level. As a result, in the i-th row pixel circuit 110, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 changes to the ON state.

[0080] Also, in the initialization period (A2), the control signal / Drst changes to H level, the control signal Grst changes to H level, the control signal Gop maintains L level (the control signal / Gop is H level), and the control signal / Gini maintains L level. Therefore, in the initialization period (A2), the transistor 611 changes to the OFF state, the transistor 612 changes to the ON state, the transmission gate 613 maintains the OFF state, and the transistor 614 maintains the ON state.

[0081] Therefore, the data signal output line 14c maintains the potential Vini, and the data line 14 becomes the potential Gnd. In the pixel circuit 110 of the i-th row, the transistors 123 and 123 are turned on, so that the pixel electrode 131, which is the anode of the OLED 130, is reset to the potential Gnd through the transistors 124 and 123, the data line 14, and the transistor 612 in this order. Note that the pixel electrode 131 is reset in order to eliminate the influence of the voltage applied during the immediately preceding light emission period, since the OLED 130 has a parasitic capacitance.

[0082] In the initialization period (A3) of the i-th row, the scanning signal / Gwr(i) changes to the L level, the control signal / Gcmp(i) changes to the H level, and the control signal / Gel(i) changes to the H level. As a result, in the i-th row pixel circuit 110, the transistor 122 changes to the ON state, the transistor 123 changes to the OFF state, and the transistor 124 changes to the OFF state.

[0083] Also, in the initialization period (A3), the control signal / Drst maintains the H level, the control signal Grst changes to the L level, the control signal Gop changes to the H level (the control signal / Gop is the L level), and the control signal / Gini maintains the L level. Therefore, in the initialization period (A3), the transistor 611 maintains the off state, the transistor 612 changes to the off state, the transmission gate 613 changes to the on state, and the transistor 614 maintains the on state.

[0084] Therefore, the data signal output line 14c is maintained at the potential Vini, and the potential Vini reaches the gate node g of the transistor 121 via the transmission gate 613, the data line 14, and the transistor 122 in this order. In the DA conversion circuit 41, during the initialization period (A3), the state of the initial periods (A1) and (A2), that is, the state of charge stored in the capacitance elements C0 to C9 according to the capacitance values, is maintained.

[0085] After the initialization period (A3) ends, the compensation period (B) begins. In the compensation period (B) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the L level, and the control signal / Gel(i) maintains the H level. Therefore, in the i-th row pixel circuit 110, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0086] During this compensation period (B), the transistor 121 is in a diode-connected state via the on-state transistor 123, the data line 14, and the transistor 122, so that the voltage between the gate node g and the source node s of the transistor 121 converges to (a voltage close to) the threshold voltage of the transistor 121. Note that the potentials of the gate node g and the data line 14 of the transistor 121 at this time are set to a potential equivalent to the threshold.

[0087] Furthermore, in the compensation period (B), the control signal / Drst maintains the H level, the control signal Grst maintains the L level, the control signal Gop maintains the H level (the control signal / Gop is the L level), and the control signal / Gini changes to the H level. Therefore, in the initialization period (A3), the transistor 611 maintains the off state, the transistor 612 maintains the off state, the transmission gate 613 maintains the on state, and the transistor 614 changes to the off state.

[0088] Therefore, at the end of the compensation period (B), the threshold-equivalent potential at the data line 14 and the gate node g of the transistor 121 reaches, via the transmission gate 613, the other end of the capacitance element Cser and the other ends of the capacitance elements C5 to C9.

[0089] In the compensation period (B), one end of the capacitance elements C0 to C9 is maintained at the potential VL by the selection circuits 410 to 419, and one end of the capacitance element Cser and the other end of the capacitance elements C0 to C4 are maintained at the potential Vrst due to the on state of the switch Rsw. The potential Vrst is set to a potential equivalent to the average threshold voltage of the transistor 121. Therefore, at the end of the compensation period (B), the voltages applied across the capacitance elements C0 to C4 and the voltages applied across the capacitance elements C5 to C9 are substantially the same. Therefore, during the compensation period (B), it may be considered that charges according to the capacitance values ​​are still stored in the capacitance elements C0 to C9.

[0090] After the compensation period (B) ends, the writing period (C) begins. In the writing period (C) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the H level, and the control signal / Gel(i) maintains the H level. Therefore, in the i-th row pixel circuit 110, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, and the transistor 124 maintains the OFF state.

[0091] Furthermore, in the write period (C), the control signal / Drst maintains the H level, the control signal Grst maintains the L level, the control signal Gop maintains the H level (the control signal / Gop maintains the L level), and the control signal / Gini maintains the H level. Therefore, in the initialization period (A3), the transistor 611 maintains the off state, the transistor 612 maintains the off state, the transmission gate 613 maintains the on state, and the transistor 614 maintains the off state.

[0092] However, in the DA conversion circuit 41 of each column, the control signal Rst changes to L level, and the switch Rsw changes to the OFF state. Also, in the writing period (C), the bits D0 to D9 have values ​​corresponding to the video data Vdata.

[0093] Among the selection circuits 410-414, the selection circuits with a bit of "1" selected the potential VPL, and the selection circuits with a bit of "0" selected the potential VL. Among the selection circuits 415-419, the selection circuits with a bit of "1" selected the potential VPH, and the selection circuits with a bit of "0" selected the potential VL.

[0094] During the write period (C), the voltage at one end of the capacitive element corresponding to the bit "0" among the capacitive elements C0 to C9 does not change from the compensation period (B), and therefore does not contribute to the voltage increase of the data signal output line 14c, or further, the data line 14 via the transmission gate 613 in the on state. Among the capacitive elements C5 to C9 corresponding to the upper five bits, one end of the capacitive element corresponding to the bit "1" changes from the potential VL to the potential VPH in the write period (C). Therefore, among the capacitive elements C5 to C9, the capacitive element corresponding to the bit "1" raises the data line 14 from the threshold equivalent potential in the compensation period (B) by an amount according to the weight of the capacitance value. Of the capacitive elements C0 to C4 corresponding to the lower 5 bits, one end of the capacitive element corresponding to the bit "1" changes from the potential VL to the potential VPL during the write period (C). However, unlike the other ends of the capacitive elements C5 to C9, the other ends of the capacitive elements C0 to C4 are connected to the data line 14 via the capacitive element Cser. Therefore, the change from the potential VL to the potential VPL at one end of the capacitive element corresponding to the bit "1" among the capacitive elements C0 to C4 is compressed by a compression ratio k (1 / 32 in the above example), and the voltage of the data line 14 is increased.

[0095] In this manner, during the writing period (C), for example, the DA conversion circuit 41 in column (3j-2) raises the data line 14 in column (3j-2) from the threshold potential by a voltage corresponding to the video data Vdata in row i, column (3j-2), i.e., a voltage specifying the luminance of the OLED in row i, column (3j-2).

[0096] During the writing period (C) of the i-th row, the transistor 122 in the i-th row pixel circuit 110 is in the on state, so that the potential of the data line 14 reaches the gate node g of the transistor 121 and is held by the capacitance element 140. Furthermore, during the writing period (C) of the i-th row, the transistor 124 continues to be in the off state in the i-th row pixel circuit 110.

[0097] When the scanning signal / Gwr(i) changes to H level, the writing period (C) of the i-th row ends. When the scanning signal / Gwr(i) becomes H level, the transistor 122 in the i-th row pixel circuit 110 is turned off, but the voltage difference between the potential of the gate node g and the potential Vel is held in the capacitance element 140.

[0098] After the writing period (C) ends, the light emission period (D) begins. When the light emission period (D) of the i-th row begins, the control signal / Gel(i) is inverted to the L level, and the transistor 124 is turned on. As a result, a current corresponding to the voltage held by the capacitance element 140 flows through the OLED 130 by the transistor 121. As a result, the OLED 130 is in an optical state corresponding to the current, that is, it is in a state of emitting light with a luminance.

[0099] Note that, while FIG. 11 shows an example in which the light emission period (D) continues after the selection of the i-th row of scanning line 12 is completed, the period during which the control signal / Gel(i) is at the L level may be intermittent or may be adjusted according to the brightness adjustment. In addition, the level of the control signal / Gel(i) in the light emitting period (D) may be increased from the L level in the compensation period (B). In other words, the level of the control signal / Gel(i) in the light emitting period (D) may be an intermediate level between the H level and the L level.

[0100] In Figure 11, during the horizontal scanning period (H) of the i-th row, the explanation has been given with focus on the DA conversion circuit 41 corresponding to a certain column and the pixel circuit 110 in the i-th row corresponding to that column, but similar operations are also performed for the DA conversion circuits 41 and pixel circuits 110 corresponding to the other columns. In addition, in FIG. 11, the horizontal scanning period (H) of the i-th row is focused on and the operation during that horizontal scanning period (H) is described, but similar operations are sequentially performed for the horizontal scanning periods (H) of the 1st, 2nd, 3rd, ..., 1079th, and 1080th rows.

[0101] In the pixel circuit 110, during the writing period (C) and the light emission period (D), the potential of the gate node g of the transistor 121 is a potential changed from the threshold equivalent potential during the compensation period (B) according to the grayscale level of the pixel circuit 110. Similar operations are performed in the other pixel circuits 110, so in the embodiment, a current according to the grayscale level flows through the OLED 130 in a state in which the thresholds of the transistors 121 are compensated across all pixel circuits 110 in 1080 rows and 5785 columns. Therefore, in this embodiment, the variation in luminance is reduced, enabling a high-quality display.

[0102] Here, for convenience of explanation, a comparative example to the embodiment will be described. In short, the comparative example is configured such that the selection circuit 821 in the first layer of the inspection circuit 80 is replaced with the same selection circuits as the selection circuit 822 in the second layer to the selection circuit 827 in the seventh layer. In the comparative example, in the inspection operation, although not shown, the selection signals Sel_1 to Sel_7 are instructed by a tester. On the other hand, in the display operation, the selection signals Sel_1 to Sel_7 are not instructed by the tester, so they are indefinite, or the selection signals Sel_1 to Sel_7 are fixed at L or H level, or the selection signals Sel_1 to Sel_7 that select only one specific column are supplied.

[0103] In a comparative example having such a configuration, in a display operation, for example, when the same video data Vdata (with the same bits D0 to D9) is commonly supplied to all pixel circuits 110, that is, when a so-called solid display is performed, display unevenness occurs in a cycle of 122 columns along the Y direction, as shown in Fig. 12. The cause of this will be considered.

[0104] In the comparative example, the selection circuit in the first hierarchical level selects one of the data lines 14 in two columns, the selection circuit 822 in the second hierarchical level selects one of the two selection circuits in the first hierarchical level, and similarly, the selection circuit 827 in the seventh hierarchical level selects one of the two selection circuits 826 in the sixth hierarchical level. The data lines 14 that are not selected by the selection circuit in the first layer are cut off at the input terminal of the selection circuit, whereas the data lines 14 that are selected by the selection circuit in the first layer are extended to the input terminal of the selection circuit 822 in the second layer. For this reason, the substantial path length of the selected data line 14 becomes longer than the path length of the non-selected data line 14. Note that the substantial path length of the data line 14 mentioned here includes not only the data line 14 itself but also the wiring that is selected and electrically connected in the tournament circuit 82. The data lines 14 not selected by the selection circuit 822 in the second layer are cut off at the input terminal of the selection circuit 822, whereas the data lines 14 selected by the selection circuit 822 in the second layer are further extended to the input terminal of the selection circuit 823 in the third layer. Similarly, the data lines 14 not selected by the selection circuit 827 in the seventh layer are cut off at the input terminal of the selection circuit 827, whereas the data lines 14 selected by the selection circuit 827 in the seventh layer are extended to the input terminal of the amplifier 84.

[0105] In this way, in the comparative example, the effective path length of the data lines 14 varies depending on the selection by the seventh-level selection circuit during display operation. Since the data lines 14 have parasitic capacitance, if the path length varies, the parasitic capacitance of the data lines 14 also varies for each data line 14. In particular, in a configuration like the DA conversion circuit 41 of this embodiment, in which the charges accumulated in the capacitance elements C0 to C9 during the reset period are boosted according to the bits D0 to D9 during the output period and output to the data signal output line 14c (data line 14), if the parasitic capacitance of the output destination data line 14 is different, even if the bits D0 to D9 are the same (the gradation level is the same), the potential of the data line 14 during the output period will be different for each data line 14, and this will appear as display unevenness. Since the pattern in which the 122 columns of data lines 14 are selected is the same in the 48 tournament circuits 82, display irregularities appear in a 122-column cycle.

[0106] In contrast, in this embodiment, in the display operation, the lines S1_a and S1_b are always at the L level, and the lines / S1_a and / S1_b are always at the H level, so that in the selection circuit 821 of the first layer, both of the transmission gates Swa and Swb are in the OFF state. In one tournament circuit 82, the data lines 14 of 122 columns are cut off at the input terminal of the selection circuit 821, and in the other 47 tournament circuits 82, the data lines 14 are similarly cut off at the input terminals of the selection circuit 821. Therefore, in this embodiment, the substantial path lengths of the data lines 14 of 5856 columns are made uniform in the display operation. Therefore, according to this embodiment, the parasitic capacitances of the 5856 data lines 14 during display operation are uniform, so that display unevenness as shown in FIG. 12 can be suppressed.

[0107] Depending on the type, format, etc. of the tester, the number of voltages that can be measured simultaneously may be limited. For example, the number of voltages that can be measured simultaneously may be smaller, such as "4", rather than "48" as in the first embodiment. Therefore, a second embodiment will be described that is capable of measuring voltages output from 5856 columns of data lines 14 even with a tester that can measure, for example, "4" voltages simultaneously. The electro-optical device 10 according to the second embodiment is the same as the first embodiment except for the configuration of the inspection circuit 80. Therefore, in the second embodiment, the inspection circuit 80 will be mainly described.

[0108] 13 is a diagram showing the inspection circuit 80 of the electro-optical device 10 according to the second embodiment. In the inspection circuit 80 of the second embodiment, the tournament circuits 82 and amplifiers 84 are grouped in groups of four, starting from the left in the figure. Therefore, if the number of tournament circuits 82 is 48, the same as in the first embodiment, the number of groups is "12." In the second embodiment, there are four test output terminals 88, and wiring 87 is electrically connected to each test output terminal 88. In the second embodiment, switch circuits 85 are provided in one-to-one correspondence with the 12 groups. Selection signals Sctl_1 to Sct_12 are supplied to the 12 switch circuits 85 from the left, for example, from a tester, and each switch circuit 85 includes four switches. The four switches included in one switch circuit 85 are simultaneously turned on when the corresponding selection signals are at H level, and are simultaneously turned off when the corresponding selection signals are at L level.

[0109] One end of each switch is connected to the output terminal of the amplifier 84, and the other end of each switch is connected to one of the four wires 87 in the following relationship: In detail, of the four tournament circuits 82 belonging to one group, the other end of a switch having one end connected to the output terminal of the amplifier 84 corresponding to the first one counting from the left is connected to the first wire 87. The other end of a switch having one end connected to the output terminal of the amplifier 84 corresponding to the second one counting from the left is connected to the second wire 87. Similarly, the other end of a switch having one end connected to the output terminal of the amplifier 84 corresponding to the third one counting from the left is connected to the third wire 87, and the other end of a switch having one end connected to the output terminal of the amplifier 84 corresponding to the fourth one counting from the left is connected to the fourth wire 87.

[0110] In a test operation, the tester selects one of the 12 groups and sets only the selection signal for the selected group to level H. For example, when the tester selects the first group counting from the left, it sets only the selection signal Sct_1 of the selection signals Sct_1 to Sct_12 to level H and sets the other selection signals Sct_2 to Sct_12 to level L. During a period in which one group is selected, the tester selects one of the 122 data lines 14 using selection signals Sel_1a, Sel_1b, and Sel2 to Sel_7. The voltage of the selected data line 14 is amplified by an amplifier 84 and output from a test output terminal 88. Therefore, the tester checks whether the voltage output from the selected data line 14 is within a predetermined range. This check is performed while sequentially selecting the 122 data lines 14 and for each of the voltages output from the four test output terminals 88. Furthermore, the tester repeats such an operation while selecting each of the 12 groups in order, thereby checking whether or not the voltages output to the data lines 14 of the 5,856 columns are within a predetermined range.

[0111] According to the second embodiment, even if the number of voltages that the tester simultaneously measures is "4", which is smaller than "48", it is possible to measure voltages output from 5856 columns of data lines 14. In the second embodiment, similarly to the first embodiment, the parasitic capacitances of the 5856 data lines 14 are uniform during the display operation, so that the display unevenness shown in FIG. 12 can be suppressed.

[0112] In the above-described first and second embodiments (hereinafter referred to as "embodiments"), various modifications and applications are possible as follows.

[0113] In the embodiment and the like, the OLED 130 has been described as an example of the light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an LED, or a liquid crystal element combined with an illumination mechanism. In other words, the light-emitting element may be an electro-optical element that changes its optical state according to the voltage of the data line 14. In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 41, but the present invention is not limited to this.

[0114] In the embodiment and the like, the threshold voltage of the transistor 121 in the pixel circuit 110 is compensated for, but the threshold voltage may not be compensated for, specifically, the transistor 123 may be omitted. The channel type of the transistors 121 to 124, 611, 612, and 614 is not limited to that in the embodiment. The transistors 121 to 124, 611, 612, and 614 may be replaced with transmission gates as appropriate. Conversely, the transmission gates 613, Swa, Swb, Swc, and Swd may be replaced with transistors of one channel type.

[0115] Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

[0116] FIG. 14 is a diagram showing the appearance of a head mounted display, and FIG. 15 is a diagram showing the optical configuration thereof. First, as shown in Fig. 14, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. Also, as shown in Fig. 15, the head mounted display 300 has an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure). The image display surface of the electro-optical device 10L is disposed to the left in FIG. 15. As a result, the image displayed by the electro-optical device 10L is output in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed to the right, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is output in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

[0117] In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head mounted display 300, when the electro-optical device 10L displays an image for the left eye and the electro-optical device 10R displays an image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0118] In addition, electronic devices including the electro-optical device 10 can be applied to electronic viewfinders in video cameras and interchangeable lens digital cameras, portable information terminals, display units of wristwatches, light bulbs of projection projectors, and the like, in addition to the head mounted display 300.

[0119] From the above-mentioned exemplary embodiments, the following aspects can be understood, for example.

[0120] A driving circuit for an electro-optical device according to one aspect (aspect 1) includes a first conversion circuit that converts first gradation data into an analog signal and supplies it to a first data line, a second conversion circuit that converts second gradation data into an analog signal and supplies it to a second data line, a third conversion circuit that converts third gradation data into an analog signal and supplies it to a third data line, a fourth conversion circuit that converts fourth gradation data into an analog signal and supplies it to a fourth data line, a tournament circuit including a first selection circuit, a second selection circuit, and a third selection circuit, and a test output terminal, and in a first operation, the first selection circuit selects the first data line or the second data line and electrically connects it to one input terminal of the third selection circuit. the second selection circuit selects the third data line or the fourth data line and electrically connects it to the other input end of the third selection circuit, the third selection circuit selects the one input end or the other input end and, when a predetermined condition is satisfied, outputs the tournament circuit, a voltage based on the selection of the tournament circuit appears at the test output terminal, and in a second operation, the first selection circuit electrically disconnects both the first data line and the second data line from one input end of the third selection circuit, and the second selection circuit electrically disconnects both the third data line and the fourth data line from the other input end of the third selection circuit. According to the first aspect, it is possible to suppress display unevenness caused by the parasitic capacitance of the data line.

[0121] The inspection operation is an example of a first operation, and the display operation is an example of a second operation. The data line 14 in the first column is an example of a first data line, the data line 14 in the second column is an example of a second data line, the data line 14 in the third column is an example of a third data line, and the data line 14 in the fourth column is an example of a fourth data line. The DA conversion circuit 41 corresponding to the first column is an example of a first conversion circuit, the DA conversion circuit 41 corresponding to the second column is an example of a second conversion circuit, the DA conversion circuit 41 corresponding to the third column is an example of a third conversion circuit, and the DA conversion circuit 41 corresponding to the fourth column is an example of a fourth conversion circuit. In the tournament circuit 82, the selection circuit 821 in the first layer that inputs the data line 14 in the first column and the data line 14 in the second column is an example of a first selection circuit, and the selection circuit 821 in the second layer that inputs the data line 14 in the third column and the data line 14 in the fourth column is an example of a second selection circuit. Also, the selection circuit 822 in the second layer, the first one counting from the left in FIG. 8, is an example of a third selection circuit. The specified condition refers to the condition under which the selection result in the third selection circuit ultimately becomes the output of the tournament circuit, specifically, the condition under which the first selection circuit 822 in the second hierarchical layer is selected by the first selection circuits 823-837 in the third to seventh hierarchical layers.

[0122] In a driving circuit of an electro-optical device which is a specific aspect 2 of aspect 1, the first selection circuit includes a first switching element which is turned on or off based on a first selection signal between the first data line and one input end of the third selection circuit, and a second switching element which is turned on or off based on a second selection signal between the second data line and one input end of the third selection circuit, and the second selection circuit includes a third switching element which is turned on or off based on the first selection signal between the third data line and the other input end of the third selection circuit, and a fourth switching element which is turned on or off based on the second selection signal between the fourth data line and the other input end of the third selection circuit. In the first selection circuit 821, the transmission gate Swa is an example of a first switching element, and the transmission gate Swb is an example of a second switching element. In the second selection circuit 821, the transmission gate Swa is an example of a third switching element, and the transmission gate Swb is an example of a fourth switching element. The selection signal Sel_1a is an example of a first selection signal, and the selection signal Sel_1b is an example of a second selection signal.

[0123] In the drive circuit of the electro-optical device according to the specific mode 3 of mode 2, an amplifier that amplifies the signal selected by the tournament circuit and supplies it to the test output terminal is included. According to mode 3, even when the output impedance of the data line 14 is high, the voltage of the data line 14 can be accurately measured.

[0124] In the drive circuit of the electro-optical device according to another specific mode 4 of mode 1, the number of tournament circuits is p (p is an integer of 2 or more), the number of test output terminals is q (q is an integer satisfying q < p), and a switch circuit that selects q signals out of the signals based on the p tournament circuits and electrically connects them one-to-one to the q test output terminals is included. According to mode 4, signals selected by a plurality of tournament circuits can be measured at a small number of test output terminals.

[0125] In the drive circuit of the electro-optical device according to the specific mode 5 of mode 4, q amplifiers that amplify the signals selected by the p tournament circuits and output them as signals based on the p tournament circuits are included. According to mode 5, even when the output impedance of the data line 14 is high, the voltage of the data line 14 can be accurately measured.

[0126] The electro-optical device of aspect 6 includes a scanning line driving circuit for selecting a scanning line, and has a first pixel circuit arranged corresponding to the intersection of the scanning line and the first data line and including a light-emitting element that emits light in response to the voltage of the first data line when the scanning line is selected, a second pixel circuit arranged corresponding to the intersection of the scanning line and the second data line and including a light-emitting element that emits light in response to the voltage of the second data line when the scanning line is selected, a third pixel circuit arranged corresponding to the intersection of the scanning line and the third data line and including a light-emitting element that emits light in response to the voltage of the third data line when the scanning line is selected, and a fourth pixel circuit arranged corresponding to the intersection of the scanning line and the fourth data line and including a light-emitting element that emits light in response to the voltage of the fourth data line when the scanning line is selected. A pixel circuit 110 corresponding to an intersection of a scanning line in a certain row and a data line in a first column is an example of a first pixel circuit, a pixel circuit 110 corresponding to an intersection of a scanning line in a certain row and a data line in a second column is an example of a second pixel circuit, a pixel circuit 110 corresponding to an intersection of a scanning line in a certain row and a data line in a third column is an example of a third pixel circuit, and a pixel circuit 110 corresponding to an intersection of a scanning line in a certain row and a data line in a fourth column is an example of a fourth pixel circuit.

[0127] An electronic device according to a seventh aspect includes the electro-optical device according to the sixth aspect. [Explanation of symbols]

[0128] 10...electro-optical device, 12...scanning line, 14...data line, 20...control circuit, 40...data signal output circuit, 41...DA conversion circuit, 60...initialization circuit, 82...tournament circuit, 84...amplifier, 85...switch circuit, 88...test output terminal, 110, 110R, 110G, 110B...pixel circuit, 120...scanning line driving circuit, 821 to 827...selection circuit, Swa, Swb...transmission gate.

Claims

1. a first conversion circuit that converts the first gradation data into an analog signal and supplies the analog signal to a first data line; a second conversion circuit that converts the second gradation data into an analog signal and supplies the analog signal to a second data line; a third conversion circuit that converts the third gradation data into an analog signal and supplies the analog signal to a third data line; a fourth conversion circuit that converts the fourth gradation data into an analog signal and supplies the analog signal to a fourth data line; a tournament circuit including a first selection circuit, a second selection circuit, and a third selection circuit; A test output terminal; Including, In the first operation, The first selection circuit is selecting the first data line or the second data line and electrically connecting it to one input terminal of the third selection circuit; The second selection circuit is Selecting the third data line or the fourth data line and electrically connecting it to the other input terminal of the third selection circuit; The third selection circuit is Select the one input terminal or the other input terminal, and when a predetermined condition is satisfied, output the selected terminal as the tournament circuit output; A voltage based on the selection of the tournament circuit appears at the test output terminal, In the second operation, The first selection circuit is electrically disconnecting both the first data line and the second data line from one input terminal of the third selection circuit; The second selection circuit is Both the third data line and the fourth data line are electrically disconnected from the other input terminal of the third selection circuit. A driving circuit for an electro-optical device.

2. The first selection circuit is a first switching element that is turned on or off based on a first selection signal between the first data line and one input terminal of the third selection circuit; a second switching element that is turned on or off based on a second selection signal between the second data line and one input terminal of the third selection circuit; Including, The second selection circuit is a third switching element that is turned on or off based on the first selection signal and is disposed between the third data line and the other input terminal of the third selection circuit; a fourth switching element that is turned on or off based on the second selection signal between the fourth data line and the other input terminal of the third selection circuit; Includes 2. A driving circuit for an electro-optical device according to claim 1.

3. an amplifier that amplifies the signal selected by the tournament circuit and supplies the signal to the test output terminal; 3. A driving circuit for an electro-optical device according to claim 2.

4. The number of tournament circuits is p (p is an integer of 2 or more), the number of test output terminals is q (q is an integer satisfying q<p); Selecting q signals from the p tournament circuits, A switch circuit electrically connected to the q test output terminals in a one-to-one manner is included.

2. A driving circuit for an electro-optical device according to claim 1.

5. A number of q amplifiers are included which amplify the signals selected by the number of p tournament circuits and output the signals as signals based on the number of p tournament circuits.

5. A driving circuit for an electro-optical device according to claim 4.

6. The driving circuit for an electro-optical device according to claim 1 comprises: a scanning line driver circuit for selecting a scanning line; a first pixel circuit including a light emitting element provided at a location corresponding to an intersection of the scanning line and the first data line, the light emitting element emitting light in response to a voltage of the first data line when the scanning line is selected; a second pixel circuit including a light emitting element provided at a location corresponding to an intersection of the scanning line and the second data line, the light emitting element emitting light in response to a voltage of the second data line when the scanning line is selected; a third pixel circuit including a light emitting element provided at a location corresponding to an intersection of the scanning line and the third data line, the light emitting element emitting light in response to a voltage of the third data line when the scanning line is selected; a fourth pixel circuit including a light emitting element provided at a location corresponding to an intersection of the scanning line and the fourth data line, the light emitting element emitting light in response to a voltage of the fourth data line when the scanning line is selected; An electro-optical device having

7. An electronic device comprising the electro-optical device according to claim 6.

Images