Plasma processing apparatus, power supply system, and plasma processing method

Abstract

To provide a technique of supplying ions with different energy to a substrate.SOLUTION: A plasma processing apparatus includes a chamber, a substrate supporter, and a power source system. The substrate supporter includes an electrode and is configured to support a substrate in the chamber. The power source system is electrically connected to the electrode. The power source system is configured to output a first pulse as bias voltage to the electrode in a first period and output a second pulse to the electrode in a second period after the first period. The first pulse and the second pulse are voltage pulses. The voltage level of the first pulse is different from the voltage level of the second pulse.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Exemplary embodiments of the present disclosure relate to a plasma processing apparatus and a plasma processing method. [Background technology]

[0002] A plasma processing apparatus is used in plasma processing of a substrate. The plasma processing apparatus includes a chamber and a substrate holding electrode. The substrate holding electrode is provided in the chamber. The substrate holding electrode holds a substrate placed on a main surface of the substrate holding electrode. One type of such a plasma processing apparatus is described in Japanese Patent Application Laid-Open No. 2009-187975 (hereinafter referred to as "Patent Document 1").

[0003] The plasma processing apparatus described in Patent Document 1 further includes a radio frequency generator and a DC negative pulse generator. The radio frequency generator applies a radio frequency voltage to a substrate holding electrode. In the plasma processing apparatus described in Patent Document 1, the radio frequency voltage is alternately switched on and off. In addition, in the plasma processing apparatus described in Patent Document 1, a DC negative pulse voltage is applied from the DC negative pulse generator to the substrate holding electrode in accordance with the timing of turning on and off the radio frequency voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-187975 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides techniques for delivering ions having different energies to a substrate. [Means for solving the problem]

[0006] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, and a power system. The substrate support has an electrode and is configured to support a substrate in the chamber. The power system is electrically connected to the electrode of the substrate support and configured to apply a bias voltage to the electrode of the substrate support to attract ions from the plasma in the chamber to a substrate on the substrate support. The power system is configured to output a first pulse to the electrode of the substrate support for a first period as the bias voltage, and to output a second pulse to the electrode of the substrate support for a second period after the first period. Each of the first pulse and the second pulse is a pulse of voltage. A voltage level of the first pulse is different from a voltage level of the second pulse. Effect of the Invention

[0007] According to one exemplary embodiment, it is possible to provide ions having different energies to the substrate. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating a plasma processing apparatus according to an exemplary embodiment; [Diagram 2] 4 is a timing chart of a bias voltage in the first example. [Diagram 3] 13 is a timing chart of the bias voltage in the second example. [Figure 4] 13 is a timing chart of the bias voltage in the third example. [Diagram 5] 13 is a timing chart of the bias voltage in the fourth example. [Figure 6] 13 is a timing chart of the bias voltage in the fifth example. [Figure 7] FIG. 1 illustrates a power supply system according to an exemplary embodiment. [Figure 8] FIG. 1 illustrates a power supply system according to another exemplary embodiment. [Figure 9] 13A and 13B illustrate configurations of a substrate support according to another exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Various exemplary embodiments are described below.

[0010] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, and a power system. The substrate support has an electrode and is configured to support a substrate in the chamber. The power system is electrically connected to the electrode of the substrate support and configured to apply a bias voltage to the electrode of the substrate support to attract ions from the plasma in the chamber to a substrate on the substrate support. The power system is configured to output a first pulse to the electrode of the substrate support for a first period as the bias voltage, and to output a second pulse to the electrode of the substrate support for a second period after the first period. Each of the first pulse and the second pulse is a pulse of voltage. A voltage level of the first pulse is different from a voltage level of the second pulse.

[0011] In the above embodiment, the voltage level of the first pulse is different from the voltage level of the second pulse. Therefore, the energy of the ions supplied from the plasma to the substrate in the first period is different from the energy of the ions supplied from the plasma to the substrate in the second period. Therefore, according to the above embodiment, it is possible to supply ions having different energies to the substrate.

[0012] In one exemplary embodiment, the second period may be consecutive to the first period. Each of the first pulse and the second pulse may be a negative polarity voltage pulse. An absolute value of the voltage level of the first pulse may be less than an absolute value of the voltage level of the second pulse.

[0013] In one exemplary embodiment, each of the first pulse and the second pulse may be a negative polarity voltage pulse. An absolute value of a voltage level of the first pulse may be greater than an absolute value of a voltage level of the second pulse. The power supply system may be configured such that an output voltage to the electrode of the substrate support is 0V during a period between the first period and the second period.

[0014] In one exemplary embodiment, the second period may be consecutive to the first period. Each of the first pulse and the second pulse may be a negative polarity voltage pulse. An absolute value of the voltage level of the first pulse may be greater than an absolute value of the voltage level of the second pulse.

[0015] In one exemplary embodiment, the power supply system may be configured to output a third pulse to the electrode of the substrate support during a third time period after the second time period. The third pulse may be a negative polarity voltage pulse. An absolute value of the voltage level of the third pulse may be greater than an absolute value of the voltage level of the second pulse. An absolute value of the voltage level of the third pulse may be the same as an absolute value of the voltage level of the first pulse.

[0016] In one exemplary embodiment, the power supply system may be configured to output a positive voltage pulse to the electrode of the substrate support before the start of a first period in a subsequent period of two periods, each period including a first period and a second period. According to this embodiment, when the positive voltage pulse is output to the electrode of the substrate support, electrons are supplied to the substrate. As a result, the amount of positive charge on the substrate is reduced.

[0017] In one exemplary embodiment, the power supply system may be configured to output a first pulse intermittently to the electrode of the substrate support during a first time period. The power supply system may be configured to output a second pulse intermittently to the electrode of the substrate support during a second time period.

[0018] In one exemplary embodiment, each of the first pulse and the second pulse may be a negative voltage pulse. The power supply system may be configured to alternately output the first pulse and the positive voltage pulse to the electrode of the substrate support during a first period. The power supply system may be configured to alternately output the second pulse and the positive voltage pulse to the electrode of the substrate support during a second period. According to this embodiment, electrons are supplied to the substrate when the positive voltage pulse is output to the electrode of the substrate support. As a result, the amount of positive charge on the substrate is reduced.

[0019] In one exemplary embodiment, the power supply system may be configured to output a pulse of positive voltage to the electrode of the substrate support during a period between the first period and the second period. According to this embodiment, when the pulse of positive voltage is output to the electrode of the substrate support, electrons are supplied to the substrate. As a result, the amount of positive charge on the substrate is reduced.

[0020] In another exemplary embodiment, a plasma processing method is provided. The plasma processing method includes providing a substrate on a substrate support disposed in a chamber of a plasma processing apparatus. The substrate support includes an electrode. The plasma processing method further includes outputting a first pulse from a power supply system to the electrode of the substrate support for a first period as a bias voltage for attracting ions from the plasma in the chamber to the substrate. The plasma processing method further includes outputting a second pulse from the power supply system to the electrode of the substrate support for a second period as a bias voltage. Each of the first pulse and the second pulse is a pulse of voltage. The voltage level of the first pulse is different from the voltage level of the second pulse.

[0021] In one exemplary embodiment, the second period may be consecutive to the first period. Each of the first pulse and the second pulse may be a negative polarity voltage pulse. An absolute value of the voltage level of the first pulse may be less than an absolute value of the voltage level of the second pulse.

[0022] In one exemplary embodiment, each of the first pulse and the second pulse may be a negative polarity voltage pulse. An absolute value of a voltage level of the first pulse may be greater than an absolute value of a voltage level of the second pulse. The plasma processing method may further include setting an output voltage from the power supply system to an electrode of the substrate support to 0 V during a period between the first period and the second period.

[0023] In one exemplary embodiment, the second period may be consecutive to the first period. Each of the first pulse and the second pulse may be a negative polarity voltage pulse. An absolute value of the voltage level of the first pulse may be greater than an absolute value of the voltage level of the second pulse.

[0024] In one exemplary embodiment, the plasma processing method may further include outputting a third pulse from the power supply system to the electrode of the substrate support during a third period after the second period. The third pulse may be a pulse of a negative polarity voltage. The absolute value of the voltage level of the third pulse may be greater than the absolute value of the voltage level of the second pulse. The absolute value of the voltage level of the third pulse may be the same as the absolute value of the voltage level of the first pulse.

[0025] In one exemplary embodiment, the plasma processing method may further include outputting a positive polarity voltage pulse from the power supply system to an electrode of the substrate support before the start of a first period in a subsequent period of two periods, each period including a first period and a second period.

[0026] In one exemplary embodiment, a first pulse may be intermittently output from the power supply system to the electrode of the substrate support during a first period of time, and a second pulse may be intermittently output from the power supply system to the electrode of the substrate support during a second period of time.

[0027] In one exemplary embodiment, each of the first pulse and the second pulse may be a negative voltage pulse. The plasma processing method may further include intermittently outputting a positive voltage pulse from a power supply system to an electrode of a substrate support during a first period. The positive voltage pulse may be output alternately with the first pulse. The plasma processing method may further include intermittently outputting a positive voltage pulse from a power supply system to an electrode of a substrate support during a second period. The positive voltage pulse may be output alternately with the second pulse.

[0028] In one exemplary embodiment, the plasma processing method may further include outputting a positive polarity voltage pulse from the power supply system to an electrode of the substrate support during a period between the first period and the second period.

[0029] Various exemplary embodiments will now be described in detail with reference to the drawings, in which the same or corresponding parts are designated by the same reference numerals.

[0030] Fig. 1 is a schematic diagram of a plasma processing apparatus according to an exemplary embodiment. The plasma processing apparatus 1 shown in Fig. 1 is a capacitively coupled plasma processing apparatus. The plasma processing apparatus 1 includes a chamber 10. The chamber 10 provides an internal space 10s therein. The central axis of the chamber 10 is an axis AX, which extends in the vertical direction.

[0031] In one embodiment, the chamber 10 may include a chamber body 12. The chamber body 12 has a substantially cylindrical shape. An internal space 10s is provided in the chamber body 12. The chamber body 12 is made of, for example, aluminum. The chamber body 12 is electrically grounded. A plasma-resistant film is formed on the inner wall surface of the chamber body 12, i.e., the wall surface defining the internal space 10s. This film may be a ceramic film, such as a film formed by anodization or a film formed from yttrium oxide.

[0032] A passage 12p is formed in the sidewall of the chamber body 12. The substrate W passes through the passage 12p when being transferred between the internal space 10s and the outside of the chamber 10. A gate valve 12g is provided along the sidewall of the chamber body 12 to open and close the passage 12p.

[0033] The plasma processing apparatus 1 further includes a substrate support 16. The substrate support 16 is configured to support a substrate W placed thereon in the chamber 10. The substrate W has a substantially disk shape. The substrate support 16 may be supported by a support 15. The support 15 extends upward from the bottom of the chamber body 12. The support 15 has a substantially cylindrical shape. The support 15 is made of an insulating material such as quartz.

[0034] The substrate support 16 has a lower electrode 18. The substrate support 16 may further have an electrostatic chuck 20. The substrate support 16 may further have an electrode plate 19. The electrode plate 19 is made of a conductive material such as aluminum and has a substantially disk-like shape. The lower electrode 18 is provided on the electrode plate 19. The lower electrode 18 is made of a conductive material such as aluminum and has a substantially disk-like shape. The lower electrode 18 is electrically connected to the electrode plate 19. The central axes of the lower electrode 18 and the electrode plate 19 substantially coincide with the axis AX.

[0035] The lower electrode 18 provides a flow path 18f therein. The flow path 18f is a flow path for a heat exchange medium. For example, a refrigerant is used as the heat exchange medium. A circulation device (for example, a chiller unit) for the heat exchange medium is connected to the flow path 18f. This circulation device is provided outside the chamber 10. The heat exchange medium from the circulation device is supplied to the flow path 18f via a pipe 23a. The heat exchange medium supplied to the flow path 18f is returned to the circulation device via a pipe 23b.

[0036] The electrostatic chuck 20 is provided on the lower electrode 18. When the substrate W is processed in the internal space 10s, it is placed on the electrostatic chuck 20 so that its center is located on the axis line AX. The electrostatic chuck 20 is configured to hold the substrate. The electrostatic chuck 20 has a body and an electrode. The body of the electrostatic chuck 20 is formed from a dielectric material such as aluminum oxide or aluminum nitride. The body of the electrostatic chuck 20 has a substantially disk shape. The central axis line of the electrostatic chuck 20 substantially coincides with the axis line AX.

[0037] The electrodes of the electrostatic chuck 20 are provided within the body of the electrostatic chuck 20. The electrodes of the electrostatic chuck 20 are films formed from a conductor. A DC power supply is electrically connected to the electrodes of the electrostatic chuck 20. When a DC voltage is applied from the DC power supply to the electrodes of the electrostatic chuck 20, an electrostatic attractive force is generated between the electrostatic chuck 20 and the substrate W. The generated electrostatic attractive force attracts the substrate W to the electrostatic chuck 20 and the substrate W is held by the electrostatic chuck 20.

[0038] The substrate support 16 may further support an edge ring ER mounted thereon. The edge ring ER has an annular shape and is made of, for example, silicon or silicon carbide. The edge ring ER is mounted on the substrate support 16 such that its central axis is located on the axis AX. In one embodiment, the edge ring ER may be partially mounted on the electrostatic chuck 20. Note that the substrate W is disposed on the electrostatic chuck 20 and within a region surrounded by the edge ring ER.

[0039] The plasma processing apparatus 1 may further include a gas supply line 25. The gas supply line 25 supplies a heat transfer gas, for example, He gas, from a gas supply mechanism to a gap between the upper surface of the electrostatic chuck 20 and the rear surface (lower surface) of the substrate W.

[0040] The plasma processing apparatus 1 may further include a cylindrical portion 28 and an insulating portion 29. The cylindrical portion 28 extends upward from the bottom of the chamber body 12. The cylindrical portion 28 extends along the outer periphery of the support 15. The cylindrical portion 28 is made of a conductive material and has a substantially cylindrical shape. The cylindrical portion 28 is electrically grounded. The insulating portion 29 is provided on the cylindrical portion 28. The insulating portion 29 is made of an insulating material. The insulating portion 29 is made of a ceramic such as quartz. The insulating portion 29 has a substantially cylindrical shape. The insulating portion 29 extends along the outer periphery of the electrode plate 19, the outer periphery of the lower electrode 18, and the outer periphery of the electrostatic chuck 20.

[0041] The plasma processing apparatus 1 further includes an upper electrode 30. The upper electrode 30 is provided above the substrate support 16. The upper electrode 30 closes the upper opening of the chamber body 12 together with a member 32. The member 32 is made of an insulating material. The upper electrode 30 is supported on the upper part of the chamber body 12 via the member 32.

[0042] The upper electrode 30 may include a top plate 34 and a support 36. The lower surface of the top plate 34 defines an internal space 10s. A plurality of gas discharge holes 34a are formed in the top plate 34. The plurality of gas discharge holes 34a penetrate the top plate 34 in the plate thickness direction (vertical direction). The top plate 34 is made of, for example, silicon. Alternatively, the top plate 34 may have a structure in which a plasma-resistant film is provided on the surface of an aluminum member. This film may be a ceramic film, such as a film formed by anodizing or a film formed of yttrium oxide.

[0043] The support 36 detachably supports the top plate 34. The support 36 is made of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support 36. A plurality of gas holes 36b extend downward from the gas diffusion chamber 36a. The plurality of gas holes 36b are connected to the plurality of gas discharge holes 34a, respectively. A gas introduction port 36c is formed in the support 36. The gas introduction port 36c is connected to the gas diffusion chamber 36a. A gas supply pipe 38 is connected to the gas introduction port 36c.

[0044] The gas source group 40 is connected to the gas supply pipe 38 via the valve group 41, the flow rate controller group 42, and the valve group 43. The gas source group 40, the valve group 41, the flow rate controller group 42, and the valve group 43 configure a gas supply unit. The gas source group 40 includes a plurality of gas sources. Each of the valve group 41 and the valve group 43 includes a plurality of valves (e.g., on-off valves). The flow rate controller group 42 includes a plurality of flow rate controllers. Each of the plurality of flow rate controllers of the flow rate controller group 42 is a mass flow controller or a pressure control type flow rate controller. Each of the plurality of gas sources of the gas source group 40 is connected to the gas supply pipe 38 via a corresponding valve of the valve group 41, a corresponding flow rate controller of the flow rate controller group 42, and a corresponding valve of the valve group 43. The plasma processing apparatus 1 can supply gas from one or more gas sources selected from the plurality of gas sources of the gas source group 40 to the internal space 10s at individually adjusted flow rates.

[0045] A baffle member 48 may be provided between the cylindrical portion 28 and the side wall of the chamber body 12. The baffle member 48 may be a plate-shaped member. The baffle member 48 may be formed, for example, by coating an aluminum plate with ceramic such as yttrium oxide. The baffle member 48 has a plurality of through holes. Below the baffle member 48, an exhaust pipe 52 is connected to the bottom of the chamber body 12. An exhaust device 50 is connected to the exhaust pipe 52. The exhaust device 50 has a pressure controller such as an automatic pressure control valve and a vacuum pump such as a turbo molecular pump, and can reduce the pressure in the internal space 10s.

[0046] The plasma processing apparatus 1 further includes a high-frequency power supply 61. The high-frequency power supply 61 is a power supply that generates a first high-frequency power for generating plasma. The frequency of the first high-frequency power may be within a range of 27 to 100 MHz, for example, 40 MHz or 60 MHz. The high-frequency power supply 61 is connected to the lower electrode 18 via a matching device 61m and an electrode plate 19. The matching device 61m has a matching circuit for matching the impedance of the load side (lower electrode 18 side) of the high-frequency power supply 61 to the output impedance of the high-frequency power supply 61. Note that the high-frequency power supply 61 does not need to be electrically connected to the lower electrode 18, and may be connected to the upper electrode 30 via the matching device 61m.

[0047] The plasma processing apparatus 1 may further include a high-frequency power supply 62. The high-frequency power supply 62 is a power supply that generates a second high-frequency power. The frequency of the second high-frequency power is lower than the frequency of the first high-frequency power. The high-frequency power supply 62 is connected to the lower electrode 18 via a matching device 62m and an electrode plate 19. The matching device 62m has a matching circuit for matching the impedance of the load side (lower electrode 18 side) of the high-frequency power supply 62 to the output impedance of the high-frequency power supply 62. Note that the plasma processing apparatus 1 does not necessarily have to include the high-frequency power supply 62 and the matching device 62m.

[0048] In the plasma processing apparatus 1, a gas is supplied from a gas supply unit to the internal space 10s. Then, high-frequency power is supplied to excite the gas in the internal space 10s. As a result, plasma is generated in the internal space 10s. The substrate W is processed by chemical species such as ions and / or radicals from the plasma.

[0049] The plasma processing apparatus 1 further includes a power supply system 70. The power supply system 70 is electrically connected to the lower electrode 18. The power supply system 70 is configured to apply a bias voltage to the lower electrode 18 to attract ions from the plasma to the substrate on the substrate support 16. The power supply system 70 may be connected to the lower electrode 18 via a filter 70f. The filter 70f includes a filter circuit that blocks or reduces high frequency power directed to the power supply system 70. Details of the power supply system 70 will be described later.

[0050] The plasma processing apparatus 1 may further include a control unit MC. The control unit MC is a computer including a processor, a storage device, an input device, a display device, etc., and controls each part of the plasma processing apparatus 1. Specifically, the control unit MC executes a control program stored in the storage device, and controls each part of the plasma processing apparatus 1 based on recipe data stored in the storage device. Under the control of the control unit MC, a process specified by the recipe data is executed in the plasma processing apparatus 1. The plasma processing methods according to various embodiments can be executed in the plasma processing apparatus 1 under the control of each part of the plasma processing apparatus 1 by the control unit MC.

[0051] The bias voltages generated by the power supply system 70 will be described below with reference to Fig. 2 to Fig. 6. Fig. 2 to Fig. 6 are timing charts of bias voltages according to first to fifth examples, respectively. In addition, plasma processing methods according to various exemplary embodiments will be described below.

[0052] In various exemplary embodiments, the plasma processing method includes providing a substrate W on a substrate support 16. The plasma processing method is performed while the substrate W is placed on the substrate support 16.

[0053] The plasma processing method includes a step of generating plasma in the chamber 10. To generate plasma, a processing gas is supplied from a gas supply unit into the chamber 10. The pressure of the gas in the chamber 10 is adjusted to a designated pressure by the exhaust device 50. A first high frequency power is supplied from the high frequency power supply 61. As a result, plasma is generated from the processing gas in the chamber 10. During the generation of plasma, a second high frequency power from the high frequency power supply 62 may be supplied to the lower electrode 18. The steps of the plasma processing method described below are performed during the period when plasma is generated in the chamber 10.

[0054] As shown in FIGS. 2 to 6, the plasma processing method includes a step of outputting a first pulse PL1 as a bias voltage from a power supply system 70 to the lower electrode 18 in a first period P1. The first pulse PL1 is a voltage pulse. The first pulse PL1 may be a DC voltage pulse. The first pulse PL1 may have a waveform other than a rectangular wave, such as a triangular wave or an impulse wave. The first pulse may have a waveform whose voltage value changes at its leading edge and trailing edge.

[0055] As shown in FIGS. 2 to 6, the plasma processing method includes a step of outputting a second pulse PL2 as a bias voltage from a power supply system 70 to the lower electrode 18 in a second period P2. The second period P2 is a period following the first period P1. The second pulse PL2 is a voltage pulse. The voltage level of the first pulse PL1 is different from the voltage level of the second pulse PL2. The second pulse PL2 may be a DC voltage pulse. The second pulse PL2 may have a waveform other than a rectangular wave, such as a triangular wave or an impulse wave. The second pulse may have a waveform whose voltage value changes at its leading edge and trailing edge.

[0056] In the examples shown in each of FIG. 2 to FIG. 6, each of the first pulse PL1 and the second pulse PL2 is a pulse of a negative voltage (for example, a negative DC voltage). The difference between the voltage level of one of the first pulse PL1 and the second pulse PL2 (hereinafter referred to as an "H-level pulse") and a reference level (for example, 0V) may be 6 kV or more. The difference between the voltage level of the H-level pulse and the reference level may be 10 kV or 20 kV or more. The difference between the voltage level of the other of the first pulse PL1 and the second pulse PL2 (hereinafter referred to as an "L-level pulse") and a reference level (for example, 0V) may be 5 kV or less.

[0057] In the plasma processing method, a period CY may be repeated as shown in Figures 2 to 6. The period CY includes a first period P1 and a second period P2. In the first to third examples shown in Figures 2 to 4, the frequency defining the period CY may be a frequency not less than 100 kHz and not more than 1 MHz. In the fourth and fifth examples shown in Figures 5 to 6, the frequency defining the period CY may be not less than 0.2 Hz and not more than 1 Hz.

[0058] In one embodiment, the second period P2 may be continuous with the first period P1, as in the first example shown in Fig. 2. In this embodiment, the absolute value of the voltage level of the first pulse PL1 may be smaller than the absolute value of the voltage level of the second pulse PL2.

[0059] In the first example shown in FIG. 2, the reference level of the bias voltage is 0V. This reference level may have a positive or negative value. In the first example, as long as the difference between the reference level and the voltage level of the first pulse PL1 is smaller than the difference between the reference level and the voltage level of the second pulse PL2, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have any value. That is, in the first example, as long as the voltage level of the second pulse PL2 is lower than the voltage level of the first pulse PL1, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have any value.

[0060] In another embodiment, the absolute value of the voltage level of the first pulse PL1 may be greater than the absolute value of the voltage level of the second pulse PL2, as in a second example shown in Fig. 3. In this embodiment, the plasma processing method may further include setting the output voltage from the power supply system 70 to the lower electrode 18 to 0 V in a period PG1 between the first period P1 and the second period P2.

[0061] In the second example shown in FIG. 3, the reference level of the bias voltage is 0V. This reference level may have a positive or negative value. In the second example, as long as the difference between the reference level and the voltage level of the first pulse PL1 is greater than the difference between the reference level and the voltage level of the second pulse PL2, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have any value. That is, in the second example, as long as the voltage level of the first pulse PL1 is lower than the voltage level of the second pulse PL2, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have any value.

[0062] In yet another embodiment, the second period P2 may be continuous with the first period P1, as in a third example shown in Fig. 4. In this embodiment, the absolute value of the voltage level of the first pulse PL1 may be greater than the absolute value of the voltage level of the second pulse PL2.

[0063] In yet another embodiment, as in a third example shown in FIG. 4, the plasma processing method may further include a step of outputting a third pulse PL3 from the power supply system 70 to the lower electrode 18 in a third period P3 after the second period P2. The third pulse PL3 may be a negative voltage pulse, and the absolute value of the voltage level of the third pulse PL3 may be greater than the absolute value of the voltage level of the second pulse PL2. The absolute value of the voltage level of the third pulse PL3 may be the same as the absolute value of the voltage level of the first pulse PL1. That is, the third pulse PL3 may be an H-level pulse. The difference between the voltage level of the third pulse PL3 and a reference level (e.g., 0V) may be 6 kV or more. The difference between the voltage level of the third pulse PL3 and the reference level may be 10 kV or 20 kV or more.

[0064] In the third example shown in FIG. 4, the reference level of the bias voltage is 0V. This reference level may have a positive or negative value. In the third example, if the difference between the reference level and the voltage level of the first pulse PL1 is greater than the difference between the reference level and the voltage level of the second pulse PL2, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have an arbitrary value. That is, in the third example, if the voltage level of the first pulse PL1 is lower than the voltage level of the second pulse PL2, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have an arbitrary value. Also, in the third example, if the difference between the reference level and the voltage level of the third pulse PL3 is greater than the difference between the reference level and the voltage level of the second pulse PL2, the voltage level of the third pulse PL3 and the voltage level of the second pulse PL2 may each have an arbitrary value. That is, in the third example, as long as the voltage level of the third pulse PL3 is lower than the voltage level of the second pulse PL2, the voltage level of the third pulse PL3 and the voltage level of the second pulse PL2 may each have any value.

[0065] In yet another embodiment, the plasma processing method may further include a step of outputting a positive voltage pulse PPL, as in the first to third examples shown in FIGS. 2 to 4. The voltage level of the voltage pulse PPL is higher than a reference level (e.g., 0 V). The voltage pulse PPL may be a positive DC voltage pulse. The pulse PPL is output during a period PP. The period PP is a period before the start of a first period P1 in a subsequent period CY of any two consecutive periods CY. The period PP may be a period immediately before the subsequent first period P1. In this case, it is possible to supply ions having high energy to the substrate W during the subsequent first period P1.

[0066] In the first example shown in Fig. 2, the period PP is the period after the period PG. In the first example shown in Fig. 2, the period PG is the period after the second period P2. In the first example shown in Fig. 2, during the period PG, the output voltage from the power supply system 70 to the lower electrode 18 is set to 0 V (i.e., the reference level).

[0067] In the second example shown in Fig. 3, the period PP is the period after the period PG2. In the second example shown in Fig. 3, the period PG2 is the period after the second period P2. In the second example shown in Fig. 3, in the period PG2, the output voltage from the power supply system 70 to the lower electrode 18 is set to 0V.

[0068] In the third example shown in Figure 4, the period PP is the period after the period PG. In the third example shown in Figure 4, the period PG is the period after the third period P3. In the third example shown in Figure 4, during the period PG, the output voltage from the power supply system 70 to the lower electrode 18 is set to 0V (i.e., the reference level).

[0069] In still another embodiment, as in a fourth example shown in Fig. 5 and a fifth example shown in Fig. 6, the first pulse PL1 may be intermittently output from the power supply system 70 to the lower electrode 18 in the first period P1. The first pulse PL1 may be periodically output from the power supply system 70 to the lower electrode 18 in the first period P1. The first pulse PL1 is output in a subperiod SP1 in the first period P1. The first pulse PL1 may be periodically output at a frequency of 100 kHz or more and 1 MHz or less.

[0070] In still another embodiment, as in a fourth example shown in Fig. 5 and a fifth example shown in Fig. 6, the second pulse PL2 may be intermittently output from the power supply system 70 to the lower electrode 18 in the second period P2. The second pulse PL2 may be periodically output from the power supply system 70 to the lower electrode 18 in the second period P2. The second pulse PL2 is output in a subperiod SP2 in the second period P2. The second pulse PL2 may be periodically output at a frequency of 100 kHz or more and 1 MHz or less.

[0071] In the fourth example shown in Fig. 5 and the fifth example shown in Fig. 6, the absolute value of the voltage level of the first pulse PL1 is greater than the absolute value of the voltage level of the second pulse PL2. The absolute value of the voltage level of the first pulse PL1 may be smaller than the absolute value of the voltage level of the second pulse PL2.

[0072] 5, the reference level of the bias voltage is also 0V. This reference level may have a positive or negative value. In the fourth example, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have any value, as long as the difference between the reference level and the voltage level of the first pulse PL1 is different from the difference between the reference level and the voltage level of the second pulse PL2.

[0073] In yet another embodiment, the plasma processing method may further include a step of intermittently outputting a positive voltage pulse PPL1 from the power supply system 70 to the lower electrode 18 in the first period P1, as in a fourth example shown in FIG. 5. The voltage level of the voltage pulse PPL1 is higher than a reference level (e.g., 0 V). The voltage pulse PPL1 may be a positive DC voltage pulse. In this embodiment, the positive voltage pulse PPL1 may be output alternately with the first pulse PL1. The positive voltage pulse PPL1 is output in the period SPP1. The period SPP1 may be a period following the period SPG1. The period SPG1 is a period following the sub-period SP1. In the period SPG1, the output voltage from the power supply system 70 to the lower electrode 18 may be set to 0 V (i.e., the reference level). The period SPP1 may be a period immediately before the subsequent sub-period SP1. In this case, it becomes possible to supply ions having high energy to the substrate W in the subsequent sub-period SP1.

[0074] In yet another embodiment, the plasma processing method may further include a step of intermittently outputting a positive voltage pulse PPL2 from the power supply system 70 to the lower electrode 18 in the second period P2, as in a fourth example shown in FIG. 5. The voltage level of the voltage pulse PPL2 is higher than a reference level (e.g., 0 V). The voltage pulse PPL2 may be a positive DC voltage pulse. In this embodiment, the positive voltage pulse PPL2 may be output alternately with the second pulse PL2. The positive voltage pulse PPL2 is output in the period SPP2. The period SPP2 may be a period following the period SPG2. The period SPG2 is a period following the sub-period SP2. In the period SPG2, the output voltage from the power supply system 70 to the lower electrode 18 may be set to 0 V (i.e., the reference level). The period SPP2 may be a period immediately before the subsequent sub-period SP2. In this case, it becomes possible to supply ions having high energy to the substrate W in the subsequent sub-period SP2.

[0075] In yet another embodiment, the plasma processing method may further include a step of outputting a positive voltage pulse PPL1 from the power supply system 70 to the lower electrode 18 in a period SPP1 between the first period P1 and the second period P2, as in a fifth example shown in FIG. 6. The voltage level of the voltage pulse PPL1 is higher than a reference level (e.g., 0 V). The voltage pulse PPL1 may be a positive DC voltage pulse. The period SPP1 may be a period immediately before the subsequent sub-period SP2. In this case, ions having high energy can be supplied to the substrate W in the subsequent sub-period SP2.

[0076] In yet another embodiment, the plasma processing method may further include a step of outputting a positive voltage pulse PPL2 from the power supply system 70 to the lower electrode 18 during a period SPP2, as in a fifth example shown in FIG. 6. The voltage level of the voltage pulse PPL2 is higher than a reference level (e.g., 0 V). The voltage pulse PPL2 may be a positive DC voltage pulse. The period SPP2 is a period between the second period P2 and the subsequent first period P1. The period SPP2 may be a period immediately before the subsequent sub-period SP1. In this case, it is possible to supply ions having high energy to the substrate W during the subsequent sub-period SP1.

[0077] 6, the reference level of the bias voltage is 0V. This reference level may have a positive or negative value. In the fifth example, the voltage level of the first pulse PL1 and the voltage level of the second pulse PL2 may each have an arbitrary value, as long as the difference between the reference level and the voltage level of the first pulse PL1 is different from the difference between the reference level and the voltage level of the second pulse PL2.

[0078] In the various exemplary embodiments described above, the energy of the ions supplied from the plasma to the substrate W in the first period P1 is different from the energy of the ions supplied from the plasma to the substrate W in the second period P2. Therefore, it is possible to supply ions having different energies to the substrate W.

[0079] Also, in some exemplary embodiments, a pulse of a positive DC voltage is supplied to the lower electrode 18. By supplying a pulse of a positive DC voltage to the lower electrode 18, electrons are supplied to the substrate W. As a result, the amount of positive charge on the substrate W is reduced.

[0080] When the film on the substrate W is etched using the bias voltages of the first to third examples to form an opening in the substrate W, deposits on the substrate W can be removed and the shape of the opening can be adjusted during the period when the L level pulse is supplied. In this case, ions can be supplied to the bottom of a deep opening during the period when the H level pulse is supplied.

[0081] The bias voltages of the fourth and fifth examples can be used for etching a multilayer film having different film types. The bias voltages of the fourth and fifth examples can be used for etching in the manufacture of a NAND device, for example. In the manufacture of a NAND device, a multilayer film including an alternating stack of a silicon oxide film and a silicon nitride film or a polycrystalline silicon film is etched. The silicon oxide film can be etched with ions of relatively high energy, and the silicon nitride film or the polycrystalline silicon film can be etched with ions of relatively low energy. When the bias voltages of the fourth and fifth examples are used, the silicon oxide film can be etched in the first period P1, and the silicon nitride film or the polycrystalline silicon film can be etched in the second period P2.

[0082] Hereinafter, power supply systems according to some exemplary embodiments that can be employed as the power supply system 70 of the plasma processing apparatus 1 will be described.

[0083] Fig. 7 is a diagram showing a power supply system according to an exemplary embodiment. A power supply system 70A shown in Fig. 7 can be employed as the power supply system 70 of the plasma processing apparatus 1. The power supply system 70A can output the bias voltages of the first to fifth examples described above. The power supply system 70A can include a DC power supply 71, a pulse unit 72, and a pulse controller PC.

[0084] The DC power supply 71 is a power supply that generates a negative DC voltage. The positive electrode of the DC power supply 71 is connected to the ground. The DC power supply 71 may be a variable DC power supply.

[0085] The pulse unit 72 is configured to generate a voltage pulse from a negative polarity DC voltage from the DC power supply 71. In one embodiment, the pulse unit 72 may include one or more switching transistors 72a, one or more switching transistors 72b, a diode 72c, and a diode 72d.

[0086] One or more switching transistors 72a are connected between the positive pole of the DC power supply 71 and the node 721. When the pulse unit 72 includes multiple switching transistors 72a, the switching transistors 72a are connected in series between the positive pole of the DC power supply 71 and the node 721.

[0087] One or more switching transistors 72b are connected between the negative pole of the DC power supply 71 and the node 721. When the pulse unit 72 includes multiple switching transistors 72b, these switching transistors 72b are connected in series between the negative pole of the DC power supply 71 and the node 721.

[0088] The diode 72c is connected in parallel with one or more switching transistors 72a. The diode 72c is connected between the positive electrode of the DC power supply 71 and a node 722. The cathode of the diode 72c is connected to the positive electrode of the DC power supply 71, and the anode of the diode 72c is connected to the node 722. The node 722 is connected to the node 721.

[0089] The diode 72d is connected in parallel with the one or more switching transistors 72b. The diode 72d is connected between the negative electrode of the DC power supply 71 and a node 722. The anode of the diode 72d is connected to the negative electrode of the DC power supply 71, and the cathode of the diode 72d is connected to the node 722.

[0090] The pulse controller PC is configured to set an output duration of a pulse of voltage from the pulse unit 72 by providing a control signal to the pulse unit 72. In one embodiment, the pulse controller PC provides a pulse control signal as the control signal to a control terminal of the one or more switching transistors 72a and a control terminal of the one or more switching transistors 72b.

[0091] When one or more switching transistors 72a are closed and one or more switching transistors 72b are open by a pulse control signal from the pulse controller PC, the node 722 is connected to ground, and as a result, the output voltage of the power supply system 70A becomes 0 V (i.e., the reference level).

[0092] When one or more switching transistors 72a are opened and one or more switching transistors 72b are closed by a pulse control signal from the pulse controller PC, the node 722 is connected to the negative electrode of the DC power supply 71. As a result, a pulse of a negative voltage (for example, a negative DC voltage) is output from the power supply system 70A. Each of the above-mentioned first pulse, second pulse, and third pulse is generated by adjusting the output voltage level of the DC power supply 71 to adjust the voltage level of the pulse output from the node 722.

[0093] In one embodiment, the power supply system 70A may further include a DC power supply 73 and a pulse unit 74. The DC power supply 73 is a power supply that generates a positive DC voltage. The negative terminal of the DC power supply 73 is connected to the ground. The DC power supply 73 may be a variable DC power supply.

[0094] The pulse unit 74 is configured to generate a voltage pulse from a positive polarity DC voltage from the DC power supply 73. In one embodiment, the pulse unit 74 may include one or more switching transistors 74a, one or more switching transistors 74b, a diode 74c, and a diode 74d.

[0095] One or more switching transistors 74a are connected between the positive terminal of the DC power supply 73 and the node 741. When the pulse unit 74 includes multiple switching transistors 74a, the switching transistors 74a are connected in series between the positive terminal of the DC power supply 73 and the node 741.

[0096] One or more switching transistors 74b are connected between the negative terminal of the DC power supply 73 and the node 741. When the pulse unit 74 includes multiple switching transistors 74b, these switching transistors 74b are connected in series between the negative terminal of the DC power supply 73 and the node 741.

[0097] The diode 74c is connected in parallel with one or more switching transistors 74a. The diode 74c is connected between the positive electrode of the DC power supply 73 and a node 742. The cathode of the diode 74c is connected to the positive electrode of the DC power supply 73, and the anode of the diode 74c is connected to the node 742. The node 742 is connected to the node 741.

[0098] The diode 74d is connected in parallel with the one or more switching transistors 74b. The diode 74d is connected between the negative terminal of the DC power supply 73 and a node 742. The anode of the diode 74d is connected to the negative terminal of the DC power supply 73, and the cathode of the diode 74d is connected to the node 742.

[0099] The pulse controller PC may be configured to set the duration of the output of the pulses of voltage from the pulse unit 74 by providing a control signal to the pulse unit 74. In one embodiment, the pulse controller PC provides as the control signal a pulse control signal to a control terminal of the one or more switching transistors 74a and a control terminal of the one or more switching transistors 74b.

[0100] When one or more switching transistors 74a are opened and one or more switching transistors 74b are closed by a pulse control signal from the pulse controller PC, the node 742 is connected to ground, and as a result, the output voltage of the power supply system 70A becomes 0 V (i.e., the reference level).

[0101] When one or more switching transistors 74a are closed and one or more switching transistors 74b are opened by a pulse control signal from the pulse controller PC, the node 742 is connected to the positive electrode of the DC power supply 73. As a result, a pulse of a positive voltage (for example, a positive DC voltage) is output from the power supply system 70A.

[0102] When the power supply system 70A outputs a negative voltage pulse, one or more switching transistors 74a and one or more switching transistors 74b may be set to an open state, and when the power supply system 70A outputs a positive voltage pulse, one or more switching transistors 72a and one or more switching transistors 72b may be set to an open state.

[0103] In one embodiment, the pulse controller PC may provide a pulse control signal to the high frequency power supply 61 and / or the high frequency power supply 62. The high frequency power supply 61 may output a pulse of a first high frequency power in response to the pulse control signal. The pulse of the first high frequency power may be output in the same phase as the pulse of the DC voltage output from the power supply system 70A, or may be output in a different phase. The high frequency power supply 62 may output a pulse of a second high frequency power in response to the pulse control signal. The pulse of the second high frequency power may be output in the same phase as the pulse of the DC voltage output from the power supply system 70A, or may be output in a different phase. The high frequency power supply 61 may output a continuous wave of the first high frequency power. Also, the high frequency power supply 62 may output a continuous wave of the second high frequency power.

[0104] Reference will now be made to FIG. 8. FIG. 8 is a diagram showing a power supply system according to another exemplary embodiment. A power supply system 70B shown in FIG. 8 can be employed as the power supply system 70 of the plasma processing apparatus 1. The power supply system 70B can output the bias voltages of the first to fifth examples described above. Below, differences between the power supply system 70B and the power supply system 70A will be described.

[0105] The pulse unit 72 of the power supply system 70B further includes a switching transistor 72e. The switching transistor 72e is connected between the node 722 and a node 701. The node 701 is connected to the lower electrode 18.

[0106] The switching transistor 72e switches between an open state and a closed state in response to a control signal (pulse control signal) provided to its control terminal from the pulse controller PC. When the switching transistor 72e is in an open state, the pulse unit 72 is electrically isolated from the node 701 and the lower electrode 18. When the switching transistor 72e is in a closed state, the pulse unit 72 is connected to the node 701 and the lower electrode 18, and a pulse of a negative voltage is output from the pulse unit 72 to the lower electrode 18. The pulse of a negative voltage output from the pulse unit 72 to the lower electrode 18 is used as one of the first pulse PL1 and the second pulse PL2. When the pulse unit 72 outputs the first pulse PL1, the pulse unit 72 may further output a third pulse PL3.

[0107] The power supply system 70B further includes a DC power supply 75 and a pulse unit 76. The DC power supply 75 is a power supply that generates a negative DC voltage. The positive terminal of the DC power supply 75 is connected to ground. The DC power supply 75 may be a variable DC power supply. The level of the negative DC voltage generated by the DC power supply 75 is different from the level of the negative DC voltage generated by the DC power supply 71.

[0108] The pulse unit 76 is configured to generate voltage pulses from the negative polarity DC voltage from the DC power supply 75. In one embodiment, the pulse unit 76 may include one or more switching transistors 76a, one or more switching transistors 76b, a diode 76c, a diode 76d, and a switching transistor 76e.

[0109] One or more switching transistors 76a are connected between the positive terminal of the DC power supply 75 and the node 761. When the pulse unit 76 includes multiple switching transistors 76a, the switching transistors 76a are connected in series between the positive terminal of the DC power supply 75 and the node 761.

[0110] One or more switching transistors 76b are connected between the negative terminal of the DC power supply 75 and the node 761. When the pulse unit 76 includes multiple switching transistors 76b, the switching transistors 76b are connected in series between the negative terminal of the DC power supply 75 and the node 761.

[0111] The diode 76c is connected in parallel with one or more switching transistors 76a. The diode 76c is connected between the positive electrode of the DC power supply 75 and a node 762. The cathode of the diode 76c is connected to the positive electrode of the DC power supply 75, and the anode of the diode 76c is connected to the node 762. The node 762 is connected to a node 761. The node 762 is connected to a node 701 via a switching transistor 76e. That is, the switching transistor 76e is connected between the node 762 and the node 701.

[0112] The diode 76d is connected in parallel with the one or more switching transistors 76b. The diode 76d is connected between the negative terminal of the DC power supply 75 and a node 762. The anode of the diode 76d is connected to the negative terminal of the DC power supply 75, and the cathode of the diode 76d is connected to the node 762.

[0113] In the power supply system 70B, the pulse controller PC is configured to set an output duration of a pulse of voltage from the pulse unit 76 by providing a control signal to the pulse unit 76. In one embodiment, the pulse controller PC provides a pulse control signal as the control signal to a control terminal of one or more switching transistors 76a and a control terminal of one or more switching transistors 76b.

[0114] In the power supply system 70B, the pulse controller PC provides a pulse control signal to a control terminal of the switching transistor 76e. The switching transistor 76e switches between an open state and a closed state in response to the pulse control signal provided to the control terminal by the pulse controller PC.

[0115] When the switching transistor 76e is open, the pulse unit 76 is electrically isolated from the node 701 and the bottom electrode 18. When the switching transistor 76e is closed, the pulse unit 76 is connected to the node 701 and the bottom electrode 18.

[0116] When one or more switching transistors 76a are closed and one or more switching transistors 76b are open by a pulse control signal from the pulse controller PC, the node 762 is connected to ground, so that the voltage at the node 762 becomes 0V (i.e., the reference level).

[0117] When one or more switching transistors 76 a are opened and one or more switching transistors 76 b are closed by a pulse control signal from the pulse controller PC, the node 762 is connected to the negative electrode of the DC power supply 75 .

[0118] When the pulse unit 76 is connected to the node 701 and the node 762 is connected to the negative electrode of the DC power supply 75, a pulse of a negative voltage (e.g., a negative DC voltage) is output from the pulse unit 76. The pulse of the negative voltage output from the pulse unit 76 to the lower electrode 18 is used as the other of the first pulse PL1 and the second pulse PL2. When the pulse unit 76 outputs the first pulse PL1, the pulse unit 76 may further output a third pulse PL3.

[0119] Hereinafter, reference will be made to Fig. 9. Fig. 9 is a diagram showing the configuration of a substrate support according to another exemplary embodiment. The substrate support 16A shown in Fig. 9 can be adopted in place of the substrate support 16 in the plasma processing apparatus 1.

[0120] The substrate support 16A has a lower electrode 18A and an electrostatic chuck 20A. The lower electrode 18A is made of a conductive material such as aluminum and has a substantially disk shape. A high frequency power supply 61 may be connected to the lower electrode 18A via a matching device 61m. As described above, the high frequency power supply 61 may be connected to the upper electrode 30 via the matching device 61m.

[0121] The electrostatic chuck 20A is provided on the lower electrode 18A. The electrostatic chuck 20A has a dielectric portion 20d and an electrode 21a. The electrostatic chuck 20A may further have an electrode 22a and an electrode 22b. When the substrate W is processed in the internal space 10s, the substrate W is placed on the electrostatic chuck 20A and held by the electrostatic chuck 20A. An edge ring ER is mounted on the substrate support 16A. The edge ring ER is mounted on the substrate support 16A so that its central axis coincides with the axis AX. The substrate W accommodated in the chamber 10 is disposed on the electrostatic chuck 20A and in a region surrounded by the edge ring ER.

[0122] The substrate support 16A has a first region 21 and a second region 22. In FIG. 9, the boundary between the first region 21 and the second region 22 is indicated by a dashed line. The first region 21 is a central region of the substrate support 16A. The first region 21 includes a central region of the electrostatic chuck 20A and a central region of the lower electrode 18A. The second region 22 extends in a circumferential direction radially outward from the first region 21. The second region 22 includes a peripheral region of the electrostatic chuck 20A and a peripheral region of the lower electrode 18A. The electrostatic chuck of the first region 21 and the electrostatic chuck of the second region 22 may be provided by a single electrostatic chuck. That is, the electrostatic chuck of the first region 21 and the electrostatic chuck of the second region 22 may be integrated. In addition, in another embodiment, the electrostatic chuck in the first region 21 and the electrostatic chuck in the second region 22 may be separate electrostatic chucks.

[0123] The first region 21 is configured to support the substrate W placed thereon (i.e., on its upper surface). The first region 21 is a region having a disk shape. The central axis of the first region 21 approximately coincides with the axis AX. The first region 21 shares the dielectric portion 20d with the second region 22. The dielectric portion 20d is made of a dielectric material such as aluminum nitride or aluminum oxide. The dielectric portion 20d has an approximately disk shape. In one embodiment, the thickness of the dielectric portion 20d in the second region 22 is smaller than the thickness of the dielectric portion 20d in the first region 21. The vertical position of the upper surface of the dielectric portion 20d in the second region 22 may be lower than the vertical position of the upper surface of the dielectric portion 20d in the first region 21.

[0124] The first region 21 has an electrode 21a (chuck electrode). The electrode 21a is a film-like electrode and is provided in the dielectric portion 20d within the first region 21. A DC power supply 101p is connected to the electrode 21a via a switch 101s. When a DC voltage from the DC power supply 101p is applied to the electrode 21a, an electrostatic attractive force is generated between the first region 21 and the substrate W. Due to the generated electrostatic attractive force, the substrate W is attracted to the first region 21 and held by the first region 21.

[0125] The first region 21 further includes a first electrode 21c. The first electrode 21c is a film-like electrode and is provided in the dielectric portion 20d in the first region 21. Note that the electrode 21a may extend closer to the top surface of the first region 21 in the vertical direction than the first electrode 21c.

[0126] A power supply system 81 is connected to the first electrode 21c via a filter 81f. The power supply system 81 has the same configuration as the power supply system 70, and is configured to apply the above-mentioned bias voltage to the first electrode 21c. The filter 81f has the same configuration as the filter 70f.

[0127] The second region 22 extends to surround the first region 21. The second region 22 is a substantially annular region. The central axis of the second region 22 substantially coincides with the axis AX. The second region 22 is configured to support an edge ring ER placed thereon (i.e., on its upper surface). The second region 22 shares the dielectric portion 20d with the first region 21.

[0128] In one embodiment, the second region 22 may hold the edge ring ER by electrostatic attraction. In this embodiment, the second region 22 may have one or more electrodes (chuck electrodes). In the example shown in FIG. 9, the second region 22 has a pair of electrodes, namely, the electrode 22a and the electrode 22b. The electrode 22a and the electrode 22b are provided in the dielectric portion 20d in the second region 22. The electrode 22a and the electrode 22b configure a bipolar electrode. Each of the electrode 22a and the electrode 22b is a film-like electrode. The electrode 22a and the electrode 22b may extend at approximately the same height position in the vertical direction.

[0129] A DC power supply 102p is connected to the electrode 22a via a switch 102s and a filter 102f. The filter 102f is configured to cut off or attenuate the high-frequency power. A DC power supply 103p is connected to the electrode 22b via a switch 103s and a filter 103f. The filter 103f is configured to cut off or attenuate the high-frequency power.

[0130] The DC power supplies 102p and 103p apply DC voltages to the electrodes 22a and 22b, respectively, to generate electrostatic attractive forces that attract the edge ring ER to the second region 22. The set potentials of the electrodes 22a and 22b may be any of a positive potential, a negative potential, and 0 V. For example, the potential of the electrode 22a may be set to a positive potential, and the potential of the electrode 22b may be set to a negative potential. The potential difference between the electrodes 22a and 22b may be formed using a single DC power supply instead of two DC power supplies.

[0131] When a DC voltage is applied to the electrodes 22a and 22b, an electrostatic attractive force is generated between the second region 22 and the edge ring ER. The edge ring ER is attracted to the second region 22 by the generated electrostatic attractive force and is held by the second region 22.

[0132] The second region 22 further includes a second electrode 22c. The second electrode 22c is a film-like electrode. The second electrode 22c is provided in the dielectric portion 20d in the second region 22. The second electrode 22c is separated from the first electrode 21c. The electrodes 22a and 22b may extend closer to the top surface of the second region 22 than the second electrode 22c in the vertical direction. The second electrode 22c may be disposed outside the second region 22. For example, the second electrode 22c may be provided below the edge ring ER and in the insulating portion 29.

[0133] The power supply system 82 is connected to the second electrode 22c via a filter 82f. The power supply system 82 has the same configuration as the power supply system 70, and is configured to apply the above-mentioned bias voltage to the second electrode 22c. The filter 82f has the same configuration as the filter 70f. The bias voltage applied to the second electrode 22c by the power supply system 82 may be synchronized with the bias voltage applied to the first electrode 21c by the power supply system 81. The phase of the bias voltage applied to the second electrode 22c by the power supply system 82 may match the phase of the bias voltage applied to the first electrode 21c by the power supply system 81. The bias voltage applied to the second electrode 22c by the power supply system 82 may have a phase difference with respect to the bias voltage applied to the first electrode 21c by the power supply system 81.

[0134] The second region 22 may further include a gas line 22g. The gas line 22g is provided to supply a heat transfer gas, for example, He gas, to the gap between the second region 22 and the edge ring ER. The gas line 22g is connected to a gas supply mechanism 104 that is a source of the heat transfer gas.

[0135] The power supply system 81 may be connected to the electrode 21a. In this case, the substrate support 16A may not have the first electrode 21c. The power supply system 82 may be connected to at least one of the electrodes 22a and 22b. In this case, the substrate support 16A may not have the second electrode 22c. The second region 22 may not have the electrodes 22a and 22b. The power supply system 81 may apply a bias voltage to the first electrode 21c and the second electrode 22c. In this case, the plasma processing apparatus 1 may not have the power supply system 82.

[0136] The electrostatic chuck 20A may also have a source electrode to which high frequency power is supplied from the high frequency power supply 61. The source electrode is provided in at least one of the dielectric portions 20d of the first region 21 and the second region 22. When the source electrode is provided in the dielectric portion 20d of the first region 21, the source electrode may be provided below the first electrode 21c, and the first electrode 21c may be provided below the electrode 21a. Alternatively, the source electrode may be provided above the first electrode 21c and below the electrode 21a. When the source electrode is provided in the dielectric portion 20d of the second region 22, the source electrode may be provided below the second electrode 22c, and the second electrode 22c may be provided below the electrodes 22a and 22b. Alternatively, the source electrode may be provided above the second electrode 22c and below the electrodes 22a and 22b.

[0137] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. In addition, elements in different embodiments can be combined to form other embodiments.

[0138] For example, each of the power supply systems 70, 81, and 82 may have one or more power supplies (e.g., DC power supplies) capable of outputting pulses of voltage (e.g., DC voltage) instead of the configurations shown in Figures 7 and 8. Each of the one or more power supplies may be a variable DC power supply. The bias voltages of the various examples described above can be generated by such one or more power supplies.

[0139] Further, the pulse controller PC may be a component associated with the high frequency power supply 61 or the high frequency power supply 62, instead of being a component of the power supply systems 70, 81, and 82.

[0140] 3, the second pulse PL2 may be generated by connecting the node 722 to ground after the end of the first period P1 and electrically isolating the node 722 from the DC power supply 71 before the potential of the node 722 becomes 0 V. To connect the node 722 to ground, one or more switching transistors 72a are set to a closed state, and one or more switching transistors 72b are set to an open state. To electrically isolate the node 722 from the DC power supply 71, one or more switching transistors 72a and one or more switching transistors 72b are set to an open state.

[0141] In another embodiment, the plasma processing apparatus may be another type of plasma processing apparatus instead of a capacitively coupled plasma processing apparatus. The other type of plasma processing apparatus may be an inductively coupled plasma processing apparatus, an electron cyclotron resonance (ECR) plasma processing apparatus, or a plasma processing apparatus that generates plasma using surface waves such as microwaves. Such other types of plasma processing apparatus may be used in the plasma processing methods according to various exemplary embodiments.

[0142] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various changes may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0143] Reference Signs List 1: plasma processing apparatus, 10: chamber, 16: substrate support, 18: lower electrode, 70: power supply system.

Claims

1. A chamber; a substrate support having an electrode and disposed within the chamber; a power supply system configured to apply a pulsed voltage signal to the electrodes during each cycle; Equipped with The power supply system includes: a sequence of a plurality of first voltage pulses in a first period within each cycle, each pulse having a first voltage level and a negative polarity; a sequence of a plurality of second voltage pulses in a second period within each cycle, each second voltage pulse having a second voltage level different from the first voltage level and a negative polarity; a third voltage pulse having a positive polarity during a third period between the first period and the second period in each cycle; having a fourth voltage pulse having a positive polarity in a fourth period after the second period in each cycle; configured to generate the pulsed voltage signal; Plasma processing equipment.

2. The plasma processing apparatus of claim 1, wherein the power supply system is configured to periodically output the plurality of first voltage pulses at a frequency of 100 kHz or more and 1 MHz or less during the first period, and to periodically output the plurality of second voltage pulses at a frequency of 100 kHz or more and 1 MHz or less during the second period.

3. A plasma processing apparatus as described in claim 1 or 2, wherein a frequency, which is the inverse of the time length of the cycle, is 0.2 Hz or more and 1 Hz or less.

4. A plasma processing apparatus as described in any one of claims 1 to 3, wherein the power supply system is configured to set the absolute value of the first voltage level to a value greater than the absolute value of the second voltage level.

5. A plasma processing apparatus as described in any one of claims 1 to 3, wherein the power supply system is configured to set the absolute value of the first voltage level to a value smaller than the absolute value of the second voltage level.

6. The substrate support, comprising: the power system is configured to apply the pulsed voltage signal to the electrode to attract ions from the plasma in the chamber to the substrate on the substrate support. The plasma processing apparatus according to any one of claims 1 to 5.

7. A method for plasma processing comprising the steps of: applying a pulsed voltage signal to an electrode of a substrate support in a chamber of a plasma processing apparatus during each cycle; The pulsed voltage signal is a sequence of a plurality of first voltage pulses in a first period within each cycle, each pulse having a first voltage level and a negative polarity; a sequence of a plurality of second voltage pulses in a second period within each cycle, each second voltage pulse having a second voltage level different from the first voltage level and a negative polarity; a third voltage pulse having a positive polarity during a third period between the first period and the second period in each cycle; a fourth voltage pulse having a positive polarity in a fourth period after the second period in each cycle; Power supply system.

8. The power supply system of claim 7, wherein the power supply system is configured to periodically output the plurality of first voltage pulses at a frequency of 100 kHz or more and 1 MHz or less during the first period, and to periodically output the plurality of second voltage pulses at a frequency of 100 kHz or more and 1 MHz or less during the second period.

9. A power supply system as described in claim 7 or 8, wherein a frequency, which is the inverse of the time length of the cycle, is 0.2 Hz or more and 1 Hz or less.

10. A power supply system as described in any one of claims 7 to 9, wherein the power supply system is configured to set the absolute value of the first voltage level to a value greater than the absolute value of the second voltage level.

11. A power supply system as described in any one of claims 7 to 9, wherein the power supply system is configured to set the absolute value of the first voltage level to a value smaller than the absolute value of the second voltage level.

12. A power supply system as described in any one of claims 7 to 11, wherein the power supply system is configured to apply the pulsed voltage signal to the electrode to attract ions from the plasma in the chamber to a substrate on the substrate support.

13. providing a substrate on a substrate support disposed within a chamber of a plasma processing apparatus, the substrate support including an electrode; outputting a pulsed voltage signal from a power supply system to the electrodes in each cycle; Including, The pulsed voltage signal is a sequence of a plurality of first voltage pulses in a first period within each cycle, each pulse having a first voltage level and a negative polarity; a sequence of a plurality of second voltage pulses in a second period within each cycle, each second voltage pulse having a second voltage level different from the first voltage level and a negative polarity; a third voltage pulse having a positive polarity during a third period between the first period and the second period in each cycle; a fourth voltage pulse having a positive polarity in a fourth period after the second period in each cycle; Plasma treatment method.

14. The plasma processing method of claim 13, wherein the power supply system is configured to periodically output the plurality of first voltage pulses at a frequency of 100 kHz or more and 1 MHz or less during the first period, and to periodically output the plurality of second voltage pulses at a frequency of 100 kHz or more and 1 MHz or less during the second period.

15. A plasma processing method as described in claim 13 or 14, wherein a frequency, which is the inverse of the time length of the cycle, is 0.2 Hz or more and 1 Hz or less.

16. A plasma processing method described in any one of claims 13 to 15, wherein the power supply system is configured to set the absolute value of the first voltage level to a value greater than the absolute value of the second voltage level.

17. A plasma processing method described in any one of claims 13 to 15, wherein the power supply system is configured to set the absolute value of the first voltage level to a value smaller than the absolute value of the second voltage level.

18. The substrate support, comprising: the power system is configured to apply the pulsed voltage signal to the electrode to attract ions from the plasma in the chamber to the substrate on the substrate support. The plasma processing method according to any one of claims 13 to 17.

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