Memory System

Abstract

To provide a memory system that can improve performance of write processing.SOLUTION: A memory system includes: a nonvolatile memory; a first write buffer; a second write buffer smaller in capacity than the first write buffer and larger in band width than the first write buffer; and a controller. In a case where a writing speed of a first group is less than a first value, the controller loads unloaded data in first data into a first write buffer, and writes the first data into a first writing destination block after the amount of the first data becomes more than or equal to a minimum writing size of a nonvolatile memory. In a case where a writing speed of a second group is more than or equal to the first value, the controller loads second data having the minimum writing size into the second write buffer, and writes the second data into a second writing destination block.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present invention relate to a memory system including a non-volatile memory and a method for controlling a memory system. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread. As one of such memory systems, for example, a solid-state drive (SSD) equipped with a nonvolatile memory such as a NAND flash memory and a controller that controls the nonvolatile memory is known.

[0003] The controller of the memory system processes input / output (I / O) signals (data, commands) received from an external host via a host interface that complies with a specified standard, thereby performing operations such as read processing to read data from a non-volatile memory and write processing to write data to a non-volatile memory.

[0004] In memory systems, technology that can improve the performance of write processing is required. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2022 / 0222011 [Patent Document 2] US Patent Application Publication No. 2022 / 0197543 [Patent Document 3] U.S. Pat. No. 10,013,177 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a memory system and a control method capable of improving the performance of a write process. [Means for solving the problem]

[0007] According to an embodiment, a memory system includes a non-volatile memory including a plurality of blocks, a first write buffer, a second write buffer, and a controller. The second write buffer has a smaller capacity than the first write buffer and a larger bandwidth than the first write buffer. The controller is configured to manage a plurality of destination blocks allocated from the plurality of blocks. The controller is capable of receiving a write command from a host, the write command including first information indicating a size of data to be written to the non-volatile memory and second information capable of directly or indirectly specifying a destination block associated with the data. The controller classifies the received write command into a first group for writing data to a first destination block or a second group for writing data to a second destination block based on the second information included in the received write command. The controller determines whether a write speed indicating an amount of data requested to be written per predetermined time is equal to or greater than a first value for the first and second groups based on the first information included in the received write command. When the write speed of the first group is less than the first value, the controller loads unloaded data of the first data associated with the first group from the memory of the host to the first write buffer, and writes the first data to a first destination block assigned to the first group after an amount of the first data is equal to or greater than a minimum write size of the non-volatile memory. When the write speed of the second group is equal to or greater than the first value, the controller loads second data associated with the second group and having the minimum write size from the memory of the host to the second write buffer, and writes the second data to a second destination block assigned to the second group. [Brief description of the drawings]

[0008] [Figure 1]1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of a configuration showing the relationship between multiple channels and multiple flash dies used in a memory system according to an embodiment. [Diagram 3] FIG. 2 is a diagram showing an example of the configuration of a superblock used in the memory system according to the embodiment. [Figure 4] FIG. 11 is a diagram showing the flow of write data in a write process of a memory system according to a first comparative example. [Diagram 5] FIG. 11 is a diagram showing the flow of write data in a write process of a memory system according to a second comparative example. [Figure 6] 1 is a diagram showing a flow of write data in a write process in a memory system according to an embodiment. [Figure 7] FIG. 11 is a diagram showing a flow of write data in another write process in the memory system according to the embodiment. [Figure 8] 11 is a flowchart showing a first example of a procedure of a write process in the memory system according to the embodiment. [Figure 9] 11 is a flowchart showing a second example of a procedure of a write process in the memory system according to the embodiment. [Figure 10] 11 is a flowchart showing a procedure when a write command is received in the memory system according to the embodiment. [Figure 11] 1 is a flowchart showing the procedure of a write operation executed in a memory system according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] In the following, it is assumed that the memory system according to the embodiment is realized as a solid-state drive (SSD). Fig. 1 is a block diagram showing a configuration example of an information processing system 1 including the memory system according to the embodiment. The information processing system 1 includes a host (host device) 2 and an SSD 3.

[0011] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile device. The host 2 accesses the SSD 3. Specifically, the host 2 issues a write command to the SSD 3, which is a command for writing data. The host 2 also issues a read command to the SSD 3, which is a command for reading data.

[0012] The SSD 3 is a storage device that can be connected to the host 2. The SSD 3 includes a non-volatile memory. The SSD 3 is capable of writing data to the internal non-volatile memory. The SSD 3 is also capable of reading data from the internal non-volatile memory.

[0013] The communication between the SSD 3 and the host 2 is performed via a bus 7. The bus 7 is a transmission path that connects the host 2 and the SSD 3. The bus 7 is, for example, a PCI express TM (PCIe TM ) bus. The PCIe bus is a full duplex transmission path. The full duplex transmission path includes both a transmission path for transmitting data and input / output (I / O) commands from the host 2 to the SSD 3, and a transmission path for transmitting data and responses from the SSD 3 to the host 2. The I / O command is a command for writing data to the nonvolatile memory or reading data from the nonvolatile memory. The I / O command is, for example, a write command or a read command.

[0014] The logical interface standard for connecting the host 2 and the SSD 3 is, for example, NVM express. TM (NVMe TM) standard may be used. In the NVMe standard interface, communication between the host 2 and the SSD 3 is performed using a pair of queues including at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ). This pair of queues is called a submission queue / completion queue pair (SQ / CQ pair).

[0015] Next, the configuration of the host 2 will be described.

[0016] The host 2 includes a processor 21 and a memory 22. The processor 21 and the memory 22 are interconnected via an internal bus 20.

[0017] The processor 21 is, for example, a CPU. The processor 21 executes software (host software) loaded into the memory 22 from the SSD 3 or another storage device connected to the host 2. The host software includes, for example, an operating system, a file system, and an application program.

[0018] The memory 22 is, for example, a volatile memory. The memory 22 is also called a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM). A part of the storage area of ​​the memory 22 is used as a host write buffer 221. The host write buffer 221 is a storage area that temporarily stores data to be written to the non-volatile memory of the SSD 3.

[0019] Also, another part of the storage area of ​​the memory 22 is used to store SQ / CQ pairs 222. Each of the submission queues SQ included in the SQ / CQ pairs 222 is a queue used to issue an I / O command (write command, read command) to the SSD 3. Each of the submission queues SQ includes a plurality of slots. Each of the plurality of slots is capable of storing one I / O command. The host 2 creates the submission queues SQ in the memory 22 of the host 2. Also, the host 2 issues a submission queue create command to the SSD 3. The SSD 3 is notified by the submission queue create command of the addresses indicating the storage positions in the memory 22 where each of the submission queues SQ was created, the sizes of each of the submission queues SQ, the identifiers of the completion queues CQ associated with these submission queues SQ, and the like.

[0020] The completion queue CQ included in the SQ / CQ pair 222 is a queue used to receive a completion response from the SSD 3 indicating the completion of an I / O command. The completion response includes information indicating a status indicating the success or failure of processing the completed command. The completion response is also called a command completion or a command completion notification. The completion queue CQ includes a plurality of slots. Each of the plurality of slots is capable of storing one completion response. The host 2 creates the completion queue CQ in the memory 22 of the host 2. The host 2 also issues a completion queue create command to the SSD 3. The address indicating the storage location in the memory 22 where the completion queue CQ is created, the size of this completion queue CQ, etc. are notified to the SSD 3 by the completion queue create command.

[0021] Next, the internal configuration of the SSD 3 will be described. In the following, it is assumed that the nonvolatile memory included in the SSD 3 is realized by a NAND type flash memory. Note that the NAND type flash memory may be other flash memories or other nonvolatile memories such as MRAM, ReRAM, FeRAM, and phase change memory.

[0022] The SSD 3 includes a controller 4 and a NAND flash memory 5. The SSD 3 may further include a random access memory, for example, a dynamic random access memory (DRAM) 6 which is a volatile memory.

[0023] The NAND type flash memory 5 may be a two-dimensional flash memory or a three-dimensional flash memory. The NAND type flash memory 5 includes a plurality of blocks. Each of the plurality of blocks is the minimum unit of a data erase operation. Each of the plurality of blocks is also referred to as a memory block or a physical block. Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages is each unit of a data write operation and a data read operation. A page includes a set of memory cells connected to the same word line. A page is also referred to as a physical page.

[0024] The NAND flash memory 5 includes multiple dies. The dies are also called memory dies, flash dies, memory chips, or flash chips. Each of these dies is realized as a NAND flash memory die. Hereinafter, the dies are called flash dies. In FIG. 1, a case where the NAND flash memory 5 includes 32 flash dies #0 to #31 is shown as an example.

[0025] The controller 4 is a memory controller. The controller 4 is, for example, a control circuit such as a System-on-a-Chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes each I / O command received from the host 2, thereby executing a read process for reading data from the NAND flash memory 5 and a write process for writing data to the NAND flash memory 5. For example, a Toggle interface or an Open NAND Flash Interface (ONFI) is used as a physical interface connecting the controller 4 and the NAND flash memory 5. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

[0026] The controller 4 manages a plurality of write destination blocks. A write destination block is an open block to which data can be written (a block in which data is being written). In a write process, the controller 4 executes a process for writing different types of data to different write destination blocks. Here, the different types of data are, for example, data from different applications or different end users (tenants such as containers and virtual machines), data with different lifetimes, and the like.

[0027] For example, if write data is sent from different applications at different times and SSD3 writes in that order, data from different applications may be mixed in one block. This increases the frequency of garbage collection, which involves swapping data between blocks, and worsens write amplification (write processing efficiency). To prevent this kind of decrease in write processing efficiency, stream writing is performed, in which data is collected by application and written to consecutive physical addresses in a certain block. In recent years, the number of streams has increased, making it necessary to support a large number of streams for a limited memory capacity. Writing to multiple streams in this way is called multi-stream writing.

[0028] When executing multi-stream writing, the controller 4 recognizes the identifiers assigned by the command for each of the multiple streams, and manages multiple write destination blocks corresponding to each identifier. At this time, the controller 4 sets the same number of blocks as the number of active streams to an open state. The controller 4 then assigns an open write destination block to each of the multiple active streams.

[0029] When using multiple zones defined in the NVMe Zoned Namespace standard, the controller 4 manages multiple blocks corresponding to the multiple zones. In this case, the controller 4 sets the same number of blocks as the number of opened zones to an open state. The controller 4 then assigns an open write destination block to each opened zone.

[0030] Furthermore, when a system configuration is used in which the host 2 issues a write command to the SSD 3 specifying a block address indicating a write destination block (e.g., a write destination superblock), the controller 4 allocates a plurality of write destination blocks to the host 2. The controller 4 manages these write destination blocks allocated to the host 2.

[0031] In addition, when creating and managing multiple storage areas (QoS domains) and managing multiple destination blocks corresponding to multiple placement IDs for each QoS domain, the controller 4 manages, for each QoS domain, the same number of destination blocks as the number of placement IDs used in each QoS domain.

[0032] Furthermore, when a storage area is physically divided for each namespace, the controller 4 manages write destination blocks, the number of which is the same as the number of namespaces, as physical storage areas for these namespaces.

[0033] The DRAM 6 includes a storage area for storing a logical-to-physical address translation table (L2P table) 61. The DRAM 6 further includes a storage area for storing a block management table 62, a storage area used as a DRAM write buffer 63, and a storage area for storing a plurality of virtual write buffers (VWBs) 64.

[0034] The L2P table 61 is a table that stores mapping information. The mapping information is information that indicates the mapping between each logical address and each physical address of the NAND flash memory 5 in a unit of a predetermined management size. The logical address is an address used by the host 2 to access the SSD 3. For example, a logical block address (LBA) is used as the logical address. The physical address is an address that indicates a storage location in the NAND flash memory 5. The physical address can be expressed by, for example, a flash die address, a block address, a page address, an offset address in the page, or any combination of all or part of these. In addition, when the address included in the I / O command transmitted from the host 2 is a physical address and a logical address, the L2P table may be stored in the memory 22 of the host 2.

[0035] The block management table 62 is a table for holding information for managing the state of each of the multiple blocks included in the NAND flash memory 5.

[0036] The DRAM write buffer 63 is a storage area that temporarily stores data to be written to the NAND flash memory 5. The DRAM write buffer 63 is also referred to as a first write buffer.

[0037] The multiple VWBs 64 correspond to multiple write destination blocks in a one-to-one relationship, respectively. Each VWB 64 is used to hold the amount of unwritten data for the corresponding write destination block, etc. The multiple VWBs 64 will be described in detail later.

[0038] Next, the internal configuration of the controller 4 will be described. The controller 4 includes, for example, a host interface (host I / F) 41, a static RAM (SRAM) 42, a CPU 43, a direct memory access controller (DMAC) 44, an error correction circuit 45, a NAND interface (NAND I / F) 46, and a DRAM interface (DRAM I / F) 47. The host interface 41, SRAM 42, CPU 43, DMAC 44, error correction circuit 45, NAND interface 46, and DRAM interface 47 are interconnected via an internal bus 40.

[0039] The host interface 41 is a communication interface circuit that executes communication with the host 2. The host interface 41 is realized by, for example, a PCIe controller. For example, when the host interface 41 is a fifth generation PCIe controller and the number of lanes included in the bus 7 is four, the data reception speed of the host interface 41 is about 16 Gbytes / second. Alternatively, when the host interface 41 is a sixth generation PCIe controller and the number of lanes included in the bus 7 is four, the data reception speed of the host interface 41 is about 30 Gbytes / second. The host interface 41 also includes an arbitration mechanism (not shown). This arbitration mechanism is a mechanism that selects a submission queue SQ from which an I / O command should be fetched from a plurality of submission queues SQ included in the SQ / CQ pair 222. The arbitration mechanism is, for example, a round robin arbitration mechanism or a weighted round robin arbitration mechanism.

[0040] The SRAM 42 is a volatile memory. The storage area of ​​the SRAM 42 is used, for example, as a working area for the CPU 43. The SRAM 42 also includes a storage area for storing an SRAM write buffer 421. The SRAM write buffer 421 is a storage area for temporarily storing data to be written to the NAND flash memory 5. The SRAM write buffer 421 has a smaller capacity than the DRAM write buffer 63 and a larger bandwidth than the DRAM write buffer 63. The SRAM write buffer 421 is also referred to as a second write buffer.

[0041] Here, an example of the relationship between the capacity and bandwidth of the DRAM write buffer 63 and the capacity and bandwidth of the SRAM write buffer 421 will be described.

[0042] A typical bandwidth of DRAM available in the SSD 3 is, for example, 25 GB / sec. Therefore, the DRAM write buffer 63 has a bandwidth of 25 GB / sec. A write process using the DRAM write buffer 63 requires a process of writing data to the DRAM write buffer 63 and a process of reading data from the DRAM write buffer 63. Therefore, when data is written to the NAND flash memory 5 via the DRAM write buffer 63, the speed of data passing through the DRAM write buffer 63 is half the speed of the bandwidth of the DRAM write buffer 63, that is, about 12.5 GB / sec.

[0043] The capacity of the DRAM write buffer 63 is set to a capacity given by, for example, [minimum write size of the NAND flash memory 5]×[number of write destination blocks]. The minimum write size of the NAND flash memory 5 is the minimum size of data required for a data write operation in the NAND flash memory 5. For example, when the page size is 16 KiB, the data write operation mode is a triple level cell (TLC) mode that stores 3 bits per memory cell, and the number of planes per flash die is 4, the minimum write size is 192 KiB (=16 KiB×3 bits×4 planes).

[0044] In addition, when data is written in parallel to multiple flash dies via multiple channels, the minimum write size becomes even larger. For example, assume that the number of channels used for parallel writing is 8. In this case, the minimum write size is about 1.5 MiB (= 16 KiB × 3 bits × 4 planes × 8 ch). Here, when the number of write destination blocks is 1000, the capacity of the DRAM write buffer 63 can be set to about 1.5 GB.

[0045] On the other hand, the bandwidth of a typical SRAM available to the controller 4 is sufficiently larger than the bandwidth of a DRAM. Therefore, when data is written to the NAND flash memory 5 via the SRAM write buffer 421, the speed of data passing through the SRAM write buffer 421 is sufficiently faster than the speed of data passing through the DRAM write buffer 63. In addition, the capacity of the SRAM write buffer 421 is set to a capacity given by, for example, the [minimum write size of the NAND flash memory 5]. In other words, if the minimum write size of the NAND flash memory 5 is 1.5 MiB, the capacity of the SRAM write buffer 421 can be set to 1.5 MiB.

[0046] The CPU 43 is a processor. The CPU 43 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the SRAM 42. The CPU 43 then executes the firmware to perform various processes. The firmware may be loaded into the DRAM 6.

[0047] The CPU 43, for example, as a flash translation layer (FTL), manages data stored in the NAND flash memory 5 and manages blocks included in the NAND flash memory 5. The management of data stored in the NAND flash memory 5 includes, for example, management of mapping information. The CPU 43 uses the mapping information in the L2P table 61 to manage the mapping between each logical address and each physical address in units of a management size. The management size is, for example, 4 KiB.

[0048] In the NAND flash memory 5, data can be written to a page in a block only once per program / erase cycle of the block. That is, new data cannot be directly overwritten to a memory location (physical memory location) in a block where data has already been written. For this reason, when updating data already written to a physical memory location in a block, the controller 4 writes the new data to an unwritten page (free page) in the block (or another block) and treats the previous data as invalid data. In other words, the controller 4 writes update data corresponding to a certain logical address to a different physical memory location, not to the physical memory location where the previous data corresponding to this logical address is stored. Then, the controller 4 updates the L2P table 61 to associate the logical address with a physical address indicating this different physical memory location.

[0049] The management of blocks contained in the NAND type flash memory 5 includes management of defective blocks (bad blocks) contained in the NAND type flash memory 5, wear leveling, and garbage collection (GC).

[0050] The DMAC 44 is a circuit that executes direct memory access (DMA). The DMAC 44 executes data transfer between the memory 22 of the host 2 and the SRAM 42 (or the DRAM 6). For example, in a write process, the DMAC 44 executes a process of transferring write data from the host write buffer 221 to the SRAM 42 (or the DRAM 6).

[0051] The error correction circuit 45 executes an encoding process when data is written to the NAND flash memory 5. In the encoding process, the error correction circuit 45 adds an error correction code (ECC) as a redundant code to the data to be written to the NAND flash memory 5. In the decoding process, the error correction circuit 45 executes a decoding process when data is read from the NAND flash memory 5. In the decoding process, the error correction circuit 45 executes error correction of the data read from the NAND flash memory 5 by using the ECC added to the data.

[0052] The NAND interface 46 is a circuit that controls the NAND flash memory 5. The NAND interface 46 is electrically connected to a plurality of flash dies included in the NAND flash memory 5.

[0053] Each flash die can operate independently. Therefore, the flash die functions as a unit capable of operating in parallel. The NAND interface 46 includes, for example, NAND controllers 461-0, 461-1, ..., 461-7. The NAND controllers 461-0, 461-1, ..., 461-7 are connected to channels ch0, ch1, ..., ch7, respectively. Each of the NAND controllers 461-0, 461-1, ..., 461-7 is connected to one or more flash dies via a corresponding channel. FIG. 1 illustrates a case in which four flash dies are connected to each of channels ch0, ch1, ..., ch7. In this case, the NAND controller 461-0 is connected to flash dies #0, #8, #16, and #24 via channel ch0. The NAND controller 461-1 is connected to flash dies #1, #9, #17, and #25 via channel ch1. And, the NAND controller 461-7 is connected to the flash dies #7, #15, #23, and #31 via the channel ch7. The flash dies #0, #1, ..., #7 are treated as the bank BNK0 by the controller 4. The flash dies #8, #9, ..., #15 are treated as the bank BNK1 by the controller 4. The flash dies #16, #17, ..., #23 are treated as the bank BNK2 by the controller 4. The flash dies #24, #25, ..., #31 are treated as the bank BNK3 by the controller 4. The bank is a unit for operating multiple flash dies in parallel by interleaving operation.

[0054] FIG. 2 is a block diagram showing an example of a configuration showing the relationship between multiple channels and multiple flash dies used in a memory system according to the embodiment.

[0055] As shown in FIG. 2, each of the flash dies #0 to #31 includes a plurality of blocks BLK1 to BLKx-1. In the configuration example shown in FIG. 1 and FIG. 2, the controller 4 can access the flash dies #0 to #31 in parallel by using eight channels and a bank interleave operation. Therefore, the controller 4 can write or read data to a maximum of 32 flash dies in parallel. Each of the flash dies #0 to #31 may have a multi-plane configuration having a plurality of planes. For example, when each of the flash dies #0 to #31 includes four planes, the controller 4 can write or read data to a maximum of 128 planes in parallel.

[0056] Each of the multiple write destination blocks may be a single block (physical block), or may be a superblock including a set of multiple physical blocks capable of operating in parallel.

[0057] Although not limited thereto, one superblock may include a total of 32 physical blocks selected one by one from the NAND flash memory dies #0 to #31. Each of the NAND flash memory dies #0 to #31 may have a multi-plane configuration. For example, when each of the NAND flash memory dies #0 to #31 has a multi-plane configuration including four planes, one superblock may include a total of 128 physical blocks selected one by one from the 128 planes corresponding to the NAND flash memory dies #0 to #31.

[0058] Fig. 3 is a diagram showing an example of the configuration of a superblock used in the memory system according to the embodiment. Fig. 3 shows an example of one superblock (SB) including 32 physical blocks (here, physical block BLK2 of NAND flash memory die #0, physical block BLK3 of NAND flash memory die #1, physical block BLK7 of NAND flash memory die #2, ..., physical block BLK4 in NAND flash memory die #24, physical block BLK6 in NAND flash memory die #25, ..., physical block BLK3 in NAND flash memory die #31).

[0059] In addition, a configuration in which one superblock includes only one physical block may be used, in which case one superblock is equivalent to one physical block. Also, in this example, the superblocks for each flash die #0 to #31 are the same Page 0, 1, 2, ..., but this is not limiting and can be set.

[0060] Returning to the explanation of Fig. 1, the DRAM interface 47 is a circuit that controls the DRAM 6. The DRAM interface 47 stores data in the DRAM 6. In addition, the DRAM interface 47 reads the data stored in the DRAM 6.

[0061] Next, a description will be given of the functional configuration of the CPU 43. The CPU 43 includes a read processing unit 431 and a write processing unit 432 in addition to the components that function as an FTL.

[0062] A part or the whole of each of the read processing unit 431 and the write processing unit 432 may be realized by dedicated hardware of the controller 4.

[0063] The read processing unit 431 executes read processing by processing each read command received from the host 2. The read processing includes a process of converting a logical address specified by the read command into a physical address by referring to the L2P table 61, a process of reading data from a storage location in the NAND flash memory 5 indicated by the physical address, and a process of transferring the read data to the memory 22 of the host 2.

[0064] The write processing unit 432 executes write processing by processing each write command received from the host 2. The write processing includes a process of loading (transferring) write data from the host write buffer 221 to the SRAM write buffer 421 or the DRAM write buffer 63, a process of writing the write data loaded to the SRAM write buffer 421 or the DRAM write buffer 63 to a storage location in the NAND flash memory 5, and a process of updating the L2P table 61 to map a physical address indicating the storage location where the write data has been written to a logical address specified by the write command.

[0065] The write processing unit 432 includes a flash management unit 433 and a scheduler 434 .

[0066] The flash management unit 433 receives a write command from a submission queue (SQ) of the host 2. The write command includes at least information (also referred to as first information) indicating the size of write data to be written to the NAND flash memory 5, and information (second information) capable of directly or indirectly specifying a write destination block associated with the write data. The information capable of indirectly specifying a write destination block is, for example, (1) a stream identifier included in a write command used for multi-stream writing, (2) the upper bit portion of a logical address (start LBA:SLBA) included in a write command used in the zoned namespace standard, (3) a combination of a QoS domain ID and a placement ID included in a write command specifying a QoS domain of the write destination, or (4) a namespace identifier included in a write command when a storage area is physically divided for each namespace.

[0067] Information capable of directly specifying a write destination block is, for example, a block address (super block address) included in a write command issued by the host 2 in a system configuration in which multiple write destination blocks are assigned to the host 2.

[0068] The flash management unit 433 classifies the received write command into a first group for writing data to a first destination block or a second group for writing data to a second destination block based on the second information included in the received write command. The first group is a set of write commands for writing data to the same destination block (here, the first destination block). Data associated with the first group, that is, data associated with the set of write commands belonging to the first group, is written to the first destination block corresponding to this first group. The second group is a set of write commands for writing data to the same destination block (here, the second destination block). Data associated with the second group, that is, data associated with the set of write commands belonging to the second group, is written to the first destination block corresponding to this second group. The flash management unit 433 manages data associated with the first group and not yet written to the NAND flash memory 5 (unwritten data) by using the VWB64 corresponding to the first destination block. Furthermore, the flash management unit 433 manages data (unwritten data) that is associated with the second group and has not yet been written to the NAND flash memory 5, by using the VWB64 that corresponds to the second write destination block.

[0069] The flash management unit 433 judges whether or not the write speed indicating the amount of data requested to be written per predetermined time is equal to or greater than a first value for the first and second groups based on the first information (information indicating the size of write data to be written to the NAND flash memory 5) included in the received write command. In this case, the flash management unit 433 calculates the amount of unwritten data associated with the same group for each of the multiple groups based on the first information included in each of the received write commands. For example, the flash management unit 433 calculates the amount of unwritten data associated with the first group based on the first information included in each of the write commands classified into the first group. Also, the flash management unit 433 calculates the amount of unwritten data associated with the second group based on the first information included in each of the write commands classified into the second group.

[0070] For example, assume that write commands CMD1 to CMD5 are received, and write commands CMD1 to CMD3 are classified into a first group, and write commands CMD4 to CMD5 are classified into a second group. In this case, the flash management unit 433 calculates the total size of the write data specified by the write commands CMD1 to CMD3 as the amount of unwritten data associated with the first group. Also, the flash management unit 433 calculates the total size of the write data specified by the write commands CMD4 to CMD5 as the amount of unwritten data associated with the second group.

[0071] The flash management unit 433 determines whether the write speed of the first group is equal to or greater than a first value based on the amount of unwritten data (also referred to as first data) associated with the first group. Also, the flash management unit 433 determines whether the write speed of the second group is equal to or greater than a first value based on the amount of unwritten data (also referred to as second data) associated with the second group.

[0072] If the writing speed of the first group is equal to or greater than the first value, the flash management unit 433 determines that the first group is a group having a high writing speed. If the writing speed of the first group is less than the first value, the flash management unit 433 determines that the first group is a group having a low writing speed. Similarly, if the writing speed of the second group is equal to or greater than the first value, the flash management unit 433 determines that the second group is a group having a high writing speed. If the writing speed of the second group is less than the first value, the flash management unit 433 determines that the second group is a group having a low writing speed.

[0073] The scheduler 434 executes a scheduling process. The scheduling process includes a process of periodically selecting a write destination block to which data should be written from a plurality of write destination blocks. In other words, the scheduling process is a process of selecting one of a plurality of groups including at least the first and second groups as a group permitted to be written to the NAND flash memory 5. The scheduler 434 executes a scheduling process of selecting one of the groups including a new write command to which write data has not yet been loaded, according to the start or end of a data write operation in the NAND flash memory 5. In other words, the scheduler 434 selects one of the first and second groups including a new write command to which write data has not yet been loaded. The unloaded write data is the write data stored in the host write buffer 221 that has not yet been loaded into either the DRAM write buffer 63 or the SRAM write buffer 421, among the unwritten data. For example, in the scheduling process, the scheduler 434 selects one VWB64 from among a plurality of VWB64, thereby selecting one group corresponding to one write destination block as a group permitted for writing to the NAND flash memory 5. The scheduler 434 selects one of the VWB64s to which a new write command has arrived and to which write data has not yet been loaded, as a group permitted for writing to the NAND flash memory 5.

[0074] When a VWB64 (i.e., a group) is selected by the scheduler 434, the flash management unit 433 determines whether the write speed of the selected group is greater than or equal to a first value, i.e., whether the selected group is a group having a fast write speed or a group having a slow write speed.

[0075] Here, it is assumed that the first group is selected and the first group is a group with a slow write speed, that is, the write speed of the first group is less than the first value. The flash management unit 433 loads the unloaded write data, that is, the write data stored in the host write buffer 221, of the write data corresponding to the first group, into the DRAM write buffer 63. Then, the flash management unit 433 transmits to the host 2 one or more completion responses corresponding to one or more write commands associated with the write data loaded into the DRAM write buffer 63. Then, after one or more new write commands belonging to the first group are received and the total amount of unwritten write data corresponding to the first group becomes equal to or greater than the minimum write size of the NAND flash memory 5, the flash management unit 433 writes the write data from the DRAM write buffer 63 to the write destination block. This write destination block is the first write destination block assigned to the first group. When writing write data to the first destination block, the write data read from the DRAM write buffer 63 may be transferred directly to the NAND flash memory 5, or the write data read from the DRAM write buffer 63 may be transferred to the NAND flash memory 5 via another data buffer, for example, the SRAM write buffer 421.

[0076] Next, assume that the second group is selected and the second group is a group with a high write speed, that is, the write speed of the second group is equal to or greater than the second value. The flash management unit 433 loads the write data associated with the second group and having the minimum write size from the host write buffer 221 to the SRAM write buffer 421, and immediately writes the write data to the write destination block. This write destination block is the second write destination block assigned to the selected second group. In this case, the write data loaded to the SRAM write buffer 421 is transferred to the NAND flash memory 5, and then written to the second write destination block assigned to the second group. When the transfer of the write data to the NAND flash memory 5 is completed, the storage area of ​​the SRAM write buffer 421 is released. Thus, the SRAM write buffer 421 becomes available for storing the next write data having the minimum write size.

[0077] In the above description, the write speed of each group is determined to be equal to or greater than the first value by determining whether the amount of unwritten data is equal to or greater than the minimum write size at the timing when preparation for the next write to the NAND flash memory 5 can be started, but the determination of whether the write speed is equal to or greater than the first value can be performed using various other methods based on the first information included in each write command. The first value is automatically controlled so as to approach a value determined by the size of the SRAM write buffer 421, the DRAM write buffer 63, or the virtual write buffer 64, the bandwidth of the SRAM 42, the bandwidth of the DRAM 6, etc.

[0078] Next, the flow of write data in a memory system according to a comparative example will be described. Fig. 4 is a diagram showing the flow of write data in a write process in a memory system according to a first comparative example. The first comparative example is an example in which write data corresponding to all groups is written to a NAND flash memory 5A via a small size write buffer 421A, which is a volatile memory.

[0079] In the first comparative example, the controller manages the total amount of write data (unwritten data) corresponding to each of a plurality of groups. When the total amount of write data corresponding to a certain group becomes equal to or larger than the minimum write size, the controller loads the write data having the minimum write size from the host write buffer 221A to the small size write buffer 421A. Then, the controller writes the write data loaded to the small size write buffer 421A to the NAND type flash memory 5A. Since data having a size that can be written to the NAND type flash memory 5A is loaded to the small size write buffer 421A, the period during which the write data is stored in the small size write buffer 421A becomes shorter. As a result, each piece of write data on the small size write buffer 421A is not overtaken by any other write data.

[0080] That is, the write data loaded from the host write buffer 221A to the small size write buffer 421A first is written from the small size write buffer 421A to the NAND flash memory 5A first. The write data loaded from the host write buffer 221A to the small size write buffer 421A second is written from the small size write buffer 421A to the NAND flash memory 5A second. The write data loaded from the host write buffer 221A to the small size write buffer 421A third is written from the small size write buffer 421A to the NAND flash memory 5A third. And the write data loaded from the host write buffer 221A to the small size write buffer 421A fourth is written from the small size write buffer 421A to the NAND flash memory 5A fourth.

[0081] For this reason, the order in which the write data is loaded from the host write buffer 221A to the small size write buffer 421A is the same as the order in which the write data is written from the small size write buffer 421A to the NAND type flash memory 5A.

[0082] However, the write data associated with the group having a slow write speed may take a long time until the total amount of the write data reaches or exceeds the minimum write size. In this case, the write data is not loaded from the host write buffer 221A to the small size write buffer 421A for a long time. Until the write data associated with the group having a slow write speed is loaded to the small size write buffer 421A, the write data needs to be maintained in the host write buffer 221A. For this reason, the controller cannot return a completion response to each of the write commands belonging to the group having a slow write speed to the host, and the latency of command processing becomes longer.

[0083] Furthermore, when there are a large number of groups with slow write speeds, the host write buffer 221A may end up being occupied by the write data of these groups with slow write speeds.

[0084] 5 is a diagram showing the flow of write data in a write process of a memory system according to a second comparative example. In the second comparative example, write data corresponding to all groups is written to a NAND flash memory 5B via a large-size write buffer 63B, which is a volatile memory.

[0085] In the second comparative example, in response to receiving one write command, the controller loads the write data associated with the write command from the host write buffer 221B to the large size write buffer 63B. Then, when the total amount of write data corresponding to one group among the write data stored in the large size write buffer 63B reaches the minimum write size, the controller writes the write data having the minimum write size from the large size write buffer 63B to the NAND flash memory 5. Therefore, the write data loaded to the large size write buffer 63B stays in the large size write buffer 63B until it reaches the minimum write size. Therefore, the period during which the write data is stored in the large size write buffer 63B becomes longer. Therefore, there is a case where the write data is overtaken by the write data associated with another group on the large size write buffer 63B.

[0086] That is, even if the write data is loaded from the host write buffer 221B to the large size write buffer 63B first, if the total amount of unwritten data of the group corresponding to the write data reaches the minimum write size secondly, the write data is written from the large size write buffer 63B to the NAND flash memory 5B secondly. Even if the write data is loaded from the host write buffer 221B to the large size write buffer 63B secondly, if the total amount of unwritten data of the group corresponding to the write data reaches the minimum write size fourthly, the write data is written from the large size write buffer 63B to the NAND flash memory 5B fourthly. Even if the write data is loaded from the host write buffer 221B to the large size write buffer 63B thirdly, if the total amount of unwritten data of the group corresponding to the write data reaches the minimum write size firstly, the write data is written from the large size write buffer 63B to the NAND flash memory 5B firstly. Furthermore, even if the write data is loaded from the host write buffer 221B to the large size write buffer 63B fourth, if the total amount of unwritten data in the group corresponding to that write data reaches the minimum write size third, then the write data will be written from the large size write buffer 63B to the NAND flash memory 5B third.

[0087] For this reason, the order in which the write data is loaded from the host write buffer 221B to the large size write buffer 63B differs from the order in which the write data is written from the large size write buffer 63B to the NAND flash memory 5B.

[0088] Next, a write process executed in the SSD 3 according to the embodiment will be described. Fig. 6 is a diagram showing the flow of write data in a write process in the memory system according to the embodiment.

[0089] In response to receiving the multiple write commands, the flash management unit 433 of the SSD 3 classifies the multiple write commands into multiple groups for writing data to different destination blocks. Specifically, the flash management unit 433 classifies the multiple write commands into multiple groups based on the second information included in each of the multiple write commands.

[0090] When each write command issued to the SSD3 is a write command that directly specifies a destination superblock, each write command includes a size of write data, a superblock address, a start LBA, and a data pointer. The size of write data is expressed, for example, by the number of LBAs. The superblock address is information indicating a destination superblock to which the write data should be written. The start LBA is the first LBA among the LBAs corresponding to the write data. The data pointer is information indicating a storage location in the host write buffer 221 where the write data is stored. The flash management unit 433 classifies the received write commands into a plurality of groups based on the superblock address included in each of the received write commands, so that a set of write commands that specify the same superblock address belongs to the same group.

[0091] If each write command issued to the SSD3 is a write command used for multi-stream writing, each write command includes a size of write data, a stream ID, a start LBA, and a data pointer. Data associated with a set of write commands having the same stream ID is, for example, data having the same expected lifetime or data associated with the same application. The flash management unit 433 classifies the received write commands into multiple groups based on the stream ID included in each of the received write commands, such that sets of write commands specifying the same stream ID belong to the same group.

[0092] When each write command issued to the SSD 3 is a write command that specifies a destination QoS domain, each write command includes a size of write data, a QoS domain ID, a placement ID, a start LBA, and a data pointer. The flash management unit 433 classifies the received write commands into a plurality of groups based on the QoS domain ID and placement ID included in each of the received write commands, so that a set of write commands having the same combination of the specified QoS domain ID and the specified placement ID belong to the same group.

[0093] If each write command issued to the SSD3 is a write command used in accordance with the Zoned Namespace standard, each write command includes a size of write data, a start LBA, and a data pointer. The upper bit portion of the start LBA is an address that specifies the zone to which the data is written. The flash management unit 433 classifies the received write commands into a plurality of groups based on the upper bit portion of the start LBA included in each of the received write commands, so that a set of write commands that specify the same zone belongs to the same group.

[0094] If each write command issued to the SSD3 is a write command that specifies a namespace, each write command includes the size of the write data, a namespace ID, a start LBA, and a data pointer. If the storage area is physically divided for each namespace, one write destination block is specified by the namespace ID. In this case, the flash management unit 433 classifies the received write commands into multiple groups based on the upper bit portion of the start LBA included in each of the received write commands, so that a set of write commands that specify the same namespace ID belongs to the same group.

[0095] Hereinafter, the multiple groups are also referred to as multiple streams. The streams are not limited to streams specified in the narrow sense by a stream ID, but are streams specified in the broad sense by various identifiers or various addresses described above.

[0096] The flash management unit 433 calculates the write speed for each of the multiple streams based on the size of the write data included in each of the multiple received write commands. The write speed is calculated, for example, from the total amount of write data associated with the write commands issued per specified time.

[0097] First, the data flow of streams (also called the first group) whose writing speed is equal to or higher than a first value among the multiple streams will be described.

[0098] The flash management unit 433 determines that this stream is a stream having a high write speed (hereinafter also referred to as a high-speed stream). The flash management unit 433 loads write data that is associated with a set of write commands belonging to this stream and has a minimum write size from the host write buffer 221 to the SRAM write buffer 421. Then, the write data loaded to the SRAM write buffer 421 is written to the NAND flash memory 5. Since data having a size that can be written to the NAND flash memory 5 is loaded to the SRAM write buffer 421, the period during which the write data is stored in the SRAM write buffer 421 becomes short. As a result, each piece of write data on the SRAM write buffer 421 is not overtaken by any other write data.

[0099] That is, the write data loaded first from the host write buffer 221 to the SRAM write buffer 421 is written first from the SRAM write buffer 421 to the NAND flash memory 5. The write data loaded second from the host write buffer 221 to the SRAM write buffer 421 is written second from the SRAM write buffer 421 to the NAND flash memory 5. The write data loaded third from the host write buffer 221 to the SRAM write buffer 421 is written third from the SRAM write buffer 421 to the NAND flash memory 5. And the write data loaded fourth from the host write buffer 221 to the SRAM write buffer 421 is written fourth from the SRAM write buffer 421 to the NAND flash memory 5.

[0100] Therefore, the order in which the write data is loaded from the host write buffer 221 to the SRAM write buffer 421 is the same as the order in which the write data is written from the SRAM write buffer 421 to the NAND flash memory 5.

[0101] In this way, the write data associated with the fast stream is written to the NAND flash memory 5 via the SRAM write buffer 421. Therefore, compared to the case where the write data associated with the fast stream is written to the NAND flash memory 5 via the DRAM write buffer 63, the write data associated with the fast stream can be written to the NAND flash memory 5 at high speed.

[0102] Next, the data flow of streams (also referred to as the second group) whose writing speed is less than the first value among the multiple streams will be described.

[0103] The flash management unit 433 determines that this stream is a stream having a slow write speed (hereinafter, also referred to as a slow stream). The flash management unit 433 loads the write data associated with the set of write commands belonging to this stream from the host write buffer 221 to the DRAM write buffer 63. Then, when the total amount of unwritten write data corresponding to one group among the write data stored in the DRAM write buffer 63 reaches the minimum write size, the flash management unit 433 writes the write data having the minimum write size from the DRAM write buffer 63 to the NAND flash memory 5. For this reason, the write data loaded into the DRAM write buffer 63 is held in the DRAM write buffer 63 until it reaches the minimum write size. Therefore, the period during which the write data is stored in the DRAM write buffer 63 becomes long. Also, overtaking of write data on the DRAM write buffer 63 may occur.

[0104] In other words, even if the write data is loaded from the host write buffer 221 to the DRAM write buffer 63 first, if the total amount of unwritten data of the group corresponding to that write data reaches the minimum write size secondarily, the write data will be written from the DRAM write buffer 63 to the NAND flash memory 5 secondarily. Even if the write data is loaded from the host write buffer 221 to the DRAM write buffer 63 secondarily, if the total amount of unwritten data of the group corresponding to that write data reaches the minimum write size fourtharily, the write data will be written from the DRAM write buffer 63 to the NAND flash memory 5 fourtharily. Even if the write data is loaded from the host write buffer 221 to the DRAM write buffer 63 thirdarily, if the total amount of unwritten data of the group corresponding to that write data reaches the minimum write size firstarily, the write data will be written from the DRAM write buffer 63 to the NAND flash memory 5 firstarily. Furthermore, even if the write data is loaded from the host write buffer 221 to the DRAM write buffer 63 fourth, if the total amount of unwritten data in the group corresponding to that write data reaches the minimum write size third, then the write data will be written from the DRAM write buffer 63 to the NAND flash memory 5 third.

[0105] For this reason, the order in which the write data is loaded from the host write buffer 221 to the DRAM write buffer 63 and the order in which the write data is written from the DRAM write buffer 63 to the NAND flash memory 5 are different.

[0106] In this way, even if the total amount of write data associated with a slow stream is less than the minimum write size, this write data is loaded from the host write buffer 221 to the DRAM write buffer 63. When this write data is loaded into the DRAM write buffer 63, the storage area in the host write buffer 221 in which this write data is stored can be released. Therefore, when the loading of the write data into the DRAM write buffer 63 is completed, it is possible to return a completion response to each of the write commands belonging to the slow stream to the host 2. Therefore, compared to the comparative example described in FIG. 4, it is possible to shorten the latency of command processing for a slow stream.

[0107] FIG. 7 is a diagram showing a flow of write data in another write process in the memory system according to the embodiment.

[0108] The write speed of each stream may change dynamically. In the second example, a write process capable of tracking the dynamic change in the write speed of each stream is executed.

[0109] Figure 7 shows an example in which VWB64 contains four VWBs #1 to #4 corresponding to the write destination superblocks SB #1 to SB #4, and four first-in, first-out (FIFO) buffers corresponding respectively to the four VWBs #1 to #4.

[0110] The flash management unit 433 fetches a plurality of write commands from the submission queue 222 a of the host 2 .

[0111] The flash management unit 433 classifies the fetched write commands into four streams corresponding to the four write destination super-blocks SB#1 to SB#4, based on the second information included in each of the fetched write commands.

[0112] Then, for the stream corresponding to the write destination super-block SB#1, the flash management unit 433 stores each of the write commands belonging to this stream in the FIFO corresponding to the VWB#1. Then, the flash management unit 433 registers, in the VWB#1, information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating the storage location in the host write buffer 221 where this write data is stored. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super-block SB#1. The unwritten data is data that has not yet been written to the NAND flash memory 5. In this way, the flash management unit 433 manages the unwritten data associated with the stream corresponding to the write destination super-block SB#1 by using the VWB#1.

[0113] For the stream corresponding to the write destination super-block SB#2, the flash management unit 433 stores each of the write commands belonging to this stream in the FIFO corresponding to VWB#2. The flash management unit 433 then registers, in VWB#2, information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating the storage location in the host write buffer 221 where this write data is stored. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super-block SB#2. In this way, the flash management unit 433 manages the unwritten data of the stream corresponding to the write destination super-block SB#2 using VWB#2. For the stream corresponding to the write destination super-block SB#3, the flash management unit 433 stores each of the write commands belonging to this stream in the FIFO corresponding to VWB#3. The flash management unit 433 then registers, in VWB#3, information indicating the total amount of write data associated with the set of write commands stored in this FIFO, and information indicating the storage location in the host write buffer 221 where this write data is stored. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super-block SB#3. In this way, the flash management unit 433 manages the unwritten data of the stream corresponding to the write destination super-block SB#3 using VWB#3. For the stream corresponding to the write destination super-block SB#4, the flash management unit 433 stores each of the write commands belonging to this stream in the FIFO corresponding to VWB#4. Then, the flash management unit 433 registers, in VWB#4, information indicating the total amount of write data associated with the set of write commands stored in this FIFO and information indicating the storage location in the host write buffer 221 where this write data is stored. The total amount of write data associated with the set of write commands stored in this FIFO indicates the amount of unwritten data associated with the stream corresponding to the write destination super-block SB#4. In this way, the flash management unit 433 manages the unwritten data of the stream corresponding to the write destination super-block SB#4 using VWB#4.

[0114] Of VWBs #1 to #4, a VWB to which a new write command for which data has not been loaded has arrived notifies scheduler 434 of the presence of a write request. Therefore, scheduler 434 holds a list of VWBs to which a new write command for which data has not been loaded has arrived, that is, a list of streams including a new write command for which data has not been loaded.

[0115] At the timing when preparation for the next write to the NAND flash memory 5 can begin, that is, in response to the start or end of the data write operation to the NAND flash memory 5, the scheduler 434 selects one of the VWBs to which a new write command for which data has not yet been loaded has arrived, that is, one of the streams including a new write command for which data has not yet been loaded, as a VWB (stream) for which writing is permitted.

[0116] The flash management unit 433 determines whether the amount of unwritten data registered in the VWB selected by the scheduler 434 is equal to or larger than the minimum write size.

[0117] For example, assume that VWB#3 corresponding to destination superblock (SB)#3 is selected by the scheduler 434. The flash management unit 433 determines whether the amount of unwritten data registered in VWB#3 is equal to or greater than the minimum write size. Since VWB#3 corresponds to destination superblock SB#3, the amount of unwritten data registered in VWB#3 is the amount of data to be written to destination superblock SB#3, that is, the amount of unwritten data associated with the stream corresponding to VWB#3. Here, assume that the amount of unwritten data registered in VWB#3 is equal to or greater than the minimum write size.

[0118] In this case, the flash management unit 433 determines that the stream corresponding to VWB#3 has a high write speed. Then, the flash management unit 433 determines whether or not there is data that has already been loaded into the DRAM write buffer 63 among the unwritten data registered in VWB#3. For example, if the amount of unwritten data registered in VWB#3 is less than the minimum write size when VWB#3 is selected in the previous scheduling process, some of the unwritten data currently registered in VWB#3 has already been loaded into the DRAM write buffer 63. On the other hand, if the amount of unwritten data registered in VWB#3 is equal to or greater than the minimum write size when VWB#3 is selected in the previous scheduling process, all of the unwritten data registered in VWB#3 is present in the host write buffer 221, so none of the unwritten data registered in VWB#3 is present in the DRAM write buffer 63.

[0119] If there is unwritten data loaded into the DRAM write buffer 63, the flash management unit 433 loads the unwritten data from each of the DRAM write buffer 63 and the host write buffer 221 into the SRAM write buffer 421 so that the total amount of unwritten data loaded into the SRAM write buffer 421 from both the DRAM write buffer 63 and the host write buffer 221 is the minimum write size.

[0120] For example, assume that the minimum write size is 1.5 MiB, 1.3 MiB of the unwritten data registered in VWB#3 has already been loaded into the DRAM write buffer 63, and 0.2 MiB of the unwritten data registered in VWB#3 is unloaded data.

[0121] In this case, the flash management unit 433 loads (copies) 1.3 MiB of data from the DRAM write buffer 63 to the SRAM write buffer 421, and loads 0.2 MiB of data from the host write buffer 221 to the SRAM write buffer 421, either via the DRAM write buffer 63 or directly.

[0122] Thereafter, the flash management unit 433 writes the unwritten data loaded into the SRAM write buffer 421 to the write destination super-block SB#3.

[0123] In response to the completion of writing to the destination super-block SB#3, the flash management unit 433 performs the following process. That is, the flash management unit 443 issues one or more completion responses corresponding to one or more write commands associated with the write data loaded from the host write buffer 221 to the SRAM write buffer 421 and written to the destination super-block SB#3, and stores them in the completion queue 222b. That is, the flash management unit 433 transmits one or more completion responses corresponding to 0.2 MiB of data among the unwritten data registered in VWB#1 to the host 2. This is because the completion responses corresponding to 1.3 MiB of data among the unwritten data registered in VWB#3 have already been transmitted to the host 2 when these data were loaded to the DRAM write buffer 63.

[0124] When there is no unwritten data loaded into the DRAM write buffer 63 among the unwritten data registered in the VWB#3, the flash management unit 433 loads the unwritten data registered in the VWB#3 and having the minimum write size from the host write buffer 221 to the SRAM write buffer 421. After that, the flash management unit 433 writes the unwritten data loaded into the SRAM write buffer 421 to the write destination super-block SB#3. In response to the completion of writing to the write destination super-block SB#3, the flash management unit 433 performs the following process. That is, the flash management unit 443 issues one or more completion responses corresponding to one or more write commands associated with the write data loaded from the host write buffer 221 to the SRAM write buffer 421 and written to the write destination super-block SB#3, and stores them in the completion queue 222b. In other words, since all of the 1.5 MiB of data registered in VWB#3 has been loaded from the host write buffer 221 to the SRAM write buffer 421, the flash management unit 433 sends to the host 2 all completion responses corresponding to this 1.5 MiB of data.

[0125] Next, a case will be described in which VWB#1 corresponding to the write destination super-block SB#3 is selected by the scheduler 434. The flash management unit 433 judges whether the total amount of unwritten data registered in VWB#1 is equal to or greater than the minimum write size. Since VWB#1 corresponds to the write destination super-block SB#1, the unwritten data registered in VWB#1 is data that should be written to the write destination super-block SB#1. Here, it is assumed that the unwritten data registered in VWB#1 is less than the minimum write size.

[0126] In this case, the flash management unit 433 determines that the stream corresponding to VWB#1 has a slow write speed. Then, the flash management unit 433 loads the unloaded data among the unwritten data registered in VWB#1 from the host write buffer 221 to the DRAM write buffer 63. Then, the flash management unit 433 issues one or more completion responses corresponding to one or more write commands associated with the data loaded to the DRAM write buffer 63, and stores them in the completion queue 222b.

[0127] Thus, in the second example of the write process, the scheduler 434 selects one VWB each time preparation for the next write to the NAND flash memory 5 can be started. Then, the DRAM write buffer 63 or the SRAM write buffer 421 is selectively used based on whether the total amount of unwritten data registered in the selected VWB is equal to or larger than the minimum write size. Therefore, even if the write speed of some streams changes dynamically, it is possible to appropriately switch the load destination write buffer between the DRAM write buffer 63 and the SRAM write buffer 421 in accordance with the dynamic change in the write speed.

[0128] In the above explanation, the data loaded into the DRAM write buffer 63 is copied to the SRAM write buffer 421. However, it is also possible to use a method in which the data loaded into the DRAM write buffer 63 is directly written to the NAND flash memory 5.

[0129] Next, a procedure of a write process will be described below with reference to a flowchart of FIG 8, which shows a first example of a procedure of a write process in the memory system according to the embodiment.

[0130] The controller 4 receives a plurality of write commands from the host 2 (step S101).

[0131] The controller 4 classifies the received write commands into a plurality of groups corresponding to the plurality of write destination blocks, respectively (step S102). Specifically, the controller 4 classifies each of the received write commands into a plurality of groups based on the second information included in each of the received write commands.

[0132] The controller 4 selects one of the groups including a new write command for which data has not yet been loaded as a group permitted to be written to the NAND flash memory 5 (step S103). The process of selecting a group may be performed at a predetermined timing, and the timing of selecting a group is not particularly limited.

[0133] The controller 4 determines whether the write speed of the group selected in S103 is equal to or higher than the first value (step S104). Specifically, the controller 4 calculates the write speed based on the first information included in each of the multiple write commands received in S101.

[0134] If the write speed is equal to or greater than the first value (Yes in S104), the controller 4 loads the unloaded data associated with the group selected in S103 and having the minimum write size from the host write buffer 221 to the SRAM write buffer 421 (step S105). The flash management unit 433 of the controller 4 may register information indicating the storage location in the SRAM write buffer 421 where the data has been loaded, in the VWB corresponding to the selected group.

[0135] The controller 4 writes the data, which has the minimum write size and has been loaded into the SRAM write buffer 421 in S105, to the write destination block (step S106).

[0136] In response to the completion of the write process of S106, the controller 4 transmits to the host 2 one or more completion responses indicating the completion of one or more write commands associated with the data written to the NAND flash memory 5 (step S107).

[0137] If there are any unselected groups remaining among the groups including a new write command for which data has not yet been loaded, the controller 4 may select another group from the remaining unselected groups and perform the same processing on the newly selected group.

[0138] In this case, the controller 4 judges whether or not all of the groups including the new write command for which data has not yet been loaded have been selected (step S108).

[0139] If all of the groups containing the new write command for which data has not yet been loaded have already been selected in S103 (Yes in S108), the controller 4 ends the write process.

[0140] If there are any unselected groups remaining among the groups including the new write command to which data has not been loaded (No in S108), the controller 4 returns to S103 and selects one group from the groups that have not yet been selected among the groups including the new write command to which data has not been loaded.

[0141] On the other hand, if the write speed of the group selected in S103 is less than the first value (No in S104), the controller 4 loads unloaded data associated with the group selected in S103 from the host write buffer 221 to the DRAM write buffer 63 (step S109). The flash management unit 433 of the controller 4 may register information indicating the storage location in the DRAM write buffer 63 where the data has been loaded, in the VWB corresponding to the selected group.

[0142] The controller 4 transmits to the host 2 one or more completion responses indicating the completion of one or more write commands associated with the data loaded into the DRAM write buffer 63 in S109 (step S110).

[0143] If the same group as the group selected in S103 was selected in the previous write process, data associated with this group may have already been loaded into the DRAM write buffer 63. For this reason, the controller 4 determines whether the amount of unwritten data associated with the group selected in S103 is equal to or larger than the minimum write size (step S111). For example, the flash management unit 433 of the controller 4 calculates the amount of unwritten data based on information indicating the size of the write data registered in the VWB 64 corresponding to the selected group.

[0144] If the amount of unwritten data corresponding to the group selected in S103 is equal to or larger than the minimum write size (Yes in S111), the controller 4 writes the data to the write destination block corresponding to the group selected in S103 (step S112).

[0145] If the amount of unwritten data corresponding to the group selected in S103 is less than the minimum write size (No in S111), the controller 4 skips the procedure of S112.

[0146] In the next write process, the group selected in S103 may be selected again. In this case, the unloaded data associated with this group is loaded from the host write buffer 221 to the DRAM write buffer 63. Then, when the amount of unwritten data for this group is equal to or greater than the minimum write size, the controller 4 writes the unwritten data corresponding to this group to the write destination block corresponding to this group.

[0147] FIG. 9 is a flowchart showing a second example of a procedure of a write process in the memory system according to the embodiment.

[0148] Here, it is assumed that the write buffer to which data is loaded is appropriately switched between the DRAM write buffer 63 and the SRAM write buffer 421 in accordance with dynamic changes in the write speed of the stream.

[0149] The controller 4 receives a plurality of write commands from the host 2 (step S201).

[0150] The controller 4 classifies the received write commands into a plurality of groups corresponding to the plurality of write destination blocks, respectively (step S202). Specifically, the controller 4 classifies the received write commands into a plurality of groups based on the second information included in each of the plurality of write commands.

[0151] The controller 4 calculates the amount of unwritten data associated with the same group for each of the multiple groups (step S203). Specifically, the controller 4 calculates the amount of unwritten data for each group based on the first information indicating the size of the write data registered in each VWB.

[0152] The controller 4 determines whether or not a data write operation in the NAND flash memory 5 has been started or ended (step S204).

[0153] If the timing does not correspond to either when a data write operation in the NAND type flash memory 5 is started or ended (No in S204), the controller 4 waits until a data write operation in the NAND type flash memory 5 is started or ended.

[0154] When a data write operation in the NAND flash memory 5 is started or ended (Yes in S204), the controller 4 selects any one of the groups including a new write command to which data has not yet been loaded (step S205).

[0155] The controller 4 determines whether or not the amount of unwritten data associated with the group selected in S205 is equal to or larger than the minimum write size, based on the amount of unwritten data calculated in S203 (step S206).

[0156] If the amount of unwritten data is less than the minimum write size (No in S206), the controller 4 loads the unloaded data associated with the group selected in S205 from the host write buffer 221 to the DRAM write buffer 63 (step S207). The flash management unit 433 of the controller 4 may register information indicating the storage location in the DRAM write buffer 63 where the data has been loaded, in the VWB corresponding to the selected group.

[0157] The controller 4 transmits to the host 2 one or more completion responses indicating the completion of one or more write commands associated with the data loaded into the DRAM write buffer 63 in S207 (step S209).

[0158] If the amount of unwritten data associated with the group selected in S205 is equal to or greater than the minimum write size (Yes in S206), the controller 4 determines whether there is unwritten data associated with the group selected in S205 and loaded into the DRAM write buffer 63 (step S209).

[0159] If there is unwritten data associated with the group selected in S205 and loaded into the DRAM write buffer 63 (Yes in S209), the controller 4 loads the unwritten data associated with the selected group from each of the DRAM write buffer 63 and the host write buffer 221 into the SRAM write buffer 421 so that the total amount of unwritten data loaded into the SRAM write buffer 421 from both the DRAM write buffer 63 and the host write buffer 221 becomes the minimum write size (step S210).

[0160] The controller 4 writes the data loaded into the SRAM write buffer 421 in S210 to the write destination block (step S211).

[0161] In response to completion of the data write process in S211, the controller 4 sends one or more completion responses to the host 2 indicating the completion of one or more write commands associated with the write data loaded from the host write buffer 221 to the SRAM write buffer 421 in S210 and written to the destination block in S211 (step S212).

[0162] The controller 4 that has transmitted the completion response in S212 judges whether or not all of the groups including the new write command for which data has not yet been loaded have been selected (step S213).

[0163] When all of the groups including the new write command for which data has not yet been loaded have been selected in S205 (Yes in S213), the controller 4 ends the write process.

[0164] If an unselected group remains among the groups including a new write command to which data has not been loaded (No in S213), the controller 4 returns to S204. Then, at either the timing when the data write operation in the NAND flash memory 5 is started or ended, the controller 4 selects one group from the groups that have not yet been selected among the groups including a new write command to which data has not been loaded.

[0165] If there is no unwritten data associated with the selected group and loaded into the DRAM write buffer 63 (No in S209), the controller 4 loads unloaded data associated with the group selected in S205 and having the minimum write size from the host write buffer 221 to the SRAM write buffer 421 (step S213).

[0166] Then, the controller 4 writes the data loaded into the SRAM write buffer 421 in S214 to the destination block (step S211), and sends one or more completion responses to the host 2 indicating the completion of one or more write commands associated with the data written to the destination block in S211 (step S212).

[0167] The controller 4 that has transmitted the completion response in S212 judges whether or not all of the groups including the new write command for which data has not yet been loaded have been selected (step S213).

[0168] When all groups including a new write command for which data has not yet been loaded have been selected in S205 (Yes in S213), the controller 4 ends the write process.

[0169] If there are any unselected groups remaining among the groups including the new write command for which data has not been loaded (No in S213), the controller 4 returns to S204.

[0170] Next, a detailed description will be given of the operation when a write command is received from the host 2. Fig. 10 is a flowchart showing the procedure when a write command is received in the memory system according to the embodiment.

[0171] The controller 4 receives a write command from the host 2 (step S301). Specifically, the controller 4 fetches the write command from the submission queue 222a.

[0172] The controller 4 adds the size of the write data associated with the received write command to the amount of unwritten data of the group to which the write command received in S301 belongs, thereby updating the amount of unwritten data (step S302).

[0173] The controller 4 determines whether or not unwritten data is being loaded into the DRAM write buffer 63 (step S303).

[0174] If unwritten data is being loaded into the DRAM write buffer 63 (Yes in S303), the controller 4 ends the write command reception operation.

[0175] If unwritten data is not being loaded into the DRAM write buffer 63 (No in S303), the flash management unit 433 of the controller 4 notifies the scheduler 434 of the controller 4 that a new write command associated with unloaded data exists in the group to which the write command received in S301 belongs (step S304).

[0176] Next, a procedure for data write operation to the NAND flash memory after the write command receiving operation of Fig. 10 is completed will be described. Fig. 11 is a flowchart showing the procedure for the write operation executed in the memory system according to the embodiment. In the controller 4, the scheduler 434 of the controller 4 selects one group from a plurality of groups in response to the start or end of the data write operation of the NAND flash memory 5, and starts the write operation corresponding to the selected group. The scheduler 434 can select one group from the groups corresponding to the notification issued in S304 of Fig. 10, for example.

[0177] The controller 4 determines whether the total amount of unwritten data associated with the group selected by the scheduler 434 is equal to or larger than the minimum write size (step S401).

[0178] If the total amount of unwritten data is equal to or larger than the minimum write size (Yes in S401), the controller 4 determines whether or not there is unwritten data associated with the selected group and loaded into the DRAM write buffer 63 (step S402).

[0179] If there is unwritten data associated with the selected group and loaded into the DRAM write buffer 63 (Yes in S402), the controller 4 copies this unwritten data from the DRAM write buffer 63 to the SRAM write buffer 421 (step S403).

[0180] If there is no unwritten data associated with the selected group and loaded into the DRAM write buffer 63 (No in S402), the controller 4 skips the procedure of S403.

[0181] The controller 4 determines whether or not all of the write data to be written next to the destination block has been loaded into the SRAM write buffer 421 (step S404).

[0182] If there is write data to be written next to the destination block that has not yet been loaded into the SRAM write buffer 421 (No in S404), the controller 4 loads the unloaded write data from the host write buffer 221 to the SRAM write buffer 421 (step S405).

[0183] If all of the write data to be written next to the write destination block has been loaded into the SRAM write buffer 421 (Yes in S404), the controller 4 skips the procedure of S405.

[0184] The controller 4 transmits one page of write data and a write instruction from the SRAM write buffer 421 to the NAND flash memory 5 (step S406).

[0185] The controller 4 judges whether or not the write instruction for the minimum write size has been completed (step S407).

[0186] If the write instruction for the minimum write size has not been completed (No in S407), the controller 4 returns to the procedure of S402 and executes the writing of the subsequent write data.

[0187] When the write instruction for the minimum write size has been completed (Yes in S407), the controller 4 ends the write operation.

[0188] Furthermore, if the total amount of unwritten data is less than the minimum write size (No in step S401), the controller 4 notifies the scheduler 434 that the selected group will transition to a state waiting for a subsequent write command (step S408).

[0189] The controller 4 loads the unloaded data associated with the selected group into the DRAM write buffer 63 (step S409).

[0190] The controller 4 registers, in the VWB 64, information indicating the storage location in the DRAM write buffer 63 into which the data was loaded in S409 (step S410).

[0191] Then, the controller 4 determines whether or not there is a write command associated with unloaded data that has not been loaded into the DRAM write buffer 63 and exists in the host write buffer 221 (step S411). A write command associated with data that may correspond to unloaded data in S411 is, for example, a write command that was received during loading of data in S409 and for which the notification in S304 of Fig. 10 could not be issued.

[0192] If a write command associated with unloaded data exists (Yes in S411), the controller 4 notifies the scheduler 434 that a write request exists (step S412), and ends the write operation.

[0193] If there is no write command associated with unloaded data (No in S411), the controller 4 skips the procedure of S412 and ends the write operation.

[0194] As described above, in the SSD 3 of the embodiment, the controller 4 writes data using either the SRAM write buffer 421 or the DRAM write buffer 63 depending on the write speed of each of the multiple groups.

[0195] When the write speed of the selected group is high, the controller 4 loads the write data into the SRAM write buffer 421 and writes the loaded write data into the NAND flash memory 5. That is, the controller 4 writes the write data into the write destination block of the NAND flash memory 5 via the SRAM write buffer 421. In the case where the write data is written into the NAND flash memory 5 via the DRAM write buffer 63, the bandwidth of the DRAM 6 becomes a bottleneck, limiting the write performance of the SSD 3. The bandwidth of the SRAM 42 is sufficiently large compared to the bandwidth of the DRAM 6. Therefore, by writing the write data associated with the group with a high write speed into the NAND flash memory 5 via the SRAM write buffer 421, the write data can be written into the NAND flash memory 5 at a higher speed than when the write data is written into the NAND flash memory 5 via the DRAM write buffer 63.

[0196] On the other hand, if the write speed of the selected group is slow, the write data associated with the selected group is loaded into the DRAM write buffer 63, and after a subsequent write command belonging to the selected group is received and the amount of write data associated with the selected group reaches the minimum write size, the write data associated with the selected group is written into the NAND flash memory 5. Therefore, the volatile memory used as the write buffer needs to have a capacity that can store sufficient write data. Therefore, if all the volatile memory is realized by the SRAM 42, an increase in cost is caused. Therefore, by using the relatively inexpensive DRAM 6, the increase in cost can be avoided.

[0197] Furthermore, the controller 4 transmits a completion response to the host 2 when the write data is stored in the DRAM write buffer 63. This makes it possible to shorten the latency of command processing for a group with a slow writing speed.

[0198] Furthermore, in this embodiment, one VWB is selected each time preparation for the next write to the NAND flash memory 5 can be started. Then, the DRAM write buffer 63 or the SRAM write buffer 421 is selectively used based on whether the amount of unwritten data registered in the selected VWB is equal to or larger than the minimum write size. Therefore, even if the write speed of some streams changes dynamically, it is possible to appropriately switch the load destination write buffer between the DRAM write buffer 63 and the SRAM write buffer 421 in accordance with the dynamic change in the write speed.

[0199] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0200] 1...information processing system, 2...host, 3...SSD, 4...controller, 5...NAND flash memory, 6...DRAM, 7...bus, 20...internal bus, 21...processor, 22...memory, 40...internal bus, 41...host interface, 42...SRAM, 43...CPU, 44...DMAC, 45...error correction circuit, 46...NAND interface, 47...DRAM interface, 61...L2P table, 62...block management table, 63...DRAM write buffer, 64...virtual write buffer, 421...SRAM write buffer, 431...read processing unit, 432...write processing unit, 433...flash management unit, 434...scheduler.

Claims

1. A nonvolatile memory including a plurality of blocks, each of which is a unit of a data erasure operation; a first write buffer; a second write buffer having a smaller capacity than the first write buffer and a larger bandwidth than the first write buffer; a controller; The controller receiving, from a host, a plurality of write commands each including first information that directly or indirectly designates a write destination block among the plurality of blocks; classifying the received write commands into a plurality of groups so that one or more write commands specifying the same write destination block are classified into the same group; and determining whether to use the first write buffer or the second write buffer as a write buffer for temporarily storing write data associated with each of the plurality of groups based on a write speed of each of the plurality of groups. Memory system.

2. The plurality of groups includes at least a first group and a second group; each of the one or more write commands of the first group specifies a first write destination block among the plurality of blocks, and the write speed of the first group is slower than a first threshold; each of the one or more write commands of the second group specifies a second write destination block among the plurality of blocks, and the write speed of the second group is faster than the first threshold; The controller determining, based on the write speed of the first group being slower than the first threshold, to use the first write buffer as the write buffer for temporarily storing first write data associated with the first group; and determining, based on the write speed of the second group being higher than the first threshold, to use the second write buffer as the write buffer for temporarily storing second write data associated with the second group.

10. The memory system of claim 1.

3. The controller In response to at least a portion of the first write data being stored in the first write buffer, before the at least a portion of the first write data is written to the first destination block, sending a completion response to at least one of the one or more write commands of the first group associated with the at least a portion of the first write data; and transmitting a completion response to at least one of the one or more write commands of the second group, associated with at least a portion of the second write data, in response to at least a portion of the second write data being written to the second destination block.

3. The memory system of claim 2.

4. The controller is further configured to read the at least a portion of the first write data from the first write buffer and store the at least a portion of the read first write data in the second write buffer before writing the at least a portion of the first write data to the first destination block.

4. The memory system of claim 3.

5. The first write data includes a plurality of third write data; the second write data includes a plurality of fourth write data; The controller writing the plurality of third write data to the first write destination block in an order different from an order in which the plurality of third write data are stored in the first write buffer; and writing the plurality of fourth write data to the second write destination block in the same order as the order in which the plurality of fourth write data are stored in the second write buffer.

3. The memory system of claim 2.

6. The controller and determining the write speed of each of the plurality of groups based on a total size of data requested in a first period by the one or more write commands of each of the plurality of groups.

10. The memory system of claim 1.

7. The write operation to the nonvolatile memory is performed in units of a first data size; The controller and determining the write speed of each of the plurality of groups based on whether a total size of data requested by the one or more write commands and not yet written in each of the plurality of groups is smaller than the first data size when starting the write operation to the nonvolatile memory.

10. The memory system of claim 1.

8. The plurality of groups includes at least a first group and a second group; each of the one or more write commands of the first group specifies a first destination block among the plurality of blocks; each of the one or more write commands of the second group specifies a second destination block among the plurality of blocks; The controller determining, when initiating the write operation for the first group, to use the first write buffer as the write buffer for temporarily storing first write data associated with the one or more write commands of the first group if the total size of data requested by the one or more write commands of the first group and not yet written is smaller than the first data size; and determining, when starting the write operation for the second group, to use the second write buffer as the write buffer for temporarily storing second write data associated with the one or more write commands of the second group if the total size of data requested by the one or more write commands of the second group and not yet written is greater than the first data size.

8. The memory system of claim 7.

9. The method of claim 8, wherein each of the plurality of write commands includes, as the first information, a stream identifier, a zone identifier, a placement identifier, or a namespace identifier.

10. The memory system of claim 1.

10. The first write buffer is realized by a dynamic random access memory; the second write buffer is implemented with static random access memory; 10. The memory system of claim 1.

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