Semiconductor device

Abstract

To provide a semiconductor device with high reliability and high mobility.SOLUTION: A semiconductor device has a substrate, a first transistor provided on the substrate, and a second transistor provided on the first transistor. The first transistor includes: a first gate electrode provided on the substrate; a first insulating film provided on the first gate electrode; a first oxide semiconductor layer provided on the first insulating film, having a region overlapping with the first gate electrode, and having a polycrystalline structure; a second insulating film provided on the first oxide semiconductor layer; and a second gate electrode provided on the second insulating film. The second transistor includes: a third gate electrode provided on the second insulating film; a third insulating film provided on the third gate electrode; a second oxide semiconductor layer provided on the third insulating film and having a region overlapping with the third gate electrode; a fourth insulating film provided on the second oxide semiconductor layer; and a fourth gate electrode provided on the fourth insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device in which transistors using oxide semiconductors as channels are stacked and a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, the development of semiconductor devices using oxide semiconductors as channels has progressed, replacing amorphous silicon, low-temperature polysilicon, and single-crystal silicon (for example, Patent Document 1). The field-effect mobility of conventional thin-film transistors containing an oxide semiconductor layer is not very large, even when a crystalline oxide semiconductor layer is used. Therefore, transistors that require high-speed driving use crystalline silicon for the channel, while semiconductor devices using oxide semiconductors are being researched for transistors that require low off-current (for example, Patent Documents 2 and 3). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Publication No. 2013-008946 [Patent Document 3] Japanese Patent Publication No. 2011-142621 [Overview of the project] [Problems that the invention aims to solve]

[0004] To increase the integration density of semiconductor devices, transistors using crystalline silicon for the channel and transistors using oxide semiconductors for the channel are sometimes formed on the same substrate. Often, transistors using oxide semiconductors for the channel are stacked on top of transistors using crystalline silicon for the channel. However, since the manufacturing processes for transistors using crystalline silicon and those using oxide semiconductors for the channel are different, manufacturing costs increase.

[0005] One embodiment of the present invention aims to provide a semiconductor device that can be highly integrated and has reduced manufacturing costs. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the first transistor. The first transistor includes a first gate electrode provided on the substrate, a first insulating film provided on the first gate electrode, a first oxide semiconductor layer provided on the first insulating film and having a polycrystalline structure with a region overlapping with the first gate electrode, a second insulating film provided on the first oxide semiconductor layer, and a second gate electrode provided on the second insulating film. The second transistor includes a third gate electrode provided on the second insulating film, a third insulating film provided on the third gate electrode, a second oxide semiconductor layer provided on the third insulating film and having a region overlapping with the third gate electrode, a fourth insulating film provided on the second oxide semiconductor layer, and a fourth gate electrode provided on the fourth insulating film. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. [Figure 2] This is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3]It is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] It is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention. [Figure 18] It is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention. [Figure 19] It is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20]This is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] This is a plan view showing an overview of a display device according to one embodiment of the present invention. [Figure 25] A block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. [Figure 26] This is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. [Figure 27] This is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0008] The embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to clarify the explanation, the drawings may schematically represent the width, film thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] A "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are forms of semiconductor devices. The semiconductor devices in the embodiments shown below may be, for example, integrated circuits (ICs) such as display devices and microprocessors (MPUs), or transistors used in memory circuits.

[0010] A "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, in the embodiments described later, liquid crystal display devices including a liquid crystal layer and organic EL display devices including an organic EL layer will be used as examples, but the structure in these embodiments can be applied to other display devices including the electro-optical layers described above.

[0011] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upwards." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downwards." Thus, for the sake of explanation, the terms "up" or "downwards" are used, but for example, the substrate and oxide semiconductor layer may be arranged in a way that is the opposite of the illustrated relationship. In the following explanation, for example, the expression "oxide semiconductor layer on the substrate" merely describes the relationship between the substrate and the oxide semiconductor layer as described above, and other components may be arranged between the substrate and the oxide semiconductor layer. "Up" or "downwards" refers to the stacking order in a structure in which multiple layers are stacked. When referring to the pixel electrode above the transistor, the positional relationship between the transistor and the pixel electrode may not overlap in a plan view. On the other hand, when referring to the pixel electrode vertically above the transistor, it means that the positional relationship between the transistor and the pixel electrode overlaps in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0012] In this specification, the terms "film" and "layer" may be interchangeable as needed. Furthermore, in this specification, multiple oxide semiconductor layers formed from an oxide semiconductor film may be distinguished and described as "-1," "-2," etc. Similarly, multiple conductive layers and electrodes formed from a conductive film may also be described in the same manner.

[0013] In this specification, ordinal numbers are used to distinguish parts, components, locations, directions, etc., and do not indicate order or priority.

[0014] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0015] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0016] <First Embodiment> A semiconductor device 100 according to one embodiment of the present invention will be described using Figures 1 to 16.

[0017] [Configuration of semiconductor device 100] Figure 1 is a cross-sectional view showing an overview of a semiconductor device 100 according to one embodiment of the present invention.

[0018] As shown in Figure 1, the semiconductor device 100 has a first transistor 210 and a second transistor 220 provided on a substrate 10. The first transistor 210 includes a first gate electrode 12GE, first insulating films 14 and 16, a first oxide semiconductor layer 22, a second insulating film 24, and a second gate electrode 26GE-1. The first oxide semiconductor layer 22 includes a first channel region 22CH, a first source region 22S, and a first drain region 22D. The second transistor 220 includes a third gate electrode 26GE-2, third insulating films 28 and 32, a second oxide semiconductor layer 36, a fourth insulating film 38, and a fourth gate electrode 44GE. The second oxide semiconductor layer 36 includes a second channel region 36CH, a second source region 36S, and a second drain region 36D. Note that when the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 are not distinguished, they may simply be described as the channel region CH, source region S, and drain region D.

[0019] The second transistor 220 is located above the first transistor 210. The statement that the second transistor 220 is located above the first transistor 210 means that the second oxide semiconductor layer 36 is located above the first oxide semiconductor layer 22.

[0020] The first insulating films 14 and 16 function as the first gate insulating film of the first transistor 210. The second insulating film 24 functions as the second gate insulating film of the first transistor 210. The first insulating films 14 and 16 and the second insulating film 24 also function as the underlayer of the second transistor 220. The third insulating films 28 and 32 function as the third gate insulating film of the second transistor 220. The fourth insulating film 38 functions as the fourth gate insulating film of the second transistor. The third insulating films 28 and 32 and the fourth insulating film 38 also function as interlayer insulating films of the first transistor 210.

[0021] A first drain electrode 44D and a first drain electrode 44D are provided on the fourth insulating film 38. The first source electrode 44S and the first drain electrode 44D are connected to the first oxide semiconductor layer 22 via contact holes provided in the second insulating film 24 to the fourth insulating film 38. The first source electrode 44S and the first drain electrode 44D are provided on the same fourth insulating film 38 as the fourth gate electrode 44GE. In addition, the third insulating films 28 and 32 can function as interlayer insulating films of the first transistor 210 and as third gate insulating films of the second transistor 220. A fifth insulating film 46 and 48 are provided on the first source electrode 44S, the first drain electrode 44D, and the fourth gate electrode 44GE.

[0022] A second source electrode 52S and a second drain electrode 52D are provided on the fifth insulating film 48. The second source electrode 52S and the second drain electrode 52D are connected to the second oxide semiconductor layer 36 via contact holes provided in the fourth insulating film 38 and the fifth insulating films 46 and 48. A first electrode 52E-1 and a second electrode 52E-2 are also provided on the fifth insulating film 48. The first electrode 52E-1 and the second electrode 52E-2 are connected to the first source electrode 44S and the first drain electrode 44D via contact holes provided in the fifth insulating films 46 and 48.

[0023] In this embodiment, the first transistor 210 and the second transistor 220 have similar structures. Therefore, in the structure of the second transistor 220, the same structure as that of the first transistor 210 may be omitted from the explanation as appropriate.

[0024] The first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 have a polycrystalline structure containing multiple crystal grains. As will be described in detail later, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 having a polycrystalline structure can be formed by using Poly-OS (Poly-crystalline Oxide Semiconductor) technology. The configuration of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 will be described below, but the oxide semiconductor having a polycrystalline structure is sometimes referred to as Poly-OS.

[0025] The first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 contain two or more metals, including indium, with the proportion of indium in the two or more metals being 50% or more. Other metal elements that can be used include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanide elements. However, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 only need to contain Poly-OS, and may contain metal elements other than those listed above. The second oxide semiconductor layer 36 is preferably formed using an oxide semiconductor target having the same composition as the first oxide semiconductor layer 22. This reduces the manufacturing cost of the semiconductor device 100.

[0026] The grain size of the crystal grains contained in Poly-OS, observed from the upper surface of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 (or in the film thickness direction of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36) or from the cross-section of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36, is 0.1 μm or larger, preferably 0.3 μm or larger, and more preferably 0.5 μm or larger. The grain size of the crystal grains can be obtained, for example, by cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) method.

[0027] The film thickness of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 is greater than 10 nm and less than or equal to 30 nm. As described above, since the grain size of the crystal grains contained in Poly-OS is 0.1 μm or larger, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 contain regions that contain only one crystal grain in the film thickness direction. Furthermore, the film thicknesses of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 may be the same or different.

[0028] In Poly-OS, multiple crystal grains may have one type of crystal structure, or they may have multiple types of crystal structures. The crystal structure of Poly-OS can be determined using electron diffraction or XRD. That is, the crystal structures of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 can be determined using electron diffraction or XRD.

[0029] The crystal structure of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 is preferably cubic. The cubic crystal structure has high symmetry, and even when oxygen vacancies are generated in the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36, structural relaxation is less likely to occur, and the crystal structure remains stable. As described above, by increasing the ratio of indium element, the crystal structure of each of the multiple crystal grains can be controlled, and the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 having a cubic crystal structure can be formed.

[0030] The first oxide semiconductor layer 22 is heavy with the second gate electrode 26GE-1. Tatami The first region and the second gate electrode 26GE-1 are superimposed do not The first region includes the first channel region 22CH, and the second region includes the first source region 22S and the first drain region 22D. The electrical conductivity of the second region is greater than that of the first region.

[0031] The second oxide semiconductor layer 36 is heavy with the fourth gate electrode 44GE. Tatami The third region and the fourth gate electrode 44GE are superimposed. do not The fourth region includes the second channel region 36CH, where the third region corresponds to the second channel region 36CH, and the fourth region corresponds to the second source region 36S and the second drain region 36D. The electrical conductivity of the fourth region is greater than that of the third region. stomach.

[0032] The A grain boundary does not need to exist between region 1 and region 2. Furthermore, both region 1 and region 2 may be contained within a single crystal grain. In other words, the transition from region 1 to region 2 may be a continuous change in crystal structure. Similarly, a grain boundary does not need to exist between region 3 and region 4. Furthermore, both region 3 and region 4 may be contained within a single crystal grain. In other words, the transition from region 3 to region 4 may be a continuous change in crystal structure.

[0033] Furthermore, the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D all contain the same impurity element. In addition, the resistivity of the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D is lower compared to the first channel region 22CH and the second channel region 36CH due to the addition of the impurity element. In other words, the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D possess the physical properties of a conductor. Note that in each of the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D, the same impurity element may be contained in all of the aforementioned regions, or different impurity elements may be contained in each layer. For example, phosphorus may be added to the first source region 22S and the first drain region 22D, and boron may be added to the second source region 36S and the second drain region 36D.

[0034] The concentrations of impurity elements contained in the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D were measured by SIMS (secondary ion mass spectrometry) and were 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following is preferable. Here, impurity elements refer to argon (Ar), phosphorus (P), or boron (B).

[0035] By adding impurity elements, oxygen vacancies are formed in the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D. Hydrogen is trapped in these oxygen vacancies, allowing the resistances of the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D to be reduced compared to the resistances of the first channel region 22CH and the second channel region 36CH. Even when impurity elements are added to the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D, and oxygen vacancies are formed, the crystal structure remains intact. Therefore, the crystal structures of the first source region 22S, the first drain region 22D, the second source region 36S, and the second drain region 36D are identical to those of the first channel region 22CH and the second channel region 36CH.

[0036] If an oxide semiconductor layer contains many oxygen vacancies, hydrogen can become trapped in these vacancies, negatively impacting the characteristics of the transistor. Therefore, reducing the oxygen vacancies in the oxide semiconductor layer is required.

[0037] In oxide semiconductors, crystalline oxide semiconductors are less prone to oxygen vacancies than amorphous oxide semiconductors. It is also known that increasing the proportion of indium in the oxide semiconductor makes it easier to obtain crystalline oxide semiconductors. However, even when a crystalline oxide semiconductor is obtained by increasing the proportion of indium, an excessive number of oxygen vacancies remain. Oxygen vacancies can be repaired by the supply of oxygen. Therefore, it is necessary to repair the oxygen vacancies in the oxide semiconductor layer by placing an insulating film capable of releasing oxygen as an insulating film around the oxide semiconductor layer.

[0038] On the other hand, supplying more oxygen than necessary to the oxide semiconductor layer can lead to the formation of defect levels different from oxygen vacancies due to the excess oxygen contained in the oxide semiconductor layer. This may result in phenomena such as performance fluctuations during reliability testing, a decrease in field-effect mobility, or variations in characteristics.

[0039] According to a semiconductor device 100 of one embodiment of the present invention, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 contain Poly-OS. As a result, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 are layers with high crystallinity and sufficiently reduced oxygen vacancies.

[0040] Furthermore, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 have a crystalline structure not only in the channel region CH but also in the source region S and drain region D, which allows for sufficiently low resistance in the source region S and drain region D. As a result, the parasitic resistance of the source region S and drain region D is reduced, and variations in the on-current in the electrical characteristics of the first transistor 210 and the second transistor 220 can be suppressed. Since the first transistor 210 and the second transistor 220 have high mobility, when the semiconductor device 100 is used as a display device or the like, variations are suppressed and performance is improved.

[0041] In a semiconductor device 100 according to one embodiment of the present invention, the channel length L of the channel region CH of the first transistor 210 and the second transistor 220 is in the range of 2 μm to 4 μm, and the channel width of the channel region CH is in the range of 2 μm to 25 μm, and the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or higher, or 40cm 2 Electrical characteristics of / Vs or higher can be obtained. Mobility as used herein refers to the field-effect mobility in the saturation region of the transistor, and means the maximum value of the field-effect mobility in the region where the potential difference between the source electrode and the drain electrode (Vd) is greater than the value obtained by subtracting the threshold voltage of the transistor (Vth) from the voltage supplied to the gate electrode (Vg) (Vg-Vth).

[0042] Furthermore, by sufficiently reducing the oxygen vacancies in the channel region CH of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36, it is possible to suppress hydrogen from being trapped in the oxygen vacancies. This reduces characteristic fluctuations in reliability tests of the first transistor 210 and the second transistor 220, thereby improving the reliability of the semiconductor device.

[0043] Here, reliability testing refers to, for example, NGBT (Negative Gate Bias-Temperature) stress testing, which applies a negative voltage to the gate, or PGBT (Positive Gate Bias-Temperature) stress testing, which applies a positive voltage to the gate. NGBT and PGBT stress tests are types of accelerated testing that allow for the evaluation of transistor characteristic changes (aging) that occur over long-term use in a short period of time. In particular, the change in the transistor's threshold voltage before and after BT stress testing is an important indicator for determining reliability. The smaller the change in threshold voltage before and after BT stress testing, the more reliable the transistor is considered to be.

[0044] Incidentally, when stacking two transistors made of different semiconductor materials, the wiring structure for connecting the two transistors becomes complex. Furthermore, during the manufacturing process of semiconductor devices, the constituent materials of the lower transistor may adversely affect the constituent materials of the upper transistor. For example, transistors using low-temperature polysilicon require a laser irradiation process on amorphous silicon, and are therefore formed in a lower layer than transistors using oxide semiconductors. The constituent materials of transistors using low-temperature polysilicon are materials that contain a lot of hydrogen. This hydrogen is highly likely to adversely affect oxide semiconductors. Therefore, when forming transistors using low-temperature polysilicon and transistors using oxide semiconductors by stacking them on top of each other, the insulating layer may be increased or the heat treatment may be increased to reduce the effect of hydrogen emitted from the constituent materials of the low-temperature polysilicon transistor. Moreover, even if both transistors using crystalline silicon and transistors using oxide semiconductors have the same top-gate structure, the composition and film thickness of the insulating and conductive materials used in transistors using crystalline silicon and oxide semiconductors are different, so the transistor structure cannot be standardized.

[0045] Since high mobility can be obtained in both the first transistor 210 and the second transistor 220, transistors using oxide semiconductors for the channel can be used in transistors where high-speed driving is required. This eliminates the need to form transistors using crystalline silicon for the channel when high-speed driving is required. Therefore, there is no need to manufacture different transistors for high-speed driving and transistors for other characteristics.

[0046] Furthermore, in the semiconductor device 100 according to one embodiment of the present invention, since two transistors made of the same semiconductor material are stacked, the wiring structure for connecting the two transistors can be simplified. In addition, it is easy to make the structure of the first transistor 210 and the second transistor 220, which use oxide semiconductors, common. For example, the first transistor 210 and the second transistor 220 can be made into dual-gate transistors with an oxide semiconductor layer sandwiched in between. Also, the conductive material used as the gate electrode of the first transistor 210 and the second transistor 220 and the insulating material used as the gate insulating film can have the same structure.

[0047] In this embodiment, the first transistor 210 includes a first gate electrode 12GE, a stack of silicon nitride and silicon oxide films as first insulating films 14 and 16, a first oxide semiconductor layer 22, a silicon oxide film as the second insulating film 24, and a second gate electrode 26GE-1. Similarly, the second transistor includes a third gate electrode 26GE-2, a stack of silicon nitride and silicon oxide films as third insulating films 28 and 32, a second oxide semiconductor layer 36, a silicon oxide film as the fourth insulating film 38, and a fourth gate electrode 44GE. In other words, the first gate electrode 12GE corresponds to the third gate electrode 26GE-2, the first insulating films 14 and 16 correspond to the third insulating films 28 and 32, the second insulating film 24 corresponds to the fourth insulating film 38, and the second gate electrode 26GE-1 corresponds to the fourth gate electrode 44GE. Furthermore, the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 have a polycrystalline structure. Therefore, the second transistor 220 can be stacked on top of the first transistor 210, which has equivalent performance.

[0048] In this embodiment, a top-gate transistor driven by a second gate electrode 26GE-1 is used as the first transistor 210. Also, a top-gate transistor driven by a fourth gate electrode 44GE is used as the second transistor 220. Therefore, it is preferable that the film thickness of the second insulating film 24 is thinner than the film thickness of the first insulating films 14 and 16. Similarly, it is preferable that the film thickness of the fourth insulating film 38 is thinner than the film thickness of the third insulating films 28 and 32.

[0049] For example, when applying semiconductor devices to organic EL displays, a single pixel circuit may require six or more transistors in total, including both driving and switching transistors. If six transistors are to be placed on the same plane, the area required will be equivalent to that of six transistors. Therefore, further integration of the pixel circuit becomes difficult when increasing the pixel resolution.

[0050] In the semiconductor device 100, it is possible to stack transistors having the same function. For example, in a pixel circuit, the switching transistors can be stacked in the upper and lower layers, thereby reducing the area of ​​the pixel circuit. As a result, the area occupied by the pixel circuit can be reduced, making it possible to provide a higher-resolution organic EL display.

[0051] The first transistor 210 and the second transistor 220 each have high mobility. Therefore, they are suitable for drive circuits that require high-speed operation. Furthermore, when the semiconductor device 100 is applied to the drive circuit of a display device, the lower first transistor 210 and the upper second transistor 220 can be stacked so that they are close to each other, or so that part or all of them overlap each other. It is also possible to extend the wiring of the lower first transistor 210 beneath the upper second transistor 220. This reduces the area of ​​the drive circuit of the display device. As a result, a display device with a narrow bezel can be provided.

[0052] In this embodiment, a configuration is illustrated in which a top-gate transistor driven by a second gate electrode 26GE-1 is used as the first transistor 210, but the present invention is not limited to this configuration. For example, a bottom-gate transistor driven by a first gate electrode 12GE may be used as the first transistor 210. Alternatively, a dual-gate transistor driven by a first gate electrode 12GE and a second gate electrode 26GE-1 may be used as the first transistor 210. The same applies to the second transistor 220 as to the first transistor 210. The second transistor 220 is not limited to a top-gate transistor, but may be a bottom-gate transistor or a dual-gate transistor. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0053] The first gate electrode 12GE functions as a light-shielding film for the bottom gate of the first transistor 210 and the first oxide semiconductor layer 22. The first insulating films 14, 16 and the second insulating film 24 have the function of releasing oxygen through heat treatment during the manufacturing process. The second insulating film 24, the third insulating films 28, 32 and the fourth insulating film 38 have the function of insulating the first gate electrode 12GE from the first source electrode 44S and the first drain electrode 44D, and reducing parasitic capacitance between them. The operation of the first transistor 210 is mainly controlled by the voltage supplied to the second gate electrode 26GE-1. An auxiliary voltage is supplied to the first gate electrode 12GE. Alternatively, the first gate electrode 12GE may be used simply as a light-shielding film, in which case no specific voltage is supplied to the first gate electrode 12GE and it may be floating.

[0054] The third gate electrode 26GE-2 functions as a light-shielding film for the bottom gate of the second transistor 220 and the second oxide semiconductor layer 36. The third insulating film 32 and the fourth insulating film 38 have the function of releasing oxygen through heat treatment during the manufacturing process. The fourth insulating film 38 and the fifth insulating films 46, 48 have the function of insulating the fourth gate electrode 44GE from the second source electrode 52S and the second drain electrode 52D, and reducing parasitic capacitance between them. The operation of the second transistor 220 is mainly controlled by the voltage supplied to the fourth gate electrode 44GE. An auxiliary voltage is supplied to the third gate electrode 26GE-2. Alternatively, the third gate electrode 26GE-2 may be used simply as a light-shielding film, in which case no specific voltage is supplied to the third gate electrode 26GE-2, and it may be floating.

[0055] [Manufacturing method for semiconductor device 100] A method for manufacturing a semiconductor device 100 according to one embodiment of the present invention will be described using Figures 2 to 16. Figures 2 and 3 are sequence diagrams showing a method for manufacturing a semiconductor device 100 according to one embodiment of the present invention.

[0056] As shown in Figures 2 and 4, the first gate electrode 12GE is formed on the substrate 10 (step S1001 "1st GE formation" shown in Figure 2).

[0057] As the substrate 10, a rigid substrate having translucency such as a glass substrate, a quartz substrate, and a sapphire substrate is used. When the substrate 10 needs to have flexibility, as the substrate 10, a substrate containing a resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate is used. When a substrate containing a resin is used as the substrate 10, an impurity element may be introduced into the above resin in order to improve the heat resistance of the substrate 10. In particular, when the semiconductor device 100 is a top emission type display, since the substrate 10 does not need to be transparent, an impurity that reduces the transparency of the substrate 10 may be used. When the semiconductor device 100 is used in an integrated circuit that is not a display device, as the substrate 10, a substrate that does not have translucency such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless substrate may be used.

[0058] The first gate electrode 12GE is formed by processing a conductive film formed by a sputtering method. As the first gate electrode 12GE, a general metal material is used. As the first gate electrode 12GE, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As the first gate electrode 12GE, the above materials may be used in a single layer or in a laminate.

[0059] As shown in FIGS. 2 and 4, the first insulating films 14 and 16 are formed on the substrate 10 and the first gate electrode 12GE (the "1st IF film formation" in step S1002 shown in FIG. 2). The first insulating films 14 and 16 are formed by a CVD (Chemical Vapor Deposition) method or a sputtering method. As the first insulating films 14 and 16, a general insulating material is used. As the first insulating films 14 and 16, for example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x), silicon nitride (SiN x O y Inorganic insulating materials such as the above SiO are used. x N y SiN is a silicon compound that contains nitrogen (N) in a smaller proportion (x>y) than oxygen (O). x O y This is a silicon compound that contains oxygen in a smaller proportion (x > y) than nitrogen.

[0060] It is preferable that the first insulating films 14 and 16 be formed in the order of a nitrogen-containing insulating material and an oxygen-containing insulating material from the substrate 10. For example, by using a nitrogen-containing insulating material as the first insulating film 14, impurities diffusing from the substrate 10 towards the first oxide semiconductor layer 22 can be blocked. Also, by using an oxygen-containing insulating material as the first insulating film 16, oxygen can be released by heat treatment. The heat treatment temperature at which the oxygen-containing insulating material releases oxygen is, for example, 500°C or less, 450°C or less, or 400°C or less. In other words, the oxygen-containing insulating material releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 100, for example, when a glass substrate is used as the substrate 10. In this embodiment, an example in which a laminated structure of silicon nitride and silicon oxide is used as the first insulating films 14 and 16 is described, but a single-layer structure of the above-mentioned material may also be used as the first insulating film.

[0061] As shown in Figures 2 and 4, a first oxide semiconductor film 17 is deposited on the first insulating film 16 (step S1003 "1st OS film deposition" shown in Figure 2). In this step, the first oxide semiconductor film 17 may be formed on the substrate 10. The first oxide semiconductor film 17 is deposited by sputtering or atomic layer deposition (ALD). The thickness of the first oxide semiconductor film 17 is, for example, greater than 10 nm and 30 nm or less.

[0062] As the first oxide semiconductor film 17, a metal oxide having semiconductor properties can be used. The first oxide semiconductor film 17 is an oxide semiconductor containing two or more metals, including the element indium. Furthermore, the ratio of the element indium among the two or more metals is 50% or more. As the metal element other than the element indium, the first oxide semiconductor film 17 can be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanide elements.

[0063] When the first oxide semiconductor film 17 is crystallized by OS annealing, as described later, it is preferable that the first oxide semiconductor film 17 is amorphous (a state with a small amount of crystalline oxide semiconductor components) after deposition and before OS annealing. In other words, it is preferable that the deposition method for the first oxide semiconductor film 17 is such that the first oxide semiconductor film 17 does not crystallize as much as possible immediately after deposition. For example, when the first oxide semiconductor film 17 is deposited by sputtering, the first oxide semiconductor film 17 is deposited while controlling the temperature of the object to be deposited (semiconductor device 100 and the structure formed thereon).

[0064] When a film is deposited on an object by sputtering, ions generated in the plasma and atoms recoiling from the sputtering target collide with the object, causing the temperature of the object to rise during the deposition process. When the temperature of the object rises during the deposition process, microcrystals are present in the first oxide semiconductor film 17 immediately after deposition. If microcrystals are present in the first oxide semiconductor film 17, the grain size cannot be increased by subsequent OS annealing. To control the temperature of the object as described above, for example, deposition can be performed while cooling the object. For example, the object can be cooled from the opposite side of the deposition surface so that the temperature of the deposition surface (hereinafter referred to as "deposition temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the deposition temperature of the first oxide semiconductor film 17 in this embodiment is preferably 50°C or less. By forming the first oxide semiconductor film 17 while cooling the substrate, a first oxide semiconductor film 17 with a low crystalline content can be obtained immediately after deposition. In this embodiment, the first oxide semiconductor film 17 is formed at a deposition temperature of 50°C or lower, and the OS annealing described later is performed at a heating temperature of 400°C or higher. Thus, in this embodiment, it is preferable that the difference between the temperature at which the first oxide semiconductor film 17 is formed and the temperature at which the OS annealing is performed on the first oxide semiconductor film 17 is 350°C or higher.

[0065] In the sputtering process, an amorphous first oxide semiconductor film 17 is deposited under conditions where the oxygen partial pressure is 10% or less. If the oxygen partial pressure is high, the excess oxygen contained in the first oxide semiconductor film 17 will cause microcrystals to be present in the first oxide semiconductor film 17 immediately after deposition. Therefore, it is preferable to deposit the first oxide semiconductor film 17 under conditions where the oxygen partial pressure is low. The oxygen partial pressure is, for example, 3% to 5%, and preferably 3% to 4%. Note that if an oxide semiconductor film is deposited under conditions where the oxygen partial pressure is 2%, the oxide semiconductor film may not obtain sufficient crystallinity even if OS annealing is performed afterward.

[0066] As shown in Figures 2 and 5, a pattern of the first oxide semiconductor layer 18 is formed (step S1004 "1st OS pattern formation" shown in Figure 2). A resist mask 19 is formed on the first oxide semiconductor film 17, and the first oxide semiconductor film 17 is etched using the resist mask 19. Wet etching or dry etching may be used for etching the first oxide semiconductor film 17. For wet etching, etching can be performed using an acidic etchant. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used as the etchant. This allows a patterned first oxide semiconductor layer 18 to be formed. After that, the resist mask 19 is removed.

[0067] It is preferable that the pattern is formed on the first oxide semiconductor film 17 before OS annealing. When the first oxide semiconductor film 17 crystallizes due to OS annealing, it tends to become difficult to etch. Furthermore, even if the patterned first oxide semiconductor layer 18 is damaged by etching, the damage to the first oxide semiconductor layer 18 can be repaired by OS annealing, which is preferable.

[0068] As shown in Figures 2 and 6, after pattern formation of the first oxide semiconductor layer 18, the first oxide semiconductor layer 18 is subjected to a heat treatment (OS annealing) (step S1005 "1st OS annealing" shown in Figure 2). In OS annealing, the first oxide semiconductor layer 18 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300°C to 500°C, preferably 350°C to 450°C. The holding time at the temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing OS annealing, the first oxide semiconductor layer 18 is crystallized, and a first oxide semiconductor layer 22 having a polycrystalline structure is formed.

[0069] In thin-film transistors, reducing the thickness of the oxide semiconductor layer tends to increase the number of carriers near the interface with the gate insulating film, thereby reducing the back channel effect and increasing the field-effect mobility. In other words, the field-effect mobility of a thin-film transistor tends to increase as the thickness of the region that functions as a channel in the oxide semiconductor layer decreases. Therefore, a smaller oxide semiconductor layer thickness is preferable. However, even after depositing an oxide semiconductor layer with a thickness of 10 nm or less and then performing heat treatment, the oxide semiconductor layer may not achieve sufficient crystallinity.

[0070] Furthermore, in thin-film transistors, the crystallinity of the first oxide semiconductor layer 22 contributes to improving the field-effect mobility. Therefore, it is preferable that the first oxide semiconductor layer 22 has a polycrystalline structure. However, if microcrystals are present during the deposition of the first oxide semiconductor film 17, the grain size of the polycrystalline structure cannot be increased even after subsequent heat treatment. Thus, it is difficult to achieve both thinning of the oxide semiconductor layer and good crystallinity.

[0071] Therefore, when depositing the first oxide semiconductor film 17 by sputtering, the film is deposited at a low oxygen partial pressure of 3% to 5%. By depositing the first oxide semiconductor film 17 under low oxygen partial pressure conditions, it is possible to suppress the inclusion of excess oxygen in the first oxide semiconductor film 17, and to suppress the inclusion of microcrystals in the first oxide semiconductor film 17 immediately after deposition. This suppresses the growth of crystals from microcrystals during the heat treatment of the first oxide semiconductor layer 18. Consequently, even when the first oxide semiconductor film 17 is deposited with a thin film thickness greater than 10 nm and less than or equal to 30 nm, the grain size of the crystal grains in the polycrystalline structure of the first oxide semiconductor layer 22 can be increased.

[0072] As shown in Figures 2 and 7, a second insulating film 24 is deposited on the first oxide semiconductor layer 22 ("2nd IF deposition" in step S1006 shown in Figure 2). The method of depositing the second insulating film 24 and the insulating material should be described in the description of the first insulating films 14 and 16. The thickness of the second insulating film 24 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0073] It is preferable to use an insulating material containing oxygen as the second insulating film 24. Furthermore, it is preferable to use an insulating film with few defects as the second insulating film 24. For example, when comparing the oxygen composition ratio in the second insulating film 24 with the oxygen composition ratio in an insulating film with a similar composition to the second insulating film 24 (hereinafter referred to as "other insulating films"), the oxygen composition ratio in the second insulating film 24 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating films. For example, silicon oxide (SiO₂) may be used in each of the second insulating film 24 and the fifth insulating film 48. x When this is used, the oxygen composition ratio in the silicon oxide used as the second insulating film 24 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the fifth insulating film 48. For example, a film in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the second insulating film 24.

[0074] To form an insulating film with few defects as the second insulating film 24, the second insulating film 24 may be deposited at a deposition temperature of 350°C or higher. The thickness of the second insulating film 24 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm. After depositing the second insulating film 24, a process of implanting oxygen into a part of the second insulating film 24 may be performed. In this embodiment, silicon oxide is formed as the second insulating film 24 at a deposition temperature of 350°C or higher to form an insulating film with few defects.

[0075] As shown in Figures 2 and 7, a first metal oxide film 25 is deposited on the second insulating film 24 (step S1007 "1st MO film deposition" shown in Figure 2). The first metal oxide film 25 is deposited by sputtering. By depositing the first metal oxide film 25 by sputtering, oxygen is implanted into the second insulating film 24.

[0076] As the first metal oxide film 25, a metal oxide mainly composed of aluminum is used. For example, as the first metal oxide film 25, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlNxOy), aluminum nitride (AlN x An inorganic insulating layer such as ) is used. An aluminum-based metal oxide film means that the proportion of aluminum contained in the metal oxide film is 1% or more of the total first metal oxide film 25. The proportion of aluminum contained in the first metal oxide film 25 may be 5% to 70%, 10% to 60%, or 30% to 50% of the total first metal oxide film 25. The above ratios may be by mass ratio or by weight ratio.

[0077] The thickness of the first metal oxide film 25 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the first metal oxide film 25. Aluminum oxide has high barrier properties against gases such as oxygen or hydrogen. In this embodiment, the aluminum oxide used as the first metal oxide film 25 suppresses the outward diffusion of oxygen that is embedded in the second insulating film 24 during the formation of the first metal oxide film 25. In other words, barrier properties refer to the function of suppressing the permeation of gases such as oxygen or hydrogen through aluminum oxide. That is, even if gases such as oxygen are present in the layer provided below the aluminum oxide film, they will not move to the layer provided above the aluminum oxide film. Or, even if gases such as oxygen are present in the layer provided above the aluminum oxide film, they will not move to the layer provided below the aluminum oxide film.

[0078] For example, if the first metal oxide film 25 is deposited by sputtering, the process gas used in sputtering will remain in the first metal oxide film 25. For example, if Ar is used as the process gas for sputtering, Ar may remain in the second insulating film 24. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the second insulating film 24.

[0079] With the second insulating film 24 and the first metal oxide film 25 deposited on the first oxide semiconductor layer 22, a heat treatment (oxidation annealing) is performed to supply oxygen from the second insulating film 24 to the first oxide semiconductor layer 22 (the "oxidation annealing" in step S1008 shown in Figure 2). During the process from the deposition of the first oxide semiconductor film 17 to the deposition of the second insulating film 24 on the first oxide semiconductor layer 22, many oxygen vacancies are generated on the top and sides of the first oxide semiconductor layer 22. Through oxidation annealing, oxygen released from the first insulating film 16 and the second insulating film 24 is supplied to the first oxide semiconductor layer 22, and the oxygen vacancies are repaired.

[0080] In the oxide annealing process, oxygen injected into the second insulating film 24 is blocked by the first metal oxide film 25, thus suppressing its release into the atmosphere. Therefore, the oxide annealing process efficiently supplies the oxygen to the first oxide semiconductor layer 22, repairing oxygen vacancies.

[0081] As shown in Figure 2, the first metal oxide film 25 is etched (removed) (step S1009 "1st MO removal" shown in Figure 2). Wet etching or dry etching may be used for etching the first metal oxide film 25. Diluted hydrofluoric acid (DHF) can be used as a wet etching agent.

[0082] As shown in Figures 2 and 8, the second gate electrode 26GE-1 and the third gate electrode 26GE-2 are formed on the second insulating film 24 (step S1010 "Formation of 2nd GE and 3rd GE" shown in Figure 2). The second gate electrode 26GE-1 and the third gate electrode 26GE-2 are formed by processing a conductive film deposited by sputtering. For materials that can be used for the second gate electrode 26GE-1 and the third gate electrode 26GE-2, refer to the description of the material for the first gate electrode 12GE. The materials listed in the description of the first gate electrode 12GE may be used as a single layer or as a laminate for the second gate electrode 26GE-1 and the third gate electrode 26GE-2. Alternatively, the second gate electrode 26GE-1 and the third gate electrode 26GE-2 may be formed from the same material as the first gate electrode 12GE.

[0083] As shown in Figures 2 and 9, impurity elements are added to the first oxide semiconductor layer 22 using the second gate electrode 26GE-1 as a mask ("1st I / I" in step S1011 shown in Figure 2). In this embodiment, the addition of impurity elements is described in the case where it is done by ion implantation, but it may also be done by ion doping.

[0084] Specifically, impurity elements are added to the first source region 22S and the first drain region 22D by ion implantation, passing through the second insulating film 24. In the first oxide semiconductor layer 22, no impurity elements are added to the region superimposed on the second gate electrode 26GE-1, and this region functions as a channel region 26CH. For example, argon (Ar), phosphorus (P), or boron (B) can be used as the impurity element. When adding boron (B) by ion implantation, the acceleration energy should be 20 keV to 40 keV, and the amount of boron (B) implanted should be 1 × 10⁻¹⁶. 14 cm -2 The above 1 x 10 16 cm -2 The following is acceptable. In addition, impurity elements are added to the first insulating film 16 and the second insulating film 24 in the vicinity of the third gate electrode 26GE-2. Later, in order to suppress the addition of impurity elements to the region where the second oxide semiconductor layer is formed, a resist mask may be formed in the vicinity of the third gate electrode 26GE-2 before adding the impurity elements.

[0085] Ion implantation introduces 1 × 10⁻¹⁶ impurity elements into the first source region 22S and the first drain region 22D. 18 cm -3 The above 1 x 10 21 cm -3 The following concentrations can be added. In this case, oxygen vacancies are formed in the oxide semiconductor in the first source region 22S and the first drain region 22D due to the addition of impurity elements. Hydrogen is more easily trapped in these oxygen vacancies. This reduces the resistivity of the first source region 22S and the first drain region 22D, allowing them to function as conductors. Even when impurity elements are added to the first oxide semiconductor layer 22 and oxygen vacancies are formed, the crystal structure is maintained without being destroyed. Therefore, it can be said that the crystal structure of the first source region 22S and the first drain region 22D is identical to the crystal structure of the first channel region 22CH.

[0086] For example, when using an IGZO-based oxide semiconductor layer, the resistance of the oxide semiconductor layer is high, so the resistance of the source region and drain region cannot be sufficiently reduced unless the film thickness is increased. In contrast, in the first oxide semiconductor layer 22 having a polycrystalline structure, by adding impurity elements to the first source region 22S and the first drain region 22D, the sheet resistance of the first source region 22S and the first drain region 22D can be reduced to 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq.

[0087] The first transistor 210 is formed through the above process. Next, the second transistor 220, which is provided on top of the first transistor 210, is formed. In this embodiment, the structure of the second transistor 220 is the same as that of the first transistor 210. Therefore, the method for forming the second transistor 220 is the same as that for the first transistor 210, and explanations of this method will be omitted as appropriate.

[0088] As shown in Figures 3 and 10, third insulating films 28 and 32 are deposited on the second insulating film 24, the second gate electrode 26GE-1, and the third gate electrode 26GE-2 ("3rd IF deposition" in step S1012 shown in Figure 2). The deposition method and insulating material of the third insulating films 28 and 32 should be referred to in the description of the materials for the first insulating films 14 and 16. In this embodiment, for example, silicon nitride is formed as the third insulating film 28 and silicon oxide is formed as the third insulating film 32. The third insulating films 28 and 32 can function as interlayer insulating films of the first transistor 210 and as third gate insulating films of the second transistor 220.

[0089] As shown in Figures 3 and 10, a second oxide semiconductor film 33 is deposited on the third insulating film 32 (step S1013 "2nd OS film deposition" shown in Figure 3). The method and materials for depositing the second oxide semiconductor film 33 should refer to the description of the method and materials for depositing the first oxide semiconductor film 17 (step S1003 shown in Figure 2). It is preferable to use the same target for the second oxide semiconductor film 33 as for the first oxide semiconductor film 17, but a different target may be used.

[0090] As shown in Figures 3 and 11, a pattern is formed on the second oxide semiconductor layer 34 (step S1014, "2nd OS pattern formation" shown in Figure 3). For the etching method of the second oxide semiconductor film 33, refer to the explanation of the etching method for the first oxide semiconductor film 17 (step S1004 shown in Figure 2).

[0091] As shown in Figures 3 and 12, after pattern formation of the second oxide semiconductor layer 34, the second oxide semiconductor layer 34 is subjected to heat treatment (OS annealing) (the "2nd OS annealing" in step S1015 shown in Figure 3). For the conditions of OS annealing, refer to the conditions for OS annealing for the first oxide semiconductor layer 18 (step S1005 shown in Figure 2). By performing OS annealing, the second oxide semiconductor layer 34 is crystallized, and a polycrystalline second oxide semiconductor layer 36 is formed. As mentioned above, the first oxide semiconductor layer 22 has a high margin against the heating process. Therefore, the annealing conditions for the second oxide semiconductor layer 34 can be optimized for the second oxide semiconductor layer 34 without worrying about the effects of adding thermal history to the first oxide semiconductor layer 22. For example, it is possible to directly refer to the same conditions as the annealing conditions for the first oxide semiconductor layer 22 for the 2nd annealing conditions.

[0092] As shown in Figures 3 and 13, a fourth insulating film 38 is deposited on the third insulating film 32 and the second oxide semiconductor layer 36 (step S1016 "4th IF deposition" shown in Figure 3). The method for depositing the fourth insulating film 38 and the insulating material should be described in the description of the method for depositing the second insulating film 24 and the insulating material.

[0093] As shown in Figures 3 and 13, a second metal oxide film 42 is deposited on the fourth insulating film 38 (step S1017 "2nd MO film deposition" shown in Figure 3). The method and materials for depositing the second metal oxide film 42 should be referred to in the description of the method and materials for depositing the first metal oxide film 25.

[0094] As shown in Figure 3, the second metal oxide film 41 is removed (the "2nd MO removal" in step S1019 shown in Figure 3).

[0095] As shown in Figure 3, contact holes are formed in the second insulating film 24, the third insulating films 28 and 32, and the fourth insulating film 38 (step S1020 "contact opening" shown in Figure 3). This exposes the first source region 22S and the first drain region 22D of the first oxide semiconductor layer 22.

[0096] As shown in Figures 3 and 14, a first source electrode 44S, a first drain electrode 44D, and a fourth gate electrode 44GE are formed on the fourth insulating film 38 (step S1021 "Formation of 1st SD and 4th GE" shown in Figure 3). The first source electrode 44S, the first drain electrode 44D, and the fourth gate electrode 44GE are formed by processing a conductive film deposited by sputtering. The first source electrode 44S is connected to the first source region 22S and to the first drain region 22D. The fourth gate electrode 44GE is formed in the region overlapping with the second oxide semiconductor layer 36. For materials that can be used for the first source electrode 44S, the first drain electrode 44D, and the fourth gate electrode 44GE, refer to the description of the material for the first gate electrode 12GE.

[0097] As shown in Figures 3 and 15, impurity elements are added to the second oxide semiconductor layer 36 using the fourth gate electrode 44GE as a mask ("2nd I / I" in step S1022 shown in Figure 3). The ion implantation conditions should be described in step S1010 shown in Figure 2.

[0098] Through the above process, the second transistor 220 is formed.

[0099] As shown in Figures 3 and 16, fifth insulating films 46 and 48 are deposited on the fourth insulating film 38, the first source electrode 44S, the first drain electrode 44D, and the fourth gate electrode 44GE ("5th IF deposition" in step S1023 shown in Figure 3). The fifth insulating films 46 and 48 can be described by referring to the material description of the first insulating films 14 and 16. In this embodiment, for example, silicon nitride is formed as the fifth insulating film 46 and silicon oxide is formed as the fifth insulating film 48. The fifth insulating films 46 and 48 function as interlayer insulating films of the second transistor 220.

[0100] As shown in Figure 3, contact holes are formed in the fifth insulating film 46 and 48 (step S1024 "contact opening" shown in Figure 3). This exposes the first source electrode 44S, the first drain electrode 44D, and the second source region 36S and second drain region 36D of the second oxide semiconductor layer 36.

[0101] Finally, as shown in Figures 3 and 17, the first electrode 52E-1, the second electrode 52E-2, the second source electrode 52S, and the second drain electrode 52D are formed on the fifth insulating film 48 (step S1025 "2nd SD formation" shown in Figure 3). The first electrode 52E-1, the second electrode 52E-2, the second source electrode 52S, and the second drain electrode 52D are formed by processing conductive films deposited by sputtering. The first electrode 52E-1 is connected to the first source electrode 44S, and the second electrode 52E-2 is connected to the first drain electrode 44D. The second source electrode 52S is connected to the second source region 36S, and the second drain electrode 52D is connected to the second drain region 36D. For materials that can be used for the first electrode 52E-1, the second electrode 52E-2, the second source electrode 52S, and the second drain electrode 52D, refer to the description of the material for the first gate electrode 12GE.

[0102] By following the above steps, the semiconductor device 100 shown in Figure 1 can be manufactured.

[0103] When stacking two transistors made of different semiconductor materials, even if both the transistor using crystalline silicon and the transistor using oxide semiconductors have the same top-gate structure, the composition and film thickness of the insulating and conductive materials used in the low-temperature silicon transistor and the oxide semiconductor transistor will differ, making it difficult to standardize the manufacturing process.

[0104] In contrast, in the semiconductor device 100 according to one embodiment of the present invention, since two first transistors 210 and second transistors 220 made of the same semiconductor material are stacked, it is easy to standardize the manufacturing process for the two transistors. Therefore, the second transistor 220 can be manufactured using the same manufacturing process as the first transistor 210. Furthermore, since the interlayer insulating film provided on the first transistor 210 and the third gate insulating film of the second transistor 220 can be shared as third insulating films 28 and 32, the manufacturing process can be simplified. Therefore, the manufacturing cost of the semiconductor device 100 can be reduced.

[0105] In the semiconductor device 100 according to one embodiment of the present invention, when oxide semiconductor materials are used for the first oxide semiconductor layer used in the first transistor and the first oxide semiconductor layer used in the second transistor, different oxide semiconductor materials may be used. For example, Poly-OS can be used as the first oxide semiconductor layer of the first transistor, and IGZO can be used as the second oxide semiconductor layer of the second transistor.

[0106] Transistors using Poly-OS have a margin for the heating process, so even if the second transistor 220 is formed using the same process as the first transistor 210, the characteristics of the first transistor 210 can be maintained. In contrast, transistors using IGZO have a narrower margin for the heating process than transistors using Poly-OS, so it is preferable to use them as the second transistor 220. The crystallinity of IGZO is not particularly limited and may be amorphous or crystalline. The structure of the second transistor is not limited to a top-gate structure, but may be a bottom-gate structure or a dual-gate structure. Furthermore, depending on the structure of the second transistor 220, impurity elements may be added as appropriate.

[0107] <Variation 1> Figure 17 is a cross-sectional view showing a semiconductor device 100A having a structure that differs in part from that of semiconductor device 100. As shown in Figure 17, semiconductor device 100A has a third transistor 230 in addition to the first transistor 210 and the second transistor 220. The third transistor 230 is mounted on the substrate 10 in the same way as the first transistor 210.

[0108] The third transistor 230 has a fifth gate electrode 12GE-2, first insulating films 14 and 16, a third oxide semiconductor layer 22-2, a second insulating film 24, and a sixth gate electrode 26GE-3. The third oxide semiconductor layer 22-2 has a third channel region 22CH-2, a third source region 22S-2, and a third drain region. In Figure 17, only the third channel region 36CH-3 and the third source region 22S-2 of the third oxide semiconductor layer 22-2 are shown. In Figure 20, the oxide semiconductor layer of the first transistor 210 is referred to as the first oxide semiconductor layer 22-1 to distinguish it from the third oxide semiconductor layer 22-2.

[0109] The third transistor 230 is formed using the same process as the first transistor 210. Therefore, the third oxide semiconductor layer 22-2 is heavy with the sixth gate electrode. TatamiThe first region and the sixth gate electrode are superimposed do not The first region includes the second region, where the first region corresponds to the third channel region 22CH-2, and the second region corresponds to the first source region 22S and the first drain region 22D. The electrical conductivity of the second region is greater than that of the first region. 。

[0110] The second transistor 220 is provided on top of the first transistor 210 and the third transistor 230. The second transistor 220 can be superimposed on a portion of the first transistor 210 and a portion of the third transistor 230. That is, the second source region 36S of the second oxide semiconductor layer 36 is superimposed on the first drain region 22D-1 of the first oxide semiconductor layer 22-1, and the second drain region 36D of the second oxide semiconductor layer 36 is superimposed on the third source region 22S-2 of the third oxide semiconductor layer 22-2.

[0111] In the semiconductor device 100A according to one embodiment of the present invention, the second transistor 220, the first transistor 210, and the third transistor 230 can be superimposed on each other. This allows for a reduction in circuit area when the semiconductor device 100 is applied to a pixel circuit or a driving circuit, for example. In other words, it becomes possible to further integrate the semiconductor device 100.

[0112] In this embodiment, an example has been described in which the second source region 36S of the second transistor 220 and the first drain region 22D of the first transistor 210 overlap with each other, but the embodiment of the present invention is not limited to this. Although not shown, the second source region 36S may overlap with at least a part of the first channel region 22CH of the first transistor 210. Also, the third gate electrode 26GE-2 may overlap with the first drain region 22D-1. Also, the first gate electrode 12GE (or gate wiring connected to the first gate electrode 12GE) may overlap with the second source region 36S. In this way, in the semiconductor device 100A, structural constraints can be reduced when the first transistor 210 and the second transistor 220 overlap.

[0113] <Second Embodiment> In this embodiment, a semiconductor device 100B, which has a slightly different configuration from the semiconductor device 100 described in the first embodiment, will be described.

[0114] [Configuration of Semiconductor Device 100B] Figure 18 is a cross-sectional view showing an overview of semiconductor device 100B according to one embodiment of the present invention.

[0115] As shown in Figure 18, the semiconductor device 100B has a first transistor 210A and a second transistor 220A provided on the substrate 10. The configuration of the second transistor 220A is the same as that of the first transistor 210, but differs in that a first metal oxide layer 52 is provided between the first oxide semiconductor layer 22 and the first insulating film 16. Also, the configuration of the second transistor 220A is the same as that of the second transistor 220, but differs in that a second metal oxide layer 54 is provided between the second oxide semiconductor layer 36 and the third insulating film 32. Although not shown, as explained in Figure 17, when a third transistor 230 is formed on the substrate 10 on the same plane as the first transistor 210, a third metal oxide layer is provided below the third oxide semiconductor layer.

[0116] As the first metal oxide layer 52 and the second metal oxide layer 54, metal oxides mainly composed of aluminum are used. The first metal oxide layer 52 and the second metal oxide layer 54 can be made of the same material as the first metal oxide film 25. The thickness of the first metal oxide layer 52 and the second metal oxide layer 54 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the first metal oxide layer 52 and the second metal oxide layer 54. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the first metal oxide layer 52 and the second metal oxide layer 54 blocks hydrogen and oxygen released from the first insulating film 16 and the third insulating film 32, and suppresses the release of hydrogen and oxygen reaching the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36.

[0117] When excessive oxygen is supplied to the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36, the excess oxygen can form defect levels different from oxygen vacancies. This may lead to phenomena such as performance fluctuations during reliability testing, a decrease in field-effect mobility, or variations in characteristics.

[0118] By providing a first metal oxide layer 52 and a second metal oxide layer 54 beneath the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36, it is possible to suppress the supply of excess oxygen to the underside of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36. This suppresses the formation of defect levels on the underside of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36. Therefore, it is possible to suppress characteristic fluctuations, decreases in field-effect mobility, or variations in characteristics during reliability testing of the first transistor 210A and the second transistor 220A.

[0119] [Manufacturing method for semiconductor device 100B] A method for manufacturing a semiconductor device 100B according to one embodiment of the present invention will be described using Figures 19 to 23. Figures 19 and 20 are sequence diagrams showing a method for manufacturing a semiconductor device 100B according to one embodiment of the present invention. Figures 21 to 23 are cross-sectional views showing a method for manufacturing a semiconductor device 100B according to one embodiment of the present invention. Detailed explanations of steps similar to those in the first embodiment will be omitted.

[0120] As shown in Figure 19, steps S1101 to S1102 are the same as steps S1001 to S1002 shown in Figure 2.

[0121] In this embodiment, as shown in Figures 19 and 21, after step S1102, a first metal oxide film 51 mainly composed of aluminum is formed on the first insulating film 16 (step S1103 "1st MO film formation" shown in Figure 19).

[0122] The first metal oxide film 51 is formed by sputtering or atomic layer deposition. The thickness of the first metal oxide film 51 is, for example, 1 nm to 50 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the first metal oxide film 51. Aluminum oxide has high barrier properties against gases such as oxygen or hydrogen. In this embodiment, the aluminum oxide used as the first metal oxide film 51 blocks hydrogen and oxygen released from the first insulating film 16 and suppresses the release of hydrogen and oxygen from reaching the first oxide semiconductor layer 22 that is formed later.

[0123] As shown in Figures 19 and 21, a first oxide semiconductor film 17 is deposited on the first metal oxide film 51 (step S1104 "1st OS film deposition" shown in Figure 19). For the method and materials of deposition of the first oxide semiconductor film 17 in this embodiment, please refer to the description of the method and materials of deposition of the first oxide semiconductor film 17 (step S1003 shown in Figure 2).

[0124] As shown in Figure 19, a pattern is formed on the first oxide semiconductor layer (step S1105 "Formation of 1st OS pattern" shown in Figure 19). A resist mask is formed on the first oxide semiconductor film 17, and the first oxide semiconductor film 17 is etched using the resist mask. For the etching method of the first oxide semiconductor film 17 in this embodiment, refer to the description of the etching method of the first oxide semiconductor film 17 (step S1004 shown in Figure 2).

[0125] Next, after pattern formation of the first oxide semiconductor layer 18, the first oxide semiconductor layer 18 is subjected to heat treatment (OS annealing) (the "2nd OS annealing" in step S1015 shown in Figure 3). For the conditions of OS annealing, refer to the explanation of the conditions for OS annealing for the first oxide semiconductor layer 18 (step S1005 shown in Figure 2). The conditions for OS annealing for the second oxide semiconductor layer 34 may be the same as the conditions for OS annealing for the first oxide semiconductor layer 18. As shown in Figures 19 and 22, by performing OS annealing, the first oxide semiconductor layer 18 is crystallized, and a first oxide semiconductor layer 22 having a polycrystalline structure is formed.

[0126] As shown in Figures 18 and 23, the first metal oxide film 51 is patterned to form the first metal oxide layer 52 (step S1107 "1st MO pattern formation" shown in Figure 18). The first oxide semiconductor layer 22, which has been sufficiently crystallized by the heat treatment, has etching resistance. Therefore, when patterning the first metal oxide film 51 using the crystallized first oxide semiconductor layer 22 as a mask, it is possible to suppress the disappearance of the first oxide semiconductor layer 22. The first metal oxide film 51 is etched using the first oxide semiconductor layer 22 patterned in the above process as a mask. Wet etching or dry etching may be used for etching the first metal oxide film 51. For example, diluted hydrofluoric acid (DHF) can be used for wet etching. By etching the first metal oxide film 51 using the first oxide semiconductor layer 22 as a mask, the photolithography process can be omitted.

[0127] Subsequently, the steps S1108 to S1109 shown in Figure 19 are the same as the steps S1006 to S1007 shown in Figure 2, so a detailed explanation is omitted.

[0128] As shown in Figure 19, with the second insulating film 24 and the first metal oxide film 25 deposited on the first oxide semiconductor layer 22, a heat treatment (oxidation annealing) is performed to supply oxygen from the second insulating film 24 to the first oxide semiconductor layer 22 (the "oxidation annealing" in step S1110 shown in Figure 19).

[0129] In this embodiment, a first metal oxide layer 52 is provided beneath the first oxide semiconductor layer 22. When oxide annealing is performed in this state, oxygen released from the first insulating film 16 is blocked by the first metal oxide layer 52, making it difficult for oxygen to be supplied to the lower surface of the first oxide semiconductor layer 22. Oxygen released from the first insulating film 16 diffuses from the region where the first metal oxide layer 52 is not formed to the second insulating film 24 provided on top of the first insulating film 16, and reaches the first oxide semiconductor layer 22 via the second insulating film 24. As a result, oxygen released from the first insulating film 16 is difficult for it to be supplied to the lower surface of the first oxide semiconductor layer 22, and is mainly supplied to the side and top surfaces of the first oxide semiconductor layer 22. Furthermore, due to oxide annealing, oxygen released from the second insulating film 24 is supplied to the top and side surfaces of the first oxide semiconductor layer 22. Although hydrogen may be released from the first insulating films 14 and 16 due to the above oxide annealing, this hydrogen is blocked by the first metal oxide layer 52.

[0130] As described above, the oxide annealing process makes it possible to supply oxygen to the upper and side surfaces of the first oxide semiconductor layer 22, which has a large amount of oxygen vacancies, while suppressing the supply of oxygen to the lower surface of the first oxide semiconductor layer 22, which has a small amount of oxygen vacancies.

[0131] Subsequently, the steps shown in Figure 19 from step 1111 to step 1114 are the same as the steps shown in Figure 2 from step S1009 to step S1012.

[0132] The steps S1115 to S1123 shown in Figure 20 are the same as the steps S1103 to S1111 shown in Figure 19.

[0133] The steps S1124 to S1129 shown in Figure 20 are the same as the steps S1020 to S1025 shown in Figure 3.

[0134] By following the above steps, the semiconductor device 100B shown in Figure 18 can be manufactured.

[0135] In the semiconductor device 100B manufactured by the above manufacturing method, oxygen defects contained in the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36 can be further reduced compared to the manufacturing method of the semiconductor device 100 described in the first embodiment. Therefore, in the semiconductor device 100B described in this embodiment, when the channel length L of the channel region CH of the first transistor 210A and the second transistor 220A is in the range of 2 μm to 4 μm, and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 50 cm 2 / Vs or more, 55cm 2 / Vs or higher, or 60cm 2 Electrical characteristics of / Vs or higher can be obtained.

[0136] Furthermore, it is possible to suppress the supply of excess oxygen to the underside of the first oxide semiconductor layer 22 and the second oxide semiconductor layer 36. In particular, by sufficiently reducing the oxygen vacancies contained in the channel region CH, it is possible to suppress hydrogen from being trapped in the oxygen vacancies. As a result, characteristic fluctuations in reliability tests of the first transistor 210A and the second transistor 220A can be reduced, thereby improving the reliability of the semiconductor device.

[0137] Furthermore, the second transistor 220A can be formed without significant changes to the process for forming the first transistor 210A. Therefore, the manufacturing cost in the manufacturing method of the semiconductor device 100B can be reduced.

[0138] <Variation 2> In the manufacturing method of semiconductor device 100B, steps S1109 and S1110 shown in Figure 19 and steps S1121 and S1123 shown in Figure 20 may be omitted. In this case, oxide annealing is performed without the first metal oxide film 25 being formed on the second insulating film 24. Even in this state, oxygen is supplied from the second insulating film 24 provided on the first oxide semiconductor layer 22. Furthermore, since the first metal oxide layer 52 is provided below the first oxide semiconductor layer 22, it is possible to suppress the supply of excess oxygen to the lower surface of the first oxide semiconductor layer 22. Therefore, in the range where the channel length L of the channel region CH of the first transistor 210 is 2 μm or more and 4 μm or less, and the channel width of the channel region CH is 2 μm or more and 25 μm or less, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or higher, or 40cm 2 Electrical characteristics of / Vs or higher can be obtained. Furthermore, the second transistor 220 can obtain the same characteristics as the first transistor 210.

[0139] <Variation 3> In a semiconductor device according to one embodiment of the present invention, a first transistor 210 (see Figure 1) and a second transistor 220A (see Figure 18) can also be combined and configured on a substrate 10. In this case, in the sequence showing the manufacturing method of the semiconductor device shown in Figure 2, after performing the steps shown in steps S1001 to S1012, the steps shown in steps S1115 to S1129 shown in Figure 20 can be performed.

[0140] Furthermore, in a semiconductor device according to one embodiment of the present invention, a first transistor 210A (see Figure 18) and a second transistor 220 (see Figure 1) can be combined and configured on a substrate 10. In this case, in the sequence showing the manufacturing method of the semiconductor device shown in Figure 19, after performing the steps shown in steps S1101 to S1114, the steps shown in steps S1013 to S1025 shown in Figure 3 can be performed.

[0141] Thus, in the semiconductor device manufacturing method according to one embodiment of the present invention, two types of transistors with different mobilities can be stacked without significant changes to the process. Therefore, the manufacturing cost in the manufacturing method of the semiconductor device 100B can be reduced.

[0142] In the first and second embodiments, the first transistor 210 and the second transistor 220 were described using a top-gate structure, but the embodiment of the present invention is not limited thereto. A staggered transistor structure may also be used for the first transistor 210 and the second transistor 220.

[0143] <Third Embodiment> A display device 20 using a semiconductor device 100 according to one embodiment of the present invention will be described with reference to Figures 24 to 27. First, a configuration in which the semiconductor device 100 is applied to the circuit of a liquid crystal display device will be described.

[0144] [Overview of the display device 20] Figure 24 is a plan view showing an overview of a display device 20 according to one embodiment of the present invention. As shown in Figure 24, the display device 20 has an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the sealing portion 310. Multiple pixel circuits 301 are arranged in a matrix in the liquid crystal region 23 surrounded by the sealing portion 310. The liquid crystal region 23 is the region that overlaps with the liquid crystal element 311, which will be described later, in a plan view.

[0145] The sealing region 21, where the sealing portion 310 is provided, is the area surrounding the liquid crystal region 23. The FPC 330 is provided in the terminal region 27. The terminal region 27 is the area where the array substrate 300 is exposed from the opposing substrate 320, and is provided outside the sealing region 21. The area outside the sealing region 21 means the area outside where the sealing portion 310 is provided and the area enclosed by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals to drive each pixel circuit 301.

[0146] [Circuit configuration of display device 20] Figure 25 is a block diagram showing the circuit configuration of a display device 20 according to one embodiment of the present invention. As shown in Figure 25, a source driver circuit 302 is provided at a position adjacent to the liquid crystal area 23 where the pixel circuit 301 is arranged in the second direction D2 (column direction), and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal area 23 in the first direction D1 (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the seal area 21. However, the area in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the seal area 21, but can be any area outside the area in which the pixel circuit 301 is provided.

[0147] Source wiring 304 extends from source driver circuit 302 in the second direction D2 and is connected to multiple pixel circuits 301 arranged in the second direction D2. Gate gate 160 extends from gate driver circuit 303 in the first direction D1 and is connected to multiple pixel circuits 301 arranged in the first direction D1.

[0148] A terminal section 306 is provided in the terminal area 27. The terminal section 306 and the source driver circuit 302 are connected by a connecting wire 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connecting wire 307. When the FPC 330 is connected to the terminal section 306, the external device to which the FPC 330 is connected is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0149] The semiconductor device 100 can be applied to the pixel circuit 301, the source driver circuit 302, and the gate driver circuit 303. By applying the semiconductor device 100 to the source driver circuit 302 and the gate driver circuit 303, it is possible to stack the first transistor 210 and the second transistor 220. Therefore, even if the source driver circuit 302 and the gate driver circuit 303 have a high degree of integration, the occupied area can be reduced. This makes it possible to narrow the bezel of the display device 20. Although the case in which the semiconductor device 100 is applied to the source driver circuit 302 and the gate driver circuit 303 has been described, semiconductor devices 100A and 100B may also be applied to the source driver circuit 302 and the gate driver circuit 303.

[0150] [Pixel circuit 301 of liquid crystal display device] Next, we will describe the case where the semiconductor device 100 is applied to the pixel circuit of a liquid crystal display device. Figure 26 is a circuit diagram showing the pixel circuit of a display device 20 according to one embodiment of the present invention. As shown in Figure 26, the pixel circuit 301 includes elements such as a first transistor 210, a retaining capacitor 350, and a liquid crystal element 311. The first transistor 210 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to the gate wiring 305. The source electrode 201 is connected to the source wiring 304. The drain electrode 203 is connected to one end of the retaining capacitor 350 and one end (pixel electrode) of the liquid crystal element 311. In this embodiment, for the sake of explanation, the electrode indicated by reference numeral "201" is called the source electrode and the electrode indicated by reference numeral "203" is called the drain electrode, however, the electrode indicated by reference numeral "201" may function as the drain electrode and the electrode indicated by reference numeral "203" may function as the source electrode.

[0151] In the first transistor 210, the second gate electrode 26GE-1 corresponds to the gate electrode 160, the first source electrode 44S corresponds to the source electrode 201, and the first drain electrode 44D corresponds to the drain electrode 203. The first gate electrode 12GE may function as the back gate of the first transistor 210, or the first gate electrode 12GE may be in a floating state.

[0152] In the pixel circuit 301, when the second transistor 220 is used, the fourth gate electrode 44GE corresponds to the gate electrode 160, the second source electrode 52S corresponds to the source electrode 201, and the second drain electrode 52D corresponds to the drain electrode 203. The third gate electrode 26GE-2 may function as the back gate of the second transistor 220, or the third gate electrode 26GE-2 may be in a floating state.

[0153] As described in the previous embodiment, the first transistor 210 and the second transistor 220 can be superimposed. Therefore, by applying the first transistor 210 and the second transistor 220 to adjacent pixels, the first transistor 210 and the second transistor 220 can be superimposed on each other. This reduces the area occupied by the first transistor 210 and the second transistor 220 in the pixel, thereby improving the aperture ratio of the pixel. Although Figure 26 describes the case where semiconductor device 100 is applied to the pixel circuit, semiconductor devices 100A and 100B may also be applied to the pixel circuit.

[0154] [Pixel circuit 301 of EL display device] Next, we will describe the case where the semiconductor device 100 described in the first embodiment is applied to the circuit of an organic EL display device. The overview and circuit configuration of the display device 20 are the same as those shown in Figures 24 and 25, so we will omit the explanation.

[0155] Figure 27 is a circuit diagram showing the pixel circuit of a display device 20 according to one embodiment of the present invention. As shown in Figure 27, the pixel circuit 301 includes elements such as a selection transistor 11, a drive transistor 13, a holding capacitor 350, and a light-emitting element DO. Here, we will describe the case in which the first transistor 210 is applied to the selection transistor 11 and the second transistor 220 is applied to the drive transistor 13.

[0156] The source electrode of the selection transistor 11 is connected to the signal line 211, and the gate electrode of the selection transistor 11 is connected to the gate line 212. The source electrode of the drive transistor 13 is connected to the anode power line 213, and the drain electrode of the drive transistor 13 is connected to one end (pixel electrode) of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the drive transistor 13 is connected to the drain electrode of the selection transistor 11. The retaining capacitor 350 is connected to the gate electrode and drain electrode of the drive transistor 13. The signal line 211 is supplied with a gradation signal that determines the light emission intensity of the light-emitting element DO. The gate line 212 is supplied with a signal that selects the pixel row on which to write the above gradation signal.

[0157] The second gate electrode 26GE-1 of the first transistor 210 corresponds to the gate electrode of the selection transistor 11, the first source electrode 44S corresponds to the source electrode of the selection transistor 11, and the first drain electrode 44D corresponds to the drain electrode of the selection transistor 11. The first gate electrode 12GE may function as the back gate of the first transistor 210, or the first gate electrode 12GE may be in a floating state.

[0158] The fourth gate electrode 44GE of the second transistor 220 corresponds to the gate electrode 160 of the drive transistor 13, the second source electrode 52S corresponds to the source electrode 201 of the drive transistor 13, and the second drain electrode 52D corresponds to the drain electrode 203 of the drive transistor 13. The third gate electrode 26GE-2 may function as the back gate of the second transistor 220, or the third gate electrode 26GE-2 may be in a floating state.

[0159] Figure 27 illustrates a case where the lower-layer first transistor 210 is used for the selection transistor 11 and the upper-layer second transistor 220 is used for the drive transistor 13. However, the transistors used in this embodiment are not limited. For example, the upper-layer second transistor 220 may be used for the selection transistor 11 and the lower-layer first transistor 210 may be used for the drive transistor 13. Furthermore, the number of transistors constituting the pixel circuit in the EL display device is not limited. The number of transistors constituting the pixel circuit may be three or more. Therefore, among the multiple transistors constituting the pixel circuit, some may be provided in the lower layer and the remaining transistors may be provided in the upper layer. This allows multiple transistors to be configured in a small area, thereby enabling higher resolution.

[0160] In the third embodiment, an example was given of applying the semiconductor device described in the first embodiment to a liquid crystal display device and an organic EL display device. However, the semiconductor device may also be applied to other display devices (for example, self-emissive display devices other than organic EL display devices or electronic paper type display devices). Furthermore, the semiconductor device 100 can be applied to a wide range of display devices, from small to medium-sized to large, without any particular limitations. In Figure 27, the case in which the semiconductor device 100 is applied to a pixel circuit was described, but semiconductor devices 100A and 100B may also be applied to the pixel circuit.

[0161] The embodiments and modifications described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, semiconductor devices and display devices of the embodiments and modifications described above that have been modified by those skilled in the art, with additions, deletions, or design changes to components, or with additions, omissions, or changes to processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0162] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0163] 10: Substrate, 12GE: First gate electrode, 12GE-2: Fifth gate electrode, 14, 16: First insulating film, 17: First oxide semiconductor film, 18: First oxide semiconductor layer, 19: Resist mask, 22: First oxide semiconductor layer, 22-1: First oxide semiconductor layer, 22-2: Third oxide semiconductor layer, 22CH: First channel region, 22CH-2: Third channel region, 22D: First drain region, 22D-1: First drain region, 22S: First source region, 22S-2: Third source region, 24: Second insulating film, 25: First metal oxide film, 26CH: Channel region, 26GE-1: Second gate electrode, 26GE-2: Third gate electrode, 26GE-3: Sixth gate electrode, 28, 32: Third insulating film, 33: Second oxide Semiconductor film, 34: second oxide semiconductor layer, 36: second oxide semiconductor layer, 36CH: second channel region, 36CH-3: third channel region, 36D: second drain region, 36S: second source region, 38: fourth insulating film, 42: second metal oxide film, 44D: first drain electrode, 44GE: fourth gate electrode, 44S: first source electrode, 46, 48: fifth insulating film, 51: first metal oxide film, 52: first metal oxide layer, 52D: second drain electrode, 52E-1: first electrode, 52E-2: second electrode, 52S: second source electrode, 54: second metal oxide layer, 100, 100A, 100B: semiconductor device, 210, 210A: first transistor, 220, 220A: second transistor, 230: third transistor

Claims

1. A first transistor is provided on the substrate, The device comprises a second transistor provided on top of the first transistor, The first transistor is, A first gate electrode provided on the substrate, A first insulating film provided on the first gate electrode, A first oxide semiconductor layer provided on the first insulating film and having a region overlapping with the first gate electrode, A second insulating film is provided on the first oxide semiconductor layer, The device includes a second gate electrode provided on the second insulating film, The aforementioned second transistor is A third gate electrode provided on the second insulating film, A third insulating film provided on the third gate electrode, A region provided on the third insulating film and overlapping with the third gate electrode, comprising a second oxide semiconductor layer, A fourth insulating film provided on the aforementioned second oxide semiconductor layer, A semiconductor device comprising a fourth gate electrode provided on the fourth insulating film.

2. The first oxide semiconductor layer is The first region overlapping with the first gate electrode, A second region that does not overlap with the first gate electrode, The semiconductor device according to claim 1, wherein the electrical conductivity of the second region is greater than that of the first region.

3. The aforementioned second oxide semiconductor layer is A third region overlapping with the second gate electrode, A fourth region that does not overlap with the second gate electrode, The semiconductor device according to claim 2, wherein the electrical conductivity of the fourth region is greater than that of the third region.

4. The semiconductor device according to claim 3, wherein, when viewed in cross-section, the second region of the first oxide semiconductor layer and the fourth region of the second oxide semiconductor layer are superimposed.

5. The system further comprises a third transistor provided on the aforementioned substrate, The aforementioned third transistor is A fifth gate electrode provided on the aforementioned substrate, The first insulating film provided on the fifth gate electrode, A third oxide semiconductor layer provided on the first insulating film and having a region overlapping with the fifth gate electrode, The second insulating film provided on the third oxide semiconductor layer, The semiconductor device according to claim 4, further comprising a sixth gate electrode provided on the second insulating film.

6. The aforementioned third oxide semiconductor layer is A fifth region overlapping with the fifth gate electrode, A sixth region that does not overlap with the fifth gate electrode, The semiconductor device according to claim 5, wherein the electrical conductivity of the sixth region is greater than that of the fifth region.

7. The semiconductor device according to claim 6, wherein the fourth region of the second oxide semiconductor layer overlaps with the second region of the first oxide semiconductor layer and the sixth region of the third oxide semiconductor layer.

8. The semiconductor device according to claim 1, further comprising a first metal oxide layer provided between the first insulating film and the first oxide semiconductor layer.

9. The semiconductor device according to claim 1, further comprising a second metal oxide layer provided between the third insulating film and the second oxide semiconductor layer.

10. The semiconductor device according to claim 5, further comprising a third metal oxide layer provided between the first insulating film and the third oxide semiconductor layer.

11. The thickness of the second insulating film is thinner than the thickness of the first insulating film. The semiconductor device according to claim 1, wherein the thickness of the fourth insulating film is thinner than the thickness of the second insulating film.

12. The first transistor further comprises a first source electrode and a first drain electrode, which are provided on the same insulating film as the fourth gate electrode. The semiconductor device according to claim 1, wherein the first source electrode and the first drain electrode are connected to the first oxide semiconductor layer via contact holes provided in the second insulating film, the third insulating film, and the fourth insulating film.

13. The semiconductor device according to claim 1, wherein each of the first insulating film and the third insulating film has a laminated structure of a silicon nitride film and a silicon oxide film.

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