Manufacturing method of surface emission semiconductor laser element, and surface emission semiconductor laser element

Abstract

To provide a manufacturing method of a surface emission semiconductor laser element having a high quality active layer, a lower threshold, and a higher efficiency, and is capable of enhancing a resonance effect by arranging a vacancy layer and an active layer close to each other.SOLUTION: A hole formation preparation layer is formed on a substrate (a), a hole formation layer is formed by forming, on the hole formation preparation layer, holes two-dimensionally arranged at each of lattice points (b), a first embedded layer is formed by performing facet growth for occluding the holes (c), a vacancy layer having vacancies corresponding to holes is formed by performing growth of a second embedded layer for flatly embedding the first embedding layer (d), flat etching of the second embedding layer is performed by annealing in hydrogen atmosphere (e), and crystal growth of a semiconductor layer containing an active layer is performed on the flatly etched second embedded layer (f).SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a surface emitting semiconductor laser element having a photonic crystal, and to a surface emitting semiconductor laser element. [Background technology]

[0002] 2. Description of the Related Art In recent years, development of photonic-crystal surface-emitting lasers (PCSELs) using photonic crystals (PCs) has been progressing.

[0003] For example, Patent Document 1 proposes a method of embedding holes having a hexagonal columnar structure with side faces consisting of {10-10} in a group III nitride semiconductor layer using facet selective growth in order to enhance the diffraction effect in the hole layer in a photonic crystal laser and obtain a high resonance effect. It describes how this realizes a photonic crystal laser element equipped with a photonic crystal having a large filling factor and a large optical confinement coefficient.

[0004] Furthermore, Patent Document 2 proposes a method for embedding holes in a group III nitride semiconductor layer using mass transport in a photonic crystal laser, and describes how this method provides a photonic crystal laser with a large coupling coefficient for light waves propagating through the photonic crystal layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 7101370 [Patent Document 2] JP 2020-38892 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, when the method described in Patent Document 1 is used, a hole layer with a sufficient hole filling rate can be formed, but the layer thickness for embedding the hole layer becomes thick, and the distance between the hole layer and the active layer cannot be reduced, which means that the resonance effect in the hole layer cannot be enhanced.

[0007] In addition, Patent Document 2 proposes a method of filling holes using mass transport, but when this method is used, the holes are filled with a columnar structure, which is the most thermally stable cross-sectional shape, that is, a regular hexagonal columnar structure. Therefore, it is difficult to introduce asymmetry into the cross-sectional shape of the holes, and high extraction efficiency cannot be obtained. In other words, high-output operation is not possible.

[0008] For the reasons described above, in the conventional technology, it has been difficult to increase the resonance effect and lower the threshold current while maintaining a high output.

[0009] An object of the present invention is to provide a method for manufacturing a surface-emitting semiconductor laser element that is capable of increasing the resonance effect by bringing a hole layer and an active layer into close proximity, has a high-quality active layer, and has a low threshold and high efficiency, and also provides the surface-emitting semiconductor laser element. [Means for solving the problem]

[0010] A method for manufacturing a surface emitting semiconductor laser device according to one embodiment of the present invention includes the steps of: forming a hole formation preparation layer on a substrate; forming holes arranged two-dimensionally at each lattice point in the hole formation preparation layer to form a hole formation layer; forming a first burying layer by performing facet growth to close the hole; growing a second burying layer that buries the first burying layer evenly to form a void layer having voids corresponding to the holes; annealing the second buried layer in a hydrogen atmosphere to flatten the second buried layer; Crystal growth of a semiconductor layer including an active layer is performed on the flat etched second buried layer.

[0011] A surface emitting semiconductor laser device according to one embodiment of the present invention comprises: A photonic crystal surface emitting laser element manufactured by the above manufacturing method, The distance between the active layer and the hole layer is 200 nm or less. [Brief description of the drawings]

[0012] [Figure 1A] 1 is a cross-sectional view illustrating an example of the structure of a PCSEL element according to a first embodiment. [Figure 1B] 1B is an enlarged cross-sectional view showing a schematic diagram of holes arranged in the hole layer shown in FIG. 1A. [Figure 2A] FIG. 2 is a plan view showing a schematic top surface of a PCSEL element. [Figure 2B] 2 is a cross-sectional view that diagrammatically shows a cross section in a plane parallel to an n-side guide layer. FIG. [Figure 2C] FIG. 2 is a plan view showing a schematic view of the bottom surface of a PCSEL element. [Diagram 3] 1 is a flowchart showing a method for manufacturing the PCSEL device of the first embodiment. [Figure 4] 3A to 3C are cross-sectional views that diagrammatically show cross sections of an n-side guide layer in steps S0 to S3 of forming a buried layer. [Diagram 5] FIG. 2 is a plan view showing a schematic view of main openings and sub-openings in a resist, and main holes and sub-holes after etching. [Figure 6] 3 is a schematic diagram showing a cross section perpendicular to a central axis CX of a formed hole layer. FIG. [Figure 7A] 1 shows an SEM image of a wafer cross section when the etching time is (i) 5 minutes. [Figure 7B] 13 is an SEM image of a wafer cross section when the etching time is (ii) 20 minutes. [Figure 7C] 13 is an SEM image of a wafer cross section when the etching time is (iii) 50 minutes. [Figure 8] FIG. 2 is a diagram showing an AFM image of the surface of an active layer. [Figure 9A]FIG. 13 is a diagram showing the measurement results of surface roughness when the etching time is (ii) 20 minutes. [Figure 9B] FIG. 13 is a diagram showing the measurement results of surface roughness when the etching time is (iii) 50 minutes. [Figure 10] FIG. 13 is a diagram showing the measured surface roughness Ra of a 20 μm×20 μm area versus the layer thickness of the buried layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the following, preferred embodiments of the present invention will be described, which may be modified and combined as appropriate. In the following description and accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0014] [First embodiment] 1. Structure of photonic crystal surface-emitting laser element A photonic crystal surface-emitting laser element (PCSEL element) is a surface-emitting semiconductor laser element that has a resonator layer in a direction parallel to the semiconductor light-emitting structure layers (n-side guide layer, light-emitting layer, p-side guide layer) that constitute the light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.

[0015] That is, in a PCSEL element, light waves propagating in a plane parallel to the air hole layer (photonic crystal layer) are diffracted by the diffraction effect of the photonic crystal to form a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to the parallel plane. That is, in a PCSEL element, the light extraction direction is perpendicular to the resonance direction (in the plane parallel to the air hole layer).

[0016] Fig. 1A is a cross-sectional view showing an example of the structure of a photonic crystal surface-emitting laser device (PCSEL device) 10 according to an embodiment of the present invention, and Fig. 1B is an enlarged cross-sectional view showing an air hole layer 14P and air holes 14K arranged in the air hole layer 14P in Fig. 1A.

[0017] 2A is a plan view diagrammatically illustrating the upper surface of the PCSEL device 10. FIG 2B is a cross-sectional view diagrammatically illustrating the cross section of the hole layer 14P in a plane parallel to the n-side guide layer 14, and FIG 2C is a plan view diagrammatically illustrating the lower surface of the PCSEL device 10. 1A, a semiconductor structure layer 11 is formed on a light-transmitting element substrate 12. Note that semiconductor layers are stacked perpendicularly to a central axis CX of the semiconductor structure layer 11.

[0018] The semiconductor structure layer 11 is made of a hexagonal nitride semiconductor. In this embodiment, the semiconductor structure layer 11 is made of, for example, a GaN-based semiconductor.

[0019] More specifically, a semiconductor structure layer 11 consisting of a plurality of semiconductor layers is formed on an element substrate 12, in this order: an n-clad layer (first clad layer of a first conductivity type) 13, an n-side guide layer (first guide layer) 14 which is a guide layer provided on the n-side, a light distribution adjustment layer 23, an active layer (ACT) 15, a p-side guide layer (second guide layer) 16 which is a guide layer provided on the p-side, an electron barrier layer (EBL: Electron Blocking Layer) 17, a p-clad layer (second clad layer of a second conductivity type) 18, and a p-contact layer 19.

[0020] Although the case will be described where the first conductivity type is n-type and the second conductivity type opposite to the first conductivity type is p-type, the first conductivity type and the second conductivity type may be p-type and n-type, respectively.

[0021] The element substrate 12 is a hexagonal GaN single crystal substrate having a high transmittance for light emitted from the active layer 15. More specifically, the element substrate 12 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is a +c plane, which is a {0001} plane in which Ga atoms are arranged on the outermost surface. The back surface (light emission surface) is a -c plane, which is a (000-1) plane in which N atoms are arranged on the outermost surface. The -c plane is suitable as a light emission surface because it is resistant to oxidation and the like.

[0022] Although the element substrate 12 is not limited thereto, a so-called just substrate or, for example, a substrate whose main surface is offset by about 1° in the m-axis direction is preferable. For example, a substrate offset by about 0.3 to 0.7° in the m-axis direction can obtain mirror-finish growth under a wide range of growth conditions.

[0023] The back surface of the substrate opposite to the main surface is the light emitting surface, which is the "-c" surface, which is the (000-1) surface with N atoms arranged on the outermost surface. The -c surface is resistant to oxidation and is therefore suitable as a light extraction surface.

[0024] The composition, thickness, and other configurations of each semiconductor layer will be described below, but these are merely examples and can be modified as appropriate.

[0025] The n-clad layer 13 is, for example, n-Al 0.04 Ga 0.96 The N layer has a thickness of 2 μm. The aluminum (Al) composition ratio is set so that the refractive index is smaller than that of the layer adjacent to the active layer 15 side (that is, the n-side guide layer 14).

[0026] The n-side guide layer 14 is composed of a lower guide layer 14A, an air-hole layer (or PC layer) 14P, which is a photonic crystal layer, and a buried layer 14B. As shown in FIG. 1B, the air-hole layer 14P has a layer thickness d PC and the buried layer 14B has a thickness D. For example, the hole layer 14P has a thickness d PC is 40 to 180 nm.

[0027] In this specification, the air hole layer 14P refers to a layer portion from the upper end to the lower end of the air hole in the n-side guide layer 14 (see FIG. 1B). PC is equal to the height of the hole.

[0028] The lower guide layer 14A is, for example, n-GaN having a layer thickness of 100 to 400 nm. The void layer 14P is n-GaN having a layer thickness (or the height of the voids 14K) of 40 to 180 nm.

[0029] The buried layer 14B is made of n-GaN or n-InGaN, or undoped GaN or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked. The layer thickness D of the buried layer 14B is, for example, 30 to 150 nm. The buried layer 14B is made of a first buried layer 14B1 and a second buried layer 14B2. In other words, the buried layer 14B is a stacked buried layer in which the second buried layer 14B2 is stacked on the first buried layer 14B1.

[0030] A light distribution adjustment layer 23 is provided on the second embedded layer 14B2, which is the surface layer of the embedded layer 14B. The light distribution adjustment layer 23 is a hetero semiconductor layer (a heterogeneous semiconductor layer) that has a different crystal composition from the second embedded layer 14B2 and forms a heterostructure with the second embedded layer 14B2.

[0031] The light distribution adjustment layer 23 may be a semiconductor layer of the same conductivity type as the second embedded layer 14B2, or at least one of them may be an i-layer (intrinsic semiconductor layer).

[0032] The light distribution adjustment layer 23 is provided between the buried layer 14B and the active layer 15, and has a function of adjusting the coupling efficiency between the light propagating in the hole layer 14P and the hole layer 14P acting as a resonator.

[0033] In this embodiment, the light distribution adjustment layer 23 is made of undoped In. 0.03 Ga 0.97 The light distribution adjustment layer 23 has N layers and a layer thickness of, for example, 50 nm. The layer thickness of the light distribution adjustment layer 23 is selected according to the composition or refractive index of the light distribution adjustment layer 23 and the layer thickness according to the adjustment of the coupling efficiency.

[0034] The n-side semiconductor layer including the n-side guide layer 14 and the light distribution adjustment layer 23 is also referred to as a first semiconductor layer, but the light distribution adjustment layer 23 does not necessarily have to be provided.

[0035] The active layer 15, which is a light emitting layer, is, for example, a multiple quantum well (MQW) layer having two quantum well layers. The barrier layer and quantum well layer of the MQW are GaN (layer thickness 6.0 nm) and InGaN (layer thickness 4.0 nm), respectively. The central emission wavelength of the active layer 15 is 440 nm.

[0036] The active layer 15 is preferably disposed within 180 nm of the hole layer 14P (that is, within the period PK of the holes), in which case a high resonance effect is obtained by the hole layer 14P.

[0037] The p-side guide layer 16 is an undoped In 0.02 Ga 0.98 It is composed of a p-side guide layer (1) 16A which is an N layer (layer thickness 70 nm) and a p-side guide layer (2) 16B which is an undoped GaN layer (layer thickness 180 nm).

[0038] The p-side guide layer 16 is an undoped layer in consideration of light absorption by dopants (Mg: magnesium, etc.), but may be doped to obtain good electrical conductivity. In addition, the In composition and layer thickness of the p-side guide layer (1) 16A can be appropriately selected to adjust the electric field distribution in the oscillation operation mode.

[0039] The electron barrier layer (EBL) 17 is a magnesium (Mg) doped p-type Al 0.2 Ga 0.8 N layers, for example, having a layer thickness of 15 nm.

[0040] The p-cladding layer 18 is made of Mg-doped p-Al 0.06 Ga 0.94 The p-cladding layer 18 is an N layer having a thickness of, for example, 600 nm. The Al composition of the p-cladding layer 18 is preferably selected so that the refractive index is smaller than that of the p-side guide layer 16. The p-cladding layer 18 functions as a first p-cladding layer.

[0041] The p-contact layer 19 is a Mg-doped p-GaN layer having a thickness of, for example, 20 nm. The carrier density of the p-contact layer 19 is set to a concentration that allows ohmic junction with the transparent electrode 29, which is a transparent conductive layer provided on the surface of the p-contact layer 19. Instead of p-type GaN, p-type or undoped InGaN may be used. Alternatively, a layer in which a GaN layer and an InGaN layer are stacked may be used.

[0042] The layer consisting of the p-side guide layer 16, the electron barrier layer 17, the p-cladding layer 18 and the p-contact layer 19 is also referred to as a second semiconductor layer.

[0043] In this specification, "n-side" and "p-side" do not necessarily mean n-type and p-type. For example, the n-side guide layer means a guide layer provided on the n-side of the active layer, and may be an undoped layer (or an i-layer).

[0044] In addition, the n-cladding layer 13 may be composed of multiple layers instead of a single layer, and in that case, all layers do not need to be n layers (n-doped layers) and may include an undoped layer (i layer). The same applies to the guide layer 16 and the p-cladding layer 18.

[0045] Furthermore, it is not necessary to provide all of the semiconductor layers described above, and it is sufficient to have a configuration having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer (light-emitting layer) sandwiched between these layers.

[0046] Furthermore, in this embodiment, the case where the vacancy layer 14P is provided in the first semiconductor layer (n-type semiconductor layer) has been described, but the vacancy layer may be provided in the second semiconductor layer (p-type semiconductor layer). On the p-contact layer 19, a p-electrode 20B (second electrode) is formed as a translucent electrode / Ag / Au layer in which a translucent electrode 29 (not shown), a silver (Ag) layer, and a gold (Au) layer are laminated in this order. That is, the p-electrode 20B functions as a light reflecting layer, and the interface between the translucent electrode 29 and the Ag layer of the p-electrode 20B is a reflecting surface SR. The reflecting surface SR is provided parallel to the hole layer 14P.

[0047] The p-electrode 20B has a circular shape with a diameter RA centered on the central axis CX of the hole formation region 14R. Specifically, the light-transmitting electrode 29 has a diameter of, for example, RA=300 μm in top view (i.e., when viewed from a direction perpendicular to the semiconductor structure layer 11).

[0048] The p-electrode 20B may also be made of Pd, Al, an Al alloy, etc. A pad electrode or the like may be provided on the p-electrode 20B.

[0049] The transparent electrode 29 is formed of a transparent conductor, for example, indium tin oxide (ITO). Note that the transparent electrode 29 is not limited to ITO, and other transparent conductors such as zinc tin oxide (ZTO), GZO (ZnO:Ga), and AZO (ZnO:Al) can be used.

[0050] The side and top surfaces of the semiconductor structure layer 11 and the side surfaces of the p-electrode 20B are made of SiO 2 The p-electrode 20B is covered with an insulating film 21 such as the insulating film 21. The insulating film 21 is formed so as to overlap the p-electrode 20B and cover the edge of the upper surface of the p-electrode 20B.

[0051] The insulating film 21 also functions as a protective film, protecting the aluminum (Al)-containing crystal layers that make up the PCSEL element 10 from corrosive gases and the like. It also prevents short circuits caused by adhesions or solder creeping up during mounting, contributing to improved reliability and yield. The material of the insulating film 21 is SiO 2 Not limited to ZrO 2 , HfO 2 , TiO 2 , Al 2 O 3 , SiNx, etc. can be selected.

[0052] A circular cathode electrode 20A (first electrode) (see FIG. 2C) is formed on the back surface of the element substrate 12. In addition, an anti-reflection (AR) coating layer 27 is formed on the inner side of the cathode electrode 20A.

[0053] The cathode electrode 20A is made of Ti / Au and is in ohmic contact with the element substrate 12. In addition to Ti / Au, the electrode material may be selected from Ti / Al, Ti / Rh, Ti / Al / Pt / Au, Ti / Pt / Au, and the like.

[0054] The light emitted from the active layer 15 is diffracted by the air hole layer (PC layer) 14P. The light diffracted by the air hole layer 14P (diffraction surface WS) and directly emitted from the air hole layer 14P (direct diffracted light Ld: first diffracted light) and the light emitted by the diffraction of the air hole layer 14P and reflected by the reflecting surface SR (reflected diffracted light Lr: second diffracted light) are emitted to the outside from a light emission region 20L (FIG. 2C) of the rear surface (emission surface) 12R of the element substrate 12.

[0055] As shown in Fig. 2B, in the hole layer 14P, the holes 14K are periodically arranged in, for example, a rectangular hole-formation region 14R. As shown in Fig. 2C, the anode region RA is formed so as to be included in the hole-formation region 14R.

[0056] The cathode electrode 20A is provided as a ring-shaped electrode outside the p-electrode 20B so as not to overlap with the p-electrode 20B when viewed from a direction perpendicular to the hole layer 14P.

[0057] The region inside the cathode electrode 20A is the light emission region 20L. Also provided is a bonding pad 20C that is electrically connected to the cathode electrode 20 and for connecting a wire for power supply from the outside.

[0058] 2. Manufacturing method of the void layer and recrystallization growth The fabrication process and recrystallization growth of the hole layer are described below. Metalorganic Vapor Phase Epitaxy (MOVPE) is used as the crystal growth method. Note that the formation method is described below using the case where the hole layer 14P is a double lattice photonic crystal layer as an example, but a single lattice photonic crystal layer and a multiple lattice photonic crystal layer can also be formed in the same manner.

[0059] (a) Manufacturing flow Fig. 3 is a flowchart showing a method for manufacturing the PCSEL device 10. Below, with reference to Fig. 3, a detailed description will be given of the steps for manufacturing the PCSEL device 10 by forming air holes in the air hole layer by performing filling growth in the recesses (holes) and then growing the active layer and p-side guide layer.

[0060] 4 is a cross-sectional view that typically illustrates the cross section of the n-side guide layer 14 in steps S0 to S3 of forming the embedded layer 14B. For ease of explanation and understanding, FIG. 4 illustrates a case in which the hole layer 14P is a single lattice photonic crystal layer, but a multiple lattice photonic crystal layer can also be formed in the same manner.

[0061] The buried layer 14B (laminated buried layer) formed on the air-holes by recrystallization growth will be described in detail below with reference to FIGS.

[0062] (Step S0) Formation of holes First, an n-type Al layer having an Al composition of 4% was formed on a substrate 12 as an n-clad layer 13. 0.04 Ga 0.96 An N layer was grown. Then, a hole formation preparation layer 14E, which is an n-type GaN layer, was grown on the n-cladding layer 13. This hole formation preparation layer 14E is a preparation layer for forming the lower guide layer 14A and the hole layer 14P containing holes. The hole formation preparation layer 14E has a surface (upper surface) consisting of a flat (0001) plane.

[0063] After the hole formation preparation layer 14E was formed, the substrate was removed from the chamber of the MOVPE apparatus, and fine recesses (holes) were formed on the surface of the growth layer. After obtaining a clean surface by cleaning, a silicon nitride film (SiN x A resist for electron beam lithography was applied on top of this, and the device was placed in an electron beam lithography system to pattern a two-dimensional periodic structure.

[0064] Fig. 5 is a plan view showing the main opening K1 and sub-opening K2 of the resist, and the main hole 14H1 and sub-hole 14H2 after etching. As shown in Fig. 5, a pair of openings consisting of an oval main opening K1 and a sub-opening K2 smaller than the main opening K1 was two-dimensionally arranged in the plane of the resist in a square lattice shape with a period PK. For clarity of the drawing, the openings are shown with hatching.

[0065] More specifically, the main apertures K1 are arranged two-dimensionally with their centers of gravity CD1 in two mutually orthogonal directions (x-direction and y-direction) on the lattice points of a square lattice with a period PK, and the sub-apertures K2 are arranged two-dimensionally with their centers of gravity CD2 in the x-direction and y-direction on the lattice points of a square lattice with a period PK.

[0066] The major axes of the main aperture K1 and the sub aperture K2 are parallel to the <11-20> direction of the crystal orientation, and the minor axes of the main aperture K1 and the sub aperture K2 are parallel to the <1-100> direction.

[0067] The center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 by Δx and Δy. Here, Δx=Δy. That is, the center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 in the <1-100> direction.

[0068] The distance Δx, Δy between the centers of gravity of the main opening K1 and the sub-opening K2 was set to Δx=Δy=0.46PK. After developing the patterned resist, a SiN x The film was selectively dry etched. As a result, main openings K1 and sub-openings K2 arranged two-dimensionally on the lattice points of a square lattice with a period PK were formed in the SiN x formed to penetrate the membrane.

[0069] The period (hole spacing) PK was set to PK=177.5 nm in order to set the oscillation wavelength (λ) to 438 nm.

[0070] Next, the resist is removed and the patterned SiN x Using the film as a hard mask, recesses (holes) were formed on the GaN surface. A main hole 14H1 and a sub-hole 14H2, which are oblong cylindrical recesses dug vertically on the GaN surface, were formed by dry etching the GaN in the depth direction using a chlorine-based gas and argon gas in an ICP-RIE apparatus.

[0071] In addition, the recesses dug in the surface portion of the hole formation preparation layer 14E (GaN) by the above etching are simply called holes to distinguish them from air holes in the vacancy layer 14P. In addition, when there is no particular distinction between the main holes 14H1 and the sub-holes 14H2, they may be called holes 14H.

[0072] The shape of the hole 14H is not limited to an elongated cylindrical shape, but may be a cylindrical shape, a polygonal shape, or the like.

[0073] As a result of the above, holes 14H were formed in the hole formation preparation layer 14E, and a hole formation layer 14J was formed (FIG. 4, S0).

[0074] (Step S1) Hole Closure - First Buried Growth First, the substrate (FIG. 4, SO) on which the hole 14H was formed was cleaned, and then it was introduced into the reactor of the MOVPE apparatus again to perform recrystallization growth. 3 ), trimethylgallium (TMG) was supplied to perform a first burying growth by facet growth, and the opening of hole 14H was closed.

[0075] Specifically, the first burying growth was performed at a first temperature (920° C.) at which the shape of the hole 14H was transformed by mass transport into a shape composed of thermally stable surfaces.

[0076] More specifically, in this first temperature region, N atoms are attached to the top surface of the growth substrate, so that N-polarity faces are selectively grown. Therefore, as shown in FIG. 4, a crystal whose surface is a {1-101} facet is selectively grown. When the opposing {1-101} facets collide with each other, the hole 14H is blocked and filled (facet growth). This first filling growth by facet growth is performed, and a vacancy 14K is formed corresponding to the hole 14H. In FIG. 4, the hole formation layer 14J (GaN layer) before the buried layer 14B is formed is indicated by a dashed line.

[0077] (Step S2) Planarization filling - second filling growth Subsequently, the hole 14H was closed by facet growth, and then the second burying layer 14B2 having a thickness D2 of 50 nm was grown. The growth of the second burying layer 14B2 was performed by increasing the substrate temperature (growth temperature) to 1050° C. (second burying temperature) and then ionizing the GaN layer with triethylgallium (TEG) and NH 3 The second embedding temperature was higher than the first embedding temperature. However, if the growth surface of the second embedding layer 14B2 can be grown to be the (0001) plane, the temperature relationship between the second embedding temperature and the first embedding temperature may be reversed.

[0078] 4, a thermal effect causes mass transport to occur, and a second buried growth (flattened buried growth) is performed to form a second buried layer 14B2 having a (0001) surface. The first buried growth and the second buried growth form a buried layer 14B.

[0079] For ease of explanation, the layer from the upper surface of the hole layer 14P (the surface closer to the active layer 15) to the upper surface 14JS of the hole formation layer 14J (including a part of the hole formation layer 14J) is referred to as a first buried layer 14B1, and the layer from the upper surface 14JS of the hole formation layer 14J to the flat surface formed by the second buried growth is referred to as a second buried layer 14B2 (see FIG. 4, S3).

[0080] Moreover, the entire semiconductor layer from the upper surface of the hole layer 14P to the upper surface of the second buried layer 14B2 (including a part of the hole-formed layer 14J) is referred to as the buried layer 14B.

[0081] Here, the thickness of the first buried layer 14B1 is defined as D1, and the thickness of the second buried layer 14B2 is defined as D2. Therefore, the thickness of the buried layer 14B is given by D=D1+D2. In this specification, for each semiconductor layer of the n-side guide layer (first guide layer) 14, the “upper surface” refers to the surface on the side closer to the active layer 15.

[0082] In this embodiment, GaN is used for the second burying growth. The second burying layer 14B2 also functions as a light distribution adjusting layer for adjusting the coupling efficiency (light field) between light and the hole layer 14P.

[0083] That is, in this embodiment, undoped GaN is used for the first buried growth and the second buried growth. However, the first buried growth and the second buried growth are not limited to GaN, and n-GaN, n-InGaN, undoped GaN, undoped InGaN, or a combination of these semiconductors may be used.

[0084] (Step S3) H 2 Etching by annealing Next, hydrogen (H 2 5 shows a case where the second buried layer 14B2 is etched flat from its surface by a thickness TE.

[0085] More specifically, H 2 In annealing in the atmosphere, the (0001) plane is a thermally stable plane, and the buried layer 14B can be etched and thinned while maintaining the flatness of the surface. Therefore, a high-quality active layer with high flatness can be grown on the buried layer 14B. The annealing atmosphere may contain Group III and Group V materials.

[0086] More specifically, in Group III nitride semiconductors, H 2 When high-temperature annealing is performed in an atmosphere, surface atoms are desorbed, and the surface is etched. At this time, the surface with the slowest etching rate remains, so the most thermally stable (0001) surface is formed on the surface. Therefore, when a +c-plane substrate is used, etching can be performed while maintaining the (0001) surface parallel to the substrate. This allows the second buried layer 14B2 to be made thinner, and the distance between the vacancy layer 14P and the active layer 15 to be reduced.

[0087] H in III-nitride semiconductors 2 The annealing is preferably carried out in the temperature range of 900 to 1100°C.

[0088] In the etching process of the second buried layer 14B2, H 2 N 2 An inert gas such as a gas may be mixed in. In this case, since the etching rate decreases when the partial pressure of the inert gas is increased, the etching rate can be controlled by controlling the partial pressure of the gas.

[0089] In addition, the III-nitride semiconductor is 2 When annealing in an atmosphere, nitrogen atoms are more likely to be desorbed than group III atoms, which leads to the formation of nitrogen vacancies and Ga droplets. To suppress this, NH 3 It is useful to mix gases, such as NH 3 Gas may be mixed as appropriate.

[0090] (Step S4) Recrystallization growth Next, on the substrate on which the embedding layer 14B had been etched, crystal growth was further carried out in the reactor for the layers above the light distribution adjustment layer 23.

[0091] Specifically, the light distribution adjustment layer 23 is grown on the second buried layer 14B2. 0.03 Ga 0.97It is an N layer, which is a semiconductor layer (heterogeneous semiconductor layer) having a different crystal composition from the buried layer 14B (GaN layer).

[0092] Next, the active layer 15, the p-side guide layer (second guide layer) 16, the electron barrier layer (EBL) 17, the p-cladding layer 18, and the p-contact layer 19 were sequentially grown on the light distribution adjustment layer 23. In this manner, the PCSEL device 10 was fabricated.

[0093] (b) Vacancy layer The above-mentioned embedding step formed a double lattice structure hole layer 14P in which hole pairs 14K consisting of a main hole 14K1 and a sub-hole 14K2 are two-dimensionally arranged at each of the square lattice points. Here, the sub-hole 14K2 has a smaller hole diameter and height than the main hole 14K1. In the present invention, the upper surface of the hole in the multi-lattice structure hole layer 14P means the upper surface of the main hole 14K1 or the sub-hole 14K2 that is closer to the upper layer (active layer) (i.e., the hole having a shallower upper surface). Note that the hole pair 14K may be a single lattice structure in which holes of the same size are two-dimensionally arranged at each of the square lattice points, instead of the main hole 14K1 and the sub-hole 14K2 having different sizes.

[0094] 6 is a schematic diagram showing a cross section of the formed void layer 14P perpendicular to the central axis CX. When filling the holes 14H in the group III nitride, the shape of the holes 14H is deformed by mass transport into a shape composed of thermally stable surfaces, and voids 14K are formed.

[0095] That is, in the +c-plane substrate, the inner side surface of the hole 14H changes shape to a (1-100) plane (i.e., an m-plane), that is, changes shape from an oval cylindrical shape to an oval hexagonal prism-shaped hole 14K whose side surface is formed of an m-plane.

[0096] The formed primary void 14K1 had a long hexagonal prism shape with a long diameter of 72.5 nm, a short diameter of 43.5 nm, and a long diameter / short diameter ratio of 1.67. The secondary void 14K2 had a long diameter of 44.6 nm, a short diameter of 38.3 nm, and a long diameter / short diameter ratio of 1.16, and had a long hexagonal prism shape closer to a regular hexagonal prism than the primary void 14K1.

[0097] It was also confirmed that the distances Δx and Δy between the centers of gravity of the main hole 14K1 and the subhole 14K2 were 81.6 nm (Δx=Δy=0.46PK) and had not changed since before filling. It was also confirmed that the major axes of the main hole 14K1 and the subhole 14K2 were parallel to the <11-20> axis (i.e., the a-axis).

[0098] In addition, the void filling ratios (filling factors) FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 were calculated to be FF1 = 8.8% and FF2 = 4.2%. Here, the void filling ratio is the ratio of the area occupied by each void per unit area in a two-dimensional regular array. Specifically, when the areas of the main voids 14K1 and the sub-voids 14K2 in the void layer 14P are S1 and S2, respectively, the void filling ratios FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 are given by the following formulas.

[0099] FF1=S1 / PK 2 , FF2=S2 / PK 2 Through the above steps, the formation of the n-side guide layer 14 including the hole layer 14P is completed.

[0100] (c) Etched buried layer and its flatness The buried layer 14B was annealed at a temperature of 1,050° C. for annealing times of (i) 5 minutes, (ii) 20 minutes, and (iii) 50 minutes. 2 After etching by annealing, the light distribution control layer 23 and the active layer 15 were grown on the buried layer 14B, and the cross section was observed with a SEM (Scanning Electron Microscope), and the surface of the active layer 15 was observed with an AFM (Atomic Force Microscope).

[0101] 7A-7C are SEM images of the cross section of the wafer when the etching time is (i) 5 minutes, (ii) 20 minutes, and (iii) 50 minutes, respectively. In the figures, D is the thickness of the buried layer 14B after etching (i.e., the total thickness of the first buried layer 14B1 and the second buried layer 14B2 after etching), and DE is the layer thickness of the second buried layer 14B2 after etching. In the SEM images of Figures 7A-7C, the cross section of the hole formation layer 14J is observed with slight shading. For clarity of the drawing, the semiconductor layers of the buried layer 14B, the active layer 15, and the light distribution adjustment layer 23 are indicated by their respective reference numerals.

[0102] When the etching time was 5 minutes, D=140 nm, DE=60 nm, when it was 20 minutes, D=109 nm, DE=31 nm, when it was 20 minutes, D=82 nm, DE<2 nm.

[0103] 8 shows an AFM image of the surface of the active layer 15. When the etching time was 5 minutes, the surface roughness was Ra=0.602 nm and 0.210 nm in the regions of 20 μm×20 μm and 2 μm×2 μm, respectively, and when the etching time was 20 minutes, the surface roughness was Ra=0.576 nm and 0.197 nm, respectively. When the etching time was 50 minutes, the surface roughness was Ra=2.06 nm and 0.634 nm, respectively.

[0104] It was found that the surface roughness increases with increasing etching time, and that when the etching time is longer than 50 minutes, i.e., when the DE is less than 2 nm, the surface roughness is large and an active layer with good crystal quality cannot be obtained on such a surface.

[0105] H 2 It was believed that the reason why the surface roughness occurs when the etching time by annealing is long is that a large amount of Si is deposited on the surface of the hole formation layer 14J in which the holes 14H are formed. More specifically, the Si is deposited by the hard mask (SiN film, etc.) used when forming the holes 14H and siloxane in the atmosphere adhering to the surface of the hole formation layer 14J.

[0106] Highly reactive nitrogen atmosphere (i.e., NH 3 In a high-temperature atmosphere (where N is dissociated), Si reacts with N on the semiconductor (GaN) surface to form SiN. Since SiN forms an inversion domain on the GaN surface, the polarity of the GaN layer is locally inverted, causing significant surface roughness when the shape changes due to mass transport. Figure 8 shows that the surface roughness caused by the inversion domain generated on the semiconductor (GaN) surface appears on the top surface of the active layer 15 even after the active layer is formed.

[0107] 9A and 9B show the results of measuring the surface roughness (surface height) along the MM line (see FIG. 8) in an area of ​​20 μm×20 μm for etching times of (ii) 20 minutes and (iii) 50 minutes, respectively.

[0108] When the etching time is (ii) 20 minutes, the surface condition of the active layer 15 is not rough enough to affect the threshold current, whereas when the etching time is (iii) 50 minutes, the surface roughness of the active layer 15 is large, making it difficult to grow an active layer of good quality.

[0109] 10 shows the measured surface roughness Ra of a 20 μm×20 μm area when the thickness DE of the second embedded layer 14B2 after etching is changed. The boundary (DE=0 nm) between the top surface of the hole formation layer 14J and the second embedded layer 14B2 is indicated by a dashed line. The arrow indicates the thickness at which the surface roughness Ra changes critically with respect to the thickness DE of the second embedded layer 14B2.

[0110] As shown in FIG. 10, when the layer thickness DE of the second embedded layer 14B2 after etching is 2 nm or more, the surface roughness Ra is less than 1.0 nm at most. On the other hand, when the layer thickness DE is less than 2 nm, the surface roughness increases significantly, making it difficult to grow an active layer with good crystal quality.

[0111] Therefore, H 2By etching the surface of the second buried layer 14B2 to make it flat and setting the layer thickness DE of the second buried layer 14B2 to 2 nm or more by annealing, it is possible to grow an active layer and a semiconductor layer with good crystal quality on the second buried layer 14B2.

[0112] From the viewpoint of the coupling efficiency between the active layer 15 and the hole layer 14P, it is preferable that the distance between the active layer 15 and the hole layer 14P, i.e., the distance between the upper surfaces of the holes 14K in the hole layer 14P and the active layer 15, is 200 nm or less. From the viewpoint of obtaining high coupling efficiency, it is even more preferable that the distance between the upper surfaces of the holes 14K in the hole layer 14P and the active layer 15 is 150 nm or less.

[0113] In addition, when the active layer 15 is an active layer having a quantum well structure, the distance between the upper surface of the hole 14K and the active layer 15 refers to the distance between the upper surface of the hole 14K and the first quantum well layer (i.e., the quantum well layer closest to the hole layer 14P).

[0114] In addition, in the conventional multi-lattice structure, in order to obtain a high hole filling rate, a thicker buried layer may be required than in the single-lattice structure. According to the present invention, even in such a case, a thin buried layer can be used, and a high coupling efficiency (resonance effect) between the hole layer and the active layer can be obtained.

[0115] As described above in detail, according to the present invention, it is possible to provide a manufacturing method for a photonic crystal surface-emitting laser element that can bring the air hole layer and the active layer into close proximity to each other to enhance the resonance effect, and that has a high-quality active layer and has a low threshold and high efficiency, and a photonic crystal surface-emitting laser element.

[0116] Unless otherwise specified, the numerical values ​​and the like in the above-described embodiments are merely examples and may be modified as appropriate. In addition, although a double lattice structure PCSEL element has been illustrated, the present invention can be applied to a single lattice structure PCSEL element and generally to a multiple lattice structure PCSEL element.

[0117] Furthermore, although the present invention has been exemplified with respect to a photonic crystal layer (hole layer) in which the holes have a hexagonal columnar shape, the present invention can also be applied to cases in which the holes in the photonic crystal layer have an irregular columnar shape, such as a cylindrical, rectangular, polygonal, or teardrop shape. [Explanation of symbols]

[0118] 10: PCSEL element 12: Element substrate 13: First cladding layer 14: First guide layer 14A: Lower guide layer 14B: Buried layer 14B1: First buried layer 14B2: second buried layer 14E: Hole formation preparation layer 14J: Hole forming layer 14K: Hole / hole pair 14K1 / 14K2: Main / secondary hole 14P: Hole layer (photonic crystal layer) 15:Active layer 16: Second guide layer 17: Electron barrier layer 18: Second cladding layer 19: Contact layer 23: Light distribution adjustment layer

Claims

1. A method for manufacturing a surface-emitting semiconductor laser element, (a) A hole formation preparation layer is formed on the substrate, (b) A hole-forming layer is formed in the hole-forming preparation layer by forming holes arranged two-dimensionally at each of the grid points, (c) Facet growth is performed to close the hole and form a first embedded layer, (d) Growing a second embedded layer that embeds the first embedded layer flat to form a void layer having a void corresponding to the hole, (e) The second embedded layer is etched flat by annealing in a hydrogen atmosphere. (f) A manufacturing method comprising growing a semiconductor layer including an active layer on the second embedded layer which has been flat-etched.

2. The aforementioned surface-emitting semiconductor laser element is a GaN-based semiconductor laser element. The crystal growth surface of the substrate is the {0001} plane. The surface of the second embedded layer after the planar etching is a {0001} plane. The manufacturing method according to claim 1.

3. The manufacturing method according to claim 1, wherein the thickness of the second embedding layer on the upper surface of the hole-forming layer after the flat etching is 2 nm or more.

4. The manufacturing method according to claim 1, wherein the distance from the upper surface of the pores in the porous layer to the active layer is 200 nm or less.

5. The manufacturing method according to claim 2, wherein the facet growth is characterized by selective growth of crystals whose surface has {1-101} facets.

6. A photonic crystal surface-emitting laser element manufactured by the manufacturing method described in claims 1 to 4, A photonic crystal surface-emitting laser element in which the distance between the active layer and the vacancy layer is 200 nm or less.

7. A photonic crystal surface-emitting laser element manufactured by the manufacturing method described in claims 1 to 4, A photonic crystal surface-emitting laser element in which the distance between the active layer and the vacancy layer is 150 nm or less.

8. A surface-emitting laser element made of a nitride semiconductor system, A translucent substrate, A first semiconductor layer provided on the substrate, An active layer provided on the first semiconductor layer, The active layer comprises a second semiconductor layer having the opposite conductivity to the first semiconductor layer, provided on the active layer. The first semiconductor layer comprises a vacancy layer which is a photonic crystal layer having vacancies arranged with two-dimensional periodicity in a plane parallel to the active layer, and a filling layer. The embedded layer comprises a first embedded layer that closes the void and a second embedded layer provided on the first embedded layer. A photonic crystal surface-emitting laser element in which the distance between the vacancy layer and the active layer is 200 nm or less.

9. The photonic crystal surface-emitting laser element according to claim 8, wherein the thickness of the embedded layer is 30 nm or more and 200 nm or less.

10. The photonic crystal surface-emitting laser element according to claim 8 or 9, wherein the thickness of the second embedded layer is 2 nm or more.

11. The photonic crystal surface emitting laser element according to claim 8, wherein the surface roughness Ra measured in a 20 μm × 20 μm region on the upper surface of the active layer is less than 1.0 nm.

12. The surface-emitting semiconductor laser element according to claim 11, wherein the surface roughness Ra measured in at least a portion of a 2 μm × 2 μm region on the upper surface of the active layer is less than 0.21 nm.

13. The surface-emitting laser element according to claim 8, wherein the second embedded layer is a layer having an etched surface.

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