Semiconductor device

Abstract

To provide a transistor having an excellent electric characteristic, suitable for refining, and having a high switching speed.SOLUTION: A semiconductor device has a transistor including an oxide semiconductor, a gate electrode, a gate insulator, and the oxide semiconductor has a first region in which the oxide semiconductor and the gate electrode are overlapped each other via the gate insulator. In the transistor, a threshold voltage is larger than 0 V, and the switching speed is less than 100 nano seconds.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. In particular, The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a storage Alternatively, the present invention relates to a semiconductor device, a semiconductor device, a display device, a light-emitting device, The present invention relates to a method for manufacturing a lighting device, a power storage device, a memory device, or a processor. A method for driving a display device, a light-emitting device, a lighting device, a power storage device, a storage device, or a processor Regarding.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices The vessel may include a semiconductor device. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0004] For example, a transistor can be fabricated using zinc oxide or an In-Ga-Zn oxide semiconductor. Techniques for achieving this have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, an oxide semiconductor with a crystal structure oriented along the c-axis was used as the active layer of a transistor. A high-definition, low-power consumption display device has been disclosed (see Non-Patent Document 1).

[0006] In recent years, miniaturized transformers have become increasingly popular as electronic devices become more compact and lightweight. Demand is increasing for integrated circuits in which semiconductor elements such as transistors are densely integrated.

[0007] For example, an oxide semiconductor with a crystal structure in which the c-axis is oriented perpendicular to the surface is used as the active layer. The transistor used has an extremely low off-state current (see Non-Patent Document 2), and this characteristic is utilized Applications of this technology to LSIs such as non-volatile memories, CPUs, and image sensors have been proposed ( (See Non-Patent Documents 3 to 5). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., The Society for Information Display 2012 International Symposium Digest, pp. 183-186 [Non-Patent Document 2] K. Kato et al., Japanese Journal of Applied Physics 2012, volume 51, 021201 [Non-Patent Document 3] H. Inoue et al., The Institute of Electrical and Electronics Engineers Journal of Solid-State Circuits 2012, volume 47, pp. 2258-2065 [Non-Patent Document 4] T. Ohmaru et al., Extented Abstract, Solid State Devices and Materials 2012, pp. 1144-1145 [Non-Patent Document 5] T. Aoki et al., Symposia on VLSI Technology Digest of Technical Papers, 2011, pp. 174-175 Summary of the Invention [Problem to be solved by the invention]

[0010] One of the objects of the present invention is to provide a transistor having good electrical characteristics. One of the objectives is to provide a transistor suitable for switching speed. One of the objectives is to provide a transistor with a high speed. Another object of the present invention is to provide a transistor having a large capacitance. Another object of the present invention is to provide a semiconductor device having the transistor. An object of the present invention is to provide a semiconductor device with high speed response.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a transistor including an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor has a gate insulator and the oxide semiconductor is connected to the gate insulator through the gate insulator. a gate electrode and a first region overlapping each other, and the transistor has a threshold voltage of This semiconductor device has a voltage greater than 0V and a switching speed of less than 100 nanoseconds.

[0013] Alternatively, one embodiment of the present invention is a semiconductor device comprising: This is a semiconductor device in which a current flows through the entire oxide semiconductor.

[0014] Alternatively, in one aspect of the present invention, the carrier density of the first region is 1×10 15 cm -3 Less than The present invention relates to a semiconductor device.

[0015] Alternatively, in one embodiment of the present invention, an oxide semiconductor is provided. The semiconductor device has a second region that faces a side surface and the gate electrode.

[0016] Alternatively, one embodiment of the present invention includes a conductor in contact with an oxide semiconductor, and the oxide semiconductor has a conductive property. The third region has a site of oxygen vacancy, and the site of oxygen vacancy is The present invention relates to a semiconductor device having hydrogen.

[0017] Alternatively, one embodiment of the present invention is a semiconductor device in which the third region is an n-type conductive region. Effect of the Invention

[0018] It is possible to provide a transistor having good electrical characteristics. It is possible to provide a transistor with a high switching speed. Alternatively, a transistor that has a large current when conducting can be provided. Alternatively, a semiconductor device including the transistor can be provided. According to the present invention, a semiconductor device having the transistor and operating at high speed can be provided. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 10] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1 shows a configuration of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1 shows a configuration of a CPU according to an embodiment of the present invention. [Figure 14] 1 is a configuration of a chip and a module according to an embodiment of the present invention. [Figure 15] 1 is an electronic device according to an embodiment of the present invention. [Figure 16] 1A to 1C are a schematic view, a cross-sectional view, and a cross-sectional STEM image illustrating a transistor according to one embodiment of the present invention. [Figure 17] X-ray diffraction spectrum, unit cell structure, high-resolution TEM image of a cross section, and high-resolution TEM image of a surface of CAAC-IGZO. [Figure 18] High-resolution TEM image of single crystal IGZO. [Figure 19] 1 shows electrical characteristics of a transistor according to one embodiment of the present invention. [Figure 20] 1 shows the drain voltage dependence of turn-on voltage and SS of a transistor according to one embodiment of the present invention. [Figure 21] 13 shows channel width dependence of electrical characteristics of a transistor according to one embodiment of the present invention. [Figure 22] 1 shows channel width dependence of turn-on voltage and SS of a transistor according to one embodiment of the present invention. [Figure 23] 13 shows channel length dependence of electrical characteristics of a transistor according to one embodiment of the present invention. [Figure 24] 1 shows channel length dependence of turn-on voltage and SS of a transistor according to one embodiment of the present invention. [Diagram 25] 1 is a memory circuit according to one embodiment of the present invention. [Figure 26] 13 is a timing chart of a write operation of a memory circuit according to one embodiment of the present invention. [Figure 27] 4 shows the write time characteristics of a memory circuit according to one embodiment of the present invention. [Figure 28] 1 shows the relationship between the storage capacitance and the write time of a memory circuit according to one embodiment of the present invention. [Figure 29] 1 shows characteristics of a memory circuit according to an embodiment of the present invention. [Diagram 30] Electron current density distribution in the active layer obtained by device calculation. [Diagram 31]Electron current density distribution in the active layer obtained by device calculation. [Diagram 32] 1 shows channel length dependence of drain current of a transistor according to one embodiment of the present invention. [Diagram 33] 13 shows a relationship between off-state current and on-state current of a transistor according to one embodiment of the present invention. [Diagram 34] 1 is a cross-sectional STEM image of a transistor according to an embodiment of the present invention. [Diagram 35] 1 shows electrical characteristics of a transistor according to one embodiment of the present invention. [Diagram 36] 1 shows electrical characteristics of a transistor according to one embodiment of the present invention. [Figure 37] Electron current density distribution in the active layer obtained by device calculation. [Figure 38] High-resolution TEM image and local Fourier transform image of a cross section of an oxide semiconductor. [Figure 39] A nanobeam electron diffraction pattern of an oxide semiconductor and an example of a transmission electron diffraction measurement device. [Diagram 40] An example of structural analysis using transmission electron diffraction measurements, and a high-resolution TEM image on a plane. [Diagram 41] 13 is a cumulative frequency distribution of threshold voltages of a transistor according to one embodiment of the present invention. [Diagram 42] 13 is a cumulative frequency distribution of threshold voltages of a transistor according to one embodiment of the present invention. [Diagram 43] 13 is a cumulative frequency distribution of threshold voltages of a transistor according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0021] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0022] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". .

[0023] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. However, the ordinal numbers used to identify an aspect of the present invention may not be consistent.

[0024] Even if a material is described as a "semiconductor," if its electrical conductivity is sufficiently low, it may be considered an "insulator." In addition, the boundary between "semiconductor" and "insulator" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguishable from "insulator." Similarly, the term "insulator" used in this specification may be interpreted as "semiconductor." " This can sometimes be rephrased as ".

[0025] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it should be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear, and Therefore, the term "semiconductor" as used herein may not be distinguished from "conductor." Similarly, the term "conductor" used in this specification may be used interchangeably with "semiconductor." " This can sometimes be rephrased as ".

[0026] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. Also, if the semiconductor is silicon, impurities that change the properties of the semiconductor may occur. Examples of the elements include oxygen, elements of Group 1 except hydrogen, elements of Group 2, elements of Group 13, elements of Group 15, Group elements, etc.

[0027] In the following embodiments, unless otherwise specified, the insulator is, for example, boron. , carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, a argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, An insulator containing one or more of hafnium and tantalum may be used in a single layer or a multilayer structure. Alternatively, resin may be used as the insulator. For example, polyimide, polyamide, acrylic, etc. The resin used can be a resin containing silane or silicone. In some cases, flattening is not necessary. Also, resin can form a thick film in a short time. As the insulator, aluminum oxide is preferably used. Silicon oxide nitride, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide Insulators containing tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide , may be used in a single layer or in a laminated layer.

[0028] In the following embodiments, unless otherwise specified, the conductor is, for example, boron. , nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, Baltic, Nickel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum, Ru Conductors containing one or more of tungsten, silver, indium, tin, tantalum, or tungsten For example, the material may be an alloy or a compound, such as aluminum. Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese, Conductors containing tin and oxygen, titanium and nitrogen, etc. may also be used. stomach.

[0029] In this specification, when it is stated that A has a region of concentration B, for example, If the entire depth direction of a region has a concentration of B, the average If the value is concentration B, then if the median value in the depth direction in a region of A is concentration B, then A If the maximum value in the depth direction in a region of A is concentration B, then If the minimum value in the direction is concentration B, then the convergence value in the depth direction in a region of A is concentration B. This includes cases where the area in which a reliable value of A can be obtained through measurement is concentration B.

[0030] In this specification, A has an area of ​​size B, length B, thickness B, width B or distance B. For example, when describing an area of ​​A, the whole area has size B, length B, and thickness B. , width B or distance B, the average value of A in a certain area has size B, length B, thickness If A has size B, width B or distance B, then the median value of an area of ​​A has size B, length B, thickness B If A has a length B, width B, or distance B, then the maximum value in a certain area of ​​A has a size B, length B, If thickness B, width B, or distance B, the minimum value of an area of ​​A is size B, length B , thickness B, width B or distance B, the convergence value in a region of A is the size B, length When B, thickness B, width B or distance B is used, a certain value of A itself can be obtained by measurement. This includes cases where the area has size B, length B, thickness B, width B or distance B, etc.

[0031] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0032] In the following description, a semiconductor device including an oxide semiconductor in a channel formation region will be described as an example unless otherwise specified. A conductor device will now be described.

[0033] FIG. 1(A) is a top view, and FIG. 1(B) is a cross section taken along the dashed line A1-A2 shown in FIG. ) In addition, the cross section along the dashed line A3-A4 shown in FIG. 1(A) corresponds to FIG. 1(C). In Figures 1(A), (B), and (C), some elements have been enlarged for clarity. The direction of the dashed dotted line A1-A2 is the channel length direction. The direction of the dashed dotted line A3-A4 may be referred to as the channel width direction.

[0034] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on-state). or a source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is a value, a maximum value, or a minimum value in the region where the channel is formed. Or the average value.

[0035] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the current flowing part, or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is a value, a maximum value, or a minimum value in the region where the channel is formed. Or the average value.

[0036] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0037] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0038] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0039] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width may be used. The value may differ from that calculated using the channel width.

[0040] The transistor 101 includes an insulator 120 on a substrate 110 and an oxide semiconductor layer on the insulator 120. A conductor 130, a source electrode 140 and a drain electrode 140 electrically connected to the oxide semiconductor 130. The source electrode 140 and the drain electrode 150 are connected to the oxide semiconductor 130. The gate insulator 160, the oxide semiconductor 130, a part of the source electrode 140 and the drain It has a gate electrode 170 overlapping a portion of the electrode 150 via a gate insulator 160 . Also, an insulator 180 may be provided on the gate insulator 160 and the gate electrode 170. Moreover, an insulator 185 made of an oxide may be formed on the insulator 180. However, the insulator 185 does not have to be provided. Furthermore, another insulator may be formed on the upper portion. stomach.

[0041] The transistor according to one embodiment of the present invention has a top-gate In addition, the gate electrode 170 and the source electrode 140 overlap each other in a region 1. 91 (LovS) and the region 1 where the gate electrode 170 and the drain electrode 150 overlap each other The width of the region 191 and the region 192 in the channel length direction is To reduce the capacitance, the thickness is preferably 3 nm or more and less than 300 nm.

[0042] In addition, in the region where the channel is formed, the thickness of the oxide semiconductor 130 is 30 nm or more. For example, it may be 100 nm or more and 200 nm or less. The height of the protrusion formed by over-etching the insulator 120 is added to the value. That is, the height of the protrusion and the thickness of the oxide semiconductor 130 may be combined. It may be 30 nm or more and 300 nm or less (for example, 100 nm or more and 200 nm or less). do not have.

[0043] In addition, the value obtained by dividing the thickness of the oxide semiconductor 130 by the channel width is preferably 0.5 or more. For example, it is preferable that the ratio is 0.5 or more and 5 or less, or 1 or more and 3 or less.

[0044] The thickness of the gate insulator 160 is set to 2 nm or more and 30 nm or less in terms of the equivalent oxide thickness. The thickness of the insulator 120 is preferably 10 nm or more and 1000 nm or less in terms of the equivalent oxide thickness. It is preferable to set it to m or less.

[0045] In the transistor 101 shown in FIG. 1, the gate electrode 170 is a In particular, as shown in FIG. 2, the gate electrode 17 0 surrounds the oxide semiconductor 130 not only on the top surface but also on the side surfaces thereof, and In this way, the gate electrode can be oxidized to below 0. The structure of a transistor in which the channel width direction of a semiconductor is electrically surrounded is called a surroun This is called a dedicated channel (s-channel) structure.

[0046] The transistor 101 has a surrounded channel structure, and the channel width is narrowed. By reducing the thickness of the oxide semiconductor 130, carriers can be controlled by the gate electric field on the side surface of the oxide semiconductor 130. This makes it easier to achieve excellent subthreshold characteristics and extremely small off-current. In addition, the oxide semiconductor 13 is formed in the above-described structure. In some cases, a channel may form in the bulk of the 0. In the s-channel structure, A large current can flow between the source and drain of a transistor, and the current when it is conductive (on-current) ) can be increased.

[0047] In addition, at least a portion ( or all of the oxide semiconductor 130 may be formed on the surface, side, top, and / or The oxide semiconductor is in contact with at least a part (or the whole) of the lower surface. In the conductor 130, hydrogen enters the oxygen vacancy site to form a donor level. The state in which hydrogen enters the oxygen vacancy site is called V O H As a result, current flows through the N-type conductive region, resulting in a good on-state current. can be obtained.

[0048] In addition, the impurity concentration in the channel formation region of the oxide semiconductor 130 is reduced. It is useful to make it intrinsic or substantially intrinsic. Here, substantially intrinsic means that the oxide semiconductor The carrier density of the conductor is 1×10 17 pieces / cm 3 Less than or equal to 1×10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 Less than 1×10 is particularly preferable. 10 pieces / cm 3 is less than or equal to 1 x 10 -9 pcs / c m 3 In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and Metal elements other than the main component are impurities. For example, hydrogen and nitrogen are involved in the formation of donor levels. This contributes to an increase in the carrier density.

[0049] The transistor including the oxide semiconductor has a low carrier density in a channel formation region. Therefore, the threshold voltage rarely becomes negative. Transistors using semiconductors have low electrical characteristics because there are few carrier traps in the oxide semiconductor. In addition, the transistor using the oxide semiconductor has small fluctuation in the electrical conductivity and high reliability. The off-state current of the transistor can be made very low.

[0050] In addition, when the transistor 101 is an accumulation type transistor in which electrons are the majority carriers, an oxide semiconductor A channel forming region extending from a region of 130 in contact with a source electrode 140 and a drain electrode 150 The electric field extending to the gate electrode is easily shielded, and carriers can be controlled by the gate electric field even in a short channel. Cheap.

[0051] In addition, by forming a transistor on an insulating surface, the semiconductor substrate can be used as a channel. Unlike the case where the gate electrode is used as a region, Since no parasitic capacitance is formed, it is easy to control carriers by the gate electric field. Good switching characteristics are obtained.

[0052] By adopting such a structure, good electrical properties can be obtained. It has excellent threshold characteristics, extremely small off-current, and good on-current.

[0053] By using such a structure, good electrical characteristics can be obtained even in miniaturized transistors. As transistors become smaller, the various parasitic capacitances of the transistors decrease, resulting in good Good switching characteristics can be obtained.

[0054] As an example, the channel length and width can be 50 nm. In the region where the oxide semiconductor 130 is formed, the thickness of the oxide semiconductor 130 is set to 40 nm, and the thickness of the gate insulator 160 is set to 100 nm. The thickness is set to 11 nm in terms of the equivalent oxide thickness, and the thickness of the insulator 120 is set to 390 nm in terms of the equivalent oxide thickness. m.

[0055] As a result, the channel width is defined as the width at a gate voltage of 3 V, a drain voltage of 1 V, and a source voltage of 0 V. The rated on-current is 58μA / μm, and the off-current is 0.1pA or less. In addition, the threshold voltage can be made positive (also known as normally-off electrical characteristics). ), and it is also possible to set the gate voltage at which the drain current becomes 1 pA to 0 V or higher. In addition, DIBL (Drain Induced Barrier Lowering) ) is 45mV / V or more and 100mV / V or less, typically 67mV / V, SS(Subt threshold swing value) is 60mV / dec or more, 120mV / dec c or less, typically 92 mV / dec, providing excellent electrical characteristics.

[0056] By using a transistor with such a structure, a normally-off transistor The switching speed of the transistor is less than 100ns, preferably less than 10ns, and 10ps or more. It is possible.

[0057] As an example, a transistor with a channel length of 64 nm and a channel width of 68 nm was written. When used as a resistor to charge a capacitance, a capacitance of 14 fF is charged for 90 ns. It can be charged to 0%.

[0058] In addition, the switching speed of the transistor is less than 10 ns, 10 ps or more, and preferably less than 3 ns. It can be made to be more than 100ps.

[0059] In addition, the switching speed of a transistor is fast. This refers to the short time it takes for a transistor to switch. The charge speed is the time it takes for the gate capacitance of a transistor to be charged to 90%. represents the time it takes for a transistor to go from a non-conducting state to a conducting state under no load. This means that when the gate voltage is changed, the increment of the transistor's drain current is proportional to the gate capacitance. The increment of the stored charge can be interpreted as the charging time. The time required for switching is the time required for the current gain to be The maximum frequency f that is greater than or equal to 1 T (also called the cutoff frequency), 1 / (2×f T ) Or, the maximum frequency f where the power gain is 1 or more max (Maximum oscillation frequency (also called the number) and use 1 / (2×f max The power gain is sometimes expressed as Directional power gain or maximum available power gain can be used.

[0060] The switching speed may be actually measured or may be verified by calculation. Therefore, SPICE can be used for verification. Transistor model parameters It is preferable to extract the data from the electrical characteristics of a transistor that is actually measured. Measurements may be performed at room temperature, low temperature (e.g. -40°C), or high temperature (e.g. 125°C). The electrical characteristics of the transistor may be measured in addition to the RPI (Re Using the model of the Institute of Social Sciences (IISS) It is also possible to extract parasitic elements such as parasitic capacitance and parasitic resistance based on the layout. It is preferable that

[0061] As an example, a transistor with a channel length of 64 nm and a channel width of 68 nm was extracted. In SPICE calculations using transistor model parameters, a capacitance of 1fF or less is charged. When this is done, it can be charged to 90% in less than 5ns.

[0062] In addition, by using a transistor with this structure, the equivalent oxide thickness is 11 nm. Even if the channel length is shortened to about 50 nm, the off-current is extremely small with a relatively thick gate insulator. Thus, very good subthreshold characteristics can be obtained.

[0063] In addition, by using a transistor with this structure, the equivalent oxide thickness is 11 nm. Despite the relatively thick gate insulator and the gate overlap structure, Even when the length of the transistor is shortened to about 50 nm, the transistor has extremely low off-state current and excellent subthreshold current. characteristics are obtained.

[0064] The use of a relatively thick gate insulator reduces leakage current through the gate insulator. In addition, compared to forming a thin gate insulator, it is easier to manufacture and has less film thickness variation. It is possible to form a small gate insulator.

[0065] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it in a variety of ways.

[0066] In addition, at least a part ( or all of the oxide semiconductor 130 may be formed on the surface, side, top, and / or is provided on at least a part (or the entirety) of the lower surface.

[0067] Or, at least a portion of the source electrode 140 (and / or the drain electrode 150) (or all of) the surface, side, top, and / or Alternatively, the source electrode 14 is in contact with at least a part (or the whole) of the lower surface. At least a portion (or all) of the SiO 2 (and / or drain electrode 150) is oxidized. The semiconductor layer 130 is in contact with at least a portion (or all) of the semiconductor, such as the compound semiconductor 130.

[0068] Or, at least a portion of the source electrode 140 (and / or the drain electrode 150) (or all of) the surface, side, top, and / or Or, the solenoid is electrically connected to at least a part (or the whole) of the lower surface. At least a part (or the whole) of the source electrode 140 (and / or the drain electrode 150) ) is electrically connected to at least a part (or the whole) of a semiconductor such as the oxide semiconductor 130. This is being continued.

[0069] Or, at least a portion of the source electrode 140 (and / or the drain electrode 150) (or all of) the surface, side, top, and / or Or, the sole is disposed adjacent to at least a part (or the entirety) of the lower surface. At least a part (or the whole) of the source electrode 140 (and / or the drain electrode 150) ) is disposed adjacent to at least a part (or the whole) of a semiconductor such as the oxide semiconductor 130. It is placed there.

[0070] Or, at least a portion of the source electrode 140 (and / or the drain electrode 150) (or all of) the surface, side, top, and / or Or, the source voltage is disposed on at least a part (or the entirety) of the side of the lower surface. At least a portion (or all) of the electrode 140 (and / or the drain electrode 150) , disposed on at least a portion (or all) of a semiconductor such as an oxide semiconductor 130. There are.

[0071] Or, at least a portion of the source electrode 140 (and / or the drain electrode 150) (or all of) the surface, side, top, and / or Or, it is disposed on the diagonally upper side of at least a part (or the whole) of the lower surface. At least a part (or the whole) of the source electrode 140 (and / or the drain electrode 150) ) is disposed obliquely above at least a part (or the whole) of a semiconductor such as the oxide semiconductor 130. It is placed there.

[0072] Or, at least a portion of the source electrode 140 (and / or the drain electrode 150) (or all of) the surface, side, top, and / or Or, the source voltage is disposed on at least a part (or the whole) of the lower surface. At least a portion (or all) of the electrode 140 (and / or the drain electrode 150) , which is disposed on at least a part (or the whole) of a semiconductor such as an oxide semiconductor 130. There are.

[0073] As shown in FIG. 3, the transistor 101 includes an oxide semiconductor 130 and a substrate 110. A conductor 172 may be provided between the first gate electrode and the second gate electrode. By using it as a gate, it is possible to further increase the on-current and control the threshold voltage. To increase the on-current, for example, the gate electrode 170 and the conductor 172 are set to the same potential. The transistor 101 can be driven. To control the threshold voltage, A constant potential different from that of the electrode 170 may be applied to the conductor 172 .

[0074] In addition, the transistor of one embodiment of the present invention has a structure shown in FIG. FIG. 4(A) is a top view, and the dashed line B1-B The cross sections in the two directions correspond to FIG. 4(B). Also, the cross sections in the direction of the dashed line B3-B4 shown in FIG. The cross section of FIG. 4(C) corresponds to FIG. 4(A), FIG. 4(B) and FIG. 4(C). For clarity of the drawings, some elements are enlarged, reduced, or omitted. The direction of the dashed line B1-B2 is called the channel length direction, and the direction of the dashed line B3-B4 is called the channel width direction. This may be the case.

[0075] The transistor 102 illustrated in FIGS. 4A, 4B, and 4C includes an oxide semiconductor 1 30 includes a first oxide semiconductor 131, a second oxide semiconductor 132, and The transistor 102 differs from the transistor 101 in that the first oxide semiconductor 132 and the second oxide semiconductor 133 are formed in this order.

[0076] For example, the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor The conductors 133 may be made of oxide semiconductors having different compositions. For example, the first oxide semiconductor 131 and the third oxide semiconductor 133 are the same or different. The composition may be in the vicinity of

[0077] Note that the shape of the oxide semiconductor 130 in the transistor 101 will be described later. The same effect can be obtained by applying the configuration shown in FIG. This can also be applied to the transistor 102.

[0078] In addition, the transistor of one embodiment of the present invention has a structure shown in FIG. 5A is a top view, and the dashed line C1-C The cross sections in the two directions correspond to FIG. 5(B). Also, the cross sections in the direction of the dashed line C3-C4 shown in FIG. 5(A) The cross section of FIG. 5(C) corresponds to FIG. 5(A), FIG. 5(B) and FIG. 5(C). For clarity of the drawings, some elements are enlarged, reduced, or omitted. The direction of the chain line C1-C2 is called the channel length direction, and the direction of the dashed line C3-C4 is called the channel width direction. This may be the case.

[0079] The transistor 103 illustrated in FIGS. 5A, 5B, and 5C includes an oxide semiconductor 1 30 is a first oxide semiconductor 131 and a second oxide semiconductor 132 in this order from the insulator 120 side. The stacked layer and the third oxide semiconductor 133 covering part of the stacked layer are included. The transistors 101 and 102 are different.

[0080] For example, the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor The conductors 133 may be made of oxide semiconductors having different compositions. For example, the first oxide semiconductor 131 and the third oxide semiconductor 133 are the same or different. The composition may be in the vicinity of

[0081] Specifically, the transistor 103 includes an insulator 120 on a substrate 110 and a gate insulating film 120 on the insulator 120. A stack of a first oxide semiconductor 131 and a second oxide semiconductor 132 formed in this order, A source electrode 140 and a drain electrode 150 electrically connected to a portion of the layer, A third oxide semiconductor covering a portion of the source electrode 140 and a portion of the drain electrode 150. A conductor 133, a part of the stack, a part of a source electrode 140, a part of a drain electrode 150, A gate insulator 160 and a gate electrode 170 overlapping the third oxide semiconductor 133. In addition, the source electrode 140, the drain electrode 150, and the gate electrode 170 are An insulator 180 may be provided on the insulating layer 180. The insulator 185 may be formed. The insulator 185 may not be formed. Another insulator may be formed on top of it.

[0082] In the transistor 101 shown in FIG. 1, the oxide semiconductor 13 On the other hand, in the transistor 102 shown in FIG. From the side of the substrate 10, a first oxide semiconductor 131, a second oxide semiconductor 132, and a third oxide semiconductor The transistor 103 shown in FIG. The transistor 102 has a three-layer structure of an oxide semiconductor 130. In the hole formation region, the second oxide semiconductor 132 is The oxide semiconductor 133 surrounds the insulating film 131 .

[0083] Note that in the structures of the transistors 102 and 103, the oxide semiconductor 13 By appropriately selecting the materials of the three layers constituting the second oxide semiconductor 132, the current can be made to flow through the entire second oxide semiconductor 132. A current flows through the second oxide semiconductor 132 in the oxide semiconductor 130. This makes it difficult for the interface scattering to occur and allows for a high on-state current. When the oxide semiconductor 132 is thicker, the on-state current can be increased.

[0084] Next, components of a transistor according to one embodiment of the present invention will be described in detail.

[0085] The substrate 110 is not limited to being a simple support material, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode 170, the source electrode 140, And one of the drain electrodes 150 may be electrically connected to the other devices described above. stomach.

[0086] The insulator 120 serves to prevent the diffusion of impurities from the substrate 110 and also serves to prevent the oxide semiconductor from diffusing. The insulator 120 can supply oxygen to the conductor 130. It is preferable that the insulator contains oxygen in an amount greater than the stoichiometric composition. For example, thermal desorption spectroscopy (TDS) is The oxygen released was calculated as 1 .0×10 19 atoms / cm 3 The membrane is one that satisfies the above criteria. The surface temperature of the film is 100°C to 700°C or 100°C to 500°C. As described above, the substrate 110 is a substrate on which other devices are formed. In this case, the insulator 120 also functions as an interlayer insulator. Chemical Mechanical Polishing (CMP) method, etc. It is preferable to perform the planarization treatment by using a method such as the steps of:

[0087] In this embodiment, the details will be mainly described with reference to a case where the oxide semiconductor 130 has a three-layer structure. As in the transistor 101, the oxide semiconductor 130 is a single layer. In this case, a layer corresponding to the second oxide semiconductor 132 described in this embodiment may be used. In addition, when the oxide semiconductor 130 is a two-layer structure, for example, the transistor 102 or the transistor In the configuration of the oxide semiconductor 130 shown in the register 103, a third oxide semiconductor 133 is provided. In this case, the second oxide semiconductor 132 and the first oxide semiconductor The conductor 131 can be replaced. In addition, when the oxide semiconductor 130 has four or more layers, For example, a structure in which another oxide semiconductor is stacked on the three-layer structure described in this embodiment may be used. or a configuration in which another oxide semiconductor is inserted into any of the interfaces in the three-layer structure. can be done.

[0088] For example, the second oxide semiconductor 132 may include a first oxide semiconductor 131 and a third oxide semiconductor 132. It has a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than oxide semiconductor 133. The electron affinity is the energy difference between the vacuum level and the top of the valence band ( ionization potential), the energy difference between the bottom of the conduction band and the top of the valence band (energy The value can be calculated by subtracting the gap.

[0089] The first oxide semiconductor 131 and the third oxide semiconductor 133 are The second oxide contains one or more metal elements constituting the second oxide, and for example, the energy of the conduction band minimum is Semiconductor 132 is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV. or more, and in the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less. It is preferable that the gate electrode be formed using an oxide semiconductor close to the gate level.

[0090] In such a structure, when an electric field is applied to the gate electrode 170, A channel is formed in the second oxide semiconductor 132, which has the smallest conduction band minimum energy. will be done.

[0091] The first oxide semiconductor 131 contains one metal element constituting the second oxide semiconductor 132. Since the second oxide semiconductor 132 and the insulator 120 are in contact with each other, In comparison with the interface between the second oxide semiconductor 132 and the first oxide semiconductor 131, The interface state is less likely to be formed. The interface state may form a channel, so the transistor Therefore, the threshold voltage of the first oxide semiconductor 131 may vary. By providing the transistor, the variation in the electrical characteristics such as the threshold voltage of the transistor is reduced. In addition, the reliability of the transistor can be improved.

[0092] The third oxide semiconductor 133 contains one metal element contained in the second oxide semiconductor 132. Since the second oxide semiconductor 132 and the gate insulator 160 are in contact with each other, In comparison with the interface in the case where the second oxide semiconductor 132 and the third oxide semiconductor 133 are Therefore, the third oxide semiconductor 133 is provided. This makes it possible to increase the field effect mobility of the transistor.

[0093] The first oxide semiconductor 131 and the third oxide semiconductor 133 may include, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf is added to the second oxide semiconductor 132. A material containing a high atomic ratio can be used. Specifically, the atomic ratio is 1.5 times or more. The above elements are strongly bonded to oxygen, and preferably two or more times, and more preferably three or more times. Therefore, the oxide semiconductor has a function of suppressing oxygen vacancies from being generated. The first oxide semiconductor 131 and the third oxide semiconductor 133 are It can be said that oxygen deficiency is less likely to occur than in 2.

[0094] Note that the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 13 3 is at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn When the first oxide is an In-M-Zn oxide containing a metal such as In, La, Ce or Hf, The compound semiconductor 131 is In:M:Zn=x1:y1:z1 [atomic ratio], and the second oxide semiconductor 132 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor 133 is If the atomic ratio is In:M:Zn=x3:y3:z3, then y1 / x1 and y3 / x3 is preferably greater than y2 / x2. y1 / x1 and y3 / x3 are The ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the second oxide semiconductor 132, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are improved. However, if y2 is three times or more larger than x2, the transistor Since the field effect mobility is reduced, y2 is preferably less than three times x2.

[0095] The first oxide semiconductor 131 and the third oxide semiconductor 133 are made of I except for Zn and O. The atomic ratio of n and M is preferably less than 50 atomic % for In and less than 50 atomic % for M. mic%, more preferably In is less than 25 atomic % and M is 75 atomic % or less. %. In addition, except for Zn and O in the second oxide semiconductor 132, The atomic ratio of In and M is preferably higher than 25 atomic % and M is 75 atomic % or less. mic%, more preferably In is higher than 34 atomic % and M is 66 atomic %. Less than ic%.

[0096] The thickness of the first oxide semiconductor 131 and the third oxide semiconductor 133 is 3 nm or more and 100 nm or less. The thickness of the second oxide semiconductor 132 is preferably 3 nm to 50 nm. The thickness of the film is 3 nm or more and 200 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 10 nm or more and 100 nm or less. The second oxide semiconductor 132 has a thickness of preferably 10 nm to 80 nm. The thickness of the second oxide semiconductor 131 is preferably thicker than that of the second oxide semiconductor 133.

[0097] In order to provide a transistor with an oxide semiconductor channel with stable electrical characteristics, The present invention relates to a method for reducing the impurity concentration in an oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is 1× 10 17 pieces / cm 3 Less than or equal to 1×10 15 pieces / cm 3 More preferably, 1 ×10 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following are particularly preferred: is 1×10 10 pieces / cm 3 is less than or equal to 1 x 10 -9 pieces / cm 3 It means that it is more than this.

[0098] In addition, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity levels can become traps and degrade the electrical characteristics of the transistor. Therefore, the first oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor It is preferable to reduce the impurity concentration in the layers of conductor 133 and at their respective interfaces.

[0099] In order to make the oxide semiconductor intrinsic or substantially intrinsic, secondary electron spectroscopy (SIMS) is used. In the case of Ion Mass Spectrometry (IMMS), for example, At a certain depth or in a certain region of the oxide semiconductor, the silicon concentration is set to 1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 The hydrogen concentration is, for example, At a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is better Preferably 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atom s / cm 3 The nitrogen concentration at a certain depth in the oxide semiconductor is, for example, Or, in a region of an oxide semiconductor, 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0100] In addition, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the oxide semiconductor In order to prevent the crystallinity of the oxide semiconductor from being reduced, For example, at a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor, Silicon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 It is sufficient to set it to less than. For example, at a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor The carbon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 ato ms / cm 3 less than 1×10 18 atoms / cm 3 Less than .

[0101] In addition, a transistor using the highly purified oxide semiconductor for a channel formation region as described above can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V or 5 V, , or about 10 V, the off-state current normalized by the channel width of the transistor is It is possible to reduce the flux density from several yA / μm to several zA / μm.

[0102] In addition, the highly purified oxide semiconductor has a small number of carrier generation sources as described above. Therefore, the rear density of the transistor using the oxide semiconductor can be reduced. In addition, the threshold voltage of the oxide semiconductor is rarely negative. Therefore, a transistor using this oxide semiconductor has This results in a highly reliable transistor with small fluctuations in electrical characteristics.

[0103] Note that since insulators containing silicon are often used as gate insulators for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor is It can be said that a structure that does not contact the gate insulator, such as a gate insulator, is preferable. When a channel is formed at the interface between an insulator and an oxide semiconductor, carrier scattering occurs at the interface. This may result in a decrease in the field effect mobility of the transistor. It is preferable to separate the region that will become the channel of the compound semiconductor from the gate insulator.

[0104] Therefore, the oxide semiconductor 130 is a first oxide semiconductor 131, and the second oxide semiconductor 13 The second oxide semiconductor 132 and the third oxide semiconductor 133 are stacked in a stacked structure. The transistor has high field effect mobility and stable electrical properties. In addition, a transistor having good switching characteristics can be formed.

[0105] A first oxide semiconductor 131, a second oxide semiconductor 132, and a third oxide semiconductor 133 are In the band structure, the energy of the conduction band edge changes continuously. The composition of the oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 133 are similar to each other. This can be understood from the fact that oxygen is easily diffused between the first oxide and the second oxide. The oxide semiconductor 131, the second oxide semiconductor 132, and the third oxide semiconductor 133 have different compositions. Although it is a laminate of layers, it can also be said to be physically continuous, and in the drawings of this specification The interfaces of the laminate are shown by dotted lines.

[0106] The oxide semiconductor 130, which is laminated with a common main component, is not simply laminated, but is continuously laminated. A U-shaped well junction (here, the energy of the conduction band edge changes continuously between layers) is called a The U-shaped well is formed. The impurity concentration that forms defect levels such as trap centers and recombination centers at the interface is low. If the oxide semiconductor layers are stacked such that the impurities are highly concentrated between the oxide semiconductor layers, If such a layer exists, the continuity of the energy band is lost and carriers are trapped or may disappear due to recombination.

[0107] For example, the first oxide semiconductor 131 and the third oxide semiconductor 133 are made of In:Ga:Z n=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4 or 1:9:6( The second oxide semiconductor 132 has an atomic ratio of In:Ga:Zn=1:1:1 and 5:5:6. Alternatively, In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. In addition, the first oxide semiconductor 131 has a composition ratio of In:Ga:Zn=1:6:4 or 1:9:6. (atomic ratio), the third oxide semiconductor 133 has In:Ga:Zn=1:3:2, 1:3:3 Alternatively, an In-Ga-Zn oxide having an atomic ratio of 1:3:4 may be used. A first oxide semiconductor 131, a second oxide semiconductor 132, and a third oxide semiconductor 133 In the deposition of the above-mentioned film, it is preferable to use a sputtering method using an oxide target having the above-mentioned atomic ratio. When the sputtering method is used, the oxide semiconductor film formed may have a high thermal conductivity, depending on the substrate heating temperature. The ratio of zinc to the conductor composition is reduced by 20% to 60% compared to the target composition. In addition, the ratio of gallium to the composition of the oxide semiconductor film may be The composition may be reduced by 1% to 20% compared to the get composition.

[0108] The second oxide semiconductor 132 in the oxide semiconductor 130 serves as a well. In the transistor using the semiconductor 130, a channel is formed in the second oxide semiconductor 132. In addition, the oxide semiconductor 130 has a conduction band minimum energy that changes continuously. Therefore, it can also be called a U-shaped well. It can also be called a buried channel.

[0109] In addition, the first oxide semiconductor 131 and the third oxide semiconductor 133, and a silicon oxide film or the like In the vicinity of the interface with any insulator, trap levels due to impurities or defects can be formed. The first oxide semiconductor 131 and the third oxide semiconductor 133 are provided, so that the second oxide This can keep the compound semiconductor 132 away from the trap level.

[0110] However, the energy at the bottom of the conduction band of the first oxide semiconductor 131 and the third oxide semiconductor 133 is When the difference between the energy of the first oxide semiconductor 132 and the energy of the bottom of the conduction band of the second oxide semiconductor 132 is small, Electrons in the oxide semiconductor 132 of the second semiconductor layer 132 may exceed the energy difference and reach the trap level. The negatively charged electrons are captured in the trap level, and the threshold of the transistor is The lower voltage is shifted in the positive direction.

[0111] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the first oxide semiconductor 1 The energies of the conduction band minimums of the first oxide semiconductor 31 and the third oxide semiconductor 133 and the second oxide semiconductor It is preferable to provide a certain difference between the conduction band minimum energy of 132 and that of 132. The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more. .

[0112] A first oxide semiconductor 131, a second oxide semiconductor 132, and a third oxide semiconductor 133 It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, This can provide the transistor with stable electrical characteristics.

[0113] The source electrode 140 and the drain electrode 150 have a property of extracting oxygen from the oxide semiconductor. It is preferable to use a conductor having the following properties. For example, Al, Cr, Cu, Ta, Ti, Mo, W Among the above materials, Ti, which is particularly prone to bonding with oxygen, and the following process It is more preferable to use W, which has a high melting point and allows the process temperature to be set relatively high.

[0114] The conductor that has the property of extracting oxygen from the oxide semiconductor acts to The oxygen is released from the oxide semiconductor, and oxygen vacancies are formed in the oxide semiconductor. The hydrogen that is released combines with the oxygen vacancies, causing the region to become significantly n-type. The n-type region can function as the source or drain of a transistor. Cut.

[0115] The gate insulator 160 may be aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. Silicon oxide, silicon nitride, silicon oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulator containing one or more types of tantalum oxide can be used. The gate insulator 160 can also be The gate insulator 160 may be a laminate of the above materials. , zirconium (Zr), etc. may be contained as impurities.

[0116] An example of the stacked structure of the gate insulator 160 will now be described. The gate insulator 160 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0117] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the physical thickness can be made larger than the equivalent oxide thickness, so the equivalent oxide thickness can be increased to 10n. Even if the thickness is reduced to less than 100 μm or 5 nm, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Hafnium oxide with a crystalline structure has a higher specific dielectric constant than hafnium oxide with an amorphous structure. Therefore, in order to make a transistor with a small off-state current, the crystal structure must be It is preferable to use hafnium oxide having a crystal structure such as monoclinic or cubic. However, one embodiment of the present invention is not limited to these.

[0118] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed adjacent to the channel forming region of a transistor, the interface The electrical characteristics of a transistor may be deteriorated due to the interface state. To reduce this, another film is placed between the channel formation region of the transistor and hafnium oxide. It may be preferable to space them apart by placing them in a spaced-apart relationship. The film having the buffer function may be a film included in the gate insulator 160, The film may be a film included in an oxide semiconductor. Silicon, silicon oxynitride, oxide semiconductor, etc. can be used. The film has, for example, a larger energy gap than the semiconductor that is to be the channel formation region. A large semiconductor or insulator is used. Alternatively, the film having a buffer function may be, for example, a channel A semiconductor or insulator having a smaller electron affinity than the semiconductor that is to be the hole formation region is used. For example, the film having a buffer function has a higher ionization energy than the semiconductor that is the channel formation region. A semiconductor or insulator with high energy is used.

[0119] On the other hand, the interface states (trap By trapping charge in the charge center, it may be possible to control the threshold voltage of a transistor. In order to make the charge exist stably, for example, the channel forming region and the oxide halide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium Alternatively, a semiconductor or insulator with a smaller electron affinity than hafnium oxide may be placed. Alternatively, a film having a buffer function may have a higher ionization energy than hafnium oxide. By using such an insulator, the interface The charge trapped in the level is less likely to be released, and the charge can be held for a long period of time. This can be done.

[0120] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges at the interface states in the gate insulator 160, the gate insulator 160 must be electrically connected to the oxide semiconductor 130. As a specific example, a high temperature (e.g., For example, 125°C to 450°C, typically 150°C to 300°C) The potential of the electrode 170 is set higher than the potential of the source electrode 140 and the drain electrode 150 for 1 second. Typically, the above condition may be maintained for one minute or more.

[0121] In this way, a transistor is formed in which a desired amount of electrons are trapped in the interface states of the gate insulator 160, etc. The threshold voltage of the gate electrode 170 or the voltage applied to the gate electrode 170 is shifted to the positive side. By adjusting the time, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If the charges can be trapped, the charges can be trapped not in the gate insulator 160 but in the gate insulating layer 162. A laminated film having a similar structure may be used for other insulators.

[0122] The gate electrode 170 may include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Conductors such as Ag, Ta and W can be used. The gate electrode may be a stack of materials. The gate electrode may be made of a conductor containing nitrogen. good.

[0123] The gate insulator 160 and the insulator 180 formed on the gate electrode 170 are made of aluminum oxide. The aluminum oxide film is preferably a thin film that can remove impurities such as hydrogen and moisture. The aluminum oxide film has a high blocking effect, preventing both oxygen and water from passing through the film. The film is used to prevent changes in the electrical characteristics of transistors during and after the transistor manufacturing process. Preventing impurities such as hydrogen and moisture, which are factors that cause vibration, from entering the oxide semiconductor 130; Preventing the release of oxygen from the oxide semiconductor, which is the main component material of 130, and preventing the release of oxygen from the insulator 120 It is suitable for use as a protective film that has the effect of preventing unnecessary release of oxygen from the surface of the material. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor.

[0124] In addition, it is preferable that an insulator 185 is formed on the insulator 180. These include magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride. silicon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, oxide Uses an insulator containing one or more of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Alternatively, the insulator 185 may be a laminate of the above materials.

[0125] Here, the insulator 185 has more oxygen than the stoichiometric composition, similar to the insulator 120. It is preferable that the oxygen released from the insulator 185 is transferred to the oxide layer via the gate insulator 160. Since the ions can be diffused into the channel formation region of the semiconductor 130, the channel formation region Therefore, oxygen can be supplied to compensate for the oxygen vacancies formed in the junctions. The electrical characteristics of the capacitor can be obtained.

[0126] In addition, miniaturization of transistors is essential for high integration of semiconductor devices. It is known that the electrical characteristics of a transistor deteriorate as the transistor size decreases.

[0127] In the transistor of one embodiment of the present invention shown in FIG. 5, as described above, the channel is formed A third oxide semiconductor 133 is formed so as to cover the second oxide semiconductor 132. The channel formation layer and the gate insulator are not in contact with each other. This suppresses the scattering of carriers at the interface between the gate insulating layer and the gate insulator, This allows the on-current of the capacitor to be increased, resulting in good switching characteristics. .

[0128] In the transistor of one embodiment of the present invention, the channel width direction of the oxide semiconductor 130 is Since the gate electrode 170 is formed so as to electrically surround the oxide semiconductor 13, For 0, a gate electric field is applied from the side in addition to the vertical gate electric field. That is, a gate electric field is applied to the entire oxide semiconductor 130, and a current The on-state current flows through the entire second oxide semiconductor 132 serving as a channel. As a result, good switching characteristics are obtained.

[0129] In the transistor of one embodiment of the present invention, the second oxide semiconductor 132 is By forming the second oxide semiconductor 1 on the oxide semiconductor layer 131, it is possible to prevent the formation of an interface state. By making 32 the middle layer of the three-layer structure, the influence of impurities from above and below can be eliminated. Therefore, in addition to the above-mentioned improvement in the on-state current of the transistor, Therefore, the threshold voltage can be stabilized and the SS can be improved. The current when g is 0V can be reduced, and power consumption can be reduced. When the charge (or information) stored in the transistor is controlled by the transistor, In addition, the threshold voltage of the transistor is stable. This makes it possible to improve the long-term reliability of the semiconductor device.

[0130] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0131] (Embodiment 2) In this embodiment, a manufacturing method of a transistor 490 illustrated in FIGS. 6A to 6C which is one embodiment of the present invention will be described. FIG. 6A is a plan view illustrating an example of the structure of a transistor 490. 6(B) is a cross-sectional view taken along the dashed line E1-E2 in FIG. 6(A), and a cross-sectional view taken along the dashed line E3-E4 in FIG. Cross-sectional views in four directions are shown.

[0132] First, the insulator 442 is formed. The insulator 442 is formed by a method such as sputtering or chemical vapor deposition (C VD: Chemical Vapor Deposition method, molecular beam epitaxy (MBE:Molecular Beam Epitaxy) method or pulsed laser deposition (PLD:Pulsed Laser Deposition) method, atomic layer deposition (ALD) method The film may be formed by using a method such as atomic layer deposition.

[0133] The insulator 442 is formed by DC sputtering using a metal or alloy target. In particular, in the DC sputtering method using oxygen as a reactive gas, In some cases, the reaction on the target surface is insufficient, resulting in the formation of an insulating film containing suboxides. Suboxides may capture hydrogen and oxygen and stabilize them. When 442 is an insulator containing a suboxide, it has high blocking properties against hydrogen and oxygen. It is clear that it is an edge body.

[0134] The CVD method is a method that uses plasma CVD (PECVD: Plasma ECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method Furthermore, depending on the source gas used, it can be classified into metal CVD (MCVD:Met D) method, etc. al CVD) method, Metal Organic CVD (MOCVD) method ) methods.

[0135] The plasma CVD method can produce high-quality films at relatively low temperatures. The thermal CVD method uses plasma. Since no plasma damage occurs, a film with few defects can be obtained.

[0136] In the CVD method, the composition of the resulting film can be controlled by adjusting the flow rate ratio of the source gases. For example, in the MCVD and MOCVD methods, a film of any composition can be produced by adjusting the flow rate ratio of the source gases. In addition, for example, in the MCVD method and the MOCVD method, By changing the flow rate ratio of the source gases, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the transistor 490 can be improved.

[0137] Next, a conductor that will become the conductor 413 is formed. The conductor that will become the conductor 413 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0138] Next, a part of the conductor that is to become the conductor 413 is etched to form the conductor 413.

[0139] Next, an insulator 402 is formed (see FIG. 7A). The insulator 402 is formed by sputtering. The film may be formed by a method such as a CVD method, an MBE method, a PLD method, or an ALD method. Here, the case where the insulator 402 is planarized from the top surface by a CMP method or the like will be described. By planarizing the top surface of the insulator 402, subsequent processes become easier, and the transistor For example, the CMP method can improve the yield of the insulator 402. RMS (Root Mean Square) roughness is preferably 1 nm or less. Preferably, the size is 0.5 nm or less, and more preferably, 0.3 nm or less. Ra (average surface roughness) in the range of m is less than 1 nm, preferably less than 0.6 nm, Preferably, it is less than 0.5 nm, more preferably less than 0.4 nm. Peak-Valley in the μm range is less than 10 nm, preferably less than 9 nm, More preferably, the thickness is less than 8 nm, and even more preferably, less than 7 nm. The transistor 490 is not limited to the case where the top surface of the insulator 402 is planarized.

[0140] The insulator 402 may be formed to contain excess oxygen. Oxygen may be added after the film is formed. The addition of oxygen is carried out, for example, by ion implantation using an accelerated The voltage is set to 2 kV or more and 100 kV or less, and the dose is set to 5 × 10 14 ions / cm 2 More than 5× 10 16 ions / cm 2 This can be done as follows.

[0141] When the insulator 402 is made of a laminated film, each film is formed by the above-mentioned film forming method. For example, the first layer may be formed by a CVD method, and the second layer may be formed by a CVD method. The first layer may be deposited by the ALD method. Alternatively, the first layer may be deposited by the sputtering method, and the second layer may be deposited by the ALD method. The film may be formed by the ALD method. By stacking these films, it is possible to give each layer a different function or property. By doing so, a more suitable film can be formed as the entire laminated film.

[0142] In other words, the nth layer (n is a natural number) is formed by sputtering, CVD, MBE or P The n+1th layer is formed by at least one of the LD method, ALD method, etc. At least one of the following methods is used: CVD, MBE, PLD, ALD, etc. The film is formed by one of two methods. Note that the film formation methods for the nth layer and the n+1th layer are different even if they are the same. The n-th film and the (n+2)-th film may be formed by the same film formation method. Alternatively, the deposition method may be the same for all the films.

[0143] Next, the semiconductor 436a which becomes the semiconductor 406a and the semiconductor 436 which becomes the semiconductor 406b are The semiconductor 436a which becomes the semiconductor 406a, the semiconductor 406b, and the semiconductor 406b are deposited in this order. The semiconductor 436b is formed by sputtering, CVD, MBE, PLD, or ALD. The film may be formed by using a method such as a method for forming a thin film.

[0144] The semiconductor 436a and the semiconductor 436b are formed of In-Ga-Zn oxide layers. When forming a film by the VD method, trimethylindium and trimethylgallium are used as the source gas. The combination of the raw material gases is not limited to the above. In addition, triethylindium may be used instead of trimethylindium. Triethylgallium may be used instead of trimethylgallium. Alternatively, diethyl zinc or the like may be used.

[0145] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 300° C. or higher and 500° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in an atmosphere, oxidizing gas is added at 10 ppm or more and 1 % or more, or 10% or more. , the crystallinity of the semiconductor 436a and the semiconductor 436b can be improved, and impurities such as hydrogen and water can be removed. It is possible to remove objects, etc.

[0146] Next, a conductor 416 is formed (see FIG. 7B). The conductor 416 is formed by sputtering. The film may be formed by a method such as a CVD method, an MBE method, a PLD method, or an ALD method.

[0147] The conductor 416a and the conductor 416b are formed by forming the conductor 416 on the substrate 416. Therefore, when the conductor 416 is formed, the semiconductor It is preferable to use a deposition method that does not damage the conductor 406b. For this purpose, it is preferable to use an MCVD method or the like.

[0148] When the conductor 416 is made of a laminated film, each film is formed by a sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), MBE method Alternatively, the film may be formed by a different deposition method such as PLD, ALD, etc. For example, the first layer may be formed by MOCVD and the second layer may be formed by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the MOCVD method. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the sputtering method. The first layer is deposited by the ALD method, the second layer is deposited by the sputtering method, and the third layer is deposited by the ALD method. In this way, by using different film forming methods, the film of each layer can be formed. It is possible to give the film different functions and properties. By stacking these films, As a result, a more suitable film can be formed as a whole laminated film.

[0149] That is, when the conductor 416 is made of a laminated film, for example, the n-th film is formed by sputtering. CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc.), The n+1 layer is formed by at least one of the following methods: MBE, PLD, ALD, etc. The film is formed by sputtering, CVD (plasma CVD, thermal CVD, MCVD, M At least one of the following methods is used: OCVD, MBE, PLD, ALD, etc. The deposition method may be different between the nth layer and the n+1th layer (n is the natural number). The film formation method may be the same for the nth layer and the n+2th layer. The deposition method may be the same for all the films.

[0150] In addition, the conductor 416 or at least one of the laminated films of the conductor 416 and the semiconductor The semiconductor 436a which becomes the semiconductor 406a and the semiconductor 436b which becomes the semiconductor 406b are the same. For example, the ALD method may be used for both. This allows the film to be formed without exposing it to air, which prevents the inclusion of impurities.

[0151] In addition, the conductor 416 or at least one of the laminated films of the conductor 416 and the semiconductor A semiconductor 436a which becomes the semiconductor 406a or a semiconductor 436b which becomes the semiconductor 406b, and an insulator 402, or at least one of the laminated films of the insulator 402, is formed by the same film formation method. For example, a sputtering method may be used. As a result, it is possible to prevent the inclusion of impurities. However, the method for manufacturing a semiconductor device according to one embodiment of the present invention is not limited to the above.

[0152] Next, a mask 426 is formed (see FIG. 8(A)). The mask 426 has photosensitivity. A resist may be used. The mask 426 may be an anti-reflective layer on the base of the photoresist. Bottom Anti Reflective Coating (BARC) By providing an anti-reflection film, defects due to halation can be suppressed. This allows for the creation of fine shapes.

[0153] Next, the conductor 416 is etched using the mask 426 to form the conductor 417. In order to form the conductor 417 having a fine shape, If the mask 426 having a fine shape is too thick, It is preferable that the mask has a thickness sufficient to allow it to stand on its own. The conductor 416 is etched using the mask 426 under conditions that the mask 426 can withstand. However, the conductor 416 is preferably thin enough to be etched into the transistor. The conductor 416a and the conductor 416b function as the source electrode and the drain electrode of 490. Therefore, in order to increase the on-current of the transistor 490, a certain degree of It is preferable that the thickness is large. Therefore, for example, the thickness is 5 nm or more and 30 nm or less, and preferably The thickness of the region is preferably 5 nm or more and 20 nm or less, more preferably 5 nm or more and 15 nm or less. The conductor 416 may be a conductor having a thickness of 100 .mu.m.

[0154] Next, the semiconductor 436b and the semiconductor 436a are etched using the conductor 417 as a mask. At this time, the insulator 402 is also etched to form the semiconductor 406a and the semiconductor 406b. By etching, the s-channel structure is easily formed (see FIG. 8(B)).

[0155] Next, a part of the conductor 417 is etched to form the conductor 416a and the conductor 416b. In this manner, the semiconductor 436a and the semiconductor 436b are etched. The conductor 416 formed as a mask for masking the source voltage of the transistor 490 The conductor 416a and the conductor 416b function as a positive and a drain electrode. The conductor 416 that becomes the conductor 416a and the conductor 416b can also be used as a mask. Therefore, the number of steps required to manufacture the transistor 490 can be reduced. 90, the area occupied by the conductor 416a and the conductor 416b can be reduced. This structure is suitable for fine semiconductor devices.

[0156] Next, a semiconductor film that will become the semiconductor 406c is formed. The film may be formed by deposition, CVD, MBE, PLD, ALD, or the like. .

[0157] In addition, the semiconductor 406c is a semiconductor that is made by growing an In-Ga-Zn oxide layer by MOCVD. Therefore, when forming the film, the source gas is trimethylindium, trimethylgallium, and The combination of raw material gases is not limited to the above, and may be any combination of raw material gases. Instead of methylindium, triethylindium or the like may be used. Instead of gallium, triethylgallium or the like may be used. Also, instead of dimethylzinc, Diethyl zinc and the like may also be used.

[0158] Next, a second heat treatment may be performed. A semiconductor having higher oxygen permeability than the semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than the semiconductor 406a is selected as the semiconductor to be used. For the semiconductor 406a, a semiconductor that is permeable to oxygen is selected. A semiconductor having an oxygen blocking function is selected as the semiconductor 406c. When the second heat treatment is performed, the semiconductor 406a is transferred to the insulator 402 through the semiconductor 406a. The excess oxygen migrates to the semiconductor 406b, which becomes the semiconductor 406c. Therefore, the outward diffusion of excess oxygen is difficult. By performing the second heat treatment, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the second heat treatment is performed so that excess oxygen (oxygen) in the insulator 402 is oxidized to the semiconductor 40 For example, the first heat treatment may be performed at a temperature at which the diffusion of the first and second ions occurs. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature range is from 20°C to 150°C, preferably from 40°C to 100°C. This makes it possible to suppress the excessive release of excess oxygen (oxygen) from the insulator 402. It is possible.

[0159] Next, an insulator that will become the insulator 412 is formed. The insulator that will become the insulator 412 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0160] When the insulator 412 is made of a laminated film, each film is formed by sputtering. taling method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc. ), MBE, PLD, ALD, etc., are used to form the films using different deposition methods. For example, the first layer may be formed by MOCVD and the second layer by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the MOCVD method. Alternatively, the first layer may be formed by ALD and the second layer may be formed by sputtering. Or, the first layer is deposited by ALD, the second layer by sputtering, and the third layer by A. The film may be formed by the LD method. Each layer of the film can have different functions and properties. This allows the laminated film to have a more appropriate overall film structure.

[0161] In other words, when the insulator 412 is made of a laminated film, for example, the n-th film is , sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCV The film is formed by at least one of the following methods: MBE, PLD, ALD, etc. The n+1th layer is formed by sputtering, CVD (plasma CVD, thermal CVD, M CVD method, MOCVD method, etc.), MBE method, PLD method, ALD method, etc. The nth layer and the n+1th layer may be formed by different methods. (n is a natural number). The nth film and the (n+2)th film may be formed by the same film formation method. Alternatively, the deposition method may be the same for all the films.

[0162] Next, a third heat treatment may be performed. A semiconductor having higher oxygen permeability than the semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than the semiconductor 406a is selected as the semiconductor to be used. A semiconductor having an oxygen blocking function is selected as the semiconductor for the body 406c. Alternatively, for example, the semiconductor 406a may be an insulator having a higher oxygen permeability than the insulator that becomes the insulator 412. That is, a semiconductor having a higher oxide content than the semiconductor 406a is selected as the insulator to be the insulator 412. In other words, an insulator that is permeable to oxygen is selected as the semiconductor 406a. In addition, a semiconductor having the function of blocking oxygen is selected as the insulator 412. In this case, a third heat treatment is performed to turn the semiconductor into an insulator. Excess oxygen contained in the insulator 402 moves to the semiconductor 406b via 406a. The conductor 406b is covered with a semiconductor that becomes the semiconductor 406c and an insulator that becomes the insulator 412. Therefore, the outward diffusion of excess oxygen is unlikely to occur. By carrying out the treatment, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the third heat treatment is performed so that excess oxygen (oxygen) in the insulator 402 diffuses into the semiconductor 406b. For example, the description of the first heat treatment may be referred to. Alternatively, the third heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature range is from 20°C to 150°C, preferably from 40°C to 100°C. When the insulator 412 has a function of blocking oxygen, it becomes the semiconductor 406c. The semiconductor does not necessarily have to have the function of blocking oxygen.

[0163] Next, a conductor that will become the conductor 404 is formed. The conductor that will become the conductor 404 is formed by sputtering. The film may be formed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0164] The insulator that becomes the insulator 412 functions as a gate insulator for the transistor 490. Therefore, when the conductor that becomes the conductor 404 is formed, the insulator that becomes the insulator 412 is not damaged. It is preferable to use a film formation method that does not require the use of a conductive material. It is preferable to do so.

[0165] When the conductor 404 is made of a laminated film, each film is formed by sputtering. taling method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCVD method, etc. ), MBE, PLD, ALD, etc., are used to form the films using different deposition methods. For example, the first layer may be formed by MOCVD and the second layer by sputtering. Alternatively, the first layer may be formed by the ALD method and the second layer may be formed by the MOCVD method. Alternatively, the first layer may be formed by ALD and the second layer may be formed by sputtering. Or, the first layer is deposited by ALD, the second layer by sputtering, and the third layer by A. The film may be formed by the LD method. Each layer of the film can have different functions and properties. This allows the laminated film to have a more appropriate overall film structure.

[0166] That is, when the conductor 404 is made of a laminated film, for example, the n-th film is , sputtering method, CVD method (plasma CVD method, thermal CVD method, MCVD method, MOCV The film is formed by at least one of the following methods: MBE, PLD, ALD, etc. The n+1th layer is formed by sputtering, CVD (plasma CVD, thermal CVD, M CVD method, MOCVD method, etc.), MBE method, PLD method, ALD method, etc. The nth layer and the n+1th layer may be formed by different methods. (n is a natural number). The nth film and the (n+2)th film may be formed by the same film formation method. Alternatively, the deposition method may be the same for all the films.

[0167] In addition, the conductor that becomes the conductor 404 or at least one of the laminated films of the conductor that becomes the conductor 404 At least one film and an insulator that will become the insulator 412, or a stack of insulators that will become the insulator 412 At least one of the films may be formed by the same film formation method. The LD method may also be used. This allows the film to be formed without being exposed to the air. As a result, it is possible to prevent the inclusion of impurities. The conductor 404 is connected to the insulator 412, which is in contact with the conductor 404. The same film formation method may be used for the insulating material to be formed. This allows the films to be formed in the same chamber. As a result, the inclusion of impurities can be prevented.

[0168] In addition, the conductor that becomes the conductor 404 or at least one of the laminated films of the conductor that becomes the conductor 404 At least one film and an insulator that will become the insulator 412, or a stack of insulators that will become the insulator 412 At least one of the films may be formed by the same deposition method. A deposition method may be used. This allows the film to be formed without being exposed to the air. As a result, the inclusion of impurities can be prevented.

[0169] Next, a part of the conductor that will become the conductor 404 is etched to form the conductor 404. The conductor 404 is formed to overlap at least a portion of the semiconductor 406b.

[0170] Next, a portion of the insulator that will become the insulator 412 is etched, similar to the conductor that will become the conductor 404. The insulating layer 412 is then formed.

[0171] Next, the semiconductor 40 is etched, as are the conductors that become the conductors 404 and the insulators that become the insulators 412. A portion of the semiconductor that will become 6c is etched to form semiconductor 406c.

[0172] The conductor that becomes the conductor 404, the insulator that becomes the insulator 412, and the semiconductor 406c When etching a portion of the semiconductor, the same photolithography process may be used. Alternatively, the conductor 404 may be used as a mask to form the insulator 412. The semiconductor that will become 406c may be etched. The semiconductor 406c has a similar shape in a top view. As shown in the enlarged cross section, the insulator 412 and / or the semiconductor 406c protrudes from the conductor 404. In some cases, the conductor may be in a protruding shape, or as shown in the enlarged cross section of Figure 9(C2), The shape of 404 protruding (protruding) from the insulator 412 and / or the semiconductor 406c By adopting the shapes shown in these figures, shape defects are reduced, Gate leakage current may be reduced.

[0173] Next, the insulator 408 is formed (see FIG. 9B). The insulator 408 is formed by sputtering. The film may be formed by a method such as a CVD method, an MBE method, a PLD method, or an ALD method.

[0174] Next, a fourth heat treatment may be performed. A semiconductor having higher oxygen permeability than semiconductor 406c is selected. A semiconductor having a lower oxygen permeability than that of semiconductor 406a is selected. Select a semiconductor having a blocking function. A semiconductor having a higher oxygen permeability than the insulator 412 is selected. Select a semiconductor that is less oxygen permeable than the conductor 406a. As a, a semiconductor having higher oxygen permeability than the insulator 408 is selected. As the semiconductor 406b, a semiconductor having a lower oxygen permeability than the semiconductor 406a is selected. A semiconductor having an oxygen permeability is selected as 406a. In this case, a fourth heat treatment is performed to select an insulator having an oxygen blocking function. By this, excess oxygen contained in the insulator 402 is transferred to the semiconductor 406 through the semiconductor 406a. The semiconductor 406b moves to the semiconductor 406c, the insulator 412, or the insulator 408. Because the oxygen is covered with a thin layer of chlorine, the outward diffusion of excess oxygen is difficult. By performing the fourth heat treatment in the same manner, defects (oxygen vacancies) in the semiconductor 406b can be efficiently reduced. Note that the fourth heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into a semiconductor. The temperature may be set to a temperature at which the diffusion of the metal to the metal layer 406b occurs. For example, see the description of the first heat treatment. Alternatively, the fourth heat treatment may be performed at a temperature lower than that of the first heat treatment. The temperature range to be lowered is 20°C to 150°C, preferably 40°C to 100°C. In addition, when the insulator 408 has a function of blocking oxygen, Alternatively, the insulator 412 may not have the function of blocking oxygen.

[0175] All of the first heat treatment, the second heat treatment, the third heat treatment and the fourth heat treatment are It is acceptable not to carry out any or all of the above.

[0176] Next, the insulator 418 is formed. The insulator 418 is formed by a sputtering method, a CVD method, or an MBE method. The film may be formed by a method such as a PLD method or an ALD method.

[0177] In the above manner, the transistor 490 shown in FIG. 6 can be manufactured.

[0178] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0179] (Embodiment 3) In this embodiment, an oxide semiconductor that can be used for a transistor according to one embodiment of the present invention will be described. The conductor will now be described.

[0180] Oxide semiconductors are roughly classified into non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Oxide semiconductors are CAAC-OS (C Axis Aligned Crystalline ine oxide semiconductor, polycrystalline oxide semiconductor, microcrystalline oxide The term CAAC-OS refers to amorphous semiconductors, amorphous oxide semiconductors, etc. Axis Aligned Nano Crystalline Oxide Sem It can also be called an electrical conductor.

[0181] First, let me explain about CAAC-OS.

[0182] The CAAC-OS is a type of oxide semiconductor that has multiple crystal parts aligned along the c-axis.

[0183] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of CAAC-OS were obtained by using a high-resolution microscope. By observing the high-resolution TEM image, multiple crystals can be confirmed. On the other hand, the boundaries between crystals, i.e., grain boundaries (grain bows), are clearly visible even in high-resolution TEM images. Therefore, CAAC-OS is not able to confirm the grain boundary. This means that the decrease in electron mobility caused by magnetic fields is unlikely to occur.

[0184] When a high-resolution TEM image of the cross section of CAAC-OS was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The shape reflects the unevenness of the surface on which the AAC-OS is formed (also called the surface on which it is formed) or the top surface. The CAAC-OS is then aligned parallel to the surface on which the CAAC-OS is formed or the top surface.

[0185] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0186] On the other hand, a high-resolution TEM image of the CAAC-OS plane was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal regions.

[0187] FIG. 38(A) is a high-resolution TEM image of a cross section of CAAC-OS. is a high-resolution TEM image of a cross section enlarged from that of FIG. 38(A), and is shown in Fig. 38(B) for ease of understanding. The atomic arrangement is highlighted for ease of understanding.

[0188] FIG. 38(C) shows the area surrounded by a circle (diameter approximately 4n m) are local Fourier transform images. From Fig. 38(C), it is clear that the c-axis orientation is In addition, the orientation of the c-axis is different between the AO and O-A' sections, so different gradients are observed. In addition, the c-axis angles between the A and A are 14.3° and 16.6°. 26.4°, and so on. Similarly, O-A' Between these, the c-axis angle changes gradually and continuously from -18.3° to -17.6° to -15.9°. It is clear that the

[0189] When electron diffraction was performed on CAAC-OS, spots (bright spots) indicating orientation were observed. For example, the upper surface of the CAAC-OS is subjected to an electron beam of, for example, 1 nm to 30 nm. When electron diffraction (also called nanobeam electron diffraction) is performed using See Figure 39(A).

[0190] The high-resolution TEM images of the cross section and the plan view show that the crystalline part of CAAC-OS is It is clear that the film has an orientation.

[0191] Most of the crystals in CAAC-OS are cubic with sides less than 100 nm. Therefore, the crystal part in the CAAC-OS has a side length of 10n This also includes cases where the size fits within a cube of less than 100 mm, 5 nm, or 3 nm. The multiple crystal parts in the CAAC-OS are connected to form a single large crystal region. For example, in a high-resolution TEM image of a plane, 2 That's all, 5μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0192] X-ray diffraction (XRD) equipment for CAAC-OS For example, the structure of CAAC-OS with InGaZnO4 crystals was analyzed using In the out-of-plane analysis, a peak appears at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is pointing in the right direction.

[0193] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. In the analysis by the Ie method, a peak may appear at 2θ of around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. If it is a conductor, fix 2θ at around 56° and test with the normal vector of the sample surface as the axis (φ axis). When the sample was rotated and analyzed (φ scan), the crystal planes that were assigned to the (110) plane were In contrast, in the case of CAAC-OS, six peaks are observed at 2θ of around 56°. Even when the φ scan is performed with the φ fixed at , no clear peak appears.

[0194] From the above, it is considered that the orientation of the a-axis and the b-axis is irregular between different crystal parts in CAAC-OS. However, the c-axis is oriented parallel to the normal vector of the surface on which the film is formed or the upper surface. Therefore, it is clear that the direction of the nucleation is the same as that confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in a layered fashion is parallel to the ab plane of the crystal.

[0195] The crystals were formed when the CAAC-OS was formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS is formed or the upper surface. The orientation is parallel to the normal vector of the surface. Therefore, for example, the shape of CAAC-OS When the surface is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS is formed or may not be parallel to the normal vector of the top surface.

[0196] In addition, the distribution of the c-axis oriented crystal parts in the CAAC-OS may not be uniform. For example, the crystalline part of the CAAC-OS is formed by crystal growth from the top surface of the CAAC-OS. When a crystal is formed, the area near the top surface has a higher proportion of c-axis oriented crystals than the area near the surface on which the crystal is formed. In addition, the impurity-added CAAC-OS may have a high The crystals may be altered and regions with different proportions of c-axis oriented crystals may be formed. do.

[0197] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the analysis, in addition to the peak at 2θ near 31°, a peak also appears at 2θ near 36°. The peak at 2θ around 36° may be due to the presence of c-axis orientation in some CAAC-OS. This indicates that the crystals that are not crystallized are included. CAAC-OS has a peak at 2θ of around 31°. and preferably does not exhibit a peak at 2θ of around 36°.

[0198] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are The removal of oxygen from the oxide semiconductor disrupts the atomic arrangement of the oxide semiconductor, which is a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Since the radius of the oxide semiconductor is large, when the oxide semiconductor is contained in the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed. Impurities contained in an oxide semiconductor can cause carrier transport and lead to a decrease in crystallinity. These may be sources of tripping or carrier generation.

[0199] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen deficiencies in the body act as carrier traps or capture hydrogen to reduce the amount of carriers. It can be a source of pollution.

[0200] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor is Since there are few carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor has electrical characteristics in which the threshold voltage is negative ( Also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. Oxide semiconductors are highly conductive and have few carrier traps. The transistor thus obtained has a small fluctuation in electrical characteristics and is highly reliable. However, it takes a long time for the charges trapped in the carrier traps of the oxide semiconductor to be released. Therefore, the impurity concentration is high and defects are generated. A transistor using an oxide semiconductor with high density of states may have unstable electrical characteristics. do.

[0201] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0202] Next, a microcrystalline oxide semiconductor will be described.

[0203] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) In addition, the grain boundaries of nc-OS cannot be clearly identified in high-resolution TEM images. There are cases.

[0204] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The atomic arrangement has periodicity in the region of less than 1 nm. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the layer. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a diameter larger than the crystal part is used for nc-OS. When the structure was analyzed using the out-of-plane method, peaks indicating crystal planes were In addition, the probe diameter (e.g. 5 mm) is larger than the crystal area of ​​the nc-OS. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a wavelength of 0.0 nm or more, halo On the other hand, the size of the crystal part is smaller than that of the nc-OS. When nanobeam electron diffraction is performed using an electron beam with a probe diameter close to or smaller than the crystal part, In addition, when nanobeam electron diffraction is performed on nc-OS, a circular spot is observed. In some cases, a bright area (ring-shaped) may be observed. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. (See Figure 39(B)).

[0205] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. In the case of nc-OS, there is no regularity in the crystal orientation between different crystal parts. The defect density is higher than that of C-OS.

[0206] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, a microcrystalline oxide semiconductor, or a CAAC- The OS may be a laminated film having two or more kinds.

[0207] When an oxide semiconductor has multiple structures, the structure can be analyzed by using nanobeam electron diffraction. It may be possible.

[0208] FIG. 39C shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and the A sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation chamber A transmission electron microscope having a camera 18 mounted on the observation chamber 20 and a film chamber 22 below the observation chamber 20. The diffraction measurement device is shown. The camera 18 is installed facing the inside of the observation room 20. The housing 22 may not be provided.

[0209] FIG. 39(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 39(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 The light is irradiated onto a substance 28 placed in a sample chamber 14 via an optical system 12. The electrons are incident on a fluorescent screen 32 installed inside the observation chamber 20 via the optical system 16. On the plate 32, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. can be measured.

[0210] The camera 18 is set facing the fluorescent screen 32 and captures the pattern appearing on the fluorescent screen 32. A straight line passing through the center of the lens of the camera 18 and the center of the fluorescent screen 32 The angle between the upper surface of the fluorescent screen 32 and the light source 31 is, for example, 15° to 80°, or 30° to 70°. The smaller the angle, the more difficult it is to capture with the camera 18. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be significantly distorted. If a camera is used, it is possible to correct distortions in the obtained transmission electron diffraction pattern. In some cases, it may be acceptable to place the camera 18 in the film chamber 22. The fluorescent screen 3 may be installed in the electron chamber 22 so as to face the direction of incidence of the electrons 24. It is possible to capture a transmission electron diffraction pattern with little distortion from the back surface of 2.

[0211] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function of moving the holder 28 along the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less The range is 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance 28. good.

[0212] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. The method will be explained.

[0213] For example, as shown in FIG. 39(D), the irradiation position of the nanobeam electron 24 on the material is By changing (scanning) the material, it is possible to observe how the structure of the material changes. In this case, if the material 28 is CAAC-OS, the diffraction pattern shown in FIG. If the material 28 is an nc-OS, the pattern shown in FIG. A diffraction pattern like this is observed.

[0214] By the way, even if substance 28 is a CAAC-OS, it may be partially similar to nc-OS, etc. Therefore, the quality of CAAC-OS can be judged by a certain The ratio of the area in which the diffraction pattern of CAAC-OS is observed (also called the CAAC conversion rate) For example, a good CAAC-OS can be expressed as CA The AC ratio is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably Preferably, the ratio is 95% or more. In addition, in the region where a diffraction pattern different from that of CAAC-OS is observed, The percentage of areas that are not CAAC is referred to as the non-CAAC rate.

[0215] As an example, the film is deposited immediately after (denoted as-sputtered), or in an oxygen-containing atmosphere. The top surface of each sample with CAAC-OS after the 450°C heat treatment was scanned. Transmission electron diffraction patterns were obtained while scanning at a speed of 5 nm / sec for 60 sec. The diffraction pattern was observed while scanning, and the observed diffraction pattern was converted to a still image every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the ion beam. A nano-beam electron beam was used. The same measurements were performed on six samples. The conversion rate was calculated using the average value of six samples.

[0216] The CAAC ratio in each sample is shown in FIG. The C content was 75.7% (non-CAAC content was 24.3%). The CAAC rate for the subsequent CAAC-OS was 85.3% (non-CAAC rate was 14.7%). It can be seen that the CAAC conversion rate is higher after the heat treatment at 450°C than immediately after the film formation. Heat treatment at high temperatures (e.g., 400°C or higher) reduces the non-CAAC ratio. It can be seen that the CAAC conversion rate is high even in heat treatment at temperatures below 500°C. It can be seen that a CAAC-OS with a high CAAC content can be obtained.

[0217] Here, most of the diffraction patterns different from the CAAC-OS are similar to those of the nc-OS. In addition, no amorphous oxide semiconductor was observed in the measurement area. Therefore, the heat treatment resulted in the formation of adjacent regions with a structure similar to that of nc-OS. This suggests that the rearrangement is influenced by the structure of the region where the CAAC is formed.

[0218] 40(B) and 40(C) show the CAAC-O immediately after deposition and after heat treatment at 450° C. 40(B) and 40(C) are high-resolution TEM images of the S surface. It can be seen that the film quality of the CAAC-OS after the 450°C heat treatment is more uniform. It can be seen that the film quality of the CAAC-OS is improved by heat treatment at a high temperature.

[0219] By using such a measurement method, it is possible to analyze the structure of oxide semiconductors having multiple structures. There may be cases where this occurs.

[0220] The above is an oxide semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, etc. The structure of the body.

[0221] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0222] (Embodiment 4) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. Please refer to the following for explanation.

[0223] [Cross-sectional structure] FIG 10A shows a cross-sectional view of a semiconductor device of one embodiment of the present invention. The device has a transistor 2200 using a first semiconductor material on the bottom and a transistor 2200 using a second semiconductor material on the top. The transistor 2100 is made of a conductive material. As the transistor 2100 using the material, the transistor exemplified in the above embodiment is used. The left side of the dashed line is a cross section of the transistor in the channel length direction. The right side is a cross section in the channel width direction.

[0224] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide) The second semiconductor is a The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0225] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. In addition to using a transistor according to one embodiment of the present invention using a nitride semiconductor, other materials and structures are not required. For example, the specific configuration of the semiconductor device is not necessarily limited to that shown here.

[0226] In the structure shown in FIG. 10A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate are used to connect the wiring provided in the upper and lower layers. The electrodes are electrically connected to an insulator 2204 that covers the transistor 2100. 2204, a wiring 2205 and a conductive layer having the same conductivity as the pair of electrodes of the transistor 2100 are provided on the insulator 2204. A wiring 2206 obtained by processing the body is provided.

[0227] In this way, by stacking two types of transistors, the area occupied by the circuit is reduced, Multiple circuits can be arranged at higher density.

[0228] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor of the transistor 2200 is a dangling of silicon. This has the effect of terminating the ring bonds and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the layer, the transistor 210 Hydrogen in an insulator provided near a semiconductor of 0 generates carriers in the oxide semiconductor. This may be one of the factors that reduces the reliability of the transistor 2100. Therefore, an oxide semiconductor is formed on the upper layer of the transistor 2200 using a silicon-based semiconductor material. When the transistors 2100 using a conductor are stacked, hydrogen diffusion between them is prevented. It is particularly effective to provide the insulator 2207 having a function of preventing the electric shock. In addition, the reliability of the transistor 2200 is improved by trapping hydrogen in the lower layer. Therefore, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, thereby improving the reliability of the transistor 2100. At the same time, the performance can be improved.

[0229] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0230] In addition, a transistor 2100 including an oxide semiconductor is formed on the transistor 2100 so as to cover the transistor 2100. A blocking film 2208 (transistor 1) having a function of preventing hydrogen diffusion is formed on the transistor 2100. In the transistors 101 to 103, it is preferable to form an insulator 180. The insulating film 2208 may be made of the same material as the insulator 2207, and in particular, may be made of oxidized aluminum. It is preferable to use aluminum oxide. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. The membrane has a high blocking effect, preventing both oxygen and water from passing through. An aluminum oxide film is used as the block film 2208 that covers the transistor 2100. This can prevent oxygen from being released from the oxide semiconductor included in the transistor 2100. In addition, water and hydrogen can be prevented from entering the oxide semiconductor.

[0231] It should be noted that the transistor 2200 is not limited to a planar type transistor, but may be of various types. For example, FIN type, TRI-GATE type, In this case, the transistor may be a ligate type transistor. As shown in FIG. 10(D), an insulator 2212 is provided on a semiconductor substrate 2211. The conductive substrate 2211 has a protruding portion (also called a fin) with a thin tip. When the protrusions are formed, the semiconductor substrate 2 may be provided with an insulator. It functions as a mask to prevent 211 from being etched. The protrusion does not have to have a thin tip. For example, the protrusion may be a substantially rectangular parallelepiped protrusion, or the tip may be thick. A gate insulator 2214 is provided on the protruding portion of the semiconductor substrate 2211. A gate electrode 2213 is provided on the semiconductor substrate 2211. A source region and a drain region 2215 are formed. Although an example in which the electrode 2211 has a protrusion is shown, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, a semiconductor region having a protrusion may be formed by processing an SOI substrate. do not have.

[0232] [Circuit configuration example] In the above configuration, the electrodes of the transistor 2100 and the transistor 2200 are appropriately connected. In the following, a semiconductor device according to one embodiment of the present invention will be described. An example of a circuit configuration that can be realized by using the device will be described below.

[0233] [CMOS inverter circuit] The circuit diagram shown in FIG. 10B includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected. 4 shows the configuration of an S inverter.

[0234] [CMOS Analog Switch] In addition, the circuit diagram shown in FIG. 10C shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch.

[0235] [Example of storage device] By using a transistor according to one embodiment of the present invention, it is possible to preserve memory contents even in a state where power is not supplied. FIG. 11 shows an example of a semiconductor device (memory device) that can store data and has no limit on the number of times it can be written. As shown in.

[0236] The semiconductor device illustrated in FIG. 11A includes a transistor 3200 using a first semiconductor material and a The semiconductor device includes a transistor 3300 using the semiconductor material of the second embodiment, and a capacitor element 3400 . Note that the transistor 3300 is a transistor described in the above embodiment. It is possible.

[0237] 11B is a cross-sectional view of the semiconductor device shown in FIG. In the example shown, a back gate is provided in the transistor 3300. It is also possible to adopt a configuration in which no.

[0238] In FIG. 11A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0239] In the semiconductor device shown in FIG. 11A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0240] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and one of the electrodes of the capacitor 3400. That is, the capacitor 3400 is Here, two potential levels, a low level and a high level, are given. The capacitance element 3400 is given one of two electric charges corresponding to two potential levels. After that, the potential of the fourth wiring 3004 is changed so that the transistor 3300 is turned off. By applying a potential to the capacitor 3400 to turn off the transistor 3300, In this manner, the charge is written to the semiconductor device shown in FIG. Do the following.

[0241] Since the off-state current of the transistor 3300 is extremely small, the voltage applied to the capacitor 3400 Therefore, the memory contents can be restored even when the power is not supplied. Retention is possible.

[0242] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the capacitance element 3 Depending on the amount of charge held in 400, the second wiring 3002 takes on different potentials. If the transistor 3200 is an n-channel type, then H Apparent threshold voltage V when a given igh level potential is given th_H is a transistor The apparent threshold voltage V when a low-level potential is applied to the gate electrode of 3200 t h_LHere, the apparent threshold voltage is the voltage at which the transistor 32 The potential of the fifth wiring 3005 required to turn ON the fifth wiring 3005 is referred to as the potential of the fifth wiring 3005. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L The potential between them is V0. In this way, the potential applied to the gate electrode of the transistor 3200 can be determined. For example, In the case where a high-level potential is applied in writing, the fifth wiring 3005 The potential of V0 (>V th_H ), transistor 3200 is in the "on state." When a low-level potential is applied, the potential of the fifth wiring 3005 becomes V0 ( <V t h_L ), the transistor 3200 remains in the “off state”. By determining the potential of the wiring 3002 in FIG. 2, the stored data can be read out. .

[0243] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, when the information is not read out, the capacitance element 3400 A potential at which the transistor 3200 is in an “off state” regardless of the amount of charge retained; That is, V th_H A smaller potential may be applied to the fifth wiring 3005. Regardless of the amount of charge held by element 3400, transistor 3200 is "on." The potential at which the th_L A larger potential may be applied to the fifth wiring 3005. .

[0244] In the semiconductor device described in this embodiment, the transistor 3300 is a semiconductor having an oxide semiconductor. The transistor 3300 is a transistor in which a channel is formed in a conductor. Because it is small, it is possible to retain memory contents for a long period of time by using it. That is, no refresh operation is required or the frequency of refresh operation is very low. Since it is possible to reduce the number of semiconductor memory devices, the power consumption can be sufficiently reduced. Cut.

[0245] In the semiconductor device described in this embodiment, the transistor 3300 is a semiconductor having an oxide semiconductor. The transistor 3300 is a transistor in which a channel is formed in a conductor. By applying the transistor shown in the figure, excellent subthreshold characteristics can be obtained. In addition, the switching speed is fast, allowing for high-speed operation. On the other hand, the transistor 3200 can be formed using a semiconductor material other than an oxide semiconductor. These transistors use crystalline silicon and other materials, enabling miniaturized transistors and high-speed operation. By combining these, a small semiconductor device can be realized. This enables write and read operations.

[0246] The semiconductor device shown in FIG. 11C is different from the semiconductor device shown in FIG. 11A in that the transistor 3200 is not provided. In this case, the writing and holding of information is performed in the same manner as above. It is possible.

[0247] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in the free state and the capacitor element 3400 are electrically connected to each other. Charge is redistributed between the associated wiring capacitance and the capacitive element 3400. As a result, the third wiring The potential of the third wiring 3003 changes. The change in the potential of the third wiring 3003 is input to the capacitor 3400. Depending on the accumulated charge (or the potential of one of the electrodes of the capacitor 3400), do.

[0248] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The wiring capacitance associated with the wiring 3003 of the first wiring 3003 before the charge is redistributed is CB. The potential of the fifth wiring 3005 is set to 0 V, and the potential of the third wiring 3003 is set to VB0. If the potential of the other electrode of the wiring capacitance is 0 V, the third wiring 300 after the charge is redistributed is The potential of memory cell 3 is (CB×VB0+C×V) / (CB+C). In this state, the potential of one electrode of the capacitor 3400 is in two states of V1 and V0 (V1>V0). In this case, the potential of the third wiring 3003 when the potential V1 is held (=(CB × VB0 + C × V1) / (CB + C)) is the current of the third wiring 3 when the potential V0 is maintained. It can be seen that the potential of the 003 (=(CB×VB0+C×V0) / (CB+C)) is higher than that of the Light.

[0249] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0250] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be laminated on the driver circuit.

[0251] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0252] In the semiconductor device described in this embodiment, the transistor 3300 is a semiconductor having an oxide semiconductor. The transistor 3300 is a transistor in which a channel is formed in a conductor. By applying the transistor shown in the figure, excellent subthreshold characteristics can be obtained. In addition, the switching speed is fast, allowing for high-speed operation. As a result, a small semiconductor device can be realized. A read operation is then possible.

[0253] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is an issue with semiconductors, and reliability has been dramatically improved. Furthermore, information can be written depending on whether the transistor is conductive or non-conductive. This allows high speed operation.

[0254] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0255] (Embodiment 5) FIG. 12 illustrates a configuration example of a semiconductor device according to one embodiment of the present invention.

[0256] A semiconductor device 200 illustrated in FIG. 12 includes a first memory circuit 201, a second memory circuit 202, and The semiconductor device 200 includes a third memory circuit 203 and a reading circuit 204. The potential difference between potential V1 and potential V2 is supplied as a power supply voltage. The potential V1 is at a high level, and the other is at a low level. A configuration example of a semiconductor device according to one embodiment of the present invention will be described taking a high-level example as an example. This shall be done.

[0257] During a period in which a power supply voltage is supplied to the semiconductor device 200, the first memory circuit 201 When a signal D containing data is input, the semiconductor device has a function of holding the data. During a period in which the power supply voltage is supplied to the body device 200, the first memory circuit 201 outputs: A signal Q including the stored data is output. During the period when the power supply voltage is not supplied to the device 200, data cannot be held. In other words, the first memory circuit 201 can be called a volatile memory circuit.

[0258] During a period in which the power supply voltage is supplied to the semiconductor device 200, the second memory circuit 202 The data stored in the first memory circuit 201 is read, and the data is saved. The third memory circuit 203 has a function of storing a power supply voltage to the semiconductor device 200. During the period, the data stored in the second memory circuit 202 is read, The read circuit 204 has a function of saving data. During the period in which the signal is supplied to the second memory circuit 202 or the third memory circuit 203, The EEPROM has the function of reading out the stored data.

[0259] As shown in FIG. 12, the second memory circuit 202 includes a transistor 212 and a capacitor 219. The third memory circuit 203 includes a transistor 213 and a transistor 215. The read circuit 204 includes a transistor 210 and a capacitor 220. The second input terminal includes a transistor 218, a transistor 209, and a transistor 217.

[0260] The transistor 212 stores a charge according to the data stored in the first memory circuit 201. The transistor 212 has a function of charging and discharging the capacitor 219. 1 can be quickly charged and discharged to and from the capacitance element 219 according to the data held in the capacitance element 219. Specifically, the transistor 212 is preferably made of crystalline silicon (preferably It is preferable that the channel forming region contains polycrystalline silicon, and more preferably single crystal silicon. I wish.

[0261] The transistor 213 is turned on or off depending on the charge held in the capacitor 219. The transistor 215 is in a non-conductive state when the transistor 213 is in a conductive state. When the wiring 244 is turned on, the capacitor 220 is charged with and discharged from the capacitor 220 in response to the potential of the wiring 244 . It is preferable that the off-state current of the transistor 215 is extremely small. The chuck 215 is made of an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). It is desirable to include it in the channel forming region.

[0262] To explain the connection relationship of each element specifically, the source and drain of the transistor 212 are One end of the transistor 212 is connected to the first memory circuit 201. The other drain is connected to one electrode of the capacitor 219, the gate of the transistor 213, and the The other electrode of the capacitor 219 is connected to the gate of the transistor 218. 2. One of the source and drain of the transistor 213 is connected to the wiring 244 The other of the source and drain of the transistor 213 is connected to a transistor The source and drain of the transistor 215 are connected to one of the sources and drains of the transistor 215. The other of the drain and the gate of the transistor 210 is connected to one electrode of the capacitor 220. The other electrode of the capacitor 220 is connected to a wiring 243. One of the source and drain of the transistor 210 is connected to a wiring 241. The other of the source and drain of the transistor 210 is connected to the source and drain of the transistor 218. The other of the source and drain of transistor 218 is connected to The transistor 209 is connected to one of the source and drain of the transistor 20 The other of the source and drain of transistor 9 is connected to one of the source and drain of transistor 217. , and the first memory circuit 201. The source and drain of the transistor 217 are connected to The other drain is connected to a wiring 240. In addition, in FIG. The gate of transistor 209 is connected to the gate of transistor 217, while the gate of transistor 20 The gate of transistor 9 does not necessarily have to be connected to the gate of transistor 217.

[0263] In FIG. 12, the third memory circuit 203 and the read circuit 204 are connected to each other. In both cases, the second memory circuit 202 and the read circuit 204 are connected to each other. However, one aspect of the present invention is not necessarily limited to this configuration. 4 is connected to at least the third memory circuit 203 and is not connected to the second memory circuit 202. However, the read circuit 204 may not necessarily be connected to the second memory circuit 20. The configuration connected to the second memory circuit 202 reads out the data stored in the second memory circuit 202. Since the data can be supplied to the first storage circuit 201 by the above-mentioned method, the data can be stored in a time-granular manner. This is preferable for performing fine power gating.

[0264] By using the transistor described in the above embodiment as the transistor 215, Not only does it have a small current, but it also has excellent subthreshold characteristics, making it ideal for miniaturized transistors. In addition, the fast switching speed allows high-speed operation. In addition, the data stored in the first memory circuit 201 can be read out. This allows for high-speed power gating, which allows fine-grained power gating in terms of time. It is possible to do so.

[0265] (Embodiment 6) An example of the configuration of a device using a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. He explains.

[0266] The semiconductor device 300 shown in FIG. The power management unit 321 includes a power converter 322 and a peripheral circuit 322. The peripheral circuit 322 includes a cache controller 302 and a power switch 303. a cache 304 having a memory; a bus interface (BUS I / F) 305; and a debug interface (Debug I / F) 306. 01 includes a data bus 323, a control device 307, a PC (program counter) 308, A pipeline register 309, a pipeline register 310, an ALU (Arithmetic logic unit 311 and a register file 312. Data is exchanged between the 301 and the peripheral circuit 322 such as the cache 304 via a data bus 303. The semiconductor device according to one embodiment of the present invention includes a PC (program counter). ) 308, a pipeline register 309, a pipeline register 310, or / and The present invention can be applied to the register file 312 and the like. As an example of a circuit to which the semiconductor device can be applied, if the circuit has a register, it can be used in other circuits. The semiconductor device according to one embodiment of the present invention can be applied to these circuits. In this way, a semiconductor device capable of actively suppressing power consumption can be provided.

[0267] The control unit 307 includes a PC 308, a pipeline register 309, and a pipeline register 3 10, ALU 311, register file 312, cache 304, bus interface The operation of the power controller 302 is controlled by the By controlling the entire system, the commands contained in the input application programs can be The device has the function of decoding and executing the above.

[0268] The ALU 311 has a function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0269] The cache 304 has a function of temporarily storing frequently used data. A register 308 has a function of storing the address of the next instruction to be executed. Although not shown in FIG. 13, the cache 304 includes a cache memory control unit that controls the operation of the cache memory. A cache controller is provided.

[0270] The pipeline register 309 is a register that has the function of temporarily storing instruction data. be.

[0271] The register file 312 includes a number of registers including general-purpose registers. The data read from the main memory of the ALU307 or the data obtained by the arithmetic processing of the ALU311 The data, etc., can be stored.

[0272] The pipeline register 310 stores data to be used in the arithmetic processing of the ALU 311, or A register that temporarily stores data obtained as a result of the calculations of U311. It is.

[0273] The bus interface 305 is a bus interface between the semiconductor device 300 and various external devices. It functions as a data path between the device and the debug interface 30. 6 is a signal path for inputting a command for controlling debugging to the semiconductor device 300; The bus interface 305 and the debug interface 306 Each of these has a register attached thereto.

[0274] The power switch 303 is a power supply that is provided in the semiconductor device 300 other than the power controller 302. It has the function of controlling the supply of power supply voltage to various circuits. Each circuit belongs to a power domain, and various circuits that belong to the same power domain are called power switches. The power supply voltage is controlled by the power controller 303. 02 has a function of controlling the operation of the power switch 303 .

[0275] Regarding the flow of power gating operations in the semiconductor device 300 having the above configuration, An example will be given to explain this.

[0276] First, the CPU core 301 determines the timing to stop the supply of the power supply voltage by the power controller. Then, the CPU core 301 sets the register of the power controller 302. 2 to start power gating. The various registers and caches 304 included in the semiconductor device start to save data. The power supply voltage is supplied to various circuits other than the power controller 302 of the device 300. The power supply is stopped by the power switch 303. Then, an interrupt signal is sent to the power controller 302. When this signal is input, the supply of power supply voltage to various circuits in the semiconductor device 300 begins. A counter is provided in the power controller 302 so that the power supply voltage is notified when the power supply voltage is started. The timing of the interrupt is determined by the counter, not by the input of an interrupt signal. Then, the various registers and caches 304 start to restore the data. Then, execution of instructions in the control unit 307 resumes.

[0277] The transistor according to one embodiment of the present invention is used in a register or cache memory of a processor. By using it in storage devices such as the above, data loss in the storage device due to power supply interruption can be prevented. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor or any part of the processor can be restored to the original state. In addition, power can be cut off for short periods of time in multiple logic circuits, reducing power consumption. This can reduce electricity consumption.

[0278] The transistor according to one embodiment of the present invention has a low off-state current and an excellent subthreshold current. This allows for excellent short circuit characteristics and makes it possible to fabricate fine transistors. As a result, the transistor exemplified in the previous embodiment can be operated at high speed. By applying a register using a capacitor, a small semiconductor device can be realized. Since it is possible to evacuate at high speed, power gating with fine granularity in time can be performed. As a result, power consumption can be reduced.

[0279] Note that a memory circuit including a transistor according to one embodiment of the present invention can be used in not only a CPU but also a DS P(Digital Signal Processor), Custom LSI, PLD( Programmable Logic Devices, LSIs, RF (Radio Frequency o Frequency) tag, GPU (Graphics Processing U This can also be applied to nit.

[0280] (Embodiment 7) In this embodiment, an example of use of a semiconductor device according to one embodiment of the present invention will be described.

[0281] Figure 14(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 14A is a perspective view of a semiconductor device according to one embodiment of the present invention. The corresponding chip 751 is connected to the terminals on the interposer 750 by wire bonding. The terminal 752 is connected to the chip 751 of the interposer 750. The chip 751 is placed on a surface that is covered with a molding resin 753. Although it may be sealed, it is preferable that the sealing be performed while leaving a portion of each terminal 752 exposed.

[0282] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is shown in Fig. The mobile phone module shown in FIG. 14(B) includes a printed wiring board 80. A package 802 and a battery 804 are mounted on the display device 1. A printed wiring board 801 is mounted on the panel 800 by an FPC 803. do.

[0283] (Embodiment 8) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (a device having a display device capable of playing back recording media such as a DVD player and displaying the images) Other examples of electronic devices in which the semiconductor device according to one embodiment of the present invention can be used include Mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras, Cameras such as digital still cameras, goggle-type display devices (head-mounted displays) ), navigation systems, audio playback devices (car audio, digital audio players) Years, etc.), copiers, facsimiles, printers, printer-combinations, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 15. .

[0284] FIG. 15A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. 15A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0285] FIG. 15B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit 9 13, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 91 and the second display unit 912. At least one of the third and second display units 913 and 914 is provided with a function as a position input device. A display device may be used. The function as a position input device may be implemented by adding a touch to the display device. The function as a position input device can be added by providing a touch panel. Also, by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device, It is possible.

[0286] FIG. 15C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0287] FIG. 15(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, and a freezer door 93. 3 etc.

[0288] FIG. 15E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0289] FIG. 15(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear window. It has 954 and others.

[0290] By using the semiconductor device according to one embodiment of the present invention in these electronic devices, In other words, the transistor according to one embodiment of the present invention is incorporated in the LSI. A memory circuit that can retain memory contents even when power is not supplied is used. When the LSI is temporarily not in use, the power supply to the LSI is cut off. It is possible to save the state of the logic circuit in the memory circuit before cutting off the power. As a result, it is possible to reduce power consumption and After power is turned on, the state before the power was turned off can be quickly restored, allowing for a fast recovery.

[0291] By applying the transistor exemplified in the above embodiment, excellent subthreshold characteristics can be obtained. This allows for the fabrication of fine transistors. As a result, a small semiconductor device can be realized. As a result, the power supply can be quickly shut off. In addition, it can quickly recover after power is turned on.

[0292] This embodiment mode may be appropriately combined with other embodiment modes or examples shown in this specification. It is possible. EXAMPLES

[0293] In this example, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0294] The channel formation region is C-axis aligned crystalline In Dium-Gallium-Zinc Oxide (CAAC-IGZO) Island A transistor with a structure in which the gate electrode is surrounded not only on the top but also on the sides, i.e., a surro Unded channel (s-channel) CAAC-IGZO transistor By fabricating a MOSFET, it is possible to obtain a good subthread even when the channel length is reduced to about 50 nm. The shoulder characteristics can be maintained.

[0295] Figures 16(A) and 16(B) show the s-channel CAAC-IGZO transistor. The schematic and plan views of the transistor are shown in Fig. 1. The transistor is made of an insulator BI and a CAA on an insulator BI. An oxide semiconductor OS having C-IGZO and an electrode M electrically connected to the oxide semiconductor OS. E (source and drain electrodes), oxide semiconductor OS, and gate insulator on electrode ME The gate insulator GI overlaps with the oxide semiconductor OS and a part of the electrode ME. The transistor in Fig. 16 has a top-gate / top-contact structure. The gate electrode GE overlaps with the electrode ME that constitutes the source and drain electrodes. As shown in FIG. 16(B), the channel length L ch is the distance between the electrodes ME, and the channel width W island represents the width of the oxide semiconductor OS.

[0296] Figure 16(C) and Figure 16(D) show cross-sectional STEM (Scan ning Transmission Electron Microscope (TEM) images As shown in the figure, the transistor is made up of an insulator BI, an oxide semiconductor OS, and an electrode ME (semiconductor a gate insulator GI and a gate electrode GE, It can be confirmed that the desired device structure has been formed.

[0297] The oxide semiconductor OS was grown on the insulator BI under an atmosphere containing gaseous Ar and O2. A polycrystalline target with a composition of Ga:Zn=1:1:1 (atomic ratio) was used. The oxide semiconductor OS film in FIG. Out-of-plane X-ray diffraction spectrum is shown in Fig. 17(B). In fact, the (009) diffraction peak due to the InGaZnO4 crystal is shown in Figure 17(C). The high-resolution TEM image of the cross section of the oxide semiconductor OS shown in Fig. 1 shows that the OS is layered in the direction perpendicular to the substrate. As shown in FIG. 17(D), a structure in which atoms are arranged in a lattice pattern is observed. In the high-resolution TEM image of the surface of S, triangular and hexagonal atomic arrangements are observed. These characteristics indicate that the oxide semiconductor OS is CAAC-IGZO. For reference, Figure 18 shows the single crystalline Indium-Gal The following figure shows a high-resolution TEM image of IGZO (single crystal IGZO). FIG. 18(A) is a high-resolution TEM image of a cross section, and FIG. 18(B) is a high-resolution TEM image of a surface. It is clear that single crystal IGZO and CAAC-IGZO have different structures. do.

[0298] The thickness of the oxide semiconductor OS is 40 nm, and the thickness of the gate insulator GI is 11 nm in terms of equivalent oxide thickness. m, and the thickness of the insulator BI is 390 nm in terms of the oxide film thickness. Figure 19 (A) and (B) show the W island = 47 nm, L ch =56nm I in a transistor d -V d Characteristics and I d -V g The characteristics are as follows. d teeth Transistor drain current, V d is the drain voltage, V g indicates the gate voltage, In addition, Fig. 19(A) and (B) show the median values ​​of the nine samples measured. The output characteristics are good, and V g =3V, V dOn current at 1V is 58μA / μm. The transistor characteristics are normally off. The off-current is the same as that of a normal semiconductor. The turn-on voltage V turn-on (I d V at =1pA g ) and V for 9 samples of SS d dependence Figure 20 shows the excellent subthreshold characteristics despite the short channel. That is, DIBL (Drain Induced Barrier ier Lowering) and SS(Subthreshold swing value e) has a median value of 67mV / V and 92mV / dec(V d =1V).

[0299] This is because the channel width is sufficiently narrow, so the channel In fact, as shown in Figures 21 and 22, when the channel width is large, As the channel length L ch 5 V with the channel width fixed at 6 nm d I at 1 V d -V g The characteristics are shown in Figure. Figure 22 shows the channel width dependence of turn-on voltage and SS. As the channel width increases, , SS increases and the turn-on voltage shifts in the negative direction. Conversely, isl and Below 100 nm, the characteristic values ​​begin to saturate.

[0300] The reason why SS improves with the reduction in channel width is discussed using device calculations. 3D device calculations were performed using Opsys' Sentaurus. Device structure The structure mimics the fabricated s-channel CAAC-IGZO transistor. Figure 30(A) and (B) show the W island = 50 nm and 90 nm, L ch = Electron current density in the active layer at a cross section along the channel width of a 56 nm transistor The active layer corresponds to an oxide semiconductor. g is -1V, V d was set to 1V. As shown in FIG. 30(B), island The 90 nm transistor has a gate electrode It can be seen that the electron current density is larger on the back channel side of the active layer, which is far from the junction. On the other hand, as shown in FIG. island The 50 nm transistor is back-channel The electron current density on the W channel side is greatly reduced. island Narrow the This allows for greater control of the electron current density on the back channel side. I can say it has improved.

[0301] The results of 3D device calculations for a case where the top edge of the active layer is rounded are shown in Fig. 31(A) and As a result, in a device structure with a narrow channel width, the As shown in Fig. 24, the short channel effect is reduced. Then, the channel length L ch V d I at 1 V d -V g The characteristics are shown in Figure 24. Turn-on voltage and SS channel length L ch The channel width is set to 47 nm. When fixed, the channel length L chResults up to 56 nm show degradation of characteristics due to short channel effects is rarely seen.

[0302] In Figure 32, there are two types of transistors (in the figure, they are called Transistor A and Transistor B). The drain current I d The channel length L ch The drain current I d V d =1V , V g = 2.7V. The channel width is about 50nm. Transistor A is shown in Figure 23. d -V g Transistor B is a transistor that has the same characteristics as Compared to Transistor A, this transistor has thicker source and drain electrodes. The drain current I d The average value of six samples was used. From Figure 32, In both transistors, the drain current I d is the channel length L ch Increased with the shrinkage of It is confirmed that the drain current I d is the drain of transistor A. In current I d and the channel length L ch The increase is due to the shrinkage of the This is because the thickness of the source and drain electrodes is increased. This is because the resistance value of the electrodes is reduced.

[0303] In Figure 33, V d = 1V, V g = 2.7V (in the figure, the on-current I on and (description) and V d = 1V, V g = 0V (in the figure, the off-current I off And The data is shown in Figure 23. d -V g Obtained from a transistor with characteristics From Figure 33, V d = 1V, V g The drain current at V = 0V is d = 1V, V g = 2.7V, the lower limit of measurement is 10 -13 A or lower, low It was confirmed that the value was high.

[0304] Figure 25 shows an application example of an s-channel CAAC-IGZO transistor. The memory circuit shown in FIG. 25 is a memory circuit including a Si transistor and an s-ch The capacitor has a CAAC-IGZO transistor and a capacitance element Cs. The capacitance of element Cs is 14 fF.

[0305] In FIG. 25, the source electrode of the Si transistor is electrically connected to a source line SL. The drain electrode is electrically connected to the bit line RBL. The gate electrode of the C-IGZO transistor is electrically connected to the word line WWL, and the source One of the electrodes or drain electrodes is electrically connected to the bit line WBL. The gate electrode of the s-channel CAAC-IGZO transistor The other of the source electrode and the drain electrode is electrically connected to one of the electrodes of the capacitance element Cs. The other electrode of the capacitance element Cs is electrically connected to the word line RWL.

[0306] W island = 64 nm, L ch =68nm s-channel CAAC-IGZ A memory cell using an O transistor was fabricated, and the write time (T wr ite ) was compared. Here, the write time (T write ) is the timing shown in Figure 26 From the timing chart, the word line WWL is changed from a low level potential (L potential) to a high level potential ( H potential), the floating node (FN) potential (V FN ) is the bit line WBL The time required for the potential to reach 90% of the original potential was measured.

[0307] FIG. 26 shows an example of a timing chart for writing to a memory circuit. The word line WBL is set to a high potential (here, 1.1 V) and the word line WWL is set to a high potential (here, 3 V). Then, the s-channel CAAC-IGZO transistor turns on and the bit line When the WBL and one of the electrodes of the capacitance element Cs are electrically connected, the potential of one of the electrodes of the capacitance element (the potential of FN V FN ) approaches the potential of the bit line WBL, and writing is performed. When the voltage drops to 0 V, the s-channel CAAC-IGZO transistor turns off. Then, the bit line WBL goes to the L potential (0V in this case). In a write operation, the word line RWL is at an L potential (here, 0 V), and the source line SL is at an L potential. The potential is set to H (here, 1.1 V), and the bit line RBL is set to H potential (here, 1.1 V).

[0308] FIG. 27 shows the write time and the potential of one of the electrodes of the capacitance element (the potential V FN ) relationship. As shown in Figure 27, the write time is 60ns in the actual measurement and 50ns in SPICE. It was confirmed that the results were generally consistent.

[0309] In addition, in Fig. 28, the s-channel CAAC-IGZO transistor and W=9 Writing when the storage capacitance value is set to 0 nm and L=45 nm for a Si transistor The time variation was confirmed using SPICE. s-channel CAAC-IGZO The write time T for a Si transistor is about 30 times longer than that for a write The difference between However, the off-current of the s-channel CAAC-IGZO transistor was g When is 0V, it is 10 -19 The storage capacitance is estimated to be less than 1fF, and the lead of the FN node is If a voltage drop of 0.1 V due to the capacitance is allowed, the retention time will be longer than 1,000 s. In this case, the write time is less than 5 ns.

[0310] FIG. 29(A) shows the relationship between time at room temperature and the potential of one of the electrodes of the capacitance element (the potential V FN ) relationship between the potential V FN The data retention period will be the period until the data falls by 10%. As shown in Figure 29(A), the actual measurement shows that the 5 Data up to s (3.5 days) I found I could keep it.

[0311] Also, in FIG. 29(B), the potential V FN , the bit line RBL and the source line SL The relationship between the current flowing between and the potential V of FN is shown below. FN is s-channel The CAAC-IGZO transistor is turned on, and the potential applied to the bit line WBL is changed. The potential V FN Between the change in and the current, there is a potential V F NA positive correlation was observed in the range from 0V (strictly speaking, about 0.02V) to 1.1V. Therefore, by monitoring the above current, Retained data (potential V FN ) can be read out.

[0312] These characteristics can be applied to high-speed, low-power LSIs, especially to memory. is possible. EXAMPLES

[0313] In this example, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0314] A detailed investigation into the characteristics of miniaturized s-channel CAAC-IGZO transistors This is very important for applications to LSIs, etc. Therefore, We fabricated s-channel CAAC-IGZO transistors with a channel length of 50 nm. We fabricated these transistors and compared their current characteristics to investigate the effect of the s-channel structure.

[0315] The structure of the fabricated s-channel CAAC-IGZO transistor is shown in Figure 16(A). 16(A) and 16(B) are the same as the schematic diagram and plan view of the transistor shown in FIG. The explanation in 16(B) can be referred to as appropriate. s-channel CAAC-IGZ The O transistor has a top-gate, top-contact structure, and the gate electrode GE is The electrode ME that constitutes the electrode and drain electrode overlaps the channel side. The gate electrode GE provided on the surface covers a part of the side wall of the insulator BI under the oxide semiconductor OS. As shown in FIG. 16(B), the channel length L chis the distance between the electrodes ME, Channel width W island represents the width of the oxide semiconductor OS.

[0316] The fabrication process is as follows: An oxide semiconductor OS is formed on an insulator BI formed on a Si substrate. A 15 nm film was formed using a DC sputtering system. The target was In:Ga:Zn=1: A polycrystalline target with a composition of 1:1 (atomic ratio) was used. The deposition conditions were Ar The atmosphere contained oxygen and O2, and the substrate temperature during film formation was 300°C. The oxide semiconductor film formed under these conditions was subjected to structural analysis using an XRD device and high-resolution TEM. Observation confirmed that the film was CAAC-IGZO. AAC-IGZO islands are formed, and then the source and drain electrodes are formed by CA The AC-IGZO island was then formed on top of the island. A gate electrode made of metal and a gate insulator made of silicon were formed.

[0317] Figure 34(A) and (B) show the characteristics of s-channel CAAC-IGZO transistors. Cross-sectional STEM images in the channel length direction and channel width direction are shown in Figure 34(A) and (B), respectively. It is clear that the desired structure is obtained.

[0318] In Figure 35(A), island = 110 nm, L ch = 51 nm s-channel CAAC-IGZO transistor V d I at 0.1 V and 1 V d -V g Special In Figure 35(B), island = 50 nm, L ch =51nm s-ch V of the annular CAAC-IGZO transistord I at 0.1 V and 1 V d -V g From Figure 35(A), W island When is as wide as 110 nm, V d As I gets larger, d -V g The characteristics shift toward the negative gate voltage, which is the DIBL effect. In this case, the DIBL is 0.59 V / V. On the other hand, as shown in Figure 35(B), W island When is as narrow as 50 nm, V d Even if I becomes larger d -V g Characteristics of the game The negative shift in the output voltage is small, and it can be seen that the DIBL effect is suppressed. In this case, the DIBL is small at 0.14 V / V.

[0319] The reason for this is as follows. The distance at which the potential in the channel is affected by the drain electric field The distance is called the natural length and is expressed by equation (1).

[0320]

number

[0321] Here, λ n is the natural length, ε act is the relative dielectric constant of the active layer, ε ox is the relative dielectric constant of the gate insulator , t act is the thickness of the active layer, t ox is the thickness of the gate insulator. n is the thickness of the It represents the effective number of gates. The conductive layer is an oxide semiconductor in the s-channel CAAC-IGZO transistor. For example, a transistor having a single gate (single-gate structure) In a transistor with two gates sandwiching a semiconductor, n is 1. In a dual-gate transistor (also called a dual-gate structure), n is 2. A transistor with a gate that covers the entire direction (also called a tri-gate structure). In this case, n is 3. A transistor ( In a quadruple gate structure, n is 4. n The shorter the drain electric field This means that the effect of the potential in the channel is small. In CAAC-IGZO transistors, W island When is wide, the upper surface of the channel The contribution of the gate electrode is dominant, and n in equation (1) is close to 1. On the other hand, W island It's narrow Then, the contribution of the gate electrode on the side of the channel also increases, so that n in equation (1) approaches 3, λ n Therefore, W island It is said that DIBL has improved by narrowing It is possible.

[0322] In Figure 36, L ch is 51 nm, W island Multiple s-chans with various values ​​of I of nel CAAC-IGZO transistor d -V g Characteristics are shown. V d is 1V. In addition, the field-effect mobility μ in the linear region calculated from equation (2) FE_lin Also shown.

[0323]

number

[0324] Here, g m I d-V g Transconductance obtained from the characteristics, C ox is the gate insulation The volume of the body is compared. island 50nm, 90nm, 210nm, 510n m.

[0325] First, let us focus on the region in which the switch is off. From FIG. 36, we can see that W island As the area becomes narrower, SS improved, W island At 50 nm, SS is 103 mV / dec. On the other hand, W island Although widening the gate voltage worsens the SS, If the measurement is increased to 10 -13 In particular, the off-state current of W island When the gate width is 50 nm and 90 nm, the normally-off characteristic is also satisfied.

[0326] For example, W island For =510 nm, V g If is less than -1.5V, 10 - 13 An off-state current of less than W A has been obtained. island 50nm and 90nm In the case of V g If is less than 0V, 10 -13 An off-state current of less than A was obtained.

[0327] The reason why SS improves with the reduction in channel width is discussed using device calculations. 3D device calculations were performed using Opsys' Sentaurus. Device structure The structure mimics the fabricated s-channel CAAC-IGZO transistor. Figure 37(A) and (B) show the W island = 50 nm and 90 nm, L ch= Electron current density in the active layer at a cross section along the channel width of a 51 nm transistor The active layer corresponds to an oxide semiconductor. g is -1V, V d was set to 1V. Figure 3 As shown in 7(B), island A 90 nm transistor has a gate electrode far away from the It can be seen that the electron current density on the back channel side of the active layer is large. As shown in FIG. island The 50 nm transistor has a back channel. The electron current density on the W side is greatly reduced. island To narrow This improves the controllability of the electron current density on the back channel side. As a result, SS is improved. It can be said that it did.

[0328] Next, we focus on the region in which the device is in the on state. FE_lin is originally independent of channel width However, W island The reason for this is that W i sland As the channel size decreases, the contribution of the current flowing on the side of the channel becomes smaller than the current flowing on the top of the channel. This is because it has become larger with respect to W island The reduction in size of transistors It is possible to increase the current that can flow per one. In other words, the W of the s-channel structure island By narrowing the gap, it is possible to improve the on-current characteristics.

[0329] As described above, narrowing the channel width improves the DIBL, SS, and on-current characteristics. The reason for this is that island As the channel shrinks, This is because the contribution of the gate electrode on the side of the channel becomes large. In CAAC-IGZO transistors, W island By narrowing the channel length, Even in the microscopic region of 0 nm level, the device is normally off, and in the region where it is in the off state, the small S S and a small off-state current are obtained, and in the on-state region, excellent on-state current characteristics are obtained. By utilizing these characteristics, it is possible to realize something that cannot be achieved with Si-LSI. This may enable the realization of LSIs and other devices with low power consumption. EXAMPLES

[0330] In this example, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0331] A detailed investigation into the characteristics of miniaturized s-channel CAAC-IGZO transistors This is very important for LSI applications. We fabricated an s-channel CAAC-IGZO transistor with a channel length of 100 nm. The stability of the channel structure was investigated. The fabrication process was the same as in Example 2. The oxide semiconductor OS is deposited at 15 nm, and the gate insulator GI is deposited at 9.5 nm in equivalent oxide thickness. The film was used.

[0332] Figures 41, 42, and 43 show 234 s-channel C AAC-IGZO transistor, I d -V g Cumulative frequency of threshold Vth obtained from characteristics The size of the transistor in Figure 41 is W island = 54 nm, L ch =1 The measurement conditions were: V d = 1V. The size of the transistor in Figure 42 is , W island= 54 nm, L ch = 518 nm, and the measurement conditions were V d =1V The size of the transistor in Figure 43 is W island = 94 nm, L ch =118 nm, and the measurement conditions were V d = 1V. From Figures 41 to 43, The Vth characteristic variation (σVth) of the CAAC-IGZO transistors in By using CAAC-IGZO in transistors, the on-state current was high and the low Not only does it have excellent transistor characteristics such as low SS and extremely low off-state current, It was confirmed that the transistor characteristics were stable and had little variation. By combining these features and the features obtained in other embodiments, It is possible to stably manufacture LSIs for low power consumption that cannot be realized with Si-LSIs. It is possible. [Explanation of symbols]

[0333] 10 Electron Gun Room 12 Optical system 14 Sample Room 16 Optical system 18 Camera 20 Observation Room 22 Film Room 24 electronic 28 Substance 32 Fluorescent Screen 101 Transistor 102 Transistor 103 Transistor 110 Substrate 120 Insulator 130 Oxide Semiconductors 131 Oxide Semiconductors 132 Oxide Semiconductors 133 Oxide Semiconductors 140 Source Electrode 150 Drain electrode 160 Gate insulator 170 Gate electrode 172 Conductors 180 Insulator 185 Insulators 191 areas 192 areas 200 Semiconductor device 201 Memory circuit 202 Memory circuit 203 Memory circuit 204 Circuit 209 Transistor 210 Transistor 212 Transistor 213 Transistor 215 Transistor 217 Transistor 218 Transistor 219 Capacitive element 220 Capacitive element 240 Wiring 241 Wiring 242 Wiring 243 Wiring 244 Wiring 300 Semiconductor device 301 CPU cores 302 Power Controller 303 Power Switch 304 Cache 305 Bus Interface 306 Debug Interface 307 Control Device 308 PC 309 Pipeline Registers 310 Pipeline Registers 311 ALU 312 Register File 321 Power Management Unit 322 Peripheral Circuits 323 Data Bus 402 Insulator 404 Conductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 408 Insulator 412 Insulators 413 Conductors 416 Conductors 416a Conductor 416b Conductor 417 Conductors 418 Insulator 426 Mask 436a Semiconductors 436b Semiconductors 442 Insulator 490 Transistors 750 Interposer 751 Chips 752 Terminal 753 Molding resin 800 Panels 801 Printed Wiring Board 802 Package 803 FPC 804 Battery 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 2100 Transistor 2200 Transistor 2201 Insulators 2202 Wiring 2203 Plug 2204 Insulators 2205 Wiring 2206 Wiring 2207 Insulators 2208 Blocking membrane 2211 Semiconductor substrate 2212 Insulators 2213 Gate electrode 2214 Gate insulator 2215 Source and drain regions 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element

Claims

1. A first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, A semiconductor device, wherein a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a first insulating layer having a region located above a gate electrode of the first transistor; a first conductive layer having a region in contact with an upper surface of the first insulating layer; a second insulating layer having a region located above the first insulating layer and a region located above the first conductive layer; a third insulating layer having a region located above a gate electrode of the second transistor; a second conductive layer having a region in contact with an upper surface of the third insulating layer; a gate electrode of the first transistor is located above a channel formation region of the first transistor; a gate electrode of the second transistor is located above a channel formation region of the second transistor; a gate electrode of the second transistor is electrically connected to a gate electrode of the first transistor via the first conductive layer and the second conductive layer.

2. A first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, A semiconductor device, wherein a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a first insulating layer having a region located above a gate electrode of the first transistor; a first conductive layer having a region in contact with an upper surface of the first insulating layer; a second insulating layer having a region located above the first insulating layer and a region located above the first conductive layer; a third insulating layer having a region located above a gate electrode of the second transistor; a second conductive layer having a region in contact with an upper surface of the third insulating layer; a gate electrode of the first transistor is located above a channel formation region of the first transistor; a gate electrode of the second transistor is located above a channel formation region of the second transistor; a gate electrode of the second transistor is electrically connected to a gate electrode of the first transistor via the first conductive layer and the second conductive layer; The second conductive layer has a region overlapping with the first conductive layer.

3. A first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, A semiconductor device, wherein a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a first insulating layer having a region located above a gate electrode of the first transistor; a first conductive layer having a region in contact with an upper surface of the first insulating layer; a second insulating layer having a region located above the first insulating layer and a region located above the first conductive layer; a third insulating layer having a region located above a gate electrode of the second transistor; a second conductive layer having a region in contact with an upper surface of the third insulating layer; a gate electrode of the first transistor is located above a channel formation region of the first transistor; a gate electrode of the second transistor is located above a channel formation region of the second transistor; a gate electrode of the second transistor is electrically connected to a gate electrode of the first transistor via the first conductive layer and the second conductive layer; the second conductive layer has a region overlapping with the first conductive layer and a region overlapping with a gate electrode of the first transistor.

4. A first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, A semiconductor device, wherein a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a first insulating layer having a region located above a gate electrode of the first transistor; a first conductive layer having a region in contact with an upper surface of the first insulating layer; a second insulating layer having a region located above the first insulating layer and a region located above the first conductive layer; a third insulating layer having a region located above a gate electrode of the second transistor; a second conductive layer having a region in contact with an upper surface of the third insulating layer; a gate electrode of the first transistor is located above a channel formation region of the first transistor; a gate electrode of the second transistor is located above a channel formation region of the second transistor; a gate electrode of the second transistor is electrically connected to a gate electrode of the first transistor via the first conductive layer and the second conductive layer; the first conductive layer has a region overlapping with a gate electrode of the second transistor.

Images