Semiconductor device

Abstract

To solve a problem of increase in the number of pixels associated with high definition of a display device to cause increase in the number of gate lines and the number of signal lines; when the number of gate lines and the number of signal lines increase, it becomes difficult to mount, by bonding and the like, an IC chip which has a drive circuit for driving the number of gate lines and the number of signal lines thereby to increase manufacturing cost.SOLUTION: A semiconductor device comprises a pixel part and a drive circuit for driving the pixel part on the same substrate, in which at least a part of the drive circuit is constituted by a thin film transistor using an oxide semiconductor sandwiched by gate electrodes vertically. The semiconductor device comprises a channel protection layer provided between the oxide semiconductor and the gate electrode provided above the oxide semiconductor. By providing the pixel part and the drive circuit on the same substrate, manufacturing cost is reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates They are made of amorphous silicon and polycrystalline silicon. Thin-film transistors using GaN have low field-effect mobility, but they are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using polycrystalline silicon have a field effect mobility of Although it is expensive, it requires a crystallization process such as laser annealing, which is necessary for enlarging the area of ​​glass substrates. It has the characteristic that it is not necessarily suitable for all applications.

[0003] In response to this, thin-film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-GaAs films are used as oxide semiconductors. Thin-film transistors are fabricated using a-Zn-O oxide semiconductors, and used as switches for image display devices. Technologies used in switching elements and the like are disclosed in Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-096055 A Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors with a channel formation region in an oxide semiconductor are made of amorphous silicon. The oxide semiconductor film has a higher field effect mobility than the thin film transistors that use the oxide semiconductor film. Film formation is possible at temperatures below 300℃ using methods such as sputtering, and polycrystalline silicon The manufacturing process is simpler than that of thin film transistors using

[0006] Using such oxide semiconductors, thin film transistors can be formed on glass substrates, plastic substrates, etc. The display is then used for a liquid crystal display, an electroluminescent display, electronic paper, or the like. It is expected that this technology will be applied to display devices.

[0007] In addition, when the display area of ​​a display device is enlarged, the number of pixels increases, and the number of gate lines and signal lines also increases. In addition, as display devices become more highly precise, the number of pixels increases, and the number of gate lines and signal As the number of gate lines and signal lines increases, the number of drivers required to drive them also increases. It has become difficult to mount IC chips with operating circuits by bonding, etc., and manufacturing costs have increased. The number of cases increases.

[0008] Therefore, a thin film transistor using an oxide semiconductor is used for at least a part of a driver circuit for driving a pixel portion. One object is to reduce manufacturing costs by using transistors.

[0009] At least a part of the driving circuit for driving the pixel section is made of a thin-film transistor using an oxide semiconductor. When using a thin-film transistor, the transistor must have high dynamic characteristics (on-state characteristics and frequency characteristics (f The thin film transistor with high dynamic characteristics (on-state characteristics) is required. It is another object of the present invention to provide a driver circuit that can be driven at high speed.

[0010] In addition, one embodiment of the present invention is a thin film transistor having high reliability, in which an oxide semiconductor layer is used for a channel. It is an object of the present invention to provide a semiconductor device including a first insulating film. [Means for solving the problem]

[0011] Gate electrodes are provided above and below the oxide semiconductor layer, improving the on-state characteristics and reliability of the thin film transistor. Achieve the above.

[0012] In addition, the threshold voltage can be controlled by controlling the gate voltage applied to the upper and lower gate electrodes. The upper and lower gate electrodes may be electrically connected to each other to have the same potential. The gate electrodes may be connected to separate wirings to have different potentials. By applying a voltage to one side to control the threshold voltage, the threshold voltage can be set to zero or By moving the driving voltage closer to the threshold voltage, the power consumption can be reduced. By applying a positive voltage, the transistor can function as an enhancement type transistor. It is also possible to make the transistor function as a depletion type transistor by making the threshold voltage negative.

[0013] For example, a combination of enhancement and depletion type transistors An inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured and used in a drive circuit. The driving circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section is configured to include the above EDMOS circuit. It is preferable to use a thin film transistor capable of passing a large on-current for the depth portion. A recessed type transistor or a thin film transistor having gate electrodes above and below an oxide semiconductor layer. A transistor is used.

[0014] Fabricate thin-film transistors with different structures on the same substrate without significantly increasing the number of processes For example, a driving circuit for high-speed operation can be provided with gate electrodes above and below the oxide semiconductor layer. The EDMOS circuit is made up of thin-film transistors with electrodes, and the pixel section is made up of oxide semiconductor A thin film transistor having a gate electrode only below the body layer may be used.

[0015] When the threshold voltage of the n-channel TFT is positive, it is called an enhancement type transistor. When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition will be followed throughout the specification.

[0016] In addition, the material of the gate electrode provided above the oxide semiconductor layer is not particularly limited as long as it is a conductive film. Not specified, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), W, Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium The element selected from the group consisting of Sc, Cr, and Cr, or an alloy containing the above-mentioned elements is used. The gate electrode is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. Cut.

[0017] In addition, the gate electrode provided above the oxide semiconductor layer is made of the same material as the pixel electrode (transparent In the case of a transmission type display device, a transparent conductive film, etc. can be used. For example, In the same process as the process of forming the pixel electrode electrically connected to the thin film transistor, the oxide The gate electrode can be formed above the semiconductor layer. This greatly reduces the process. Without increasing the number of layers, a thin-film transistor with gate electrodes above and below the oxide semiconductor layer was formed. In addition, by providing a gate electrode above the oxide semiconductor layer, Bias-thermal stress test (hereinafter referred to as BT test) for investigating the reliability of thin-film transistors The change in the threshold voltage of a thin-film transistor before and after BT stress was measured. That is, by providing a gate electrode above the oxide semiconductor layer, , the reliability can be improved.

[0018] One of the configurations of the invention disclosed in this specification is a first gate electrode on an insulating surface. A first insulating layer is disposed above the gate electrode, an oxide semiconductor layer is disposed above the first insulating layer, and a A channel protection layer in contact with the oxide semiconductor layer, a source electrode or a drain electrode above the oxide semiconductor layer, and A second insulating layer is provided covering the source electrode or the drain electrode, and a second gate electrode is provided above the second insulating layer. and a second insulating layer in contact with the channel protection layer. do.

[0019] The above configuration solves at least one of the above problems.

[0020] In the above structure, the width of the second gate electrode is made wider than the width of the oxide semiconductor layer. A gate voltage can be applied to the entire oxide semiconductor layer from the second gate electrode.

[0021] Alternatively, in the above configuration, the width of the first gate electrode is narrower than the width of the second gate electrode. By doing so, the area overlapping with the source electrode or drain electrode is reduced, thereby reducing the parasitic capacitance. Furthermore, the width of the first gate electrode is wider than the width of the channel protection layer. The width of the gate electrode of 2 is made narrower than the width of the channel protection layer, so that the source electrode or It may be configured so as not to overlap with the rain electrode to further reduce parasitic capacitance.

[0022] In the above structure, a barrier layer is provided between the source electrode or the drain electrode and the oxide semiconductor layer. By providing a buffer layer, the source electrode (or drain electrode) Contact resistance between the oxide semiconductor layer and the insulating film can be reduced.

[0023] In addition, the configuration of another invention has a pixel section and a driving circuit, and the pixel section has at least a first oxide The driving circuit includes a first thin film transistor having a second oxide semiconductor layer. a second thin film transistor having a second oxide semiconductor layer and a third thin film transistor having a third oxide semiconductor layer. a third thin film transistor having a third oxide A first gate electrode is disposed below the oxide semiconductor layer, and a source electrode or The third oxide semiconductor layer has a drain electrode and a second gate electrode above the third oxide semiconductor layer. The oxide semiconductor layer has a channel protection layer between the second gate electrode and the channel protection layer. It is a semiconductor device in contact with the

[0024] In the above-mentioned structure, the first thin film transistor of the pixel portion is electrically connected to the pixel electrode, The electrode is made of the same material as the second gate electrode of the driver circuit, so that the number of processes is not increased. It can be made.

[0025] In the above-mentioned structure, the first thin film transistor of the pixel portion is electrically connected to the pixel electrode, The electrode is made of a material different from that of the second gate electrode of the driving circuit. For example, the pixel electrode is made of a transparent conductive film. By forming the second gate electrode of the driving circuit using an aluminum film, It is possible to reduce the resistance.

[0026] In the above structure, a semiconductor device having a source electrode or a drain electrode and a third oxide semiconductor layer By providing a buffer layer, the source electrode (or drain electrode) In this way, the contact resistance between the oxide semiconductor layer and the electrode can be reduced.

[0027] In addition, the third thin film transistor of the driving circuit has a third oxide semiconductor layer interposed between the first insulating layer and the third oxide semiconductor layer. and overlapping the first gate electrode via the second insulating layer and the second gate electrode via the second insulating layer. This is a so-called dual gate structure.

[0028] In addition, the first gate electrode and the second gate electrode are electrically connected to each other and set to the same potential. A gate electrode is provided from above and below to an oxide semiconductor layer disposed between the first gate electrode and the second gate electrode. Pressure can be applied.

[0029] In addition, when the first gate electrode and the second gate electrode are set to different potentials, the electric potential of the TFT is Properties such as threshold voltage can be controlled.

[0030] In addition to liquid crystal display devices, semiconductor devices having driver circuits include light emitting devices using light emitting elements. Examples of such display devices include optical display devices and display devices that use electrophoretic display elements and are also called electronic paper. do.

[0031] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0032] In a light-emitting display device using a light-emitting element, a pixel portion has a plurality of thin film transistors. In the elemental portion, the gate electrode of a thin film transistor and the source wiring of another transistor, The gate insulating film 10 has a portion for electrically connecting a drain wiring.

[0033] In addition, since thin-film transistors are easily damaged by static electricity, etc., It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the line. is preferably configured using a nonlinear element using an oxide semiconductor.

[0034] The oxide semiconductor used in this specification is InMO3(ZnO). m Thin, expressed as (m>0) A thin film is formed and a thin film transistor is fabricated using the thin film as the semiconductor layer. , Ga, Fe, Ni, Mn, and Co. For example, M can be Ga (gallium), Ga and Ni, or Ga and Fe. In addition, the oxide semiconductor may contain the above-mentioned metal elements other than Ga. In addition to the metal elements contained as M, Fe, Ni and other transition metal elements are included as impurity elements. In the present specification, the thin film Among these, those containing Ga as M are also called In-Ga-Zn-O based non-single crystal films.

[0035] The crystal structure of the In-Ga-Zn-O non-single crystal film is formed by sputtering and then heated at 200°C to 500℃, typically 300 to 400℃ for 10 to 100 minutes, the amorphous structure is observed in the XRD analysis.

[0036] Oxide semiconductors, such as In-Ga-Zn-O non-single crystal films, have an energy gap ( Since the oxide semiconductor layer has a wide Eg, even if two gate electrodes are provided above and below the oxide semiconductor layer, the off-state The increase in current can be suppressed.

[0037] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the

[0038] In addition, terms expressing degree as used in this specification, such as "roughly," "almost," and "degree" etc. are reasonable deviations from the terms that have been somewhat altered so that the end result does not change noticeably. These terms include any somewhat modified terms with a deviation of at least ±5%. should be interpreted as such, but this deviation does not negate the meaning of the term which is somewhat altered. This is subject to the conditions. Effect of the Invention

[0039] Peripheral circuits such as gate line driver circuits or source line driver circuits, or pixel sections, By forming a thin film transistor using an oxide semiconductor between the gate electrodes, Reduce manufacturing costs.

[0040] In addition, a thin-film transistor using an oxide semiconductor sandwiched between two gate electrodes on the top and bottom In the BT test, the change in the threshold voltage of the thin film transistor before and after BT stress was In other words, the oxide semiconductor sandwiched between two gate electrodes on the top and bottom can be reduced. The reliability can be improved by using thin film transistors. [Brief description of the drawings]

[0041] [Figure 1] FIG. 2A is a cross-sectional view showing an example of the display device according to the first embodiment; FIG. 2B is a cross-sectional view showing another example of the display device according to the first embodiment; and FIG. [Diagram 2] 1A is a cross-sectional view of a semiconductor device according to a second embodiment, FIG. 1B is an equivalent circuit diagram, and FIG. [Diagram 3] FIG. 11 is a block diagram illustrating a display device according to a third embodiment. [Figure 4] 13 illustrates an arrangement of wiring, input terminals, and the like in a display device of Embodiment 3. [Diagram 5] FIG. 2 is a block diagram illustrating a configuration of a shift register circuit. [Figure 6] FIG. 1 illustrates an example of a flip-flop circuit. [Figure 7] FIG. 1 shows a layout diagram (top view) of a flip-flop circuit. [Figure 8] FIG. 4 is a timing chart for explaining the operation of the shift register circuit. [Figure 9] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 10] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 11] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 12] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 13] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 14] 10A to 10C illustrate a semiconductor device of Embodiment 4. [Figure 15] 10A to 10C illustrate a semiconductor device of Embodiment 4. [Figure 16] 10A to 10C illustrate a semiconductor device of Embodiment 4. [Figure 17] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 13 illustrates a pixel equivalent circuit of the semiconductor device of Embodiment 6. [Figure 19] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment. [Figure 20] 13A and 13B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 7. [Figure 21] 13A and 13B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 6. [Figure 22] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment. [Figure 23] FIG. 1 is an external view showing an example of an electronic device. [Figure 24] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Diagram 25] FIG. 1 is an external view showing an example of a mobile phone. [Figure 26] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] The embodiments are described below.

[0043] (Embodiment 1) FIG. 1A shows a thin film transistor 430 used in a driver circuit and a second thin film transistor 430 used in a pixel portion. An example in which a transistor 170 is provided on the same substrate is shown. Note that FIG. 1A is a cross-sectional view of a display device. FIG.

[0044] The pixel section and the driver circuit are formed on the same substrate. The pixel electrode is formed using the second thin film transistor 170, which is an enhancement type transistor. The voltage applied to the second thin-film transistor 110 is switched on and off. The gate 170 uses an oxide semiconductor layer 103 and has an on-off ratio of 10 9 Because that's all This improves display contrast and reduces power consumption due to low leakage current. The on-off ratio is the ratio of the off current to the on current (I ON / I OFF ) and the larger it is, the better the switching characteristics are, and the better the display contrast is. The on-state current is the current that flows between the source electrode and the The off-state current is the current that flows between the drain electrode and the transistor. Sometimes, this refers to the current that flows between the source and drain electrodes. For example, in an n-type transistor, In the case of a transistor, when the gate voltage is lower than the threshold voltage of the transistor, the source electrode and This is the current flowing between the drain electrode and the pixel electrode. This allows for high contrast and low power consumption. In order to realize driving, it is preferable to use an enhancement type transistor in the pixel portion. In addition, 101 is a gate electrode, 104a and 104b are a source region and a drain region, Reference numeral 105a denotes a first electrode, 105b denotes a second electrode layer, and 107 denotes a protective insulating layer.

[0045] In the driver circuit, a first gate electrode 401 and an oxide semiconductor layer 405 are provided below the oxide semiconductor layer 405. A thin film transistor having an electrode 470 functioning as a second gate electrode above the semiconductor layer 405. At least one transistor 430 is used. The electrode 47 functions as the second gate electrode. 0 can also be called a back gate electrode. By forming a back gate electrode, Bias-thermal stress test (hereinafter referred to as BT test) is used to check the reliability of transistors. In the present invention, the change in the threshold voltage of a thin film transistor before and after BT stress is reduced. It is possible.

[0046] The structure of the thin film transistor 430 will be described with reference to FIG. A first gate electrode 401 provided on a plate 400 is covered with a first gate insulating layer 403. An oxide semiconductor layer 40 is formed on the first gate insulating layer 403 that overlaps the first gate electrode 401. A channel protective layer 418 is provided over the oxide semiconductor layer 405. The first wiring 409 or the second wiring 410 is provided. An insulating layer 412 is provided on and in contact with the wiring 410. A second gate electrode The electrode 470 functions as a

[0047] The material of the first gate insulating layer 403 is an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, etc.). A single layer or a laminated structure made of these materials can be used. The fabrication method is a vapor phase growth method such as plasma CVD or thermal CVD, or sputtering. In this embodiment, the first gate insulating layer is formed by a deposition method. The first layer is a silicon nitride film made by plasma CVD, and the second layer is a silicon oxide film made by plasma CVD. The first layer, a silicon nitride film, is formed on the first gate electrode 401 to prevent hillocks from forming. When using a material that may cause hillocks, it has the effect of preventing the occurrence of hillocks. The silicon nitride film formed by the plasma CVD method is dense and can be used as the first gate insulating film. In addition, the first gate insulating layer is made of nitride. When using a silicon film, impurities from the glass substrate, such as mobile ions of sodium, diffuse into the silicon film. The diffusion of the oxide semiconductor can be prevented by the diffusion of the oxide semiconductor. In either case of a layered structure or a single-layer structure, the first gate insulating layer 403 The film thickness is set to be 50 nm or more and 500 nm or less.

[0048] The oxide semiconductor layer 405 is, for example, In2O3:Ga2O3:ZnO=1:1:1. Using a target (In:Ga:Zn=1:1:0.5), sputtering was performed using argon gas. The film is formed under the conditions of a flow rate of 10 sccm and oxygen of 5 sccm. Therefore, the first gate insulating layer 403 and the oxide semiconductor layer 405 are formed without being exposed to the air. Note that when the oxide semiconductor film is exposed to the air, Before the first gate, argon gas was introduced to generate plasma and reverse sputtering was performed. Dust adhering to the surface of the insulating layer 403 may be removed.

[0049] In addition, a source or drain region 404 is provided between the oxide semiconductor layer 405 and the first wiring 409. 06a is provided between the oxide semiconductor layer 405 and the second wiring 410. The source and drain regions 406a and 406b are provided as channel regions. It is also formed on the protective layer 418. For example, between the channel protective layer 418 and the first wiring 409 A source or drain region 406a is provided. This source or drain region The oxide semiconductor layer can also be regarded as a buffer layer provided between the wiring and the oxide semiconductor layer.

[0050] In this embodiment, the source or drain regions 406a, 406b are In-Ga-Z The oxide semiconductor layer 405 is formed under different conditions from the oxide semiconductor layer 405. For example, the oxide semiconductor layer is formed under the conditions of argon gas by sputtering. The source region or the gate electrode formed of the oxide semiconductor film was obtained under the condition of a nitrogen gas flow rate of 40 sccm. The drain regions 406a and 406b have n-type conductivity and have an activation energy (ΔE In the present embodiment, the source region or the drain region is 0.01 eV or more and 0.1 eV or less. The rain regions 406a and 406b are layers formed of In-Ga-Zn-O based non-single crystal films. The source region or drain region is assumed to contain at least an amorphous component. 406a and 406b may contain crystal grains (nanocrystals) in the amorphous structure. The crystal grains (nanocrystals) in the source and drain regions 406a and 406b have a diameter of It is 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0051] The thin film transistor 430 has a channel protection layer 418 and an insulating layer 412 stacked to form a second gate. It functions as an insulating layer. The material of the channel protection layer 418 is an inorganic material (silicon oxide, nitrogen, etc.). The silicon nitride, silicon oxynitride, silicon nitride oxide, etc. can be used. Vapor phase growth methods such as plasma CVD and thermal CVD, and sputtering methods can be used. In this embodiment, a silicon oxide film obtained by sputtering is used as the channel protection layer 418. There are.

[0052] The insulating layer 412 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, an alumina film, or a silicon oxide film. Aluminum, aluminum nitride, tantalum oxide film, hafnium oxide film, hafnium oxynitride film A single layer or a laminated structure made of these materials can be used. In this embodiment, the insulating layer 412 is a silicon nitride film obtained by a plasma CVD method. The stack of the channel protection layer 418 and the insulating layer 412 functions as a second gate insulating layer. Therefore, the materials and film thicknesses are important for the electrical characteristics of the thin film transistor 430. For example, gate voltages are applied from above and below the oxide semiconductor layer 405 to generate substantially the same electric field. When a semiconductor layer 405 is desired to be formed, a first layer of a silicon nitride film and a silicon oxide film is used. The gate insulating layer of 1, the silicon oxide film (channel protection layer 418) and the silicon nitride film (insulating It is preferable that the thicknesses of the second gate insulating layers (layer 412) are approximately the same. In order to obtain desired electrical characteristics such as a threshold voltage, different gates are formed on the upper and lower sides of the oxide semiconductor layer 405. When a gate voltage is applied to the oxide semiconductor layer 405 to apply a different electric field, By appropriately adjusting the material and thickness of the first gate insulating layer and the second gate insulating layer, a desired The electrical characteristics of the thin film transistor 430 can be obtained.

[0053] The first gate electrode 401 and the electrode 470 functioning as the second gate electrode are electrically connected to each other. When the oxide semiconductor layer is at the same potential, a gate voltage is applied from above and below the oxide semiconductor layer. Since a large current can be applied to the transistor in the on-state, the current that flows can be increased.

[0054] In addition, a control signal line for shifting the threshold voltage to the negative side is connected to the first gate electrode 401. , or the electrode 470 that functions as the second gate electrode. This makes it possible to obtain a depletion type TFT.

[0055] A control signal line for shifting the threshold voltage to the positive side is connected to the first gate electrode 401, Alternatively, it may be electrically connected to either one of the electrodes 470 that functions as the second gate electrode. By this, an enhancement type TFT can be formed.

[0056] In addition, the combination of two thin film transistors used in the driving circuit is not particularly limited. A thin film transistor having a gate electrode is used as a depletion type TFT, and two gates A thin film transistor having a gate electrode may be used as an enhancement type TFT. In this case, the gate electrodes are arranged above and below the oxide semiconductor layer as thin film transistors in the pixel section. The structure shall have each of these.

[0057] In addition, as a thin film transistor in a pixel portion, a gate electrode is provided above and below the oxide semiconductor layer. The gate electrode is made of oxide semiconductor as an enhancement type TFT for the driving circuit. The gate is a depletion type TFT of the driving circuit. A structure in which electrodes are provided above and below the oxide semiconductor layer may be used. A control signal line for controlling the value voltage is electrically connected to either the upper or lower gate electrode. The gate electrode connected thereto controls the threshold voltage.

[0058] In FIG. 1A, the electrode 470 functioning as the second gate electrode is The same material as the pixel electrode 110, for example, a transparent conductive film in the case of a transmission type liquid crystal display device, is used. The number of steps is reduced, but is not particularly limited. The width of the electrode 470 is wider than the width of the first gate electrode 401, and the oxide semiconductor layer 405 In this example, the width of the first gate electrode 401 is wider than that of the first gate electrode 402, but is not limited thereto. It is wider than the width of the channel protection layer 418 (width in the channel direction).

[0059] FIG. 1B shows an example in which the material and width of the second gate electrode are different from those in FIG. 1A. (B) shows a thin film transistor 170 connected to an organic light emitting element or an inorganic light emitting element in a pixel portion. 1 is an example of a display device having

[0060] In FIG. 1B, an electrode functioning as a second gate electrode of the thin film transistor 432 The material of 471 is metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta)). Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (N d), Scandium (Sc), or an alloy containing the above elements. The width of the electrode 471 in the cross section is set to the width of the electrode functioning as the second gate electrode in FIG. The width of the electrode 471 is narrower than that of the oxide semiconductor layer 405. By narrowing the gap, the first wiring 409 and the second wiring 410 are overlapped with the insulating layer 412. This reduces the area of ​​the MOSFET and the parasitic capacitance. ), the width of the electrode 471 is wider than the width of the channel protection layer 418.

[0061] The light-emitting element has at least a first electrode 472, a light-emitting layer 475, and a second electrode 474. In FIG. 1B, the electrode 471 is made of the same material as the first electrode 472 of the pixel portion, for example. The number of steps is reduced by using aluminum or the like, but there is no particular limitation. In B), the insulating layer 473 serves as a partition wall for insulating the first electrodes of adjacent pixels. It functions as such.

[0062] FIG. 1C shows an example in which the material and width of the second gate electrode are different from those in FIG. 1A. In (C), the electrode 47 functions as the second gate electrode of the thin film transistor 433. The material of 6 is metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) , scandium (Sc), or an alloy containing the above elements. The width of the second gate electrode in cross section is narrower than that in FIG. 1(B). By narrowing the width of the first wiring 409 and the second wiring 410, the insulating layer 412 is formed between the first wiring 409 and the second wiring 410. This can prevent overlapping and further reduce parasitic capacitance. The width of the electrode 476 shown in FIG. 4C is narrower than the width of the channel protection layer 418. When forming the electrode 476, the resist mask edge is etched by wet etching or the like. It is preferable to perform the step of positioning both ends of the electrode 476 on the inner side of the ) uses a metal material different from that of the pixel electrode 110, so This will add one photolithography process and one mask.

[0063] A gate line driver circuit or a source line driver circuit used in a liquid crystal display device, a light-emitting display device, or electronic paper The oxide film sandwiched between two gate electrodes on the top and bottom of the peripheral circuits such as the driving circuits or the pixel section is By using thin film transistors made of solid semiconductors, high speed operation and low power consumption can be achieved. In addition, both the pixel section and the driver circuit can be formed on the same substrate without significantly increasing the number of processes. By providing various circuits other than the pixel portion on the same substrate, the display This allows for a reduction in the manufacturing costs of the display device.

[0064] (Embodiment 2) In the first embodiment, one thin film transistor is described as the thin film transistor of the driving circuit. However, in this example, two n-channel thin film transistors are used to form the inverter circuit of the driver circuit. The thin film transistor shown in FIG. Since the thin film transistor 430 is the same as that shown in FIG. 1A of the first embodiment, the same parts are used. The explanation will be given using symbols.

[0065] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. When two n-channel TFTs are combined to form an inverter circuit, When forming a combination of ment type transistors and depletion type transistors ( Hereinafter referred to as EDMOS circuit) and enhancement type transistors (hereinafter referred to as EEMOS circuits).

[0066] The cross-sectional structure of the inverter circuit of the driver circuit is shown in FIG. The first thin film transistor 430 is a dual gate type, and the second thin film transistor 431 is a bottom gate type thin film transistor. A semiconductor layer is a thin-film transistor in which wiring is provided via a source region or a drain region on the semiconductor layer. 1 is an example of a thin film transistor.

[0067] In FIG. 2A, a first gate electrode 401 and a gate electrode 402 are provided on a substrate 400. The material of the first gate electrode 401 and the gate electrode 402 is molybdenum, titanium, chromium, or tantalum. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a multilayer structure using a material or an alloy material mainly composed of the material. do.

[0068] For example, the two-layer laminate structure of the first gate electrode 401 and the gate electrode 402 may be made of Al. Two-layer laminate structure with a molybdenum layer on a aluminum layer, or a molybdenum layer on a copper layer or a titanium nitride or tantalum nitride layer on a copper layer. It is preferable to use a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated. A Ca-containing copper oxide layer is laminated on a Ca-containing copper layer to serve as a barrier layer, and a Mg-containing copper layer is laminated on a Mg-containing copper layer. There is also a laminated layer of copper oxide containing Mg as a barrier layer. A layer of tungsten or tungsten nitride and an alloy of aluminum and silicon or an aluminum It is preferable to use a laminated layer in which an alloy layer of aluminum and titanium is laminated with a titanium nitride layer or a titanium layer. I wish.

[0069] Also, on the first gate insulating layer 403 covering the first gate electrode 401 and the gate electrode 402 An oxide semiconductor layer 405 and a second oxide semiconductor layer 407 are provided on the first oxide semiconductor layer 402 .

[0070] A channel protective layer 418 is provided over the oxide semiconductor layer 405. A second wiring 410 is provided. The second wiring 410 is connected to a contact formed in the first gate insulating layer 403. It is directly connected to the gate electrode 402 through a contact hole 404. In the case of the first gate insulating layer 403, the contact hole 404 may be formed after the first gate insulating layer 403 is formed. Alternatively, the contact may be formed after forming the channel protection layer 418 and the second channel protection layer 419. A hole 404 may be formed. A third wiring is provided on the second oxide semiconductor layer 407. 411 shall be established.

[0071] The thin film transistor 430 includes a first gate electrode 401 and a first gate insulating layer 403. The first gate electrode 401 and the oxide semiconductor layer 405 overlap each other. The first wiring 409 This power supply line is a power supply line to which a negative voltage VDL is applied (negative power supply line). It may also be a power line (ground power line).

[0072] The second thin film transistor 431 includes a gate electrode 402 and a first gate insulating layer 40 a second oxide semiconductor layer 407 overlapping the gate electrode 402 via a third wiring 4 Reference numeral 11 denotes a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0073] In addition, between the second oxide semiconductor layer 407 and the second wiring 410, + providing a layer 408a; Between the second oxide semiconductor layer 407 and the third wiring 411, + A layer 408b is provided. Between the channel protection layer 418 and the second wiring 410, a source region or drain region 406 is provided. b is provided between the channel protection layer 418 and the first wiring 409. A drain region 406a is provided.

[0074] FIG. 2C shows a top view of the inverter circuit of the driver circuit. The cross section taken along line Z1-Z2 corresponds to FIG. 2(A).

[0075] The equivalent circuit of the EDMOS circuit is shown in FIG. 2(B). The connection structure shown in FIG. 2(B), the thin film transistor 430 is an enhancement type n-channel transistor. The second thin film transistor 431 is a depletion type n-channel transistor. This is an example of a sta.

[0076] In order to make the thin film transistor 430 an enhancement-type n-channel transistor, In this embodiment, the channel protective layer 418 and the insulating layer 412 are formed over the oxide semiconductor layer 405. An electrode 470 functioning as a second gate electrode is provided on the insulating layer 412. The threshold voltage of the thin film transistor 430 is controlled by applying a voltage to the electrode 470 that functions as an electrode. Perform value control.

[0077] In addition, in FIG. 2A and FIG. 2C, the second wiring 410 is a first gate insulating layer 403. 4 shows an example in which the gate electrode 402 is directly connected to the semiconductor substrate 401 through a contact hole 404 formed in the semiconductor substrate 401. However, this is not particularly limited, and a connecting electrode may be separately provided to connect the second wiring 410 and the gate electrode 402. Electrical connection may also be made.

[0078] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0079] (Embodiment 3) In this embodiment, a display device will be described with reference to block diagrams and the like.

[0080] FIG. 3A shows an example of a block diagram of an active matrix type liquid crystal display device. The liquid crystal display device shown in (A) has a pixel section having a plurality of pixels each having a display element on a substrate 300. 301, a scanning line driving circuit 302 for controlling the scanning lines connected to the gate electrodes of the pixels, and a signal line driver circuit 303 that controls input of a video signal to a selected pixel.

[0081] FIG. 3B shows an example of a block diagram of an active matrix light-emitting display device. The light-emitting display device shown in FIG. 1B has a pixel portion having a plurality of pixels each having a display element on a substrate 310. 311, and a first scanning line driving circuit 31 for controlling the scanning lines connected to the gate electrodes of the pixels. The second and second scanning line driver circuits 313 control the input of video signals to selected pixels. A signal line driver circuit 314 is provided. When two TFTs, a TFT for current control and a TFT for photodiode are arranged, as shown in Fig. 3(B) In the light-emitting display device shown in FIG. 1, a first scanning line The signal to be input to the first scanning line driver circuit 312 is generated by the first scanning line driver circuit 313, and the gate voltage of the current control TFT is A signal to be input to the second scanning line connected to the electrode is generated by the second scanning line driving circuit 313. However, the signal input to the first scanning line and the signal input to the second scanning line are input to the same The scanning line driver circuit may generate the signal. Depending on the number of TFTs, the first scan line used to control the operation of the switching element is In this case, the signals input to the first scanning lines may be All of these may be generated by a single scanning line driving circuit, or multiple scanning line driving circuits may be provided. It may be generated by each of them.

[0082] In this embodiment, the scanning line driver circuit 302, the first scanning line driver circuit 312, the second scanning line A driver circuit 313 and signal line driver circuits 303 and 314 are fabricated in a display device. However, the scanning line driver circuit 302, the first scanning line driver circuit 312, or the second scanning line driver circuit A part of the signal line driver circuit 303, 313 may be implemented as a semiconductor device such as an IC. A part of 14 may be implemented as a semiconductor device such as an IC.

[0083] FIG. 4 shows a signal input terminal 321, a scanning line 323, a signal line 324, and a non-transitory The positional relationship between the protection circuits 334, 335, and 336 including linear elements and the pixel section 327 will be described. On a substrate 320 having an insulating surface, scanning lines 323 and signal lines 324 are arranged to cross each other. The pixel section 327 is configured by placing the pixel section 30 shown in FIG. 1 corresponds to pixel portion 311.

[0084] The pixel section 301 includes a signal line driver circuit 303 and a plurality of signal lines S arranged in a column direction. 1 to Sm (not shown) are connected to the signal line driving circuit 303, and the scanning line driving circuit 302 A plurality of scanning lines G1 to Gn (not shown) are arranged extending in the row direction from the The matrix is ​​connected to the driving circuit 302 and corresponds to the signal lines S1 to Sm and the scanning lines G1 to Gn. Each pixel is connected to a signal line Sj( signal lines S1 to Sm), scanning lines Gi (scanning lines G1 to Gn), ) is connected.

[0085] The pixel section 327 is configured with a plurality of pixels 328 arranged in a matrix. 8 is a pixel TFT 329 connected to the scanning line 323 and the signal line 324, a storage capacitor 330, and a pixel It is configured to include a base electrode 331 .

[0086] In the pixel configuration shown here, the storage capacitor 330 has one electrode and a pixel TFT 329 3 is connected to the pixel electrode 331, and the other electrode is connected to the capacitance line 332. 331 drives display elements (liquid crystal elements, light emitting elements, contrast media (electronic ink), etc.) The other electrodes of these display elements are connected to a common terminal 333. is.

[0087] The protection circuit 335 is disposed between the pixel portion 327 and the signal line input terminal 322 . In addition, the protection circuit 334 is disposed between the scanning line driving circuit and the pixel portion 327. In the embodiment, a plurality of protection circuits are provided to protect the scanning lines 323, the signal lines 324, and the capacitive bus lines 325. 337 is applied with a surge voltage due to static electricity, etc., to prevent the pixel TFT 329 and other components from being destroyed. Therefore, when a surge voltage is applied to the protection circuit, The capacitor is configured to allow electric charge to escape.

[0088] In this embodiment, a protection circuit 334 is provided on the scanning line 323 side, and a protection circuit 33 is provided on the signal line 324 side. 5. An example is shown in which a protection circuit 336 is provided on a capacitive bus line 337. The position of the wiring is not limited to this. In addition, the scanning line driver circuit is not necessarily implemented as a semiconductor device such as an IC. In this case, the protection circuit 334 does not need to be provided on the scanning line 323 side.

[0089] By using the TFTs shown in the first and second embodiments in each of these circuits, , it has the following advantages:

[0090] The driving circuit is roughly divided into a logic circuit section and a switch section or a buffer section. The TFT provided in the switch is preferably configured so that the threshold voltage can be controlled. It is preferable that the TFT provided in the pixel section or the buffer section has a large on-state current. Alternatively, a driver circuit having the TFT shown in the second embodiment may be provided in the logic circuit portion. It is possible to control the threshold voltage of the TFT, and the on / off of the TFT in the switch section or buffer section Furthermore, the area occupied by the drive circuit can be reduced, and It also contributes to framing.

[0091] The shift register circuit constituting the scanning line driving circuit will be described below.

[0092] The shift register circuit shown in FIG. 5 includes a plurality of flip-flop circuits 351. line 352, control signal line 353, control signal line 354, control signal line 355, control signal line 356 , and a reset line 357.

[0093] As shown in the shift register circuit of FIG. 5, in the flip-flop circuit 351, A start pulse SSP is input to the input terminal IN via a control signal line 352, and the next stage and onward The input terminal IN of the flip-flop circuit 351 is connected to the output signal terminal S of the previous stage. OUT is connected In addition, the reset terminal RES of the Nth stage (N is a natural number) is the (N+3)th stage. The output signal terminal S of the flip-flop circuit out and reset wire 357 The clock terminal CLK of the Nth stage flip-flop circuit 351 is connected to the control signal line 35 Assuming that the first clock signal CLK1 is input via 3, the (N+1)th stage The clock terminal CLK of the flip-flop circuit 351 is connected to the first control signal line 354. The clock signal CLK2 of the (N+2)th stage is input to the flip-flop circuit A third clock signal CL is input to the clock terminal CLK of the clock circuit 351 via a control signal line 355. K3 is input to the clock terminal of the (N+3)th flip-flop circuit 351. A fourth clock signal CLK4 is input to the CLK through a control signal line 356. The clock terminal CLK of the (N+4)th flip-flop circuit 351 receives a control signal A first clock signal CLK1 is input via a line 353. The flip-flop circuit 351 has a gate output terminal G out Therefore, the Nth flip-flop circuit Output SRoutN.

[0094] Although the connection between the flip-flop circuit 351 and the power supply and the power supply line is not shown, Each flip-flop circuit 351 is supplied with a power supply potential Vdd and a power supply potential GND via a power supply line. is being supplied.

[0095] The power supply potential described in this specification corresponds to the potential difference when the reference potential is 0V. Therefore, the power supply potential is sometimes called the power supply voltage, and vice versa. There are also.

[0096] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, A and B are also connected electrically. Electrically connected means that there is an object between A and B that has some electrical effect. When this is done, A and B are roughly the same node through the object. In the case of the MOS transistor, A and B are connected via a switching element such as a TFT. When A and B are approximately at the same potential due to the conduction of the resistor, or when A and B are connected via a resistor, The potential difference across the resistor element does not affect the operation of the circuit including A and B. When considering the circuit operation, A and B are treated as the same node and the difference is This indicates a situation where it is not feasible to do so.

[0097] Next, in FIG. 6, a flip-flop circuit 351 included in the shift register circuit shown in FIG. The flip-flop circuit 351 shown in FIG. The logic circuit section 361 includes a TFT 363 to a TFT 368. The switch section 362 includes TFTs 369 to 372. The circuit section is a section that outputs signals to the switch section, which is the latter stage circuit, in response to signals input from the outside. The switch section is a circuit for switching the input from the outside and the control circuit section. The switching of the TFT on or off in response to the signal input to the TFT, This is a circuit for outputting a current according to the noise and structure.

[0098] In the flip-flop circuit 351, the input terminal in is connected to the gate terminal of the TFT 364, and The reset terminal RES is connected to the gate terminal of the TFT363. The clock terminal CLK is connected to the first terminal of the TFT 369 and the The power supply line to which the power supply potential Vdd is supplied is connected to the first terminal of the TFT371. 364 and the gate terminal and second terminal of the TFT 366. The power supply line to which the power supply potential GND is supplied is the second terminal of TFT363 and the second terminal of TFT365. , a second terminal of the TFT 367, a second terminal of the TFT 368, a second terminal of the TFT 370, and It is connected to the second terminal of TFT372. It is also connected to the first terminal of TFT363, TFT364 The second terminal of TFT365, the first terminal of TFT368, the gate terminal of TFT369 The gate terminal of the TFT 371 and the gate terminal of the TFT 366 are connected to each other. The first terminal is the gate terminal of the TFT365, the first terminal of the TFT367, the first terminal of the TFT368, The gate terminal of the TFT 370 and the gate terminal of the TFT 372 are connected to the gate terminal of the TFT 370. Also, the gate output terminal G out is the second terminal of the TFT369 and the first terminal of the TFT370 The output signal terminal S out is the second terminal of TFT371 and TFT37 2 is connected to the first terminal.

[0099] In this case, the TFTs 363 to 372 are all N-type TFTs. We will explain the following.

[0100] A TFT has at least three terminals including a gate, a drain, and a source. The element has a channel forming region between a drain region and a source region, and the drain region A current can be passed through the source region, the channel forming region, and the source region. The transistor and drain may be switched depending on the structure and operating conditions of the TFT. It is difficult to determine which is the source and which is the drain. The regions that function as the source and drain are not called the source or drain, but are called, for example, These are written as the first terminal and the second terminal. In this case, the terminal that functions as the gate is In this case, it is referred to as the gate terminal.

[0101] Next, an example of a layout diagram of the flip-flop circuit 351 shown in FIG. 6 is shown in FIG.

[0102] The flip-flop circuit of FIG. 7 includes a power supply line 381 to which a power supply potential Vdd is supplied, a reset Line 382, ​​control signal line 353, control signal line 354, control signal line 355, control signal line 356 , a control signal line 383, a power supply line 384 to which a power supply potential GND is supplied, a logic circuit unit 361, and The logic circuit section 361 includes a TFT 363 to a TFT 368. The switch section 362 includes TFTs 369 to 372. In Figure 7, the gate output terminal G out Wiring connected to output signal terminal S out Connected to The wiring is also shown.

[0103] In FIG. 7, a semiconductor layer 385, a first wiring layer 386, a second wiring layer 387, a third wiring The first wiring layer 386 is a layer 388 and a contact hole 389. The second wiring layer 387 is formed from a layer that forms a gate electrode, and the second wiring layer 388 is formed from a layer that forms a source electrode of the TFT or The third wiring layer 388 is formed from a layer that forms a drain electrode. However, the present invention is not limited to this, and may be formed, for example, by a third wiring layer. The layer 388 may be formed as a wiring layer separate from the layer forming the pixel electrodes.

[0104] The connections between the circuit elements in FIG. 7 are as explained in FIG. 6. Since the flip-flop circuit to which the first clock signal is input is shown, Connections to control signal lines 354 to 356 are not shown.

[0105] In the layout diagram of the flip-flop circuit in FIG. 7, the TF By controlling the threshold voltage of T366 or TFT367, the EDMOS circuit 373 Typically, the TFT366 is a depletion type, and the TFT36 7 is configured as an enhancement type EDMOS circuit 373, and the switch section 362 has The TFTs 369 to 372 are dual-gate TFTs or depletion type TFTs. In FIG. 6, the TFT 366 and the TFT The FT367 is different from the EDMOS circuit shown in Figure 2 in that the gate electrode of a depletion-type TFT The connection positions are different.

[0106] The TFT366 or TFT367 is formed as a dual-gate TFT, and the back gate By controlling the potential of the electrodes, it is possible to produce either a depletion type TFT or an enhancement type It can be a TFT.

[0107] In FIG. 7, the control gate electrode is connected to the back gate electrode for controlling the threshold voltage of the TFT366. A control signal line 390 is provided separately to make the TFT 366 a depletion type. The potential of the back gate electrode is the power supply potential V This is a different potential from the power supply line 381 to which dd is supplied.

[0108] In FIG. 7, TFTs 369 to 372 are dual-gate TFTs, and In this example, the back gate electrode and the gate electrode have the same potential. The power supply potential Vdd applied to the power supply line is the same potential as that of the power supply line.

[0109] In this way, the TFTs arranged in the pixel section and the driving circuit of the display device are formed on the oxide semiconductor layer. The TFT can be formed using only an n-channel TFT.

[0110] In addition, the TFT 366 in the logic circuit section 361 flows a current according to the power supply potential Vdd. The TFT366 is a dual-gate TFT or a depletion-type TFT. By increasing the current flowing through the FT, the TFT's performance can be improved without any degradation. It is possible to achieve miniaturization.

[0111] In addition, in the TFT constituting the switch section 362, the amount of current flowing through the TFT is increased. , and can be switched on and off quickly without compromising performance. The area occupied by the TFT can be reduced. Therefore, the circuit formed by the TFT can be The area occupied by the TFTs 369 to 369 in the switch section 362 can also be reduced. As shown in the figure, the TFT 372 has a semiconductor layer 385 connected to a first wiring layer 386 and a third wiring layer 387. A dual gate TFT can be formed by sandwiching the two layers 388.

[0112] In addition, in FIG. 7, the dual gate type TFT has a semiconductor layer 385 and a first wiring layer 386. The third wiring layer 385 is connected to the first wiring layer 386 through a contact hole 389 and has the same potential. In the example shown, the wiring layer 388 is sandwiched between the wiring layer 388, but the present invention is not limited to this configuration. For example, a control signal line may be provided separately for the third wiring layer 388, and the potential of the third wiring layer 388 may be may be configured to be controlled independently from the first wiring layer 386.

[0113] In the layout diagram of the flip-flop circuit shown in FIG. The shape of the channel forming region of FT372 may be U-shaped (U-shaped or horseshoe-shaped). In addition, in FIG. 7, the size of each TFT is the same, but the output varies depending on the size of the downstream load. Force signal terminal S out or gate output terminal G out The size of each TFT connected to the You may change it.

[0114] Next, the operation of the shift register circuit shown in FIG. 5 will be described with reference to the timing chart shown in FIG. FIG. 8 shows the control signal lines 352 to 356 shown in FIG. The start pulse SSP, the first clock signal CLK1 to the fourth clock signal CLK2 are supplied. Signal CLK4 and output signal terminals S of the first to fifth flip-flop circuits out mosquito In the explanation of FIG. 8, Sout1 to Sout5 are output from the 6 and 7 are used.

[0115] In addition, FIG. 8 shows a case where each of the TFTs in the flip-flop circuit is an N-type TFT. 1 is a timing chart of the first clock signal CLK1 to the fourth clock signal CLK2. As shown in the figure, CLK4 is shifted by 1 / 4 wavelength (one section divided by dotted lines). It is as follows.

[0116] First, during the period T1, a start pulse SSP is applied to the first stage flip-flop circuit. is input at H level, the logic circuit section 361 switches the TFTs 369 and 371 At this time, the first clock signal Since CLK1 is at the L level, Sout1 is at the L level.

[0117] During the period T1, the flip-flop circuits from the second stage onwards have a signal at the IN terminal. Since no input is input, the L level is output without operation. The following description will be given assuming that each flip-flop circuit in the flip-register circuit outputs an L level. cormorant.

[0118] Next, in the period T2, in the first stage flip-flop circuit, the logic The logic circuit unit 361 controls the switch unit 362. In the period T2, the first clock signal C Since LK1 is at the H level, Sout1 is at the H level. Also, in the period T2, In the first flip-flop circuit, Sout1 is input to the IN terminal at a H level, and the logic circuit The switch 361 turns on the TFT 369 and TFT 371 of the switch section, and the TFT 370 and At this time, the second clock signal CLK2 is at the L level, so that S out2 is at L level.

[0119] During the period T2, the flip-flop circuits from the third stage onwards have a signal at the IN terminal. Since no input is being input, the L level is output without operating.

[0120] Next, during the period T3, the first stage flip-flop circuit maintains the state of the period T2. The logic circuit section 361 controls the switch section 362 so that The first clock signal CLK1 is at H level, and Sout1 is at H level. During the period T3, in the second stage flip-flop circuit, the logic circuit part 361 controls the switch unit 362. In the period T3, the second clock signal CLK2 is Since the signal Sout2 is at the H level, the third flip-flop in the period T3 is at the H level. In the flop circuit, Sout2 is input to the IN terminal at a H level, and the logic circuit unit 361 The TFTs 369 and 371 in the switch are turned on, and the TFTs 370 and 372 are turned off. At this time, the third clock signal CLK3 is at the L level, so Sout3 is at the L level. do.

[0121] During the period T3, the flip-flop circuits from the fourth stage onwards have a signal at the IN terminal. Since no input is being input, the L level is output without operating.

[0122] Next, during the period T4, the first stage flip-flop circuit maintains the state of the period T3. The logic circuit section 361 controls the switch section 362 so that In this case, the first clock signal CLK1 is at the L level, and Sout1 is at the L level. During the period T4, the second stage flip-flop circuit maintains the state of the period T3. Thus, the logic circuit section 361 controls the switch section 362. The second clock signal CLK2 is at H level, and Sout2 is at H level. During the period T4, in the third stage flip-flop circuit, the logic circuit part 361 controls the switch unit 362. In the period T4, the third clock signal CLK3 is Since the output of the fourth flip-flop in the period T4 is at the H level, the output of the fourth flip-flop in the period T5 is at the H level. In the flop circuit, Sout3 is input to the IN terminal at a H level, and the logic circuit unit 361 The TFT 369 and the TFT 371 of the switch unit 362 are turned on, and the TFT 370 and the TFT 37 At this time, the fourth clock signal CLK4 is at L level, so t4 is L level.

[0123] During the period T4, the flip-flop circuits from the 5th stage onwards have a signal at the IN terminal. Since no input is being input, the L level is output without operating.

[0124] Next, during the period T5, the second stage flip-flop circuit maintains the state of the period T3. The logic circuit section 361 controls the switch section 362 so that In this case, the second clock signal CLK2 is at the L level, and Sout2 is at the L level. In addition, during the period T5, the third-stage flip-flop circuit maintains the state of the period T4. Thus, the logic circuit unit 361 controls the switch unit 362. The third clock signal CLK3 is at H level, and Sout3 is at H level. In the fourth stage flip-flop circuit in the period T5, the logic circuit unit 3 61 controls the switch unit 362. In the period T5, the fourth clock signal CLK4 is H Since Sout4 is at H level, the 5th and subsequent flip-flops The circuit has the same wiring relationship as the first to fourth flip-flop circuits, and the input The signal timing is also the same, so a description thereof will be omitted.

[0125] As shown in the shift register circuit of Figure 5, Sout4 is the first stage flip-flop circuit. During the period T5, Sout4 becomes H level, and this signal The reset signal is input to the reset terminal RES of the flip-flop circuit in the second stage. As a result, the TFTs 369 and 371 of the switch section 362 are turned off, and the TFT Then, the Sout1 of the first flip-flop circuit is turned on. will output an L level until the next start pulse SSP is input.

[0126] By the above-described operation, the flip-flops in the second and subsequent stages can be The logic circuit is reset based on the reset signal output from the drop circuit, As shown in ut1 to Sout5, the waveform of the clock signal is shifted by 1 / 4 wavelength. The shift register circuit can output the signal:

[0127] In addition, the logic circuit section is divided into enhancement and depletion types as flip-flop circuits. The switch section is equipped with a dual-gate TFT and an EDMOS TFT. By adopting this configuration, the amount of current flowing through the TFT constituting the logic circuit section 361 can be increased. It is possible to reduce the area occupied by the TFT and the amount of light generated by the TFT without degrading the performance. In addition, the area occupied by the circuitry configured by the switch unit 362 can be reduced. In TFTs, the amount of current flowing through the TFT is increased, enabling the device to switch between on and off quickly. This allows the area occupied by the TFT and the size of the TFT to be reduced without compromising performance. The area occupied by the circuit formed by T can be reduced. It is possible to achieve reduced edge size, miniaturization, and high performance.

[0128] In addition, a latch circuit, a level shifter circuit, and the like may be provided in the signal line driver circuit shown in FIG. A buffer section is provided at the final stage of sending signals from the signal line driver circuit to the pixel section, and the amplified signals are The signal is sent from the signal line driver circuit to the pixel section. T, typically a dual-gate TFT or a depletion-type TFT Therefore, it is possible to reduce the area of ​​the TFT and the area occupied by the signal line driving circuit. Therefore, it is possible to realize a display device with a narrower frame, smaller size, and higher performance. The shift register, which is part of the signal line driver circuit, is required to operate at high speed. It is preferable to mount the display device using C or the like.

[0129] This embodiment mode can be freely combined with the first embodiment mode or the second embodiment mode. Cut.

[0130] (Embodiment 4) In this embodiment, a manufacturing process of a display device including the thin film transistor shown in Embodiment 1 will be described. This will be described with reference to FIG. 9 to FIG.

[0131] In FIG. 9A, a light-transmitting substrate 100 is made of barium borosilicate glass or aluminum. A glass substrate such as borosilicate glass can be used.

[0132] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gates). The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 are formed. At this time, the edge is formed so that at least the end of the gate electrode layer 101 has a tapered shape. The cross-sectional view at this stage is shown in FIG. In FIG. 11, the oxide semiconductor film, the channel protection layer, and the The source and drain electrodes, contact holes, and pixel electrodes are indicated by dashed lines. When using spin coating to form a resist mask, in order to improve the uniformity of the resist film, In this case, a large amount of resist material and a large amount of developer are used, resulting in a large amount of unnecessary material consumption. When the plate becomes large, the deposition method using spin coating requires a mechanism to rotate the large substrate. This is disadvantageous for mass production because the process is large-scale, there is a loss of liquid material, and there is a large amount of waste liquid. When spin-coating a rectangular substrate, circular irregularities tend to appear in the coating film around the axis of rotation. Therefore, a selective method using a droplet ejection method such as the inkjet method or a screen printing method is used. It is preferable to form a resist material film on the substrate and then expose the resist material to light to form a resist mask. By selectively forming a resist material film, the amount of resist material used can be reduced. This allows for significant cost reductions, and the 1000mm x 1200mm, 1100mm x 125 It can also accommodate large area substrates such as 1150mm x 1300mm.

[0133] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Aluminum (Al), Copper (Cu), Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium (Sc ) or an alloy containing the above elements or a combination of the above elements The film is made of an alloy containing the above elements, or a nitride containing the above elements. It is preferable to form the plate from a low-resistance conductive material such as aluminum (Al) or copper (Cu), but aluminum alone is not suitable. Since it has problems such as poor heat resistance and susceptibility to corrosion, it is used in combination with heat-resistant conductive materials. The heat-resistant conductive material is titanium (Ti), tantalum (Ta), tungsten (Tb), etc. W, Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Scandium (S c) Use an element selected from the above.

[0134] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. For 02, a method such as sputtering is used, and the film thickness is set to 50 to 250 nm.

[0135] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering, and the thickness is 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Silicon oxide nitride film, silicon nitride film, aluminum oxide film, tantalum oxide film, etc. It may be formed as a single layer or a laminate structure made of these materials using other insulating films such as SiO2. good.

[0136] Note that before the oxide semiconductor film is formed, a reverse process in which argon gas is introduced to generate plasma is performed. It is preferable to remove dust adhering to the surface of the gate insulating layer by sputtering. Instead of the argon atmosphere, nitrogen, helium, or the like may be used. The atmosphere may be mixed with oxygen, hydrogen, NO, etc. 2. It may be performed in an atmosphere containing CF4 or the like.

[0137] Next, a first oxide semiconductor film (a first In- After the plasma treatment, the first Depositing an In-Ga-Zn-O non-single crystal film creates a gate insulating layer and a semiconductor film. It is useful in that it does not attract dust or moisture. Here, an 8-inch diameter In, Ga, and A Zn-containing oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1:1) The distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, and the DC voltage was The film is formed in an argon or oxygen atmosphere with a 0.5 kW power source. The use of In-Ga- The thickness of the Zn-O-based non-single crystal film is set to 5 nm to 200 nm. The thickness of the n-Ga-Zn-O based non-single crystal film is set to 100 nm.

[0138] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0139] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0140] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0141] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0142] Next, a channel is formed in the first In-Ga-Zn-O non-single crystal film in a region overlapping the channel forming region. The channel protection layer 133 is also made of the first In-Ga-Zn-O based non-crystalline The thin film may be formed by successively depositing the single crystal film without exposing it to the air. If the film is continuously formed without being exposed to the atmosphere, the productivity is improved.

[0143] The channel protection layer 133 may be made of an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, silicon nitride, etc.). The method of manufacture includes plasma CVD and thermal CVD. Any vapor deposition method or sputtering method can be used. The channel protection layer 133 is formed by The shape is then processed by etching. Here, a silicon oxide film is formed by sputtering. Then, the channel protection layer is formed by etching using a photolithography mask. When the channel protection layer 133 is etched, the first In-Ga- The Zn-O non-single crystal film acts as an etching stopper, preventing the film loss of the gate insulating film. This can prevent this.

[0144] Next, a second In-Ga-Zn-O-based non-single crystal film is formed on the first In-Ga-Zn-O-based non-single crystal film and the channel protection layer 133. The oxide semiconductor film (the second In-Ga-Zn-O-based non-single crystal film in this embodiment) is Here, the substrate is In2O3:Ga2O3:ZnO=1:1:1. The deposition conditions were a pressure of 0.4 Pa, a power of 500 W, and a deposition temperature of room temperature. The temperature was raised and argon gas was introduced at a flow rate of 40 sccm to perform sputtering deposition. Although a target with a2O3:ZnO=1:1:1 was intentionally used, no results were obtained. Immediately after deposition, an In-Ga-Zn-O based non-single crystal film containing crystal grains with sizes of 1 nm to 10 nm was formed. The target component ratio and deposition pressure (0.1 Pa to 2.0 Pa) may be , power (250W~3000W: 8 inch diameter), temperature (room temperature~100℃), reactive spat By appropriately adjusting the deposition conditions of the crystal grains, the presence or absence of crystal grains, the density of the crystal grains, and the diameter size can be determined. In other words, it can be said that the thickness can be adjusted in the range of 1 nm to 10 nm. The thickness of the crystal film is 5 nm to 20 nm. Of course, if the film contains crystal grains, the In this embodiment, the size of the crystal grains formed in the second In-Ga The thickness of the Zn-O based non-single crystal film is 5 nm.

[0145] The first In-Ga-Zn-O based non-single crystal film is a second In-Ga-Zn-O based non-single crystal film For example, the deposition conditions for the second In-Ga-Zn-O-based non-single crystal film are different from those for the first In-Ga-Zn-O-based non-single crystal film. The ratio of the oxygen gas flow rate to the argon gas flow rate in the first In-Ga-Zn-O system non-monocrystalline The ratio of the oxygen gas flow rate to the total film forming conditions is set to be high. The deposition conditions for the In-Ga-Zn-O non-single crystal film in 2 are rare gas (argon or helium) etc.) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and the first I The conditions for forming the n-Ga-Zn-O non-single crystal film were an oxygen atmosphere (or an oxygen gas flow rate of 1000 MPa). (The flow rate of the gas should be greater than that of the gas flow rate of the gas.)

[0146] The second In-Ga-Zn-O non-single crystal film was deposited in the same chamber as the previous reverse sputtering. The same chamber may be used for the reverse sputtering, or a different chamber may be used for the reverse sputtering. The film may be formed using a bar.

[0147] Next, a third photolithography process is performed to form a resist mask, and the first In- Etching of the Ga-Zn-O non-single crystal film and the second In-Ga-Zn-O non-single crystal film Here, the unnecessary parts are removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Ltd.). The undesired portion is removed to leave the oxide semiconductor film 109, which is a first In-Ga-Zn-O-based non-single crystal film. Then, the oxide semiconductor film 111, which is a second In-Ga-Zn-O-based non-single-crystal film, is formed. The etching method used here is not limited to wet etching, but may be dry etching. The top view at this stage is shown in FIG. 9(B). Note that the top view at this stage is shown in FIG. In FIG. 12, the source electrode and the drain electrode, which will be formed later, and the contact The holes and pixel electrodes are indicated by dashed lines.

[0148] Next, a fourth photolithography step is performed to form a resist mask and etch the By removing unnecessary parts of the gate insulating layer 102, wiring and electrodes made of the same material as the gate electrode layer are formed. A contact hole is formed that reaches the conductive layer. This contact hole is connected to the conductive film to be formed later. For example, in the driver circuit section, the gate electrode layer and the source electrode layer are directly connected to each other. Alternatively, the thin film transistor directly contacts the drain electrode layer, and the gate wiring of the terminal portion is electrically connected When a connecting terminal is to be formed, a contact hole is formed.

[0149] Next, a conductive film 13 made of a metal material is formed over the oxide semiconductor film 109 and the oxide semiconductor film 111. 2 is formed by sputtering or vacuum deposition. The top view at this stage is shown in Figure 9(C).

[0150] The material of the conductive film 132 is an element selected from Al, Cr, Ta, Ti, Mo, and W, or or an alloy film containing the above elements or a combination of the above elements. In addition, when heat treatment is performed at 200°C to 600°C, the heat resistance that can withstand this heat treatment is introduced. It is preferable to have a conductive film with aluminum as the only component. Aluminum alone has problems such as poor heat resistance and is prone to corrosion. Since there are some points, it is formed by combining it with a heat-resistant conductive material. The conductive materials are titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum. An element selected from Mo, chromium, neodymium, and scandium. or an alloy film containing the above elements or a combination of the above elements; or It is formed of a nitride containing the above-mentioned elements as components.

[0151] Here, the conductive film 132 has a single-layer structure of a titanium film. Alternatively, a titanium film may be stacked on an aluminum film. A Ti film is layered on top of the Ti film, and an aluminum film containing Nd (Al-Nd) is layered on top of the Ti film. A three-layer structure may be formed by further forming a Ti film on the conductive film 132. Alternatively, the aluminum film may have a single layer structure containing the above-mentioned.

[0152] Next, a fifth photolithography step is performed to form a resist mask 131 and etch the The unnecessary portions are removed by etching to leave the first electrode 105a, the second electrode 105b, and the source The drain regions 104a and 104b are formed by etching. For example, the conductive film 132 is made of aluminum. When using aluminum film or aluminum alloy film, use a solution of phosphoric acid, acetic acid, and nitric acid. In this case, wet etching can be performed using ammonia hydrogen peroxide (H2O2). The conductive film 132 of the Ti film was removed by wet etching using ammonia:water (5:2:2). The first electrode 105a, the second electrode 105b, and the oxide semiconductor film 111 are removed by etching. The source and drain regions 104a, 104b are formed by etching. In the etching process, the channel protection layer 133 prevents the oxide semiconductor layer 103 from being etched. Since the oxide semiconductor layer 103 functions as a protective film, the oxide semiconductor layer 103 is not etched. In the semiconductor device, a first electrode 105a, a second electrode 105b, a source region or a drain region 10 4a and 104b are etched at the same time using an etching agent of ammonia hydrogen peroxide. The first electrode 105a, the second electrode 105b and the source or drain region 104a, The ends of 04b are aligned and form a continuous structure. In order to achieve this, etching is performed isotropically, and the ends of the first electrode 105a and the second electrode 105b are The resist mask 131 is recessed from the oxide semiconductor layer 103. A thin-film transistor having a channel forming region and a channel protection layer 133 on the channel forming region. The cross-sectional view at this stage is shown in FIG. The top view without the resist mask 131 corresponds to FIG. 13. In FIG. The pixel electrodes that are to be connected are indicated by dashed lines.

[0153] In this structure, a channel protection layer 133 is provided on a channel formation region of the oxide semiconductor layer 103. Therefore, damage (edge ​​damage) to the channel formation region of the oxide semiconductor layer 103 during the process This can prevent film loss and oxidation caused by plasma and etching materials during etching. This makes it possible to improve the reliability of the thin film transistor 170.

[0154] Next, it is preferable to carry out a heat treatment at 200°C to 600°C, typically 300°C to 500°C. Here, the sample is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal film. This releases the distortion that inhibits carrier movement, so the heat treatment (including light annealing) The timing of the heat treatment is important. There are no particular limitations as long as it is performed after the formation of the single crystal film, and it may be performed, for example, after the formation of the pixel electrode.

[0155] In the fifth photolithography step, the first electrode 105a and the second electrode The second terminal 122 made of the same material as 105b is left in the terminal portion. Electrically connected to the source wiring (the source wiring including the first electrode 105a and the second electrode 105b) This is being continued.

[0156] In addition, in the terminal portion, the connection electrode 120 is formed through a contact hole formed in the gate insulating film. The terminal portion is directly connected to the first terminal 121 via the The source wiring or drain wiring of the thin film transistor of the driving circuit is formed through the same process as described above. The wiring and the gate electrode are directly connected.

[0157] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a photomask, the number of photomasks can be reduced, simplifying the process and reducing costs. It is possible to streamline the process.

[0158] Next, the resist mask 131 is removed, and the protective insulating layer 10 covering the thin film transistor 170 is removed. The protective insulating layer 107 is a silicon nitride film obtained by sputtering or the like, an oxide film, or the like. silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, oxynitride film A single layer such as an aluminum oxide film or a tantalum oxide film or a laminate of these may be used. In some thin film transistors of the driving circuit, the protective insulating layer 107 is This serves as one layer of the gate insulating layer, on which the second gate electrode is formed. The protective insulating layer 107 is a second gate insulating layer having a thickness of 50 to 400 nm. The total thickness of the first gate insulating film and the channel protection layer is approximately equal to the thickness of the first gate insulating film. Approximately the same gate voltage can be applied from the upper and lower gate electrodes. When a silicon oxynitride film or a silicon nitride film is used as the layer 107, a protective insulating film is formed. Impurities that may adhere to the layer 107 after it is formed, such as mobile ions of sodium, It is possible to block the diffusion of the metal oxide from penetrating into the oxide semiconductor.

[0159] Next, a sixth photolithography step is performed to form a resist mask and a protective insulating layer 1 A contact hole 125 reaching the second electrode 105b is formed by etching in step 07. In addition, a contact hole 127 reaching the second terminal 122 is formed by etching in this step. The contact hole 126 reaching the connection electrode 120 can also be formed using the same resist mask. A cross-sectional view at this stage is shown in FIG.

[0160] Next, the resist mask is removed, and then a transparent conductive film is formed. Indium oxide (In2O3) and indium tin oxide alloy (In2O3-SnO 2, ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid based solution. However, etching of ITO in particular Residues are easily generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0161] Next, a seventh photolithography step is performed to form a resist mask and perform etching. The unnecessary portions are removed to form the pixel electrode 110. In the process, the driving circuit uses the same material as the pixel electrode 110 for a part of the circuit. An electrode layer (back gate electrode) for controlling a threshold voltage is formed on the oxide semiconductor layer. The thin film transistor having a back gate electrode is the same as that shown in FIG. Therefore, a detailed description will be omitted here.

[0162] In addition, in this seventh photolithography step, the gate insulating layer 10 in the capacitance section 2 and the protective insulating layer 107 as dielectrics, the capacitance wiring 108 and the pixel electrode 110 form a storage capacitance. In this case, the gate insulating layer 102 and the protective insulating layer 107 are used as dielectrics. In the above example, the storage capacitor is formed by the capacitor wiring 108 and the pixel electrode 110. An electrode made of the same material as the source electrode or drain electrode is provided above the capacitance wiring. The electrodes, the capacitance wiring, and the gate insulating layer 102 between them are configured as a dielectric. A storage capacitor may be formed and its electrode may be electrically connected to the pixel electrode.

[0163] In the seventh photolithography step, the first terminal and the second terminal are formed by resist. The transparent conductive film 128 and 129 formed on the terminal portion are left covered with a mask. 8 and 129 are electrodes or wiring used for connection with the FPC. The transparent conductive film 128 formed on the connected connection electrode 120 is an input terminal of the gate line. The transparent conductive film 1 formed on the second terminal 122 serves as a terminal electrode for connection. Reference numeral 29 denotes a connection terminal electrode that functions as an input terminal for the source wiring.

[0164] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The top view at this stage corresponds to FIG.

[0165] 15(A1) and 15(A2) are top views of the gate line terminal portion at this stage. FIG. 15(A1) is a cross-sectional view taken along line C1-C2 in FIG. 15(A2). In FIG. 15(A1), a transparent insulating film 154 is formed on the protective insulating film 154. The conductive film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, a first terminal 151 made of the same material as the gate wiring and a source The gate insulating layer 152 is formed on the gate electrode 153, which is made of the same material as the gate wiring. The connection electrode 153 and the transparent conductive film 155 are connected to each other through a protective insulating film 154. The electrodes are directly connected to each other through contact holes provided in the electrodes to provide electrical continuity.

[0166] FIG. 15(B1) and FIG. 15(B2) are a top view and a cross-sectional view of a source wiring terminal portion. Also, FIG. 15(B1) is taken along the line D1-D2 in FIG. 15(B2). In FIG. 15(B1), a transparent conductive film is formed on a protective insulating film 154. The conductive film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, an electrode 156 made of the same material as the gate wiring is connected to the source wiring. The second terminal 150 is electrically connected to the electrode 152 and overlaps the electrode 152 via the gate insulating layer 152. The electrode 156 is not electrically connected to the second terminal 150. For example, by setting the potential to floating, GND, 0V, etc., noise can be reduced. A capacitance for preventing a breakdown or a capacitance for preventing static electricity can be formed. 0 is electrically connected to a transparent conductive film 155 via a protective insulating film 154 .

[0167] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0168] In this way, seven photolithography steps were performed using seven photomasks to create the bottom. A pixel having a thin film transistor 170 which is a gate-type n-channel thin film transistor. The thin film transistor and storage capacitor can be completed. Then, these are connected to the individual pixels. By configuring the pixel section in a matrix corresponding to the active matrix type, For the sake of convenience, the present specification will refer to such a substrate as one of the substrates for manufacturing a display device. Such a substrate is called an active matrix substrate.

[0169] In addition, the connection electrodes are formed using the same material as the pixel electrodes, and the gate wiring and the source wiring or the drain wiring are When the semiconductor device is to be electrically connected to the drain wiring, a third photolithography process is performed. Since the number of photolithography steps can be omitted, six photomasks are used in six photolithography steps. a second thin film transistor which is a bottom gate type n-channel thin film transistor; You can complete the carrying capacity.

[0170] In addition, when the material of the second gate electrode is made different from the material of the pixel electrode as shown in FIG. In this case, one photolithography step is added, and one photomask is added.

[0171] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The counter electrode is fixed to the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for

[0172] In addition, this embodiment is not limited to the pixel configuration of FIG. 14, and examples of top views different from those of FIG. FIG. 16 shows a case where a capacitance line is not provided, and the pixel electrode is connected to the gate line of the adjacent pixel. In this example, a storage capacitor is formed by stacking a protective insulating film and a gate insulating layer. The third terminal connected to the wiring and the capacitance wiring can be omitted. 14. The same parts as those in FIG. 14 will be described using the same reference numerals.

[0173] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0174] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the LCD, There is a driving technique called black insertion, which displays black every other frame.

[0175] In addition, by increasing the vertical sync frequency by 1.5 times or more, preferably by 2 times or more, the video characteristics will be improved. A driving technique called double speed driving may be used to improve the above.

[0176] In addition, in order to improve the video characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. In addition, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched according to the timing of the optical modulation of the liquid crystal layer. The timing of the LEDs can also be synchronized. This is particularly useful when displaying images with a large proportion of black areas occupying the entire screen. This has the effect of reducing power consumption.

[0177] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0178] The n-channel transistor obtained in this embodiment is an In-Ga-Zn-O based non-single crystal The crystal film is used in the channel formation region and has good dynamic characteristics, so these driving technologies Can be combined.

[0179] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0180] The gate line driver circuit or source line driver circuit is formed of a thin film transistor using an oxide semiconductor. By forming a thin film transistor using a driving circuit, the manufacturing cost can be reduced. By directly connecting the gate electrode and the source wiring or the drain wiring, a contact hole is formed. It is possible to provide a display device capable of reducing the number of driving circuits and reducing the area occupied by the driving circuits.

[0181] Therefore, according to the present embodiment, a display device having high electrical characteristics and high reliability can be provided at low cost. It is possible.

[0182] This embodiment mode can be freely combined with the first, second, or third embodiment mode. It can be adjusted.

[0183] (Embodiment 5) In this embodiment mode, an example of electronic paper will be shown as a semiconductor device.

[0184] FIG. 17 shows an active matrix type electronic device as an example of a semiconductor device other than a liquid crystal display device. The thin film transistor 581 used in the pixel portion of the semiconductor device is It can be fabricated in the same manner as the thin film transistor of the pixel portion shown in the fourth embodiment, and is an In-Ga-Zn-O system. The thin film transistor includes a non-single crystal film as a semiconductor layer. In this way, the pixel section and the driver circuit can be fabricated on the same substrate, and the manufacturing cost can be reduced. Child paper can be realized.

[0185] The electronic paper in FIG. 17 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a light.

[0186] The thin film transistor 581 is a thin film transistor having a bottom gate structure, and the source electrode layer The drain electrode layer is formed by a first electrode layer 587 and an opening formed on insulating layers 583, 584, and 585. The first electrode layer 587 and the second electrode layer 588 are in contact with each other and electrically connected. The cavity has black areas 590a and white areas 590b and is filled with liquid. A spherical particle 589 including a tee 594 is provided between a pair of substrates 580 and 596. The surroundings of the shaped particles 589 are filled with a filler 595 such as a resin (see FIG. 17).

[0187] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, also known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, auxiliary lights are not required. The power consumption is low, and the display can be seen even in dimly lit places. Even if power is not supplied to the device, the image once displayed can be retained. , a semiconductor device with a display function (simply a display device, or a semiconductor device equipped with a display device) from a radio wave source It is possible to store the displayed image even if the user moves the device (also called the body device) away from the camera. become.

[0188] By using the TFT shown in the first embodiment, etc., the manufacturing cost of the semiconductor device is reduced. It is possible to produce electronic paper having such a structure.

[0189] This embodiment may be appropriately combined with the configuration described in the first or second embodiment. It is possible to implement.

[0190] (Embodiment 6) In this embodiment mode, a light-emitting display device is shown as an example of a semiconductor device. Here, a light-emitting element that uses electroluminescence is used as the element. Light-emitting devices that utilize fluoroluminescence are characterized by the fact that the luminescent material is either an organic compound or an inorganic compound. Generally, the former are called organic EL elements and the latter are called inorganic EL elements. It's been discovered.

[0191] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0192] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0193] FIG. 18 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0194] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The channel formation region is made of an oxide semiconductor layer (In-Ga-Zn-O non-single crystal film). 1 shows an example in which two L-channel transistors are used in one pixel.

[0195] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408 .

[0196] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0197] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0198] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is input. In other words, the driving transistor 6402 is in the linear region when it is on. The driving transistor 6402 is operated in the linear region, so that when it is in the on state, applies a voltage higher than the voltage of the power supply line 6407 to the gate of the driving transistor 6402. When the driving transistor 6402 is in an on state (power supply line A voltage equal to or higher than the voltage + Vth of the switching transistor 6401 is applied.

[0199] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 18 can be used.

[0200] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 plus the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0201] Note that the pixel configuration shown in FIG. 18 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0202] Next, the structure of the light emitting element will be described with reference to FIG. 19(A), FIG. 19(B), and FIG. 19(C). Here, the case where the driving TFT is the thin film transistor 170 shown in FIG. The cross-sectional structure of a pixel will be described with reference to FIG. 19(A), FIG. 19(B), and FIG. The driving TFTs 7001, 7011, and 7021 used in the semiconductor device of the embodiment It can be fabricated in the same manner as the thin-film transistor 170 shown in FIG. 1, and an In-Ga-Zn-O system non-single crystal film The present invention relates to a thin film transistor that includes a semiconductor layer and has excellent electrical characteristics.

[0203] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure in which light is emitted from the side of the pixel. The present invention can also be applied to a light emitting element having an injection structure.

[0204] A light emitting element having a top emission structure will be described with reference to FIG.

[0205] In FIG. 19A, a driving TFT 7001 is the thin film transistor 170 shown in FIG. 7 is a cross-sectional view of a pixel in which light emitted from a light-emitting element 7002 exits to the anode 7005 side. In FIG. 19A, a cathode 7003 of a light-emitting element 7002 and a driving TFT 7001 are They are electrically connected to each other, and a light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. The cathode 7003 can be made of various conductive films that have a small work function and reflect light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers. In the case where the cathode is made up of multiple layers, the cathode 7003 An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on top of each other in this order. It is not necessary to provide all of these layers. The anode 7005 is a conductive material having a light-transmitting property. The insulating layer is formed using a conductive material, for example, indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc A conductive film having light transmitting properties, such as indium tin oxide or silicon oxide-added indium tin oxide, is formed. You may use it.

[0206] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 19(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0207] Note that a second gate electrode provided over the oxide semiconductor layer in the driver circuit is a cathode 7003. It is preferable to form them from the same material since this simplifies the process.

[0208] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. 011 is the thin film transistor 170 shown in FIG. 1A, and the light emitting element 7012 emits light. FIG. 19B shows a cross-sectional view of a pixel in the case where the light emitted from the driving A light-emitting element is formed on a light-transmitting conductive film 7017 electrically connected to the moving TFT 7011. A cathode 7013 of 7012 is formed, and a light-emitting layer 7014 and an anode 70 In addition, when the anode 7015 is transparent, the anode 7015 is covered with the insulating film 15. As shown in FIG. 1, a shielding film 7016 for reflecting or shielding light may be formed. As in the case of FIG. 19(A), various conductive materials with small work functions can be used. However, the thickness of the film should be such that it transmits light (preferably 5 nm to 3 For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 can be a single layer, as in FIG. The anode may be configured as a single layer or as a laminate of multiple layers. 7015 does not need to transmit light, but as in FIG. 19(A), it is a conductive material having light-transmitting properties. The shielding film 7016 can be formed of, for example, a light-reflecting metal or the like. However, it is not limited to a metal film. For example, a resin containing a black pigment may be used. You can also be there.

[0209] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 19B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0210] Note that a second gate electrode provided over the oxide semiconductor layer in the driver circuit is a cathode 7013. It is preferable to form them from the same material since this simplifies the process.

[0211] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In this example, a conductive film 7027 having a light-transmitting property and electrically connected to the driving TFT 7021 is formed on the substrate 7022. A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0212] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 19C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0213] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is a conductive film 7027 It is preferable to form the gate electrode from the same material as the gate electrode because the process can be simplified. The second gate electrode provided on the semiconductor layer is made of the same material as the conductive film 7027 and the cathode 7023. By stacking using this method, the process can be simplified and the wiring resistance can be reduced. This can be preferably reduced.

[0214] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0215] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is In the example shown here, a light-emitting element is connected, but a current control TFT is connected between the driving TFT and the light-emitting element. The configuration may be such that FT is connected.

[0216] The semiconductor device described in this embodiment mode has a structure shown in FIG. The present invention is not limited to the above-described configuration, and various modifications based on the disclosed technical concept are possible. do.

[0217] Next, a top surface of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device and The cross section will be described with reference to Fig. 21(A) and Fig. 21(B). Fig. 21(A) shows the first The thin film transistor and the light emitting element formed on the substrate are sandwiched between the substrate and the second substrate by a sealant. FIG. 21(B) is a top view of the panel sealed by the HI in FIG. 21(A). This corresponds to a cross-sectional view.

[0218] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0219] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 21B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0220] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O non-single crystal films as semiconductor layers. As a result, the highly reliable thin film transistor described in Embodiment 1 can be applied. In addition, the thin film transistor 4509 is a thin film transistor having a semiconductor layer as shown in Embodiment 1 and FIG. The gate electrodes are disposed above and below the gate electrode.

[0221] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The first electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The light emitting element 4511 is not rotated in accordance with the direction of the light to be extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0222] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0223] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0224] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0225] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0226] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0227] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0228] The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film or an acrylic plate. A light-transmitting material such as a film is used.

[0229] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used.

[0230] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0231] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared single crystal semiconductor substrate or an insulating substrate. Alternatively, the signal line driver circuit may be implemented as a driver circuit formed by a thin film. Alternatively, only a part of the scanning line driver circuit or only a part of the scanning line driver circuit may be formed separately and mounted. This embodiment is not limited to the configurations of FIGS. 21(A) and 21(B).

[0232] A light-emitting display device in which the manufacturing cost is reduced by using the TFT shown in the first embodiment and the like (Display panel) can be manufactured.

[0233] This embodiment may be appropriately combined with the configuration described in the first or second embodiment. It is possible to implement.

[0234] (Embodiment 7) In this embodiment mode, a top view and a cross section of a liquid crystal display panel, which is one mode of a semiconductor device, are shown. This will be described with reference to Figs. 20(A1) and 20(B). Fig. 20(A1) shows the first substrate 4 The In-Ga-Zn-O system non-single crystal film formed on 001 as shown in the first embodiment is The thin film transistors 4010 and 4011 and the liquid crystal element 4013 are formed as layers on the second substrate. 20 is a top view of a panel sealed between a plate 4006 and a sealing material 4005. (B) corresponds to a cross-sectional view taken along line MN in FIG. 20(A1).

[0235] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0236] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 20A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0237] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 20B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4021 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0238] The thin film transistors 4010 and 4011 are made of In-Ga-Zn-O non-single crystal films as semiconductor layers. The thin film transistor described in Embodiment 1 can be used as the thin film transistor. The transistor 4011 is a thin-film transistor having a back gate electrode shown in FIG. 2(A) of the second embodiment. Equivalent to a transistor.

[0239] The pixel electrode 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 400. 6. The pixel electrode 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode 4030 and the counter electrode layer 4031 are arranged corresponds to the liquid crystal element 4013. Insulating layers 4032 and 4033 functioning as alignment films are provided on the insulating layer 4031. A liquid crystal layer 4008 is sandwiched between 4032 and 4033 .

[0240] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0241] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode layer 4031 A spherical spacer may be used. The counter electrode layer 4031 is , which is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Using the common connection portion, the counter electrode layer 403 is connected to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 400 to the common potential line. Include in 5.

[0242] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to It is short at 100μs, has optical isotropy so no alignment treatment is required, and has small viewing angle dependency. stomach.

[0243] Although the present embodiment is an example of a transmissive liquid crystal display device, a semi-transmissive liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0244] In the liquid crystal display device of the present embodiment, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and The colored layer and the electrode layer used for the display element are provided in this order, but the polarizing plate may be provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The appropriate setting may be made depending on the material and manufacturing process conditions. A light-shielding film may be provided.

[0245] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the transistor, the thin film transistor obtained in the first embodiment is provided with a protective film or The insulating layer 4020 and the insulating layer 4021 function as a planarizing insulating film. The protective film is designed to prevent contamination by organic matter, metals, water vapor, and other contaminants suspended in the air. The protective film is formed by sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride A single layer or multilayer of an aluminum film, an aluminum oxynitride film, or an aluminum nitride oxide film. In this embodiment, an example in which the protective film is formed by sputtering is shown. The method is not limited to this, and may be a plasma CVD method or other method. In this case, the protective film functions as a second gate insulating layer, and a backgate is formed on the second gate insulating layer. The semiconductor device includes a thin film transistor having a gate.

[0246] Here, an insulating layer 4020 having a laminated structure is formed as a protective film. A silicon oxide film is formed by sputtering as the first layer of the 0. Silicon oxide film as a protective film By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0247] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. Mobile ions such as thorium penetrate into the semiconductor region and change the electrical properties of the TFT. This second insulating layer also functions as a second gate insulator in part of the drive circuit. It functions as an edge layer.

[0248] Therefore, when approximately the same gate voltage is applied to the upper and lower sides of the oxide semiconductor layer, the second gate If the first insulating layer is a stack of layers of different materials, the first gate insulating layer is also a stack of layers of different materials. In this embodiment, in the driving circuit, A first gate insulator provided on a first gate electrode of a thin film transistor having a back gate The layer is a laminate of a silicon nitride film and a silicon oxide film, and the total thickness is approximately the same as that of the insulating layer 4020. Make it so.

[0249] After forming the protective film, the semiconductor layer may be annealed (at 300° C. to 400° C.). In addition, the back gate is formed after the protective film is formed.

[0250] In addition, an insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by stacking a plurality of insulating films made of these materials, an insulating layer can be formed. 4021 may be formed.

[0251] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0252] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, In the step of bonding, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time. By combining the firing process of the edge layer 4021 with the annealing process of the semiconductor layer, a semiconductor device can be efficiently manufactured. It becomes possible to do so.

[0253] The pixel electrode 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide containing titanium dioxide, indium tin oxide (hereinafter referred to as ITO), Conductive materials with translucency such as indium zinc oxide and indium tin oxide doped with silicon oxide Conductive materials can be used.

[0254] The pixel electrode 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive layer. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical resistance is 0.1 Ω·cm or less.

[0255] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0256] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0257] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode 403 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 401 The source electrode layer and the drain electrode layer of the first transistor are formed of the same conductive film.

[0258] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0259] In addition, in FIG. 21(A1) and FIG. 21(A2), a signal line driver circuit 4003 is formed separately. 10, an example in which the first substrate 4001 is mounted is shown, but this embodiment is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as a part of the signal line driver circuit or Alternatively, only a part of the scanning line driver circuit may be formed separately and mounted.

[0260] FIG. 22 shows a liquid crystal display module formed as a semiconductor device using a TFT substrate 2600. An example is shown.

[0261] FIG. 22 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604, a colored layer 2605, and a polarizing plate 2606 are provided to form a display area. The color layer 2605 is necessary for color display. In the case of the RGB method, it is red, green, A colored layer corresponding to each color of blue and blue is provided for each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed on the outer side of the optical substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611. The circuit board 2612 is , and is connected to a wiring circuit section 2608 of the TFT substrate 2600 via a flexible wiring substrate 2609. It also includes external circuits such as a control circuit and a power supply circuit. The liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0262] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic) ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid C rystal) mode, AFLC (AntiFerroelectric Liquid Liquid crystals such as LC-LCDs can be used.

[0263] By using the TFT shown in the first embodiment, etc., the manufacturing cost of the semiconductor device can be reduced. Thus, a liquid crystal display panel can be manufactured.

[0264] This embodiment is similar to the configuration described in the first, second, or third embodiment. It is possible to carry out any suitable combination.

[0265] (Embodiment 8) The semiconductor device according to the disclosed invention can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. digital photo frames, mobile phones (also called mobile phones or mobile phone devices), These include large game machines such as small game machines, portable information terminals, audio playback devices, and pachinko machines. can be.

[0266] FIG. 23A shows an example of a mobile information terminal device 9200. The 200 has a built-in computer and is capable of performing various data processing. As a portable information terminal device 9200 such as a PDA (Personal Digital Audio Device), l Assistance).

[0267] The mobile information terminal device 9200 is composed of two housings, a housing 9201 and a housing 9203. The housing 9201 and the housing 9203 are foldably connected to each other at a connecting portion 9207. A display unit 9202 is incorporated in a housing 9201, and a keyboard and mouse are mounted on the housing 9203. Of course, the configuration of the portable information terminal device 9200 is not limited to the above. However, as long as the device has a structure including at least a thin film transistor having a back gate electrode, Other auxiliary equipment may be appropriately provided. By forming a pixel portion with a thin film transistor having high electrical characteristics, the manufacturing cost can be reduced. It is possible to realize a portable information terminal device having the above.

[0268] FIG. 23B shows an example of a digital video camera 9500. The camera 9500 has a display unit 9503 built into a housing 9501, and various operation units. The configuration of the digital video camera 9500 is not particularly limited, and at least In either case, the device may be configured to include a thin film transistor having a back gate electrode. The driving circuit and the pixel portion can be formed on the same substrate. This reduces manufacturing costs and enables the development of digital devices with thin-film transistors with excellent electrical properties. A video camera can be realized.

[0269] FIG. 23C shows an example of a mobile phone 9100. The mobile phone 9100 has a housing. It is composed of two housings, a body 9102 and a housing 9101, and is foldable by a joint 9103. The display unit 9104 is incorporated in the housing 9102. The housing 9101 is provided with operation keys 9106. is not particularly limited, and includes at least a thin film transistor having a back gate electrode. Other auxiliary equipment may be provided as appropriate. By forming the driver circuit and pixel section, the manufacturing cost is reduced, and thin film transistors with high electrical characteristics are used. It is possible to realize a mobile phone having a transistor.

[0270] FIG. 23D shows an example of a portable computer 9400. The electronic device 9400 includes a housing 9401 and a housing 9404 that are connected in an openable and closable manner. The display unit 9402 is incorporated in the device 01, and the housing 9404 is equipped with a keyboard 9403, etc. The configuration of the computer 9400 is not particularly limited, and at least a back gate power supply is required. It is sufficient that the device is configured to include a thin film transistor having a polarity, and other auxiliary equipment is provided as appropriate. By forming the driver circuit and the pixel section on the same substrate, the manufacturing cost can be reduced. This reduces costs and enables the realization of a computer having thin film transistors with excellent electrical properties.

[0271] FIG. 24A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0272] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0273] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0274] FIG. 24B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0275] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0276] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0277] FIG. 25(A) shows an example of a mobile phone 1000 different from the mobile phone shown in FIG. 23(C). The mobile phone 1000 includes a display unit 1002 built into a housing 1001, Operation buttons 1003, external connection port 1004, speaker 1005, microphone 1006, etc. It is equipped with:

[0278] In the mobile phone 1000 shown in FIG. 25A, when the display unit 1002 is touched with a finger or the like, You can also make calls or send e-mails using the display. This can be done by touching 1002 with a finger or the like.

[0279] The screen of the display unit 1002 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0280] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main input mode is the character input mode, and the input operation of the characters displayed on the screen can be performed. In this case, it is possible to display a keyboard or number buttons on most of the screen of the display unit 1002. preferable.

[0281] In addition, the mobile phone 1000 includes a sensor for detecting tilt, such as a gyro sensor or an acceleration sensor. By providing a detection device having the above, the orientation of the mobile phone 1000 (portrait or landscape) can be determined, The screen display on the display unit 1002 can be automatically switched.

[0282] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. The type of image displayed on the display unit 1002 can be selected by operating the operation button 1003. For example, the image signal to be displayed on the display unit may be changed by If the data is text data, the mode switches to input mode.

[0283] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays the If there is no input by touch operation on the display unit 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the display mode to the display mode.

[0284] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0285] FIG. 25B is also an example of a mobile phone. The mobile phone in FIG. 25B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 and a housing 9421 An operation button 9422, an external input terminal 9423, a microphone 9424, a speaker 9405, and The communication device 9420 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9420 having a telephone function in the two directions shown by the arrows. Therefore, the display device 9410 and the communication device 9420 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9420 can be attached to each other on their long axes. When only the function is required, the display device 9410 is removed from the communication device 9420, and the display device The communication device 9420 and the display device 9410 may be used alone. Images or input information can be sent and received via wireless or wired communication, and each can be recharged with a rechargeable battery. Has Terry.

[0286] (Embodiment 9) Here, a display device having a thin film transistor in which a wiring and an oxide semiconductor layer are in contact with each other is described. An example is shown in Figure 26. In Figure 26, the same reference numerals are used for the same parts as in Figure 2(A). He explains.

[0287] The first thin film transistor 480 shown in FIG. 26 is a thin film transistor used in a driving circuit. A first wiring 409 and a second wiring 410 are provided in contact with the first oxide semiconductor layer 405. The first thin film transistor 480 is provided below the oxide semiconductor layer 405. The first gate electrode 401 and the channel protection layer 418 in contact with the first oxide semiconductor layer 405 and an electrode 470 serving as a second gate electrode above the first oxide semiconductor layer 405. has.

[0288] The second thin film transistor 481 is a bottom gate type thin film transistor having a channel protection layer. A second channel protection layer 419 is provided in contact with the second oxide semiconductor layer 407. In this example, a line 410 and a third wiring 411 are provided.

[0289] In the first thin film transistor 480 and the second thin film transistor 481, a first oxide The semiconductor layer 405 is connected to the first wiring 409 and the second wiring 410, and the second oxide semiconductor The contact areas between the conductor layer 407 and the second and third wirings 410 and 411 are formed by plasma treatment. In this embodiment, before forming a conductive film to be a wiring, An oxide semiconductor layer (in this embodiment, an In-Ga-Zn-O based non-single crystal film) is grown in an argon atmosphere. The plasma treatment is carried out under atmospheric pressure.

[0290] The plasma treatment may be performed using nitrogen, helium, or the like instead of an argon atmosphere. Alternatively, the reaction may be carried out in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. The treatment may be performed in an atmosphere containing Cl2, CF4, etc.

[0291] The first oxide semiconductor layer 405 and the second oxide semiconductor layer 40 7, a conductive film is formed to form a first wiring 409, a second wiring 410, and a third wiring 411. As a result, the first oxide semiconductor layer 405, the second oxide semiconductor layer 407 and the first wiring The contact resistance between the first wiring 409, the second wiring 410, and the third wiring 411 can be reduced.

[0292] In the semiconductor device of this embodiment, the wiring and the oxide semiconductor layer are in contact with each other. The number of steps can be reduced as compared to the first embodiment.

[0293] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0294] 100 Substrates 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 107 Protective insulation layer 108 Capacitance wiring 109 Oxide semiconductor film 110 Pixel electrode 111 Second oxide semiconductor film 120 Connection electrode 121 First Terminal 122 Second Terminal 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent Conductive Film 129 Transparent conductive film 131 Resist mask 132 Conductive Film 133 Channel Protection Layer 150 Second Terminal 151 First Terminal 152 Gate Insulation Layer 153 Connection electrode 154 Protective insulating film 155 Transparent conductive film 156 Electrode 170 Thin-film transistor 400 Substrates 401 Gate electrode 402 Gate electrode 403 First gate insulating layer 404 Contact Hole 405 Oxide semiconductor layer 406a, 406b Source or drain region 407 Oxide Semiconductor Layer 408a, 408b n + layer 409 Wiring 410 Wiring 411 Wiring 412 Insulating layer 418 Channel Protection Layer 419 Second Channel Protection Layer 430 Thin Film Transistor 431 Thin Film Transistor 440 Substrate 441 Gate electrode 442 Gate electrode 443 Gate Insulation Layer 444 Contact Hole 445 Oxide Semiconductor Layer 447 Oxide Semiconductor Layer 449 Wiring 450 Wiring 451 Wiring 452 Protective layer 453 Connection Wiring 455 n+ layer 457 n+ layer 458 Channel Protection Layer 459 Channel Protection Layer 460 Thin Film Transistor 461 Thin-film transistor 480 Thin Film Transistor 481 Thin Film Transistor

Claims

1. A semiconductor device comprising first to tenth transistors, the first transistor supplies a potential of a second wiring to a first wiring when in an on state; the first transistor does not supply a potential of the second wiring to the first wiring when in an off state; the second transistor supplies a potential of a third wiring to the first wiring when in an on state; the second transistor does not supply a potential of the third wiring to the first wiring when in an off state; the third transistor supplies a potential of the second wiring to a fourth wiring when in an on state; the third transistor does not supply a potential of the second wiring to the fourth wiring when in an off state; the fourth transistor supplies a potential of the third wiring to the fourth wiring when in an on state; the fourth transistor does not supply a potential of the third wiring to the fourth wiring when in an off state; The fifth transistor has a gate to which a potential of a fifth wiring is supplied, the fifth transistor has a function of setting a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor to a potential such that the first transistor, the third transistor, and the ninth transistor are all turned on in accordance with a potential of the fifth wiring; the sixth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an on state; the sixth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an off state; The seventh transistor has a gate to which the potential of the sixth wiring is supplied, the seventh transistor supplies a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an on state; the seventh transistor does not supply a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an off state; the eighth transistor has a gate to which the potential of the fifth wiring is supplied; the eighth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an on state; the eighth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an off state; the ninth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an on state; the ninth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an off state; The tenth transistor has a gate to which the potential of the seventh wiring is supplied, the tenth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an on state; the tenth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an off state; a first conductive layer having a function as a gate of the first transistor and a gate of the third transistor overlaps with a second conductive layer having a function as one of a source or a drain of the first transistor and one of a source or a drain of the second transistor in a region separated from a semiconductor layer of the first transistor; a third conductive layer having functions as a gate of the fifth transistor and a gate of the eighth transistor overlaps with a fourth conductive layer having functions as one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and one of a source or a drain of the tenth transistor, in a region separated from a semiconductor layer of the fifth transistor.

2. A semiconductor device comprising a first transistor to a tenth transistor, the first transistor supplies a potential of a second wiring to a first wiring when in an on state; the first transistor does not supply a potential of the second wiring to the first wiring when in an off state; the second transistor supplies a potential of a third wiring to the first wiring when in an on state; the second transistor does not supply a potential of the third wiring to the first wiring when in an off state; the third transistor supplies a potential of the second wiring to a fourth wiring when in an on state; the third transistor does not supply a potential of the second wiring to the fourth wiring when in an off state; the fourth transistor supplies a potential of the third wiring to the fourth wiring when in an on state; the fourth transistor does not supply a potential of the third wiring to the fourth wiring when in an off state; The fifth transistor has a gate to which a potential of a fifth wiring is supplied, the fifth transistor has a function of setting a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor to a potential such that the first transistor, the third transistor, and the ninth transistor are all turned on in accordance with a potential of the fifth wiring; the sixth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an on state; the sixth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an off state; The seventh transistor has a gate to which the potential of the sixth wiring is supplied, the seventh transistor supplies a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an on state; the seventh transistor does not supply a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an off state; the eighth transistor has a gate to which the potential of the fifth wiring is supplied; the eighth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an on state; the eighth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an off state; the ninth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an on state; the ninth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an off state; The tenth transistor has a gate to which the potential of the seventh wiring is supplied, the tenth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an on state; the tenth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an off state; the first wiring is electrically connected to a pixel portion; the second wiring has a function of transmitting a clock signal; the third wiring has a function of transmitting a power supply potential; a first conductive layer having a function as a gate of the first transistor and a gate of the third transistor overlaps with a second conductive layer having a function as one of a source or a drain of the first transistor and one of a source or a drain of the second transistor in a region separated from a semiconductor layer of the first transistor; a third conductive layer having functions as a gate of the fifth transistor and a gate of the eighth transistor overlaps with a fourth conductive layer having functions as one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and one of a source or a drain of the tenth transistor, in a region separated from a semiconductor layer of the fifth transistor.

3. A semiconductor device comprising a first transistor to a tenth transistor, the first transistor supplies a potential of a second wiring to a first wiring when in an on state; the first transistor does not supply a potential of the second wiring to the first wiring when in an off state; the second transistor supplies a potential of a third wiring to the first wiring when in an on state; the second transistor does not supply a potential of the third wiring to the first wiring when in an off state; the third transistor supplies a potential of the second wiring to a fourth wiring when in an on state; the third transistor does not supply a potential of the second wiring to the fourth wiring when in an off state; the fourth transistor supplies a potential of the third wiring to the fourth wiring when in an on state; the fourth transistor does not supply a potential of the third wiring to the fourth wiring when in an off state; The fifth transistor has a gate to which a potential of a fifth wiring is supplied, the fifth transistor has a function of setting a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor to a potential such that the first transistor, the third transistor, and the ninth transistor are all turned on in accordance with a potential of the fifth wiring; the sixth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an on state; the sixth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an off state; The seventh transistor has a gate to which the potential of the sixth wiring is supplied, the seventh transistor supplies a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an on state; the seventh transistor does not supply a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an off state; the eighth transistor has a gate to which the potential of the fifth wiring is supplied; the eighth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an on state; the eighth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an off state; the ninth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an on state; the ninth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an off state; The tenth transistor has a gate to which the potential of the seventh wiring is supplied, the tenth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an on state; the tenth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an off state; a first conductive layer having a function as a gate of the first transistor and a gate of the third transistor overlaps with a second conductive layer having a function as one of a source or a drain of the first transistor and one of a source or a drain of the second transistor in a region separated from a semiconductor layer of the first transistor; a third conductive layer having functions as a gate of the fifth transistor and a gate of the eighth transistor overlaps with a fourth conductive layer having functions as one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and one of a source or a drain of the tenth transistor in a region separated from a semiconductor layer of the fifth transistor; A semiconductor device, wherein a fifth conductive layer having a function as a gate of the sixth transistor overlaps with a sixth conductive layer having a function as the third wiring in a region separated from a semiconductor layer of the sixth transistor.

4. A semiconductor device comprising a first transistor to a tenth transistor, the first transistor supplies a potential of a second wiring to a first wiring when in an on state; the first transistor does not supply a potential of the second wiring to the first wiring when in an off state; the second transistor supplies a potential of a third wiring to the first wiring when in an on state; the second transistor does not supply a potential of the third wiring to the first wiring when in an off state; the third transistor supplies a potential of the second wiring to a fourth wiring when in an on state; the third transistor does not supply a potential of the second wiring to the fourth wiring when in an off state; the fourth transistor supplies a potential of the third wiring to the fourth wiring when in an on state; the fourth transistor does not supply a potential of the third wiring to the fourth wiring when in an off state; The fifth transistor has a gate to which a potential of a fifth wiring is supplied, the fifth transistor has a function of setting a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor to a potential such that the first transistor, the third transistor, and the ninth transistor are all turned on, in accordance with a potential of the fifth wiring; the sixth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an on state; the sixth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an off state; The seventh transistor has a gate to which the potential of the sixth wiring is supplied, the seventh transistor supplies a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an on state; the seventh transistor does not supply a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an off state; the eighth transistor has a gate to which the potential of the fifth wiring is supplied; the eighth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an on state; the eighth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an off state; the ninth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an on state; the ninth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an off state; The tenth transistor has a gate to which the potential of the seventh wiring is supplied, the tenth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an on state; the tenth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an off state; the first wiring is electrically connected to a pixel portion; the second wiring has a function of transmitting a clock signal; the third wiring has a function of transmitting a power supply potential; a first conductive layer having a function as a gate of the first transistor and a gate of the third transistor overlaps with a second conductive layer having a function as one of a source or a drain of the first transistor and one of a source or a drain of the second transistor in a region separated from a semiconductor layer of the first transistor; a third conductive layer having functions as a gate of the fifth transistor and a gate of the eighth transistor overlaps with a fourth conductive layer having functions as one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and one of a source or a drain of the tenth transistor in a region separated from a semiconductor layer of the fifth transistor; A semiconductor device, wherein a fifth conductive layer having a function as a gate of the sixth transistor overlaps with a sixth conductive layer having a function as the third wiring in a region separated from a semiconductor layer of the sixth transistor.

5. A semiconductor device comprising a first transistor to a tenth transistor, the first transistor supplies a potential of a second wiring to a first wiring when in an on state; the first transistor does not supply a potential of the second wiring to the first wiring when in an off state; the second transistor supplies a potential of a third wiring to the first wiring when in an on state; the second transistor does not supply a potential of the third wiring to the first wiring when in an off state; the third transistor supplies a potential of the second wiring to a fourth wiring when in an on state; the third transistor does not supply a potential of the second wiring to the fourth wiring when in an off state; the fourth transistor supplies a potential of the third wiring to the fourth wiring when in an on state; the fourth transistor does not supply a potential of the third wiring to the fourth wiring when in an off state; The fifth transistor has a gate to which a potential of a fifth wiring is supplied, the fifth transistor has a function of setting a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor to a potential such that the first transistor, the third transistor, and the ninth transistor are all turned on, in accordance with a potential of the fifth wiring; the sixth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an on state; the sixth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an off state; The seventh transistor has a gate to which the potential of the sixth wiring is supplied, the seventh transistor supplies a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an on state; the seventh transistor does not supply a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an off state; the eighth transistor has a gate to which the potential of the fifth wiring is supplied; the eighth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an on state; the eighth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an off state; the ninth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an on state; the ninth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an off state; The tenth transistor has a gate to which the potential of the seventh wiring is supplied, the tenth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an on state; the tenth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an off state; a first conductive layer having a function as a gate of the first transistor and a gate of the third transistor overlaps with a second conductive layer having a function as one of a source or a drain of the first transistor and one of a source or a drain of the second transistor in a region separated from a semiconductor layer of the first transistor; a third conductive layer having functions as a gate of the fifth transistor and a gate of the eighth transistor overlaps with a fourth conductive layer having functions as one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and one of a source or a drain of the tenth transistor in a region separated from a semiconductor layer of the fifth transistor; a fifth conductive layer having a function as a gate of the sixth transistor overlaps with a sixth conductive layer having a function as the third wiring in a region separated from a semiconductor layer of the sixth transistor; A semiconductor device, wherein a seventh conductive layer having a function as a gate of the tenth transistor overlaps with the sixth conductive layer in a region separated from a semiconductor layer of the tenth transistor.

6. A semiconductor device comprising a first transistor to a tenth transistor, the first transistor supplies a potential of a second wiring to a first wiring when in an on state; the first transistor does not supply a potential of the second wiring to the first wiring when in an off state; the second transistor supplies a potential of a third wiring to the first wiring when in an on state; the second transistor does not supply a potential of the third wiring to the first wiring when in an off state; the third transistor supplies a potential of the second wiring to a fourth wiring when in an on state; the third transistor does not supply a potential of the second wiring to the fourth wiring when in an off state; the fourth transistor supplies a potential of the third wiring to the fourth wiring when in an on state; the fourth transistor does not supply a potential of the third wiring to the fourth wiring when in an off state; The fifth transistor has a gate to which a potential of a fifth wiring is supplied, the fifth transistor has a function of setting a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor to a potential such that the first transistor, the third transistor, and the ninth transistor are all turned on in accordance with a potential of the fifth wiring; the sixth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an on state; the sixth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the sixth transistor is in an off state; The seventh transistor has a gate to which the potential of the sixth wiring is supplied, the seventh transistor supplies a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an on state; the seventh transistor does not supply a potential of the sixth wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the seventh transistor is in an off state; the eighth transistor has a gate to which the potential of the fifth wiring is supplied; the eighth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an on state; the eighth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the eighth transistor is in an off state; the ninth transistor supplies a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an on state; the ninth transistor does not supply a potential of the third wiring to a gate of the second transistor, a gate of the fourth transistor, and a gate of the sixth transistor when the ninth transistor is in an off state; The tenth transistor has a gate to which the potential of the seventh wiring is supplied, the tenth transistor supplies a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an on state; the tenth transistor does not supply a potential of the third wiring to a gate of the first transistor, a gate of the third transistor, and a gate of the ninth transistor when the tenth transistor is in an off state; the first wiring is electrically connected to a pixel portion; the second wiring has a function of transmitting a clock signal; the third wiring has a function of transmitting a power supply potential; a first conductive layer having a function as a gate of the first transistor and a gate of the third transistor overlaps with a second conductive layer having a function as one of a source or a drain of the first transistor and one of a source or a drain of the second transistor in a region separated from a semiconductor layer of the first transistor; a third conductive layer having functions as a gate of the fifth transistor and a gate of the eighth transistor overlaps with a fourth conductive layer having functions as one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, and one of a source or a drain of the tenth transistor in a region separated from a semiconductor layer of the fifth transistor; a fifth conductive layer having a function as a gate of the sixth transistor overlaps with a sixth conductive layer having a function as the third wiring in a region separated from a semiconductor layer of the sixth transistor; A semiconductor device, wherein a seventh conductive layer having a function as a gate of the tenth transistor overlaps with the sixth conductive layer in a region separated from a semiconductor layer of the tenth transistor.

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