Automatic circuit generation

Abstract

To provide automatic circuit generation.SOLUTION: In some embodiments, parameters are received and a circuit schematic diagram is automatically generated by software. In some embodiments, the parameters are received and a circuit layout is automatically generated by the software. In some embodiments, a design interface may be used to generate a behavioral model of the circuit. The software can generate a circuit specification from which the schematic diagram may be generated. In various embodiments, circuit component values may be determined and generated. Certain embodiments relate to automating the circuit layout. The software may receive parameters for functional circuit components and generate the circuit schematic diagrams and / or layouts. The techniques of the present invention are particularly useful for automatically generating analog circuits.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims the benefit of priority to U.S. Patent Application No. 16 / 882,217, filed May 22, 2020, the contents of which are hereby incorporated by reference. This application further claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 854,848, filed May 30, 2019, the contents of which are hereby incorporated by reference.

[0002] TECHNICAL FIELD The present disclosure relates to electronic circuits, and more particularly to techniques for automatically generating circuit schematics and layouts. [Background technology]

[0003] Electronic circuits have become ubiquitous in modern society: from smartphones, personal computers, televisions, and many other consumer electronic devices to industrial equipment, scientific instruments, communication systems, and all aspects of the Internet, typically in the form of integrated circuits (or "chips"), and have a dramatic impact on human existence.

[0004] However, developing electronic circuits can be time-consuming and costly. Typically, a team of skilled electrical engineers and many electronic circuit specialists spends long periods of time designing circuit schematics and laying out the circuit to form a chip with the desired functionality. The schematic may include each transistor in the circuit along with the connections between the transistors. The schematic can be used to simulate how the electronic circuit will operate to ensure proper functionality. The transistors are then laid out as geometric shapes. A layout (sometimes called a "mask design") is a representation of an integrated circuit in terms of planar geometric shapes that may correspond to the physical aspects of the circuit that will be generated in silicon (e.g., on a wafer that is subsequently cut into individual chips). For example, the layout may represent the patterns of metal, oxide, or semiconductor layers that make up the physical components of the integrated circuit.

[0005] Designing a circuit schematic and generating a layout for an entire electronic circuit can be a tedious and time-consuming process. For analog circuits in particular, transistor-level schematics are typically prepared by experienced, skilled analog circuit design specialists. Designing a schematic from scratch can take several months, depending on the complexity of the circuit. Once the design is generated, the analog circuit design specialist typically collaborates with a layout specialist to generate the layout. The layout process can also take weeks or even months. Summary of the Invention [Problem to be solved by the invention]

[0006] The discovery of techniques for automatically generating schematics and layouts can reduce chip development cycle times, streamline the development process, and offer a wide range of other potential benefits. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 illustrates a system for automatic circuit generation according to one embodiment. [Figure 2] FIG. 1 illustrates a method for automatic circuit generation according to one embodiment. [Figure 3A] FIG. 1 illustrates an example of automatic circuit schematic generation according to various embodiments. [Figure 3B] FIG. 1 illustrates an example of automatic circuit schematic generation according to various embodiments. [Figure 3C] FIG. 1 illustrates an example of automatic circuit schematic generation according to various embodiments. [Figure 3D] FIG. 1 illustrates an example of automatic circuit schematic generation according to various embodiments. [Figure 4A] FIG. 10 illustrates an example of automatic circuit schematic generation according to yet another embodiment. [Figure 4B] FIG. 10 illustrates an example of automatic circuit schematic generation according to yet another embodiment. [Figure 4C] FIG. 10 illustrates an example of automatic circuit schematic generation according to yet another embodiment. [Figure 4D] FIG. 10 illustrates an example of automatic circuit schematic generation according to yet another embodiment. [Figure 5] FIG. 2 illustrates exemplary functional blocks of a generator according to an embodiment. [Figure 6A] FIG. 10 is another exemplary block diagram of an automatic circuit generator according to another embodiment. [Figure 6B] 1A-1C illustrate an exemplary process for automatically generating a circuit according to an embodiment. [Figure 7A] 10A-10C illustrate examples of pin mapping steps according to one embodiment. [Figure 7B] 10A-10C illustrate examples of pin mapping steps according to one embodiment. [Figure 8] FIG. 1 illustrates a system for automatic circuit generation according to another embodiment. [Figure 9] FIG. 1 illustrates a method for automatic circuit generation according to one embodiment. [Figure 10A] FIG. 1 illustrates an example of automatic circuit layout generation according to various embodiments. [Figure 10B]FIG. 1 illustrates an example of automatic circuit layout generation according to various embodiments. [Figure 10C] FIG. 1 illustrates an example of automatic circuit layout generation according to various embodiments. [Figure 10D] FIG. 1 illustrates an example of automatic circuit layout generation according to various embodiments. [Figure 11A] FIG. 10 illustrates an example of automatic circuit layout generation according to yet another embodiment. [Figure 11B] FIG. 10 illustrates an example of automatic circuit layout generation according to yet another embodiment. [Figure 11C] FIG. 10 illustrates an example of automatic circuit layout generation according to yet another embodiment. [Figure 11D] FIG. 10 illustrates an example of automatic circuit layout generation according to yet another embodiment. [Figure 12A] FIG. 10 illustrates an example of generating a circuit layout according to one embodiment. [Figure 12B] FIG. 10 illustrates another example of generating a circuit layout according to one embodiment. [Figure 13A] 1A-1C illustrate exemplary circuit layouts generated from different parameters and placement instructions according to an embodiment. [Figure 13B] FIG. 10 illustrates another exemplary combination of parameter values ​​and placement instructions according to another embodiment. [Figure 14] FIG. 10 illustrates another example of generating a circuit layout using a rotated layout placement instruction according to an embodiment. [Figure 15] FIG. 10 illustrates another example of generating a circuit layout using layout placement instructions according to an embodiment. [Figure 16] FIG. 1 illustrates another exemplary design interface according to an embodiment. [Figure 17] FIG. 1 illustrates an exemplary design and automatic circuit generation process according to another embodiment. [Figure 18] FIG. 1 illustrates an exemplary design and automatic circuit generation system according to another embodiment. [Figure 19] FIG. 1 illustrates symbols for different functional circuit components according to an embodiment. [Figure 20A] FIG. 20 illustrates an exemplary generator software system 2001 according to one embodiment. [Figure 20B] FIG. 1 illustrates an exemplary method for generating circuit specifications according to an embodiment. [Figure 20C] FIG. 1 illustrates an exemplary method for generating circuit specifications according to another embodiment. [Figure 21A] FIG. 1 illustrates a method for generating circuit components over a range of values ​​according to one embodiment. [Figure 21B] FIG. 10 illustrates a method for generating circuit components over a range of values ​​according to another embodiment. [Figure 21C] FIG. 10 illustrates a method for generating circuit components over a range of values ​​according to yet another embodiment. [Figure 22] FIG. 1 illustrates a computer-implemented system for automatically generating resistors according to an embodiment. [Figure 23] FIG. 1 illustrates a method for generating a resistor according to an embodiment. [Figure 24] FIG. 10 illustrates a method for generating a resistor according to another embodiment. [Figure 25A] FIG. 10 illustrates a method for generating a resistor according to yet another embodiment. [Figure 25B] FIG. 10 illustrates a method for generating a resistor according to yet another embodiment. [Figure 25C] FIG. 10 illustrates a method for generating a resistor according to yet another embodiment. [Figure 26] 1A-1C illustrate exemplary resistor wiring diagrams and layouts according to embodiments. [Figure 27A] 10A-10C illustrate example layouts generated for two resistor values ​​used with two different circuits according to an embodiment. [Figure 27B] FIG. 10 illustrates two resistor values ​​used with the same circuit according to an embodiment. [Figure 28] 10A-10C illustrate example layouts generated for resistor values ​​for different subcircuit configurations according to an embodiment. [Figure 29] 1A and 1B illustrate exemplary layouts of resistor segments according to embodiments. [Figure 30] FIG. 10 illustrates another exemplary layout of resistor segments according to an embodiment. [Figure 31] FIG. 10 illustrates resistor attribute passing according to an embodiment. [Figure 32] FIG. 10 illustrates passing resistor attributes to a wiring diagram according to another embodiment. [Figure 33] FIG. 10 illustrates the generation of a resistor specified in a user interface according to an embodiment. [Figure 34] 10A-10C illustrate exemplary layouts of resistors specified within a user interface according to an embodiment. [Figure 35] FIG. 10 illustrates the generation of resistors based on circuit parameters specified in a user interface according to an embodiment. [Figure 36] 10A-10C illustrate exemplary layouts of resistors determined from parameters according to embodiments. [Figure 37A] FIG. 1 illustrates the generation of a resistor divider according to an embodiment. [Figure 37B] FIG. 1 illustrates the generation of a resistor divider according to an embodiment. [Figure 37C] FIG. 1 illustrates the generation of a resistor divider according to an embodiment. [Figure 38A] FIG. 10 illustrates a method for generating a resistor divider including sub-circuits according to another embodiment. [Figure 38B] 1A-1C illustrate various embodiments of resistor dividers with different switch configurations. [Figure 39] FIG. 1 illustrates a computer-implemented system for automatically generating a capacitor, according to an embodiment. [Figure 40A] FIG. 1 illustrates a method for generating a capacitor according to an embodiment. [Figure 40B] FIG. 1 illustrates an exemplary technique for determining capacitor dimensions, according to an embodiment. [Figure 41A]FIG. 1 illustrates an exemplary capacitor diagram generation according to an embodiment. [Figure 41B] FIG. 1 illustrates an exemplary capacitor diagram generation according to an embodiment. [Figure 41C] FIG. 1 illustrates an exemplary capacitor diagram generation according to an embodiment. [Figure 42] 1A-1C illustrate exemplary capacitor layouts in accordance with various embodiments. [Figure 43] FIG. 10 illustrates the generation of a capacitor specified in a user interface according to an embodiment. [Figure 44] 10A-10C further illustrate exemplary layouts of capacitors determined from parameters according to embodiments. [Figure 45] FIG. 1 illustrates automatic generation of transistors according to an embodiment. [Figure 46] 1 is a flow diagram for automatically generating transistors according to an embodiment. [Figure 47A] 1A-1C illustrate example transistors generated with different parameters according to various embodiments. [Figure 47B] 1A-1C illustrate example transistors generated with different parameters according to various embodiments. [Figure 47C] 1A-1C illustrate example transistors generated with different parameters according to various embodiments. [Figure 47D] 1A-1C illustrate example transistors generated with different parameters according to various embodiments. [Figure 47E] 1A-1C illustrate example transistors generated with different parameters according to various embodiments. [Figure 47F] 1A-1C illustrate example transistors generated with different parameters according to various embodiments. [Figure 48A] FIG. 10 illustrates another example transistor generated from another set of parameter values ​​according to an embodiment. [Figure 48B]FIG. 10 illustrates another example transistor generated from another set of parameter values ​​according to yet another embodiment. [Figure 49A] FIG. 1 illustrates an exemplary method for generating a transistor according to another embodiment. [Figure 49B] FIG. 2 illustrates an exemplary method for converting a specified value of on-resistance (Ron) to gate width according to an embodiment. [Figure 50] FIG. 5 illustrates the generation of a transistor with a replicated device 5001 according to an embodiment. [Figure 51] FIG. 1 illustrates the generation of a transistor with a Kelvin connection according to an embodiment. [Figure 52A] FIG. 10 is a diagram illustrating an example of automatically generating a transistor layout according to an embodiment. [Figure 52B] FIG. 10 illustrates how increasing the number of fingers can change the aspect ratio of a transistor layout. [Figure 53A] FIG. 2 illustrates an array of transistor device cell layout instances configured to form a transistor according to an embodiment. [Figure 53B] FIG. 2 illustrates an array of transistor device cell layout instances configured to form a transistor according to an embodiment. [Figure 54] FIG. 1 illustrates the generation of a layout for a transistor according to one embodiment. [Figure 55] FIG. 1 illustrates the generation of a layout for a transistor according to one embodiment. [Figure 56A] FIG. 1 illustrates automatic placement of layout instances to form a transistor according to an embodiment. [Figure 56B] 3 shows vertical strips of metal layer 3 according to an embodiment. FIG. [Figure 57] FIG. 1 illustrates layout generation according to an embodiment. [Figure 58] FIG. 1 illustrates an exemplary system including an automatic layout generator according to an embodiment. [Figure 59]FIG. 1 illustrates the conversion of a circuit schematic diagram into layout instances and the generation of a layout according to an embodiment. [Figure 60] FIG. 1 illustrates a layout script according to an embodiment. [Figure 61] 10A-10C illustrate exemplary placement operations of layout placement instructions according to an embodiment. [Figure 62] FIG. 10 illustrates yet another example of layout generation according to yet another embodiment. [Figure 63A] 10A-10C illustrate exemplary types of stages that may be used for various layout placement instructions according to various embodiments. [Figure 63B] FIG. 10 illustrates additional parameters used in some layout placement instructions according to an embodiment. [Figure 63C] FIG. 10 illustrates additional parameters used in some layout placement instructions according to an embodiment. [Figure 64] FIG. 10 illustrates additional parameters used in some layout placement instructions according to various embodiments. [Figure 65] FIG. 1 illustrates a process for conditional layout placement instructions according to an embodiment. [Figure 66] FIG. 10 illustrates another layout placement instruction for incorporating transistors into a layout according to an embodiment. [Figure 67] FIG. 1 illustrates exemplary computer system hardware in accordance with certain embodiments. [Figure 68] FIG. 1 illustrates various computer system configurations that can be used in certain embodiments. [Figure 69] 1A to 1C are diagrams illustrating steps for making a circuit according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] This specification describes techniques for automatic circuit generation. For example, integrated circuits can be fabricated using some or all of the techniques described herein. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure, as expressed in the claims, can include some or all of the features in these examples, alone or in combination with other features described below, and can include modifications and equivalents of the features and concepts described herein.

[0009] In various embodiments and combinations, the following disclosure describes techniques for automatically generating electronic circuits using software. Some embodiments described below can generate circuit schematics or circuit layouts, or both, in response to parameters. For example, the parameters can specify various circuit characteristics, and the software system can generate circuit schematics or circuit layouts, or both, for a wide range of circuits based on these parameters. In some embodiments described herein, a design interface can allow a user to define the circuit to be generated by selecting functional circuit components and specifying parameters. For example, in some embodiments, the design interface can be a high-level representation of the circuit, such as a behavioral-level representation, which may require less knowledge or experience in circuit design techniques than might be required to define a transistor-level schematic. That is, in some exemplary embodiments, a user with much less or only minimal circuit design knowledge or experience can define the circuit, and the computer software can generate the circuit schematics or circuit layouts, or both, in response to input from a less skilled or inexperienced user. Additionally, circuit schematic design and layout development cycle times, which can be lengthy using conventional methods, can be dramatically reduced using the automated circuit design techniques described herein. The techniques of the present invention are particularly advantageous in the field of analog circuit design. Below, various innovations are disclosed for use in various embodiments of the present disclosure. For example, the innovations disclosed below can be implemented according to various embodiments, either alone or in various combinations with other innovations described herein, and used as part of a process for creating integrated circuits.

[0010] Parameterized circuit diagram generation FIG. 1 illustrates a system for automated circuit generation according to one embodiment. Features and advantages of the present disclosure include a system that can automatically generate a circuit diagram based on input parameters, e.g., different parameter values ​​can automatically generate different circuit diagrams. As shown in FIG. 1, a generator software system 102 can receive parameters 104 to generate a circuit diagram 103. The generator software system 102 can execute on at least one computer system, for example, and can include computer code that, when executed by one or more computers, causes the computer to perform operations to implement the techniques described herein. For example, parameters can be received in various data formats as information specifying the circuit to be generated in the generator 102.

[0011] For example, parameters 104 may include a plurality of circuit specification parameters corresponding to at least one functional circuit component 101. For example, the circuit specification parameters may specify characteristics of a circuit to be generated. For example, in some exemplary embodiments, the circuit specification parameters may be variables having specific values. As illustrated in more detail below, the circuit specification parameters may specify electrical properties (e.g., voltage or current) of a circuit to be generated, or may specify physical properties (e.g., whether an input uses an N-type transistor or a P-type transistor, or the physical structure of a capacitor or the physical structure of a resistor) of a circuit to be generated. In some embodiments, the circuit specification parameters may correspond to a particular functional circuit component, such as functional circuit component 101. For example, in various embodiments, the functional circuit component may be an analog functional circuit component. For example, one set of circuit specification parameters may correspond to one functional circuit component (e.g., a comparator), while another set of parameters may correspond to a different functional circuit component (e.g., a delay circuit or an oscillator). Thus, a comparator may have a different parameter set than an oscillator, but in some embodiments, separate parameter sets for different functional circuit components may have one or more of the same individual parameters (e.g., parameters specifying an input stage type or a supply voltage value). Parameters 104 may be implemented using a variety of techniques. In some embodiments, circuit specification parameters may be received as text specifying, for example, variable names and values. In other embodiments, for example, circuit specification parameters may be implemented as code (e.g., digital code values ​​or a wide variety of other encoding techniques) to specify characteristics of a circuit to be generated to embody functional circuit component 101. It is to be understood that a variety of encoding techniques may be used to embody circuit specification parameters that specify characteristics of a circuit to be generated.

[0012] Parameters 104 are received by generator 102. Generator 102 can select (i.e., determine or otherwise identify) multiple sub-circuit schematics 110-112 based on the circuit specification parameters. For example, one set of values ​​(or coding) for the received circuit specification parameters can result in the selection of sub-circuit schematic 110 and sub-circuit schematic 111. For example, another set of values ​​(or another coding) for the received circuit specification parameters can result in the selection of sub-circuit schematic 110, sub-circuit schematic 111, and sub-circuit schematic 112. Once the appropriate sub-circuit schematics have been selected, the identified sub-circuit schematics can be combined to form circuit schematic 103. Circuit schematic 103 thus implements functional circuit components 101 having the characteristics specified by parameters 104.

[0013] While the following disclosure describes combining subcircuit diagrams, it is understood that other subcircuit models may be used in other embodiments. Typically, a circuit diagram refers to a model that represents the connections of components (e.g., transistors, resistors, capacitors, and inductors) used with the circuit. The embodiments described herein may not be limited to, for example, the particular modeling techniques used to represent the subcircuits and circuits.

[0014] Disclosed embodiments of the present invention can be particularly advantageous for generating analog circuit schematics. Analog circuits differ from digital circuits in that digital circuits process binary voltages (representing zeros and ones) using simple logic circuits with transistors that are substantially either fully on or fully off, whereas analog circuits typically include circuits with transistors that can operate over a range between fully on and fully off (e.g., over a linear range). For example, analog circuits can perform a wide range of operations depending on the specific voltages and currents within the circuit, and components within the system (e.g., capacitors, transistors, resistors, inductors) operate over a range of voltages or currents. A subset of analog circuits is mixed-signal circuits. Mixed-signal circuits are analog circuits that include some digital circuitry integrated with and cooperating with the analog circuitry. For example, mixed-signal circuits must be distinguished from digital circuits that are not integrated with and / or perform functions substantially independently of the analog circuitry. The distinction between analog circuit design (e.g., analog / mixed-signal circuit design) and digital circuit design is well known by those skilled in the art.

[0015] Disclosed embodiments of the present invention can be used, for example, to automatically generate analog circuit schematics and / or circuit layouts based on circuit specification parameters. As described above, the circuit specification parameters can correspond to one or more functional analog circuits, such as a comparator, an oscillator, or a delay. For example, the circuit specification parameters can specify characteristics of the circuit to be generated, such as a comparator with a P-type input or an N-type input. In some exemplary applications, the circuit specification parameters can be used to select predetermined subcircuit schematics corresponding to particular functional analog circuit components. For example, as illustrated in the more detailed examples below, the generator 102 can select a predetermined P-type comparator subcircuit schematic, a first predetermined hysteresis subcircuit schematic, and a predetermined deglitch subcircuit schematic based on one set of parameters to create a schematic for a comparator functional circuit component having one set of characteristics, and can select a predetermined N-type comparator subcircuit schematic and another predetermined hysteresis subcircuit schematic using another set of parameters to create a schematic for a comparator functional circuit component having another set of characteristics.

[0016] FIG. 2 illustrates a method for automatic circuit generation according to one embodiment. The method may be implemented, for example, by software executing on one or more computers. At 201, a plurality of circuit specification parameters corresponding to at least one functional circuit component are received. The circuit specification parameters may be represented in various ways, such as textual variables and values ​​or as code. As described above, the received parameters may include one or more parameter sets for different functional analog circuit components (e.g., one parameter set corresponding to a first functional analog circuit component, another parameter set corresponding to a second functional analog circuit component). At 202, a particular subcircuit diagram is selected based on the circuit specification parameters. In one embodiment, different functional circuit components may have different predetermined subcircuit diagram sets. The selection may include selecting a predetermined subcircuit diagram subset corresponding to the functional circuit component based on the circuit specification parameters. For example, a comparator may have an N-type comparator subcircuit diagram, a P-type comparator subcircuit diagram, and various other subcircuit diagrams in the circuit diagram set corresponding to the comparator functional circuit component. For example, a P-type subcircuit diagram can be selected based on one or more parameters having specific values, and an N-type subcircuit diagram can be selected based on one or more parameters having different values. At 203, the software system can combine the selected subcircuit diagrams to form a diagram for the functional circuit component. The subcircuit diagrams can be in the form of functional component-level circuit blocks (or designs) having various input and output terminals (or pins) therein. Thus, for example, combining can include coupling pins between the subcircuit diagrams and / or coupling pins of the subcircuit diagrams to other pins of other circuit diagrams. Examples of pin coupling between the subcircuit diagrams are illustrated in more detail below.

[0017] 3A-3D illustrate examples of automatic circuit schematic generation according to various embodiments. As illustrated in various examples below, specific values ​​for a circuit specification parameter set can correspond to a specific instance of a specific functional circuit component (e.g., a comparator with specific characteristics to be generated). For example, there may be many identical functional circuit components with different circuit specification parameters corresponding to different circuit designs formed from different selected subcircuits. In certain embodiments, different values ​​for a circuit specification parameter set can generate different analog circuit schematics with different electrical characteristics for a corresponding functional circuit component. For example, parameter 302 corresponding to functional circuit component 303 can be encoded with different values. In this example, a set of N parameters (where N is an integer) is illustrated as variables a1, a2, a3, ..., aN having a first set of values ​​[a1=x1, a2=x2, a3=x3, ..., aN=xN]. Generator software 301 receives parameters 302 having a first set of values ​​and selects a subset of subcircuit schematics 310-315. The selected sub-circuit diagrams are combined to form a diagram for functional circuit component 303 according to the received parameters. In this example, the first set of parameter values ​​results in sub-circuit diagrams 310-312 being selected and combined to form circuit diagram 303A.

[0018] 3B shows parameter 302 having a second set of values ​​[a1=x1, a2=x2, a3=y3, ..., aN=xN]. Here, parameter a3 changes its value from x3 to y3. Accordingly, the selected subcircuit diagram changes. In this example, when a3=y3, subcircuit diagram 312 is no longer selected for inclusion in circuit diagram 303B along with subcircuit diagrams 310 and 311.

[0019] 3C shows parameters 302 having a third set of values ​​[a1=y1, a2=x2, a3=x3, ..., aN=xN]. Here, parameter a1 changes its value from x1 to y1, and parameter a3=x3. Therefore, again, the selected subcircuit diagram changes. In this example, when a1=y1, subcircuit diagram 310 is no longer selected. Instead, subcircuit diagram 313 is selected and included in circuit diagram 303C along with subcircuit diagrams 311 and 312.

[0020] 3D shows parameters 302 having a fourth set of values ​​[a1=y1, a2=y2, a3=x3, ..., aN=xN], where parameters a1 and a2, having values ​​of y1 and y2, respectively, result in sub-circuit diagram 314 being selected for inclusion in circuit diagram 303D along with sub-circuit diagrams 311 and 312.

[0021] Features and advantages of some embodiments of the present disclosure include receiving circuit specification parameters corresponding to multiple functional circuit components and automatically generating circuit schematics that implement each functional circuit component based on these parameters. FIGS. 4A-4D illustrate different parameter sets (or encodings) that generate different circuit schematics for different functional circuit components, according to embodiments. Referring to FIG. 4A, in this example, a generator software system 401 receives parameters 450 corresponding to multiple functional circuit components 402-405 (components C1, C2, C3, C4, and so on through C-N, where N is an integer corresponding to the number of different functional circuit components). C1-C-N can be, for example, comparators, oscillators, delay circuits, current generators, voltage references, or a wide variety of other analog functional circuit components used with analog circuits. In this example, generator 401 can receive N sets of circuit specification parameters, where each different functional circuit component has a corresponding set of circuit specification parameters. In particular, for example, where N is an integer representing the number of functional circuit components for which a corresponding schematic diagram is being generated, a first parameter set 451, C1_Params, corresponds to component C1 402, a second parameter set 452, C2_Params, corresponds to component C2 403, a third parameter set 453, C3_Params, corresponds to component C3 404, and so on until a final parameter set 454, CN_Params, also corresponds to component CN 405. Each parameter set 451-454 can have different parameter values ​​and thereby specify characteristics of the circuit schematic to be generated. In this example, parameter 451 has a first set of values, in this case designated "C1_Params_1." Similarly, parameter 452 has a first value set "C2_Params_1," parameter 453 has a first value set "C3_Params_1," and so on up to parameter 454, which also has the value "CN_Params_1."

[0022] 4A-4D show an example illustrating that different circuit specification parameters 450 for different corresponding functional circuit components can have different corresponding predetermined subcircuit schematic sets. For example, predetermined analog subcircuits can be stored in library 460 shown in FIG. 4A. In this example, there are multiple subcircuit sets 410, 420, 430, and 440 corresponding to different functional circuit components 402, 403, 404, and 405. Thus, for example, C1_Params 451 corresponding to functional circuit component 402 (C1) can be used to select subcircuit schematics from C1 subcircuit set ("C1_SC_Set") 410, which includes analog subcircuit schematics 411-416. Similarly, for example, C2_Params 452 corresponding to functional circuit component 403 (C2) can be used to select subcircuit schematics from C2 subcircuit set ("C2_SC_Set") 420, which includes analog subcircuit schematics 421-427. Similarly, C3_Params 453 corresponding to functional circuit component 404 (C3) can be used to select a subcircuit diagram from the C3 subcircuit diagram set ("C3_SC_Set") 430, and so on through CN_Params 454 corresponding to functional circuit component 405 (CN), which can also be used to select a subcircuit diagram from the CN subcircuit diagram set ("CN_SC_Set") 440 (subcircuit not shown).

[0023] Parameters 451-454 can have different values ​​that result in different combinations of corresponding sub-circuits. In this example, each parameter set 451-454 receives a first set of parameter values ​​(e.g., specific values ​​are denoted herein using "_1," "_2," etc.). For example, the first set of values ​​for circuit specification parameter 451 is denoted as C1_Params_1, the first set of values ​​for circuit specification parameter 452 is denoted as C2_Params_1, and so on. In this example, generator 401 receives parameter value C1_Params_1 and combines sub-circuit schematics C1_SC1 411, C1_SC2 412, and C1_SC3 413 from C1_SC_Set 410 to generate analog circuit schematic 406A corresponding to functional circuit component C1 402. Similarly, generator 401 receives parameter values ​​C2_Params_1 and combines partial circuit schematics C2_SC1 421, C2_SC2 422, C2_SC3 423, and C2_SC4 424 from C2_SC_Set 420 to generate analog circuit schematic 407A corresponding to functional circuit component C2 403. Similarly, generator 401 receives parameter values ​​C3_Params_1 and combines partial circuit schematics (not shown) from C3_SC_Set 430 to generate analog circuit schematic 408A corresponding to functional circuit component C3 404. Analog circuit schematic 408A includes a first subset (C3_SC SubsetA) 431A of partial circuit schematics from C3_SC_Set 430. Finally, generator 401 receives parameter values ​​CN_Params_1 and combines partial circuit schematics (not shown) from CN_SC_Set 440 to generate analog circuit schematic 409A corresponding to functional circuit component CN 405. Analog circuit schematic 409A includes a first subset (CN_SC SubsetB) of partial circuit schematics from CN_SC_Set 440.

[0024] 4B illustrates the generation of another circuit using another parameter set according to an embodiment. In this example, parameter sets 451-454 receive different sets of parameter values. For example, a new set of values ​​for circuit specification parameters 451 is denoted as C1_Params_2, a new set of values ​​for circuit specification parameters 452 is denoted as C2_Params_2, and so on. In this example, generator 401 receives parameter values ​​C1_Params_2 and generates analog circuit schematic 406B corresponding to functional circuit component C1 402 by combining subcircuits C1_SC4 414, C1_SC2 412, and C1_SC3 413 from C1_SC_Set 410. Similarly, generator 401 receives parameter values ​​C2_Params_2 and combines sub-circuits C2_SC5 425, C2_SC6 426, C2_SC3 423, and C2_SC4 424 from C2_SC_Set 420 to generate analog circuit schematic 407B corresponding to functional circuit component C2 403. Similarly, generator 401 receives parameter values ​​C3_Params_2 and combines a sub-circuit (not shown) from C3_SC_Set 430 to generate analog circuit schematic 408B corresponding to functional circuit component C3 404. Analog circuit schematic 408B includes a second subset (C3_SC SubsetA′) 431B of sub-circuit schematics from C3_SC_Set 430. Finally, generator 401 receives parameter values ​​CN_Params_2 and combines subcircuits (not shown) from CN_SC_Set 440 to generate analog circuit schematic 409B corresponding to functional circuit component CN 405. Analog circuit schematic 409B includes a second subset (CN_SC SubsetB') 441B of subcircuit schematics from CN_SC_Set 440.

[0025] 4C illustrates the generation of yet another circuit using yet another parameter set, according to an embodiment. In this example, each parameter set 451-454 receives a third set of parameter values. For example, the new set of values ​​for circuit specification parameters 451 is denoted as C1_Params_3, the new set of values ​​for circuit specification parameters 452 is denoted as C2_Params_3, and so on. In this example, generator 401 receives parameter values ​​C1_Params_3 and generates analog circuit schematic 406C corresponding to functional circuit component C1 402 by combining subcircuits C1_SC4 414 and C1_SC2 412 from C1_SC_Set 410. Similarly, generator 401 receives parameter values ​​C2_Params_3 and combines sub-circuits C2_SC5 425, C2_SC6 426, C2_SC3 423, and C2_SC7 427 from C2_SC_Set 420 to generate analog circuit schematic 407C corresponding to functional circuit component C2 403. Similarly, generator 401 receives parameter values ​​C3_Params_3 and combines a sub-circuit (not shown) from C3_SC_Set 430 to generate analog circuit schematic 408C corresponding to functional circuit component C3 404. Analog circuit schematic 408C includes a third subset (C3_SC SubsetA'') 431C of sub-circuit schematics from C3_SC_Set 430. Finally, generator 401 receives parameter value CN_Params_3 and combines subcircuits (not shown) from CN_SC_Set 440 to generate analog circuit schematic 409C corresponding to functional circuit component CN 405. Analog circuit schematic 409C includes a third subset (CN_SC SubsetB'') 441C of subcircuit schematics from CN_SC_Set 440.

[0026] FIG. 4D illustrates an embodiment in which different subcircuit sets for different functional circuit components can include the same subcircuits. For example, in some embodiments, different functional circuit components can have corresponding unique predetermined subcircuit schematic sets. Referring to FIG. 4A, subcircuit set C1_SC_Set 410 can be a different subcircuit schematic set than C2_SC_Set 420 or C3_SC_Set 430. In particular, subcircuits combined to form different comparators can be different from subcircuits combined to form different oscillators or different delay circuits, for example. Thus, each functional circuit component can have a corresponding unique subcircuit schematic set. However, in various embodiments, these sets can be unique, but one or more subcircuit schematics within some sets can be shared. For example, a subcircuit schematic set for a comparator can access a resistor divider subcircuit, which can be associated with a subcircuit set for an oscillator, for example. Thus, a unique set can include one or more unique predetermined analog subcircuit diagrams used only for the corresponding functional circuit component, or alternatively, can include one or more predetermined analog subcircuit diagrams used for multiple corresponding functional circuit components. This is illustrated in Figure 4D, where subcircuit diagram C1-2 SC 417 is included in sets C1_SC_Set 410 and C2_SC_Set 420. Thus, for example, parameters 451 and 452 for components C1 and C2, respectively, can generate circuit diagrams 406D and 407D, both of which include C1-2 SC 417.

[0027] FIG. 5 illustrates exemplary functional blocks of a generator according to an embodiment. As described above, in certain exemplary embodiments, generator 501 can receive circuit specification parameters corresponding to different types of functional analog circuit components (e.g., C1, C2, C3, ..., C-N). For example, these parameters can specify characteristics of a circuit to be generated using a predetermined analog subcircuit schematic. Thus, once received by generator 501, the parameters can be analyzed by function determination block 502, which determines which functional component the parameters correspond to. Block 502 can receive a set of parameters, determine the appropriate corresponding functional circuit component (here, C1, C2, C3, ..., C-N, e.g., comparator, oscillator, delay, etc.), and access one of different rule sets 510-511 to further process the parameters. Block 502 and rule set blocks 510-511 described above and in further examples below can be implemented, for example, in software code or, for example, as a combination of software code and imported data (e.g., data regarding parameters, different rules, subcircuits, circuit combinations, etc.).

[0028] For example, in some embodiments, multiple circuit diagrams, such as one or more of diagrams 406A-406D, 407A-407D, 408A-408D, and 409A-409D for different functional components, can be combined together in various combinations into a diagram for a circuit including multiple parameterized instances of the functional circuit components. A circuit diagram can include a diagram for functional circuit component C1 402 based on one parameter set (e.g., circuit diagram 406D), a diagram for functional circuit component C2 403 based on one parameter set (e.g., circuit diagram 407C), a diagram for functional circuit component C3 404 based on one parameter set (e.g., circuit diagram 408D), and a diagram for functional circuit component CN 405 based on one parameter set (e.g., circuit diagram 409B). Alternatively, a combination of parameters and functional circuit components can generate a schematic diagram that includes a schematic diagram for functional circuit component C1 402 (e.g., circuit schematic 406B) based on another parameter set, but does not include a schematic diagram for functional circuit component C2 403 (e.g., does not include C2), and a schematic diagram for functional circuit component C3 404 (e.g., circuit schematic 408C) based on another parameter set, but does not include a schematic diagram for functional circuit component CN 405 (e.g., does not include CN). Any combination of parameters for different instantiations of functional circuit components can be used to automatically generate schematic diagrams having various combinations of one or more of the same or different functional circuit components, for example. In some embodiments, the schematic diagrams can be used to simulate an entire chip of functional circuit components coupled together.Optionally, for example, the circuit schematic can be processed by an electronic design automation (EDA) software system, such as a transistor schematic layout editing tool (e.g., Cadence®, Mentor Graphics®, or Silvaco®), to generate a layout and perform layout-to-schematic ("LVS") and / or design rule checking ("DRC"), and sent to a manufacturing facility (e.g., semiconductor fabrication or "FAB") to produce integrated circuits (e.g., chips) with desired characteristics. Typically, designing a schematic for an analog integrated circuit can require a large amount of time and effort from analog circuit design experts. Advantageously, systems and methods employing the techniques described herein can generate schematics for electronic circuits (e.g., complete chips) very quickly, and in substantially less time than would be required to design each circuit using conventional techniques.

[0029] Generator 501 can analyze the parameters to determine the corresponding rule set to use. For example, one rule set may be appropriate if the parameters include one or more particular variables or values, and another rule set may be appropriate if the parameters include one or more other particular variables or values. In some embodiments, the parameters may include information specifying a functional circuit component. For example, the parameters received by generator 501 may include text specifying the functional circuit component (e.g., “comparator,” “oscillator,” or “voltage reference”) or one or more identifiers (IDs), such as one or more codes to uniquely determine the rule set to use for the corresponding functional circuit component. In other embodiments, for example, the presence of a particular parameter in a parameter set may be used to determine which functional circuit component such parameter is for and which sub-circuit set to select.

[0030] In this example, there are N different rule set blocks 510-511 corresponding to N different functional circuit component types (where N is an integer, e.g., 3, 4, 5, etc.). Parameters corresponding to different functional circuit components can have corresponding rule sets. For example, parameters 451 for C1 can be processed using a first rule set, parameters for C2 can be processed using a second rule set, parameters for C3 can be processed using a third rule set, and so on up to parameters for C N, which can also be processed using the Nth rule set. As an example, different rule sets can be configured to perform some or all of the processing, such as analyzing parameter values, selecting appropriate sub-circuit sets (e.g., for each functional circuit component), and combining the sub-circuits to form a circuit diagram for the corresponding functional circuit component. Referring again to FIG. 5, C1_Params_1 invokes one rule set to select sub-circuits 411, 412, and 413 from set 410 that, when combined, form circuit diagram 406A. Similarly, C2_Params_1 invokes a second set of rules to select sub-circuits 421, 422, 423, and 424 from set 420 that, when combined, form circuit diagram 407A. Similarly, C3_Params_1 invokes a third set of rules to select sub-circuits in subset A 431A from set 430 that, when combined, form circuit diagram 408A. Finally, CN_Params_1 invokes yet another set of rules to select sub-circuits in subset B 441A from set 440 that, when combined, form circuit diagram 409A.

[0031] In one exemplary embodiment of generator 501, a circuit specification is generated and provided to an EDA tool. For example, the circuit specification may specify subcircuit schematics and pin connections for forming a combinational circuit. For example, the circuit specification may describe a circuit as well as the subcircuit schematics used to form connections, for example, between various subcircuit schematic nodes. In some exemplary embodiments, the circuit specification may include identifiers (e.g., cell names or instance names) for specific subcircuit schematics to be included in the circuit. The circuit specification may further include a description of how pins of the subcircuit schematics are connected (e.g., a pin map, described below). As described in more detail below, for example, one exemplary circuit specification is a netlist such as Verilog.v. The EDA tool may receive the circuit specification, retrieve the specified subcircuit schematics based on the circuit specification, and generate a transistor-level schematic including the selected subcircuit schematics.

[0032] FIG. 6A shows another exemplary block diagram of an automatic circuit generator according to another embodiment. In this example, generator 609 includes program code for determining 609 functions, applying rules 612-613, retrieving 614 subcircuit diagrams, and connecting 615 subcircuit diagrams. For example, at the start of the process, function determination block 610 can, for example, evaluate one or more received parameter sets and determine which rule set (e.g., a comparator rule set, an oscillator rule set, or a voltage reference rule set) to apply. Generator 609 can invoke one of the appropriate rule sets 612-613. An exemplary rule set is illustrated in 620. In this example, rule set 620 can include, for example, subblock 621 (e.g., of code) for retrieving parameter values, subblock 622 for determining subcircuits based on the parameter values, and subblock 623 for generating a pin map. Generating the pin map can include, for example, retrieving a pin list from the subcircuits to be combined. In one embodiment, for example, the pin map connections may be embodied in a netlist such as a Verilog ".v" file. Another block 614 may retrieve the subcircuit schematic, for example, as determined by block 622. Block 615 may map the schematic pins of the subcircuit. In one embodiment, the schematic pins are connected based on the pin map, for example. The blocks described above may be implemented as software code using a variety of techniques. While the diagram shows generator 609 as a single group of blocks for illustrative purposes, it is understood that the blocks comprising generator 609 may be implemented using software coding techniques using different languages, for example, and may be implemented as multiple different modules. In one exemplary embodiment, described in more detail below, the generator software system includes blocks implemented in C++ and other blocks implemented in a scripting language.

[0033] FIG. 6B illustrates exemplary steps for automatically generating a circuit according to an embodiment. While the following step description is provided in a particular order, it is understood that one or more of these steps may be performed in a different order. At 601, the function of the circuit to be generated for the processed parameters is determined. The function may correspond to a particular functional circuit component, such as a comparator, oscillator, voltage reference, current source, or other parameterized analog building block. In this example, the function may be determined using an identifier such as the functional circuit component name (e.g., "comparator," "oscillator," "delay circuit," etc.). For example, the generator may retrieve the functional circuit component name and then select parameters to retrieve based on this name. At 602, the parameters are retrieved. At 603, for example, the parameters are analyzed to determine subcircuits to be used to form the circuit to be generated. At 604, a pin map of the subcircuits to be used to form the circuit is generated. As described in more detail below, for example, subcircuit schematic pins may be mapped, in some cases, to each other and to inputs and outputs of the circuit to be generated. Some pins can be mapped between different subcircuit diagrams, while other pins can be mapped to inputs or outputs of the circuit to be generated. The pin map can be embodied, for example, in the circuit specification described above, which specifies the mapping between the subcircuit diagrams and pins. At 605, the subcircuit diagrams to be combined are retrieved (e.g., from a library of published subcircuits). At 606, for example, the subcircuit diagram pins can be connected based on the pin map. In one exemplary embodiment described below, the generator software component can output a netlist (e.g., in the form of a Verilog ``.v'' file) mapping the pins.Blocks 614 and 615 may be implemented, for example, as scripts for an electronic design automation (EDA) system (e.g., Cadence®, Mentor Graphics®, Silvaco®) that can extract and combine subcircuit schematics as illustrated by 605 and 606.

[0034] 7A-7B show an example of pin mapping according to one embodiment. In this example, the functional circuit component is a comparator circuit, and the circuit specification parameters specify the input type (e.g., N-type input stage or P-type input stage, "N / P-input_type"), hysteresis (e.g., yes or no, "Hyst"), and deglitch (e.g., yes or no). In this example, the comparator has subcircuit schematic sets 701-705 that can be selected based on the parameters to generate a comparator with the specified characteristics (e.g., input type, hysteresis, or deglitch). For example, in this example, C1_SC1 is an N-type input stage comparator subcircuit schematic 701, C1_SC2 is a hysteresis subcircuit schematic (NHyst) 702 operable with the N-type subcircuit schematic 701, C1_SC3 is a deglitch subcircuit schematic 703, C1_SC4 is a P-type input stage comparator subcircuit schematic 704, and C1_SC5 is a hysteresis subcircuit schematic (PHyst) 705 operable with the P-type subcircuit schematic 704. Each of the subcircuit schematics 701-705 may include, for example, a transistor-level schematic for implementing the function of the particular subcircuit.

[0035] Subcircuit schematics according to some embodiments of the present disclosure can have multiple pins, including multiple analog pins for coupling voltages and currents into and out of each subcircuit schematic. In some embodiments, these pins can be mapped such that pins in a subcircuit schematic are connected to either pins of other subcircuit schematics or pins of a combinational circuit (e.g., input / output pins of the resulting combinational circuit). In one exemplary embodiment, mapping pins of different subcircuit schematics can be based on multiple pin maps, where different pin maps specify different connections between pins of multiple subcircuit schematics and / or I / O pins of a schematic for different combinations of selected subcircuit schematics. Such pin maps can be defined, for example, within the circuit generator code or defined externally (e.g., in a data record) and imported (e.g., as part of a circuit specification imported into an EDA tool). A particular mapping can be based, for example, on one of the pin maps. The pin map used to map pins can be based on the particular subcircuit schematic selected. For example, one combination of selected subcircuit schematics may have one pin map, and another combination of selected subcircuit schematics may have another pin map, each of which may ensure, for example, that each unique combination of subcircuit schematics is connected together and that the resulting schematic functions as desired across all parameter values.

[0036] Thus, mapping may include, for example, specifying a connection between one or more pins of the subcircuit diagram. In some embodiments, mapping may include specifying a connection between one or more pins of one or more subcircuit diagrams and an input or output of the circuit diagram (e.g., Vdd, ground, Vin, Vout, etc. of a symbol for the circuit diagram formed by the subcircuit diagram). In one embodiment, the software may, for example, determine which subcircuit diagrams should be used to form a particular circuit and then map unique pins to the particular subcircuit diagrams.

[0037] Referring again to FIG. 7A , in this example, N-input subcircuit schematic 701 includes pins 1-6, NHyst subcircuit schematic 702 includes pins 1-4, deglitch subcircuit schematic 703 includes pins 1-4, P-input subcircuit schematic 704 includes pins 1-6, and PHyst subcircuit schematic 705 includes pins 1-4. These pins can be mapped to one another as illustrated in the examples described below. This example comparator is only one example of many types of functional circuit components that can be generated using the techniques described herein. Other functional circuit components, such as oscillators, delay circuits, voltage references, and bias currents, can be generated from parameters using the techniques described herein, and other comparators can have other parameters, for example, for selecting other subcircuits. Therefore, this example is illustrative only.

[0038] As described above, a feature and advantage of the present disclosure is the ability to select particular subcircuit schematics based on parameters and combine these subcircuit schematics. In this example, combining these subcircuit schematics includes mapping analog pins of the subcircuit schematics to form a schematic for at least one functional circuit component (e.g., a comparator). The mapping can be performed automatically by a software system.

[0039] Circuit diagram 710 shows an example circuit diagram generated based on one set of parameter values. In this diagram, the first set of parameter values ​​(Params_1) may be "Input Type=N," "Hysteresis=Yes," and "Deglitch=Yes." Thus, N-Input subcircuit diagram 701, NHyst subcircuit diagram 702, and deglitch subcircuit diagram 703 are selected and combined to form circuit diagram 710. For this parameter combination, mapping pins may include: 1. Map pin 1 of subcircuit schematic 701 to pin 1 of subcircuit schematic 702 and pin 1 of subcircuit schematic 703 (in this example, pin 1 is the supply voltage input for each subcircuit), and map these pins to the Vdd input pin. 2. Mapping pin 2 of the partial circuit schematic 701 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 701 (eg, the input pin of the second comparator) to input pin IN2 750. 4. Mapping pin 4 of subcircuit schematic 701 (eg, hysteresis control input) to pin 3 of subcircuit 702 (eg, hysteresis control output). 5. Mapping pin 5 of subcircuit schematic 701 (eg, comparator output) to pin 2 of subcircuit 702 (eg, hysteresis input) and pin 2 of subcircuit 703 (eg, deglitch input). 6. Mapping pin 6 of partial circuit schematic 701 to pin 4 of partial circuit schematic 702 and pin 3 of partial circuit schematic 703 simultaneously and to the ground (GND) pin. 7. Map pin 4 of the partial circuit schematic 703 to the output pin (Vout) 751.

[0040] Circuit diagram 711 shows another example circuit diagram generated based on another set of parameter values. In this diagram, the second set of parameter values ​​(Params_2) can be "Input Type=N," "Hysteresis=Yes," and "Deglitch=No." Thus, the N-Input subcircuit diagram 701 and the NHyst subcircuit diagram 702 are selected and combined to form circuit diagram 711 (the deglitch subcircuit diagram 703 is not selected). For this parameter combination, mapping pins can include the following: 1. Map pin 1 of subcircuit schematic 701 to pin 1 of subcircuit schematic 702 (in this example, pin 1 is the supply voltage input for each subcircuit), and map these pins to Vdd input pins. 2. Mapping pin 2 of the partial circuit schematic 701 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 701 (eg, the input pin of the second comparator) to input pin IN2. 4. Mapping pin 4 of subcircuit schematic 701 (eg, hysteresis control input) to pin 3 of subcircuit 702 (eg, hysteresis control output). 5. Mapping pin 5 (eg, comparator output) of partial circuit schematic 701 to pin 2 (eg, hysteresis input) of partial circuit schematic 702 and to output pin Vout. 6. Map pin 6 of subcircuit schematic 701 and pin 4 of subcircuit 702 to each other and to a ground (GND) pin.

[0041] Circuit diagram 712 shows another example circuit diagram generated based on another set of parameter values. In this diagram, a third set of parameter values ​​(Params_3) may be "Input Type=P," "Hysteresis=Yes," and "Deglitch=Yes." Thus, P Input subcircuit diagram 704, PHyst subcircuit diagram 705, and Deglitch subcircuit diagram 703 are selected and combined to form circuit diagram 712. For this parameter combination, mapping pins may include: 1. Map pin 1 of subcircuit schematic 704 to pin 1 of subcircuit schematic 705 and pin 1 of subcircuit schematic 703 (in this example, pin 1 is the supply voltage input for each subcircuit), and map these pins to the Vdd input pin. 2. Mapping pin 2 of the partial circuit schematic 704 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 704 (eg, the input pin of the second comparator) to input pin IN2. 4. Mapping pin 4 of subcircuit schematic 704 (eg, hysteresis control input) to pin 3 of subcircuit 705 (eg, hysteresis control output). 5. Mapping pin 5 of subcircuit schematic 704 (eg, comparator output) to pin 2 of subcircuit schematic 705 (eg, hysteresis input) and pin 2 of subcircuit schematic 703 (eg, deglitch input). 6. Pin 6 of subcircuit wiring diagram 704, pin 4 of subcircuit 705, and pin 3 of subcircuit 703 are mapped to each other and to a ground (GND) pin. 7. Map pin 4 of the partial circuit schematic 703 to the output pin (Vout).

[0042] Circuit diagram 713 shows another example circuit diagram generated based on another set of parameter values. In this diagram, a fourth set of parameter values ​​(Params_4) may be "Input Type=P," "Hysteresis=Yes," and "Deglitch=No." Thus, P Input subcircuit diagram 704 and PHyst subcircuit diagram 705 are selected and combined to form circuit diagram 713 (Deglitch subcircuit diagram 703 is not selected). For this parameter combination, mapping pins may include the following: 1. Map pin 1 of subcircuit schematic 704 to pin 1 of subcircuit schematic 705 (in this example, pin 1 is the supply voltage input for each subcircuit) and map these pins to Vdd input pins. 2. Mapping pin 2 of the partial circuit schematic 704 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 704 (eg, the input pin of the second comparator) to input pin IN2. 4. Mapping pin 4 of subcircuit schematic 704 (eg, hysteresis control input) to pin 3 of subcircuit 705 (eg, hysteresis control output). 5. Mapping pin 5 (eg, comparator output) of partial circuit schematic 704 to pin 2 (eg, hysteresis input) of partial circuit schematic 705 and to output pin Vout. 6. Map pin 6 of subcircuit schematic 704 and pin 4 of subcircuit 705 to each other and to a ground (GND) pin.

[0043] 7B, circuit diagram 714 illustrates another example circuit diagram generated based on another set of parameter values. In this diagram, a fifth set of parameter values ​​(Params_5) may be "Input Type=N," "Hysteresis=No," and "Deglitch=Yes." Thus, N-Input subcircuit diagram 701 and Deglitch subcircuit diagram 703 are selected and combined to form circuit diagram 714 (NHyst subcircuit diagram 702 is not selected). For this parameter combination, mapping pins may include: 1. Map pin 1 of subcircuit schematic 701 to pin 1 of subcircuit schematic 703 (in this example, pin 1 is the supply voltage input for each subcircuit) and map these pins to Vdd input pins. 2. Mapping pin 2 of the partial circuit schematic 701 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 701 (eg, the input pin of the second comparator) to input pin IN2. 4. Pin 4 of the partial circuit schematic 701 (eg, hysteresis control input) can be left unconnected. 5. Mapping pin 5 (eg, comparator output) of subcircuit schematic 701 to pin 2 (eg, deglitch input) of subcircuit schematic 703. 6. Map pin 6 of subcircuit schematic 701 and pin 3 of subcircuit 703 to each other and to a ground (GND) pin. 7. Map pin 4 of the partial circuit schematic 703 to the output pin Vout.

[0044] Circuit diagram 715 shows another example circuit diagram generated based on another set of parameter values. In this diagram, a sixth set of parameter values ​​(Params_6) may be "Input Type=P," "Hysteresis=No," and "Deglitch=Yes." Thus, P Input subcircuit diagram 704 and Deglitch subcircuit diagram 703 are selected and combined to form circuit diagram 715 (PHyst subcircuit diagram 705 is not selected). For this parameter combination, mapping pins may include the following: 1. Map pin 1 of subcircuit schematic 704 to pin 1 of subcircuit schematic 703 (in this example, pin 1 is the supply voltage input for each subcircuit) and map these pins to the Vdd input pin. 2. Mapping pin 2 of the partial circuit schematic 704 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 704 (eg, the input pin of the second comparator) to input pin IN2. 4. Pin 4 of the partial circuit schematic 704 (eg, hysteresis control input) can be left unconnected. 5. Mapping pin 5 (eg, comparator output) of subcircuit schematic 704 to pin 2 (eg, deglitch input) of subcircuit 703. 6. Map pin 6 of subcircuit schematic 704 and pin 3 of subcircuit 703 to each other and to a ground (GND) pin. 7. Map pin 4 of the partial circuit schematic 703 to the output pin Vout.

[0045] Circuit diagram 716 shows another example circuit diagram generated based on another set of parameter values. In this diagram, the seventh set of parameter values ​​(Params_7) may be "Input Type=N," "Hysteresis=No," and "Deglitch=No." Therefore, N-input subcircuit diagram 701 is selected to form circuit diagram 716 (NHyst subcircuit diagram 702 and Deglitch subcircuit diagram 703 are not selected). For this parameter combination, mapping pins may include the following: 1. Map pin 1 of the partial circuit schematic 701 to the Vdd input pin. 2. Mapping pin 2 of the partial circuit schematic 701 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 701 (eg, the input pin of the second comparator) to input pin IN2. 4. Pin 4 of the partial circuit schematic 701 (eg, hysteresis control input) can be left unconnected. 5. Mapping pin 5 (eg, comparator output) of the partial circuit schematic 701 to the output pin Vout. 6. Map pin 6 of the partial circuit schematic 701 to a ground (GND) pin.

[0046] Circuit diagram 717 shows another example circuit diagram generated based on another set of parameter values. In this diagram, the eighth parameter value set (Params_8) may be "Input Type=P," "Hysteresis=No," and "Deglitch=No." Therefore, the P Input subcircuit diagram 704 is selected to form circuit diagram 717 (the PHyst subcircuit diagram 705 and the Deglitch subcircuit diagram 703 are not selected). For this parameter combination, mapping pins may include the following: 1. Map pin 1 of the partial circuit schematic 704 to the Vdd input pin. 2. Mapping pin 2 of the partial circuit schematic 704 (eg, the input pin of the first comparator) to input pin IN1. 3. Mapping pin 3 of the partial circuit schematic 704 (eg, the input pin of the second comparator) to input pin IN2. 4. Pin 4 of the partial circuit schematic 704 (eg, hysteresis control input) can be left unconnected. 5. Mapping pin 5 (eg, comparator output) of the partial circuit schematic 704 to the output pin Vout. 6. Map pin 6 of the partial circuit schematic 704 to a ground (GND) pin.

[0047] In one embodiment, at least a portion of the mapping is performed by rules as described above. For example, specific rules for specific parameter values / selected subcircuits can determine which pins are present for the selected subcircuit schematic.

[0048] Advantageously, the mapped analog pins can have predetermined compatibility. For example, since the subcircuit schematics are predetermined, the operability of different subcircuit schematics (and the subcircuit schematic pins that can be connected) can have predetermined compatibility by design. For example, in the example shown in FIGS. 7A-7B , an N-input comparator subcircuit schematic 701 can be designed for use with an N-hysteresis subcircuit schematic 702, and a P-input comparator subcircuit schematic 704 can be designed for use with a P-hysteresis subcircuit schematic 705. A deglitch subcircuit schematic can also be designed for use with either an N-type or a P-type schematic. Thus, the pins of subcircuits can be designed to automatically couple to each other to form different circuits that operate as designed. For example, an input pin on one subcircuit can be designed to receive a voltage input within a specific range. For example, a pin may be designed to have a predetermined compatibility with another pin, with one pin generating a signal having a particular voltage or current characteristic and another pin designed to receive and process this signal. Various pins may be designed to receive voltages or currents (or both) over a particular predetermined range during operation of the combinational circuit, for example.

[0049] While the above examples illustrate specific predetermined analog subcircuit schematics, it should be understood that a wide variety of predetermined subcircuit schematics can be used. In various embodiments, the predetermined subcircuit schematic can include as few as one or as many components. For example, the subcircuit schematic can include one or more active components (e.g., transistors) or one or more passive components (e.g., resistors, capacitors, or inductors). Subcircuit schematics according to various embodiments can include, for example, two transistors configured as a differential pair, a transistor and / or resistor configured as a load, a transistor configured as a current mirror, various full or partial cascode structures, various forms of delay stages, trim circuits, or even, for example, a single component. Subcircuit schematics according to other embodiments can include numerous components. Examples of more complex subcircuit schematics include bandgap stages, comparator or amplifier input stages, conditioning stages, or other more complex combinations of components to implement other analog and / or mixed-signal functions. Additionally, analog subcircuit schematics can include digital circuits, including, for example, inverters, registers, latches, and various logic gates (e.g., AND, OR, NAND, NOR, XOR) for receiving digital signal inputs from or providing signal outputs to digital circuits incorporated within the mixed-signal circuit. Advantageously, different subcircuit schematics can be combined to form different functional circuits with different operational functions (e.g., comparators with or without deglitching, trim, hysteresis, etc.). For example, a circuit designer can design various subcircuit schematics to ensure interoperability to meet a range of different operational functions. Software can then access the predetermined subcircuit schematics and automatically generate analog circuits based on circuit specification parameters (e.g., from a user). In some embodiments, subcircuit schematics for one or more functional circuit components can be included in combination with subcircuit schematics for another functional circuit component (e.g., a voltage buffer functional circuit component can be used as a subcircuit within a circuit configuration for another functional circuit component).Thus, to automate the generation of analog circuits, a wide range of analog / mixed-signal integrated circuit architectures can be decomposed into subcircuit schematics and recombined on the fly using the techniques described herein. The particular granularity and combination of the various subcircuit schematics can be a matter of design choice as would be understood in light of the present disclosure by one skilled in the art of analog circuit design.

[0050] Parameterized Circuit Layout Generation FIG. 8 illustrates a system for automatic circuit generation according to another embodiment. Features and advantages of the present disclosure include, for example, a system that can automatically generate circuit layouts based on input parameters, where different values ​​can result in different layouts. As shown in FIG. 8, generator software system 803 can receive parameters 802 and generate layout 804. Generator software system 803 can, for example, be executable on at least one computer system and can include computer code that, when executed by the computer, causes the computer to perform operations to implement the techniques described herein.

[0051] Parameters 802 may include, for example, a plurality of circuit specification parameters corresponding to at least one functional circuit component 801 substantially similar to the circuit specification parameters described above. For example, the circuit specification parameters may specify, for example, characteristics of a circuit layout to be generated and may correspond to a particular functional circuit component (e.g., a comparator having particular characteristics, an oscillator having particular characteristics, a delay circuit having particular characteristics, etc.). These parameters may be used to generate circuit layouts for particular functional circuit components having different characteristics (e.g., a layout for a comparator having a p-type input stage or a layout for a comparator having an n-type input stage, etc.) based on the parameter values. Furthermore, in one exemplary embodiment, one set of circuit specification parameters may correspond to one functional circuit component (e.g., a comparator), and another set of parameters may correspond to a different functional circuit component (e.g., a delay circuit or an oscillator). It is understood that various encoding mechanisms may be used to embody the circuit specification parameters that specify the characteristics of the circuit to be generated.

[0052] In this exemplary embodiment, parameters 802 are received by generator 803. Generator 803 can use multiple sub-circuit layouts 810-812 based on the circuit specification parameters to generate circuit layout 804. For example, one set of values ​​(or encoding) for the received circuit specification parameters can result in the use of sub-circuit layout 810 and sub-circuit layout 811. Another set of values ​​(or another encoding) for the received circuit specification parameters can result in the use of sub-circuit layout 810, sub-layout 811, and layout 812, for example. The appropriate sub-circuit layouts can be combined to form circuit layout 804. Circuit layout 804 is thus a circuit layout for functional circuit component 801 having characteristics specified by parameters 802. Layout 804 can then be used to create a physical circuit for functional circuit component 801.

[0053] Disclosed embodiments of the present invention can be particularly advantageous for generating analog circuit layouts. Disclosed embodiments of the present invention can be used, for example, to automatically generate analog circuit layouts based on parameters. The circuit specification parameters can correspond to one or more functional analog circuit components, such as a comparator, an oscillator, or a delay. The circuit specification parameters can specify characteristics of the analog circuit to be generated, such as a comparator with a P-type input or an N-type input. The circuit specification parameters can be used to determine predetermined analog subcircuit layouts corresponding to the functional analog circuit components. For example, as shown in a more detailed example below, the generator 803 can select a predetermined P-type comparator subcircuit layout, a first predetermined hysteresis circuit layout, and / or a predetermined deglitch circuit layout based on these parameters to form a layout for the comparator functional circuit component using one parameter set, and can select a predetermined N-type comparator subcircuit layout and a predetermined deglitch circuit layout using another parameter set. Subsets of the predetermined analog subcircuit layouts identified using the circuit specification parameters can be combined to form the analog circuit layout for the functional analog circuit component 801.

[0054] FIG. 9 illustrates a method for automatic circuit generation according to one embodiment. The method may be implemented, for example, by software executing on one or more computers. At 901, a plurality of circuit specification parameters corresponding to at least one (or more) functional circuit components are received. At 902, specific subcircuit layouts are combined based on the circuit specification parameters to form a circuit layout for the functional circuit component. In one embodiment, each functional circuit component may have a different predetermined subcircuit layout set, and a subset of the predetermined subcircuit layouts corresponding to the functional circuit component are combined based on the circuit specification parameters. For example, a comparator may have an N-type comparator subcircuit layout and a P-type comparator subcircuit layout in its corresponding layout set. For example, a P-type subcircuit layout may be used based on one or more parameters having specific values, and an N-type subcircuit layout may be used based on one or more parameters having different values. The subcircuit layouts may be in the form of functional circuit blocks having various input and output terminals (or pins) within the layout. Thus, combining may include, for example, coupling pins between sub-circuit layouts to each other and / or coupling pins of sub-circuit layouts to other pins of other circuit layouts.

[0055] 10A-10D illustrate examples of automated circuit layout generation according to various embodiments. In certain embodiments, different values ​​for circuit specification parameters generate different analog circuit layouts with different characteristics for the corresponding functional circuit component. For example, parameter 1002 corresponding to functional circuit component 1001 can be encoded with different values. In this example, a set of N parameters (where N is an integer) is illustrated as variables a1, a2, a3, ..., aN having a first set of values ​​[a1=x1, a2=x2, a3=x3, ..., aN=xN]. Generator software 1003 receives parameters 1002 having the first set of values ​​and uses a subset of partial circuit layouts 1010-1015. The partial circuit layouts are combined to form circuit layout 1004A for functional circuit component 1001 according to the received parameters. In this example, the first set of parameter values ​​results in partial circuit layouts 1010-1012 being combined to form circuit 1004A.

[0056] 10B shows parameters 1002 having a second set of values ​​[a1=x1, a2=x2, a3=y3, ..., aN=xN]. Here, parameter a3 changes its value from x3 to y3. Thus, different partial circuit layouts are combined to form circuit layout 1004B. In this example, when a3=y3, partial circuit layout 1012 is no longer included in circuit layout 1004B along with partial circuit layouts 1010 and 1011.

[0057] 10C shows parameters 1002 having a third set of values ​​[a1=y1, a2=x2, a3=x3, ..., aN=xN]. Here, parameter a1 changes its value from x1 to y1, and parameter a3=x3. Thus, again, the sub-circuit used changes. In this example, when a1=y1, sub-circuit layout 1010 is no longer selected. Instead, sub-circuit layout 1013 is included within circuit layout 1004C, which includes sub-circuit layouts 1011 and 1012.

[0058] 10D shows parameters 1002 having a third set of values ​​[a1=y1, a2=y2, a3=x3, ..., aN=xN], where parameters a1 and a2 have values ​​of y1 and y2, respectively, and sub-circuit layout 1014 is included within circuit layout 1004D along with sub-circuit layouts 1011 and 1012.

[0059] Features and advantages of some embodiments of the present disclosure include receiving circuit specification parameters 1150 corresponding to multiple functional circuit components and automatically generating circuit layouts that implement each functional circuit component based on these parameters. FIGS. 11A-11D illustrate different parameter sets for generating different circuit layouts for different functional circuit components, according to an embodiment. Referring to FIG. 11A, in this example, parameters 1150 corresponding to multiple functional circuit components 1102-1105 (components C1, C2, C3, C4, and so on through C-N, where N is an integer corresponding to the number of functional circuit components for which a corresponding circuit is being generated). C1-C-N can be, for example, comparators, oscillators, delay circuits, current generators, voltage references, or a wide variety of other analog functional circuit components used with analog circuits. In this example, generator 1101 can receive N sets of circuit specification parameters, where each different functional circuit component has a corresponding set of circuit specification parameters. In particular, for example, a first parameter set 1151, C1_Params, corresponds to component C1 1102; a second parameter set 1152, C2_Params, corresponds to component C2 1103; a third parameter set 1153, C3_Params, corresponds to component C3 1104, and so on until a final parameter set 1154, CN_Params, also corresponds to component CN 1105. Each parameter set 1151-1154 may, for example, specify characteristics of the circuit to be generated by having different parameter values. In this example, parameter 1151 has a first value set, denoted in this case as "C1_Params_1." Similarly, parameter 1152 has a first value set, "C2_Params_1," parameter 1153 has a first value set, "C3_Params_1," and so on up to parameter 1154, which also has value "C4_Params_1."

[0060] 11A-11D show an example of automatic circuit layout generation according to yet another embodiment. FIGS. 11A-11D show an example illustrating that different circuit specification parameters for corresponding different functional circuit components can have corresponding different predetermined subcircuit layout sets. For example, referring to FIG. 11A, predetermined analog subcircuit layouts can be stored in library 1160 (e.g., a layout library). In this example, there are multiple subcircuit layout sets 1110, 1120, 1130, and 1140 corresponding to different functional circuit components 1102, 1103, 1104, and 1105, respectively. Thus, for example, C1_Params 1151 corresponding to functional circuit component 1102 (C1) can be used to combine subcircuit layouts from C1 subcircuit layout set (“C1_LO_Set”) 1110, which includes analog subcircuit layouts 1111-1116. Similarly, for example, C2_Params 1152 corresponding to functional circuit component 1103 (C2) can be used to combine partial circuit layouts from C2 sub-circuit layout set ("C2_LO_Set") 1120, which includes analog sub-circuit layouts 1121-1127. Similarly, for example, C3_Params 1153 corresponding to functional circuit component 1104 (C3) can be used to combine partial circuit layouts from C3 sub-circuit layout set ("C3_LO_Set") 1130 (partial circuit layout not shown), and so on up to CN_Params 1154 corresponding to functional circuit component 1105 (CN), which can be used to combine partial circuit layouts from CN sub-circuit layout set ("CN_LO_Set") 1140 (partial circuit layout not shown).

[0061] The parameters 1151-1154 can have different values ​​that result in different combinations of corresponding partial circuit layouts. In this example, each parameter set 1151-1154 receives a first set of parameter values ​​(e.g., where particular values ​​are denoted using "_1," "_2," etc.). For example, the first set of values ​​for circuit specification parameter 1151 is denoted as C1_Params_1, the first set of values ​​for circuit specification parameter 1152 is denoted as C2_Params_1, and so on. In this example, generator 1101 receives parameter value C1_Params_1 and combines partial circuit layouts C1_LO1 1111, C1_LO2 1112, and C1_LO3 1113 from C1_LO_Set 1110 to generate analog circuit layout 1106A corresponding to functional circuit component C1 1102. Similarly, generator 1101 receives parameter values ​​C2_Params_1 and combines partial circuits C2_LO1 1121, C2_LO2 1122, C2_LO3 1123, and C2_LO4 1124 from C2_LO_Set 1120 to generate analog circuit layout 1107A corresponding to functional circuit component C2 1103. Similarly, generator 1101 receives parameter values ​​C3_Params_1 and combines a partial circuit layout (not shown) from C3_LO_Set 1130 to generate analog circuit layout 1108A corresponding to functional circuit component C3 1104. Analog circuit layout 1108A includes a first partial circuit layout subset (C3_LO SubsetA) 1131A from C3_LO_Set 1130. Finally, generator 1101 receives parameter values ​​CN_Params_1 and combines partial circuit layouts (not shown) from CN_LO_Set 1140 to generate an analog circuit layout 1109A corresponding to functional circuit component CN 1105. Analog circuit layout 1109A includes a first partial circuit layout subset (CN_LO SubsetB) 1141A from CN_LO_Set 1140.In some embodiments, multiple circuit layouts, such as one or more of layouts 1106A, 1107A, 1108A, and 1109A for different functional components, can be combined together into a layout for a circuit that includes multiple parameterized instances of a functional component, for example.

[0062] 11B illustrates the generation of another circuit layout using another parameter set, according to an embodiment. In this example, each parameter set 1151-1154 receives a different set of parameter values. For example, new circuit specification parameter value set 1151 is denoted as C1_Params_2, new circuit specification parameter value set 1152 is denoted as C2_Params_2, and so on. In this example, generator 1101 receives, for example, parameter values ​​C1_Params_2 and combines partial circuit layouts C1_LO4 1114, C1_LO2 1112, and C1_LO3 1113 from C1_LO_Set 1110 to generate analog circuit layout 1106B corresponding to functional circuit component C1 1102 having different characteristics than layout 1106A. Similarly, generator 1101 receives, for example, parameter values ​​C2_Params_2 and combines partial circuit layouts C2_LO5 1125, C2_LO6 ​​1126, C2_LO3 1123, and C2_LO4 1124 from C2_LO_Set 1120 to generate analog circuit layout 1107B corresponding to functional circuit component C2 1103 having different characteristics from layout 1107A. Similarly, generator 1101 receives, for example, parameter values ​​C3_Params_2 and combines a partial circuit layout (not shown) from C3_LO_Set 1130 to generate analog circuit layout 1108B corresponding to functional circuit component C3 1104 having different characteristics from layout 1108A. Analog circuit layout 1108B includes a second partial circuit layout subset (C3_LO SubsetA′) 1131B from C3_LO_Set 1130. Finally, generator 1101 receives, for example, parameter values ​​CN_Params_2 and combines partial circuit layouts (not shown) from CN_LO_Set 1140 to generate analog circuit layout 1109B corresponding to functional circuit component CN 1105 having different characteristics than layout 1109A. Analog circuit layout 1109B includes a first partial circuit layout subset (CN_LO SubsetB') 1141B from CN_LO_Set 1140.

[0063] 11C illustrates the generation of yet another circuit layout using yet another parameter set, according to an embodiment. In this example, each parameter set 1151-1154 receives a third set of parameter values. For example, new circuit specification parameter value set 1151 is denoted as C1_Params_3, new circuit specification parameter value set 1152 is denoted as C2_Params_3, and so on. In this example, generator 1101 receives, for example, parameter values ​​C1_Params_3 and combines partial circuit layouts C1_LO4 1114 and C1_LO2 1112 from C1_LO_Set 1110 to generate analog circuit layout 1106C corresponding to functional circuit component C1 1102 having different characteristics than layouts 1106A and 1106B. Similarly, generator 1101 receives parameter values ​​C2_Params_3 and combines partial circuit layouts C2_LO5 1125, C2_LO6 ​​1126, C2_LO3 1123, and C2_LO7 1127 from C2_LO_Set 1120 to generate analog circuit layout 1107C corresponding to functional circuit component C2 1103. Similarly, generator 1101 receives parameter values ​​C3_Params_3, for example, and combines a predetermined partial circuit layout (not shown) from C3_LO_Set 1130 to generate analog circuit layout 1108C corresponding to functional circuit component C3 1104 having different characteristics from layouts 1108A and 1108B. Analog circuit layout 1108C includes a third partial circuit layout subset (C3_LO SubsetA'') 1131C from C3_LO_Set 1130. Finally, generator 1101 receives parameter values ​​CN_Params_3, for example, and combines partial circuit layouts (not shown) from CN_LO_Set 1140 to generate analog circuit layout 1109C corresponding to functional circuit component CN 1105 having different characteristics than layouts 1109A and 1109B. Analog circuit layout 1109C includes a third partial circuit layout subset (CN_LO SubsetB'') 1141C from CN_LO_Set 1140.

[0064] FIG. 11D illustrates an embodiment in which different partial circuit layout sets for different functional circuit components can include the same partial circuit layout. For example, in some embodiments, different functional circuit components can have corresponding unique predetermined partial circuit layout sets. Referring to FIG. 11A , partial circuit layout set C1_LO_Set 1110 can be a different partial circuit layout set than C2_LO_Set 1120 or C3_LO_Set 1130. In particular, partial circuit layouts combined to form different comparators may be different from partial circuit layouts combined to form different oscillators or different delay circuits, for example. Thus, each circuit component can have a corresponding unique partial circuit layout set. However, in various embodiments, even if these sets are unique, one or more partial circuit layouts within some sets can be shared. For example, a partial circuit layout set for a comparator can access a resistor divider partial circuit layout, which can be associated with a partial circuit layout set for an oscillator, for example. Thus, a unique layout set may include one or more unique predetermined analog subcircuit layouts that are used only for corresponding functional circuit components, or alternatively, may include one or more predetermined analog subcircuit layouts that are used for different functional circuit components. In this example, subcircuit layout C1-2_LO 1117 is included in both C1_LO_Set 1110 and C2_LO_Set 1120. Further, in this example, for example, C1_Params_1 combines C1-2_LO 1117 with the other layouts 1111-1113 to form layout 1106D, and C2_Params_1 combines C1-2_LO 1117 with the other layouts 1121-1124 to form layout 1107D.

[0065] In some embodiments, multiple circuit layouts, such as one or more of layouts 1106A-1106D, 1107A-1107D, 1108A-1108D, and 1109A-1109D for different functional components, can be combined in various combinations with each other into layouts for circuits including multiple parameterized instances of the functional components. A single circuit layout can include a layout for functional circuit component C1 1102 based on one parameter set (e.g., circuit layout 1106D), a layout for functional circuit component C2 1103 based on one parameter set (e.g., circuit layout 1107C), a layout for functional circuit component C3 1104 based on one parameter set (e.g., circuit layout 1108D), and a layout for functional circuit component CN 1105 based on one parameter set (e.g., circuit layout 1109B). Alternatively, the combination of parameters and functional circuit components may generate a layout for functional circuit component C1 1102 (e.g., circuit layout 1106B) based on another set of parameters, but not a layout for functional circuit component C2 1103 (e.g., C2 is not included), and a layout for functional circuit component C3 1104 (e.g., circuit layout 1108C) based on another set of parameters, but not a layout for functional circuit component CN 1105 (e.g., CN is also not included). For example, any combination of parameters for different functional circuit components can be used to automatically generate layouts having various combinations of one or more of the same or different functional circuit components. In some embodiments, these layouts can be used to generate an entire chip of functional circuit components coupled together.Optionally, these layouts can be further processed by layout editing tools within the EDA software tool (e.g., using the auto-routing capabilities of tools such as Cadence®, Mentor Graphics®, or Silvaco®), for example, to perform layout-to-schematic (“LVS”) (e.g., when a schematic is also generated) and / or design rule checking (“DRC”), and can be sent, for example, to a manufacturing facility (e.g., a semiconductor fabrication or “FAB”) to generate integrated circuits (e.g., chips) having desired characteristics. Typically, designing a layout for an analog integrated circuit can require a large amount of time and effort from analog circuit design layout experts. Advantageously, systems and methods employing the techniques described herein can generate schematics or layouts, or both, for electronic circuits (e.g., complete chips) very quickly and in substantially less time than would be required to design each circuit using conventional techniques.

[0066] FIG. 12A illustrates an example of generating a circuit layout according to one embodiment. In some embodiments, combining predetermined partial circuit layouts may be based on multiple layout placement instructions for arranging the partial circuit layouts to form a circuit layout. In this example, the generator 1200 includes layout placement instructions 1210 for arranging partial circuit layouts C1_LO1 1111, C1_LO2 1112, and C1_LO3 1113. Each partial circuit layout may have a shape, such as a square or rectangle, having a height h and a width w. More specifically, in this example, C1_LO1 1111 has a height h1 and a width w1, C1_LO2 1112 has a height h2 and a width w2, and C1_LO3 1113 has a height h3 and a width w3. The various heights and widths of different partial circuit layouts may be the same, for example, but are often different. In other embodiments, the partial circuit layouts can have a wide variety of other shapes (e.g., having more sides or even open areas for placing other partial circuit layouts within the shape). It is understood that this figure shows a simple shape for illustrative purposes. The placement instructions 1210 can, for example, place the partial circuit layouts 1111, 1112, and 1113 to generate the combinational circuit layout 1250. In some instances, one or more of the layout placement instructions 1210 place the partial circuit layouts 1111-1113 according to an x,y coordinate system. In this example, the layout placement instructions 1210 can specify coordinates for placing the partial circuit layouts. As an example, the placement instructions 1210 can place the lower left corner of C1_LO1 1111 at coordinates (0,0), the lower left corner of C1_LO3 1113 at (x1=w1,0), and the lower left corner of C1_LO2 1112 at (0,y2=h3). The combined sub-circuit layouts 1111-1113 form a circuit layout 1250, which may be, for example, one example layout arrangement for forming the circuit layout 1106A corresponding to the functional circuit component C1 1102 shown in FIG. 11A.Circuit layout 1250 may include unused space (also known as "white space" or "dead space") 1201 between height y2=h3 of C1_LO3 and height y1=h1 of C1_LO1. Another unused space may exist, for example, 1202 between the right edge of C1_LO3 at x2=(w1+w3) and the edge of C1_LO2 at x3=w2. It is typically desirable to reduce the amount of unused space on an integrated circuit. Placement instructions according to various embodiments can optimize the combination of sub-circuit layouts to reduce unused space, as shown in the following example:

[0067] 12B illustrates another example of generating a circuit layout according to one embodiment. In this example, layout placement instruction 1211 is executed to combine C2_LO1 1121, which has height h1 and width w1; C2_LO2 1122, which has height h2 and width w2; C2_LO3 1123, which has height h3 and width w3; and C2_LO4 1124, which has height h4 and width w4. Here, the lower left corner of C2_LO3 is placed at (0,0), the lower left corner of C2_LO4 is placed at (x1=w3,0), the lower left corner of C2_LO2 is placed at (x1=w3,y1=h4), and the lower left corner of C2_LO1 is placed at (x1=h3,0). The resulting unused space is shown in 1203. The combined partial circuit layouts 1121-1124 form a circuit layout 1251, which is an example layout arrangement for forming the circuit layout 1107A corresponding to the functional circuit component C2 1103 shown in FIG. 11A.

[0068] Disclosed embodiments of the present invention can arrange the partial circuit layouts and connect the nodes (or pads) of the partial circuit layouts to one another using metallization layers, routing techniques, and tools known to those skilled in the art. In one embodiment, connections between pins of one partial circuit layout can be formed, for example, by a predetermined layout (e.g., of metal or polysilicon layers) and arranged as described herein to connect between pins of two partial circuit layouts. The same techniques can be used to connect between pins of combinational circuit layouts, for example, thereby reducing or eliminating the use of automated routing tools. FIG. 12B shows an exemplary predetermined metal layout 1125 arranged to connect pins on C2_LO3 1123 and pins on C2_LO1 1121.

[0069] It should be understood that any number of instances of parameterized functional circuit components can be generated in various combinations using the techniques described above to form a circuit layout. For example, FIG. 13A shows an example circuit layout generated with different parameters (e.g., C1_Params_2) and placement instructions 1301 for C1_LO4, C1_LO2, and C1_LO3 to form example circuit layout 1106B corresponding to the functional circuit component described in FIG. 11B. Similarly, FIG. 13B shows another example combination of parameter values ​​and placement instructions. When the parameter value is again changed (e.g., C1_Params_3), the resulting partial circuit layouts 1114 and 1112 and placement instructions 1302 for C1_LO4 and C1_LO2 form example circuit layout 1106C corresponding to the functional circuit component C1 described in FIG. 11C.

[0070] In one exemplary embodiment, different circuit layouts can be formed from different sets of partial circuit layouts with corresponding different layout placement instructions. For example, in one embodiment, when partial circuit layouts 1111, 1112, and 1113 are combined, a specific set of layout placement instructions (e.g., placement instructions 1210) for partial circuit layouts 1111, 1112, and 1113 are used to place the partial circuit layout shown in Figure 12A. Conversely, when partial circuit layouts 1121, 1122, 1123, and 1124 are combined, a specific set of layout placement instructions (e.g., placement instructions 1211) for partial circuit layouts 1121, 1122, 1123, and 1124 are used to place the partial circuit layout shown in Figure 12B. Similarly, when partial circuit layouts 1114, 1112, and 1113 are combined, a particular set of layout placement instructions (e.g., placement instructions 1301) for partial circuit layouts 1114, 1112, and 1113 are used to place these partial circuit layouts. Figure 13B shows another set of layout placement instructions 1302 for partial circuit layouts C1_LO4 1114 and C1_LO2 1112 used for yet another set of parameter values. As shown in Figure 13B, when partial circuit layouts 1114 and 1112 are combined, the layout placement instructions 1302 for partial circuit layouts 1114 and 1112 are used to place these partial circuit layouts.

[0071] In some embodiments, multiple layout placement instructions associated with a particular sub-circuit layout combination may be predefined. When the layout placement instructions are executed, the associated sub-circuit layouts are placed into a combinational circuit layout. As shown in the example below, the layout placement instructions may, for example, activate a particular sub-circuit layout to place (or rearrange) each sub-circuit layout in sequence to form the combinational circuit layout.

[0072] FIG. 14 illustrates another example of generating a circuit layout using layout placement instructions according to an embodiment. Features and advantages of the present disclosure may include, for example, multiple layout placement instructions for rotating a partial circuit layout. For example, in this example, the layout placement instructions illustrated in FIG. 12A further include rotating C1_LO3 1113 as shown at 1113′. Rotating C1_LO3, for example, can move C1_LO2 down along the y-axis closer to C1_LO1, thereby reducing both the unused space and the overall circuit layout area.

[0073] FIG. 15 illustrates another example of generating a circuit layout using layout placement instructions according to an embodiment. In this example, the generator software system 1500 may include layout placement instructions 1511 that access placement data 1512 from an external data record. For example, the external data record may define extensive placement data for placing the partial circuit layouts. The external data record may be, for example, an external data file that in turn specifies specific partial circuit layouts and corresponding coordinates or rotations or other placement information for placing each layout. In one embodiment, the layout placement instructions include, for example, executable instructions that access data specifying the placement of the partial circuit layouts. In one embodiment, the external data record includes placement data for placing a particular combination of partial circuit layouts. For example, if layouts A, B, and C are to be placed, an external data record for placing layouts A, B, and C may be accessed. Alternatively, if layouts A, D, and E are to be placed, a separate external data record for placing layouts A, D, and E may be accessed.

[0074] In one exemplary embodiment, the layout placement instructions are predefined in an external data record. In this example, the external data record may include a sequence of layouts and associated placement instructions to be performed on the layouts. An example of such an external data record is as follows: / / Begin placing LO1, LO2, and LO3. PLACE <path>LO1 0 0 PLACE <path>LO2 2.2 0 R90 PLACE <path>LO3 6.1 0 / / end

[0075] The externally defined placement command above is of the form <cmd> <library location><sub-circuit_layout_name=’’cell_name’’>x1 y1 R1, where: <cmd>is a layout placement command (e.g., "PLACE"), <library location>is the path to where the layout is stored,<sub-circuit_layout_name=’’cell_name’’> where _1 is the name of the layout to be operated on (e.g., file name in a directory), x1 is the x-coordinate, y1 is the y-coordinate, and R1 is the rotation. The above data records can be read into, for example, generator software 1500 and used to define the execution of layout placement instructions. In this example, generator 1500 receives the data records and, for example, places LO1 1501 at coordinates (0,0), then rotates LO2 1502 by 90 degrees to place it at coordinates (2.2,0), and then places LO3 1503 at coordinates (6.1,0) to form layout LO1-3 1504.

[0076] In some embodiments, generator software 1500 may include executable scripts for implementing the techniques described herein. In one embodiment described below, for example, a script for accessing predetermined sub-circuit layouts and placing them according to predetermined placement instructions may be executed by, for example, EDA software (e.g., Cadence®, Mentor Graphics®, or Silvaco®).

[0077] Design Interface Additional features and advantages of some embodiments include, for example, a design interface that allows a user to generate a circuit design in software and generate a circuit schematic and / or layout. FIG. 16 illustrates another exemplary embodiment, including an example of such a design interface. In this example, design interface 1601 can be used to specify one or more functional circuit components C1-CN. In various exemplary embodiments, the design interface can be a graphical user interface (UI), a datasheet (e.g., text-based), a natural language interface (e.g., receiving voice input), or a machine-to-machine interface for receiving instructions from another machine. In this example, a user can drag and drop (or otherwise select) any of the functional circuit components C1-CN from a palette 1651 onto a canvas 1652, and these components can be connected together to generate a circuit. In this example, functional circuit components C1, C2, C3, and C4 are coupled together to form a circuit. A user can then configure the functional circuit components by setting parameters associated with different functional circuit components. An exemplary set of parameters 1654 for functional circuit components C, i = 1 to N, is shown in 1650. In some exemplary embodiments, different functional circuit components may have different sets of parameters for specifying their characteristics. As described above, for example, a comparator may have an input stage type, hysteresis, deglitch, or any other type of parameter that the system (e.g., generator and predetermined sub-circuit schematic and sub-circuit layout) is designed to support. In this example, a user selects and configures two different types of functional circuit components C1 (i.e., C1 and C1′) and two different types of functional circuit components C2 (e.g., C2 and C2′).

[0078] In some embodiments, design interface 1601 can include behavioral models for parameterized functional circuit components. A behavioral model can be, for example, a higher-level model than a transistor-level model used to simulate a transistor-level circuit diagram. A behavioral model can describe the functional behavior of a circuit, including, for example, voltages, currents, and signals, but not all physical aspects of the circuit implementation. A transistor (or device)-level model attempts to capture the physical behavior of a circuit (e.g., the fundamental physical phenomena of a device and how these phenomena actually work). A behavioral model can explain (or simulate) how a circuit is assumed to work, whereas a transistor-level model can explain how a device in a design will behave. A transistor-level model can provide more detail about the operation of a circuit, while a behavioral-level model can generate simulated experimental results more quickly. In one exemplary embodiment, a behavioral model can be, for example, a piecewise linear model of the underlying model for a functional circuit component.

[0079] Features and advantages of the present disclosure include providing parameterized functional circuit components with configurable underlying behavioral models that correspond to actual simulations of combinations of specific subcircuit schematics, so that circuits can be defined within a design interface and combined schematics and / or layouts can be automatically generated. For example, a functional circuit component C may have an associated configurable (or parameterized) model 1655 such that changing parameters 1654 changes the behavior of the functional circuit component C in the design interface. The design interface may, for example, perform behavioral model simulation of the circuit. The parameters may then be used to generate schematics and circuit layouts with substantially similar behavior. For example, device-level simulations of the subcircuits that combine to form the circuit schematic 1604 may substantially match the behavioral model simulation in the design interface.

[0080] As an example, a circuit can be defined in UI 1601 by selecting a functional circuit component C1 and then selecting desired parameters for C1 (e.g., a1=x1, a2=x2, a3=x3). A behavioral model for C1 can be configurable based on these parameters. Thus, the behavioral model for C1 with parameters (a1=x1, a2=x2, a3=x3) can be simulated to provide simulation results that indicate to the user how C1 will operate. Advantageously, the same parameters (a1=x1, a2=x2, a3=x3) are used to select one or more subcircuit schematics 1610-1612 (e.g., as described in various embodiments above) that are combined to generate circuit schematic 1604. The selected partial circuit schematics can be designed and combined to generate simulation results that substantially match between, for example, a behavioral model simulation (here, C1 (a1=x1, a2=x2, a3=x3)) and a device model simulation of the partial circuit selected using parameter values ​​a1=x1, a2=x2, and a3=x3, where the device model simulation may be more detailed and take longer to obtain than the behavioral model simulation. Furthermore, one or more partial circuit layouts 1620-1622 for each of the partial circuit schematics that are combined based on the parameter values ​​to form circuit schematic 1604 can then be combined automatically to generate corresponding layout 1605, for example, using techniques described herein. Various same or different functional circuit components can be selected and configured to generate various circuits and layouts, for example, using the same or different parameters.

[0081] Thus, a user can select functional circuit components, configure them using parameter values, and connect these components to achieve a desired circuit function at a behavioral level that is typically unaffected by actual device-level engineering challenges and potential errors. Then, for example, parameters 1602 used for the selected functional circuit components can be received by generator 1603 to automatically generate a schematic and / or layout for the user's circuit. Thus, a user can define and generate highly sophisticated analog and mixed-signal circuit schematics and layouts without having to possess all the skills typically associated with analog and mixed-signal transistor-level circuit design and layout. Furthermore, this system has the advantage of generating schematics and layouts very quickly, thereby reducing the cycle time and associated costs of analog and mixed-signal circuit schematic design and layout. For example, the cycle time for analog circuit design and layout can be on the scale of months, depending on complexity. Using the techniques described herein, the generation of analog circuit designs and layouts can be on the scale of days, hours, or even minutes, depending on complexity.

[0082] Exemplary Design and Automatic Circuit Generation Process and System Figure 17 illustrates an exemplary design and automatic circuit generation process according to another embodiment. The process illustrated in Figure 17 is described below with reference to Figure 18. Figure 18 illustrates an exemplary design and automatic circuit generation system according to another embodiment.

[0083] Referring to Figure 17, the process can begin at 1701 with the selection (e.g., by a user) of a functional circuit component using design interface 1801. At 1702, circuit specification parameters are selected for the functional circuit component. The parameters may, for example, specify particular characteristics of the functional circuit component to be generated. In Figure 18, the user has selected and configured five (5) functional circuit components (e.g., C1, C2, C1', C3, and C4, where C1 and C1' are the same functional component with different parameters).

[0084] In this example, the generator software includes a generator software component 1803 for receiving and processing circuit specification parameters 1802, specifying symbols, and generating a netlist. The generator software in this example further includes a generator script 1830 for combining selected sub-circuit schematics to lay out a sub-circuit layout. The generator software in this example can send instructions to an EDA system 1805 (e.g., to edit the schematics and layout). One exemplary system that can be used for system 1805 is, for example, an EDA system from Cadence®. In other exemplary embodiments, the functionality of the EDA system can be included within the generator software. In 1703, the circuit specification parameters are received by the generator component 1803, and symbols for the functional circuit components are specified. Examples of symbol specifications are illustrated in the exemplary netlist below. FIG. 19 shows symbols for different functional circuit components according to an embodiment. Symbols can be generated, for example, based on specific values ​​of the circuit specification parameters. For example, one set of parameter values ​​can be used to define symbol 1901, and another set of parameter values ​​can be used to define symbol 1902. These symbols can be used to encapsulate (or represent) a particular subcircuit schematic, for example, selected based on the parameter values. Referring to FIG. 18, generator component 1803 can, for example, determine subcircuit schematics 1810-1812 to use from received parameter values ​​and read all pins for these subcircuit schematics through EDA system 1805. As described above, generator component 1803 can specify connections between pins of the subcircuit schematics and can specify connections between pins of the subcircuit schematics and pins of the corresponding symbols (e.g., using a pin map). Referring again to FIG. 17, at 1704, netlist 1804 can be generated for the functional circuit components.Netlist 1804 can specify connections between pins of the subcircuit diagram selected for each parameterized functional circuit component (e.g., a comparator) and connections between such pins and pins of the symbol. Furthermore, generator component 1803 can output placement data 1808 based on the parameter values ​​and the subcircuit to be combined, as described below. Netlist 1804 can, for example, provide instructions for generating symbols and connecting pins of the subcircuit diagram, and can include names of one or more subcircuit diagrams, names for the symbols, and information for connecting pins to each other. In one exemplary implementation, the netlist can be, for example, a Verilog ".v" file. An exemplary output netlist for one subcircuit diagram and one symbol is shown below: / / Parameterized Functional Circuit Component Circuit Generator / / Functional circuit component: comparator / / Parameters: / / Name: comparator_XU0, Speed: slow, Type: n, Edge: rising / / Hysteresis: Resistor, Hysteresis: 20mV, Deglitch: No, VMAX: 6V / / 1. Specifies the partial circuit diagram "comparatorinnslow" accessed through the EDA system 1805. module comparatorinnslow(V,en,INN,INP,out,G,IP,INNHYSTPBIAS,RISEHYST, FALLHYST,a,SUB); / / Subcircuit name and pin input RISEHYST; input V; input INP; output INNHYSTPBIAS; output out; output[1:0]a; / / Bus output input FALLHYST; input IP; input INN; input G; input en; input SUB; endmodule / / 2. Instructions for generating symbols for parameterized functional circuit components module comparator_XU0(enable_comparator,IP,comparator_out,COMPARATOR_INP,register_comphysteresis,COMPARATOR_INN,G,V,SUB); input V; input enable_comparator; input IP; / / bias current input COMPARATOR_INP; input COMPARATOR_INN; output comparator_out; input G; input SUB; input[1:0]register_comphysteresis; / / End symbol specification. / / Define two-wire bus ''a''. wire[1:0]a; / / Generate a partial circuit instance "comparatorinnslow" with the instance name "Xcompn". / / Specifies a connection between a subcircuit pin and a symbol pin (or a pin of another subcircuit). comparatorinnslow Xcompn( .V(V), / / Specifies the connection between the stone pin name (.V) and the symbol pin name (V). .en(enable_comparator), / / Specifies the connection between enable pins. .INN(COMPARATOR_INN), .INP(COMPARATOR_INP), .IP(IP), .a({a1,a0}), / / Comparator output bus "a" to line "a" above .INNHYSTPBIAS(n1), / / float .FALLHYST(n2), / / float .RISEHYST(n3), / / float .SUB(SUB), .out(comparator_out), .G(G) ); endmodule

[0085] The above-described netlist may be stored in a location for subsequent access by, for example, generator script 1830. It is to be understood that the above-described netlist is only one exemplary technique for specifying symbols and connections between pins; other techniques may be used.

[0086] Once the netlist is generated, generator component 1803 can signal generator component 1830 to initiate scripts 1831-1833. In this example, EDA system 1805 can execute one or more scripts to generate circuit schematic 1831 to obtain the predetermined subcircuit schematic at step 1705 of FIG. 17. For example, pins can be connected according to netlist 1804, as shown in step 1706 of FIG. 17. For example, the netlist can be input into EDA system 1805 by a script to generate combinational schematic 1807. The result is one or more symbols generated as described above, with each symbol having a subcircuit schematic within it (e.g., lower in the circuit schematic hierarchy) that is used to form each symbol with pins connected to each other based on the netlist. The symbols represent, for example, transistor (or device) level circuit schematics for functional circuit components with parameter values ​​received by the generator. For multiple functional circuit components with corresponding sets of parameter values, for example, multiple symbols and corresponding schematic diagrams can be generated within an EDA system.

[0087] Referring again to FIG. 17 , at 1707, predetermined sub-circuit layouts 1820-1822 are accessed using a combinational sub-circuit schematic. For example, in one embodiment, each sub-circuit schematic 1810-1812 has one or more corresponding predetermined sub-circuit layouts 1820-1822. The sub-circuit schematic can be used by a layout generation script 1832 to retrieve the corresponding sub-circuit layout using an EDA system 1805. At 1708, the predetermined sub-circuit layout is placed based on the layout placement instructions. Advantageously, the placement data 1808 can be automatically retrieved by a layout placement script 1833, and each sub-circuit layout can be placed as described above to generate a circuit layout 1809.

[0088] Example Generator 20A shows an exemplary generator software system 2001 according to one embodiment. It is to be understood that the following implementation is only one exemplary implementation of a generator for implementing the techniques described herein. Other software architectures can be used to implement some or all of the techniques described herein.

[0089] The generator 2001 can receive parameters that specify the analog circuit to be generated. The parameters can correspond to one or more different functional circuit components. As described above, the information specifying the circuit to be generated can be received in a wide variety of ways. Accordingly, the generator 2001 can include a decoder 2002 for receiving the parameters and extracting the information. In one embodiment, the parameters are received as text, and the decoder 2002 parses the test to extract the parameters. The generator 2001 can include an FCC and subcircuit determination block 2003 for receiving the parameters and determining which functional circuit components to generate and which subcircuits to use within each functional circuit component. The generator 2001 can include a limit comparison block 2004 for comparing the parameters for the various functional circuit components to ensure that they are within predetermined limits. If the parameters are outside the limits, the circuit cannot function, and the system can trigger, for example, an error signal or a default for other parameter values.

[0090] In various embodiments, the generator system can receive predetermined information about the circuit to be generated to facilitate automatic circuit schematic generation and / or automatic layout generation. The generator according to various embodiments can, for example, generate subcircuit pin lists, layout scripts to be associated with a particular circuit schematic or family of circuit schematics, parameter limits (as described above), layout parameters (e.g., lengths of various components), access processing parameters, and / or customize functional circuit component pin lists based on the received parameters. In this example, each functional circuit component has associated data used by the generator 2001. For example, data for one functional circuit component (FCC A) 2020 may include multiple pin lists 2021-2023 for different subcircuit schematics (e.g., subcircuit schematics 1A-NA), a pin list 2024 for the functional circuit component (e.g., all possible pins used for various variants of FCC A), one or more layout scripts 2025 used for various variants of FCC A 2020, parameter limits 2026 for FCC A, layout parameters 2027 (e.g., component lengths for calculations described in more detail below), and processing parameters 2028 (e.g., used for some calculations and / or automatic layout, as described in more detail below). Other data for other functional circuit components (e.g., FCC B 2030) may include, for example, similar data 2031-2038. Such data may be stored, for example, in a file or database accessible by generator 2001. In some embodiments, some data may be hard-coded into the generator code.

[0091] Generator 2001 can access data regarding functional circuit components to perform various functions. In some embodiments, described in more detail below, generator 2001 can include code for determining resistor attributes, capacitor attributes, and / or transistor attributes (e.g., code blocks 2006-2008, respectively, referred to herein as calculated values ​​2005). One or more of the code blocks can receive, for example, layout parameters or processing parameters for a particular functional circuit component, as described in more detail below. Calculated values ​​2005 can include, for example, one or more circuit models 2009-2010 (e.g., corresponding to a particular functional circuit component) for deriving various values ​​used by blocks 2006-2008 from values ​​in the received parameters. While examples of bias current models and delay circuit models are provided below for illustrative purposes, other circuit models can be included within generator 2001, for example. The calculated value 2005 can determine a component value (e.g., for a resistor, capacitor, or transistor) that can be based on layout parameters (e.g., one or more predetermined dimensions for use with the layout). In various embodiments, multiple components (e.g., segments or unit components) are generated within the circuit specification and connected to form a combined component. In one embodiment, the component value is encoded within an identifier associated with multiple component symbols included within the circuit specification. In one embodiment, the component value is encoded within a symbol name for the component, for example, as described in more detail below.

[0092] In various embodiments, the generator may include code for generating a circuit specification based on the parameters. In this example, circuit generation specification code 2011 includes, for example, code 2012 for retrieving pins for a subcircuit schematic to be used for the circuit to be generated (Get Circuit Pins), code 2013 for generating a symbol for the circuit to be generated, and code 2014 for connecting pins of the subcircuit to pins of the symbol (e.g., Connect Pins). In this example, the connected pins in the circuit specification form a pin map as described above.

[0093] Circuit generation specification 2011 can receive an indication of which subcircuit diagrams to include in the circuit specification and can retrieve pin lists for those subcircuit diagrams (e.g., one or more of pin lists 2021-2023 or 2031-2033). An exemplary pin list for subcircuit A to be generated in the circuit specification is as follows: Module <sub-circuita>(pin1,...,pinN) Input pin1 ... output pinN endmodule

[0094] If the pin list is for N pins, some of the pins may be input pins and others may be output pins, for example. In one embodiment, the pin list may be a functional diagram of a partial circuit schematic received from EDA tool 2060, for example.

[0095] Additionally, in this example, symbol generation 2013 can determine which pins (e.g., from all possible pins for a particular functional circuit component) to include on the symbol based on the parameters. For example, it can receive FCC A pin 2024, evaluate the parameters, and determine which pins to include in the symbol for the circuit to be generated. An example symbol generated based on the parameters is as follows: Module <symbolname>(pin1,...,pinM) Input pin1 ... output pinM <sub_circuits&connections> endmodule

[0096] In the above explanation,<sub_circuits&connections> specifies the subcircuits and connections, as exemplified below. Pin connections 2014 can map pins of one or more subcircuit diagrams to pins of other subcircuit diagrams or symbols. These mappings can be included, for example, in the code for pin connections 2014. In one embodiment, the code for pin connections 2014 includes string generators for the various possible combinations of subcircuit diagrams and symbols that are selected based on parameters. The following description shows that the pin maps generated in the circuit specification are as follows: Module <symbolname>(pin1,...,pinM) Input pin1 ... output pinM sub-circuit_1(.subcir1_pin1(symbol / subcir_pin),.subcir1_pin2(symbol / subcir_pin),...,.subcir1_pinX(symbol / subcir_pin)) sub-circuit_2(.subcir2_pin1(symbol / subcir_pin),.subcir2_pin2(symbol / subcir_pin),...,.subcir2_pinY(symbol / subcir_pin)) ... sub-circuit_K(.subcirK_pin1(symbol / subcir_pin),.subcirK_pin2(symbol / subcir_pin),...,.subcirK_pinZ(symbol / subcir_pin)) endmodule

[0097] The result of the above description is a circuit specification for a symbol containing M pins with K subcircuits. Pin connections are established by "subcir1_pin1(symbol_pin / subcir_pin)". The following description establishes a connection between pin "VOUT" on subcircuit "AMP" and pin "VIN" on another subcircuit: Module EXAMPLE_SYMBOL(IN,VCC,OUT) Input IN / / Symbol pin Input VCC / / symbol pin output OUT / / symbol pin AMP_1( .VIN(IN) / / Connects the vin pin on AMP_1 to the IN pin on the symbol. .VDD(VCC) / / Connect the vdd pin on AMP_1 to the VCC pin on the symbol. .VOUT(VIN) / / Connects the VOUT pin of AMP_1 to the VIN pin of another subcircuit (not shown). endmodule

[0098] Features and advantages of some embodiments include generating a layout script for automatic layout generation of a circuit. In one embodiment, the layout script can be customized for a particular circuit embodied in the circuit specification. The generator 2001 can include code for retrieving one or more predefined layout scripts customized for the one or more circuits to be generated based on the received parameters. For example, the layout script generation code 2015 can retrieve a layout script for a particular combination or configuration of specific functional circuit components or subcircuit schematics (and calculated resistors, capacitors, or transistors, if any) based on the received parameters.

[0099] Thus, generator 2001 can generate circuit specifications 2040 / 2050 and layout scripts 2045 / 2055 for each circuit generated in response to the received parameters. As shown in 2040 for the first circuit (Ckt1 Spec) and 2050 for the second circuit (Ckt2 Spec), the circuit specifications can include, for example, subcircuit schematic pin lists 2041-2042 / 2051-2052, symbolic pins 2043 / 2053 (which can encapsulate the subcircuit schematic and any calculated components), and pin maps 2044 / 2054 that specify connections between pins. In various embodiments, one or more functional circuit components can be incorporated into the circuit specifications. Some embodiments, for example, can include multiple functional circuit components that are coupled together to form a more complex circuit.

[0100] The circuit specification and layout script can be received and processed by an EDA tool 2060. For example, the EDA tool can receive the circuit specification as a Verilog.v file and generate symbols in which, for example, predetermined subcircuits are written and connected together according to a pin map. Different circuit specifications can be used to generate various circuit schematics 2070, 2072, 2074. The schematics can be converted into layout instances and automatically arranged to form layouts 2071, 2073, and 2075.

[0101] FIG. 20B shows an exemplary method for generating a circuit specification according to an embodiment. In this example, at 2080, information specifying a circuit to be generated is received. The information may be in the form of parameters that can be parsed, for example, or in another format that can be decoded, for example. In some embodiments, the system may retrieve parameter limits and compare one or more parameters to the parameter limits to validate the parameters. At 2081, a subcircuit diagram pin list may be selected (e.g., based on the parameters specifying the circuit to be generated). For example, based on the information described above, one or more pin lists corresponding to one or more subcircuit diagrams may be selected. Each pin list may include subcircuit diagram pins for the corresponding subcircuit diagram. In one embodiment, the pin lists and symbols may correspond to particular functional circuit components. As described above, different functional circuit components may have different associated subcircuit diagram pin lists and different predetermined pins for the functional circuit component symbol. At 2082, a predetermined set of pins for the symbol is selected based on the information described above. Different realizations of each functional circuit component may have different pins (e.g., a comparator that provides shutdown may have a shutdown pin, while a comparator that does not provide shutdown may not). However, in some embodiments, symbols implemented for the same functional circuit component may have certain pins common across all parameters (e.g., a voltage-to-current converter may necessarily have a voltage input pin VIN, a power supply pin VDD, a ground GND, and a current pin that may be a source or sink based on the parameter). At 2083, connections may be established between the partial circuit diagram pins and a plurality of predetermined subsets of pins for the symbol. At 2084, a circuit specification is generated. The circuit specification includes partial circuit diagram pins from one or more pin lists corresponding to one or more partial circuit diagrams, the predetermined subset of pins for the symbol, and connections between the partial circuit diagram pins and the predetermined subset of pins for at least one symbol.The circuit specification can be processed in an EDA tool, for example, to generate a circuit schematic diagram. Additionally, a layout script configured to automatically place layout instances to generate a layout for the circuit generated from the circuit specification can be retrieved based on the information described above. The system can retrieve processing parameters. The layout script and processing parameters can be sent to the EDA tool, for example, to generate the layout.

[0102] FIG. 20C illustrates a method for generating a circuit specification according to another embodiment. Features and advantages of the present disclosure include generating symbols for computed component values, which are described in more detail below. The following technique is one exemplary technique for generating a circuit specification for computed component values. At 2090, the system receives information specifying an electronic circuit to be generated. At 2091, the system determines a component value for at least one component of the electronic circuit based on this information. In various embodiments, the component can be a resistor (e.g., the component value includes resistance), a capacitor (e.g., the component value includes capacitance), or a transistor (e.g., a FET whose component value includes gate width, number of fingers, etc.). At 2092, the system generates a plurality of component symbols. The number of symbols can be part of the component value calculation, as described below for resistors, capacitors, and transistors. At 2093, the system encodes the component value into an identifier associated with each of the component symbols. For example, the identifier can be, for example, a symbol name, and the component value can be encoded within the symbol name. At 2094, the system establishes connections between the component symbols. At 2095, the system generates circuit specifications for configuring the component symbols in series, parallel, or both. The circuit specifications can be sent to an EDA tool and used to generate circuit schematics.

[0103] It is understood that a circuit specification can include multiple symbols for multiple functional circuit components. Each symbol can include a symbol for a computational component value. Functional circuit components can be organized hierarchically, where, for example, a symbol for a first functional circuit component is encapsulated by a symbol for a second functional circuit component, and a partial circuit diagram for the first functional circuit component is coupled to a pin of the second functional circuit component symbol. Thus, commonly used functional circuit components (e.g., buffers, current mirrors, etc.) can be used, for example, as building blocks for other functional circuit components.

[0104] Calculated value The present disclosure further relates to automatically generating electronic components such as resistors, capacitors, or transistors.

[0105] In various embodiments, it may be advantageous to automatically generate circuits in which resistor, capacitor, or transistor values ​​can be varied (e.g., continuously). For example, one circuit may require a resistor, capacitor, or transistor with a particular value, and another instance of the circuit may require a resistor, capacitor, or transistor with a different value. Accordingly, techniques are disclosed herein for automatically generating resistors, capacitors, or transistors that can be varied over a range of values.

[0106] FIG. 21A illustrates a method for generating circuit components over a range of values ​​according to one embodiment. Features and advantages of the present disclosure may include generating components by configuring a plurality of such components (e.g., unit components) over a range of values ​​to form a combined component. For example, a total attribute value for the components to be generated may be received by the system at 2101. The total attribute value may be, for example, the total resistance, total capacitance, or total gate width of each of the resistors, capacitors, or transistors to be generated. The total attribute value may be received from a variety of sources. In some embodiments, the total attribute value is received as a parameter (e.g., specified by a user). In other embodiments, the total attribute value is determined by the system based on other parameters (e.g., parameters for a circuit model or on-resistance). At 2102, the total attribute value may be used to determine a second attribute value used to determine (at 2103) the number (N) of components to be combined to form the combined component having the total attribute value. As shown in the examples below for various different component types (e.g., resistors, capacitors, and transistors), unit components (e.g., resistor segments, unit capacitors, or transistors with unit gate lengths) can be combined to form a combined component having a total attribute value (e.g., total resistance, total capacitance, or total gate width). In one embodiment, at least one layout parameter is received by the system, and a second attribute value for the to-be-generated component is determined based on the at least one parameter. In various embodiments, the layout parameter can specify a length along a dimension of the to-be-generated component. For example, for a resistor, the layout parameter can specify a resistor layout segment length.For a capacitor, the layout parameter may specify the maximum length along a first dimension (e.g., maximum width) of a unit capacitor. For a transistor, the layout parameter may specify the unit gate width. Advantageously, by incorporating one or more layout parameters that specify physical attributes of the layout, both the circuit and the layout can be generated automatically, as further illustrated in the example below.

[0107] At 2104, a circuit specification is generated. As described above, the circuit specification may specify components of the circuit schematic diagram to be generated and connections between those components. For example, if the system determines that a number (N) of components having a second attribute value can be combined to form a component having a total attribute value, then the circuit specification may specify N such components (e.g., N resistors R1,...,RN, N capacitors C1,...,CN, or N transistors M1,...,MN). The circuit specification may specify connections such that the N components combine to form a total attribute value of a combinational component (e.g., resistors connected in series and / or parallel, capacitors connected in series and / or parallel, or transistors connected in parallel).

[0108] At 2105, a transistor-level schematic diagram is generated that includes a plurality of components configured with the second attribute value. For example, in one embodiment, a circuit specification can be received by an EDA software tool (e.g., as Verilog input). The EDA tool can read the circuit specification and generate an empty symbol for each component specified therein. In one exemplary embodiment, a script can be used to insert components into each symbol and configure the components with the second attribute value. Terminals of the components are then automatically connected to terminals of the symbol. The symbols can also be connected to each other based on the circuit specification. Thus, the plurality of components form a combined component having a total attribute value. At 2106, a layout is generated. The layout can include N layout instances that correspond to the components configured to generate the total attribute value. In various examples described below, each component can be converted into a layout instance (e.g., a resistor layout component, a capacitor layout component, or a transistor layout component). The layout instances can be automatically placed, for example, using a predetermined script associated with the particular circuit being generated.

[0109] FIG. 21B illustrates a method for generating circuit components across a range of values ​​according to another embodiment. As discussed above, features and advantages of the present disclosure include incorporating layout parameters into the design flow when a circuit is being generated. Typically, layout is performed after the circuit is designed. Embodiments of the present disclosure can incorporate layout parameters as part of the circuit generation process to enable automatic generation of schematics and layouts. For example, at 2110, information specifying an analog circuit to be generated is received by the system. At 2111, layout parameters are derived based at least in part on this information. For example, different implementations of a particular analog circuit (e.g., comparators, current sources, oscillators, power FETs, bias currents, etc.) may have resistors, capacitors, and transistors that differ in size based on parameters of the circuit being generated. If the circuit includes resistors, layout parameters for the resistors can be derived. If the circuit includes capacitors, layout parameters for the capacitors can be derived. If the circuit includes transistors, layout parameters for the transistors can be derived. Layout parameters can be predetermined based on the particular circuit being generated and used with the associated circuit. Thus, for example, parameters used to generate the layout (e.g., predetermined lengths along various dimensions) can be included in the circuit generation process to automate the circuit and layout generation process. At 2112, one or more attributes of the analog circuit components are determined based on information specifying the analog circuit to be generated and the layout parameters. At 2113, a transistor-level schematic diagram of the analog circuit including one or more of the analog circuit components is generated, and the one or more analog circuit components are configured using the attributes. At 2114, a layout is generated from the transistor-level schematic diagram. The layout can include multiple layout instances corresponding to one or more analog circuit components, and each layout instance is automatically placed in the layout by layout placement instructions.As shown in various examples below, layout instances can be placed based on attributes of analog circuit components (e.g., resistors can be placed based on resistor segment length, capacitors can be placed based on capacitor width, and transistors can be placed based on gate width). In some embodiments, the layout parameters used to determine the attributes of the components are also used to position layout instances derived from the schematic for the components.

[0110] 21C illustrates a method for generating circuit components over a range of values ​​according to yet another embodiment. As discussed above, features and advantages of some embodiments of the present disclosure may include techniques for specifying and generating analog circuits within EDA tools that may not support automatic analog circuit generation. For example, existing EDA tools lack mechanisms for receiving analog circuit specifications that can be used to automatically generate transistor-level analog circuit schematics and generate efficient analog circuit layouts for complex parameterized analog functional circuit components. Embodiments of the present disclosure may, for example, generate circuit specifications and convert the circuit specifications into transistor-level circuit schematics and / or layouts using predetermined scripts.

[0111] Auto-generation of resistors Features and advantages of the present disclosure include automatic resistor generation, in some embodiments, capable of generating resistors across a range of values ​​for use in, for example, transistor-level circuit schematics and / or layouts.

[0112] 22 illustrates a computer-implemented system for automatically generating resistors according to an embodiment. The computer-implemented systems described herein may include software executing on a computer system 2201, which may include one or more computers (e.g., server computers). In this example, computer system 2201 executes generator software 2202 and schematic and layout generator software 2203. It is understood that other exemplary implementations may divide the software differently (e.g., as a single software system or as more software components that perform the functions described herein).

[0113] A feature and advantage of the present disclosure is that the system can automatically generate a circuit schematic, layout, or both, including resistors based on specified or calculated resistor values ​​received by the system. For example, a system according to the present disclosure can receive resistor values ​​and automatically generate a schematic for the resistor, a layout for the resistor, or both. In this example, a resistor value Rtotal corresponding to resistor 2210 would be generated by resistor specification generator component 2212 of generator software 2202. In various embodiments, one or more resistor values ​​can be specified, for example, by a user, and received as input parameters by generator software 2202. In other embodiments, one or more resistor values ​​can be calculated, for example, based on other parameters received by generator 2202, as described in more detail below.

[0114] Features and advantages of some embodiments include converting resistor values ​​into segments, such as series resistor segments to be generated, parallel resistor segments to be generated, or one or more combinations of both series and parallel resistors. For example, resistor specification generator 2212 can determine a first number N of resistor segments to be configured in series and / or a second number M of resistor segments to be configured in parallel to approximately generate resistor value Rtotal. In one embodiment, for example, the resistances of these resistor segments can be the same. Once the numbers N and / or M are determined, circuit specifications 2213 (e.g., for Rtotal) can be generated, for example, for generating a schematic diagram, layout, or both. In this example, resistor specification generator 2212 can generate circuit specifications 2213 for configuring a first number N of resistor segments in series and / or a second number M of resistor segments in parallel. Although this specification shows one series and one parallel combination of resistors to generate Rtotal, it is understood that, for example, only series combinations, only parallel combinations, or multiple series and / or parallel combinations can be used to achieve an Rtotal that is within an acceptable tolerance.

[0115] In various embodiments, circuit specification 2213 can specify configurations for multiple components. In this example, the components correspond to resistor segments (e.g., as illustrated by resistor segments 2214-2218), and circuit specification 2213 can specify connections between these resistor segments. For example, the circuit specification can be a netlist, such as a verilog.v file as described above, where connections between components are based on commonly designated nodes in the netlist.

[0116] Exemplary embodiments of the present disclosure can further receive one or more predetermined physical dimensions for the resistor segment 2211. The predetermined physical dimensions can be set, for example, to advantageously optimize the layout of different resistor values, as further illustrated below. For example, the predetermined physical dimensions can be a predetermined length Lseg of the resistor segment and / or a predetermined width Wseg of the resistor segment. The predetermined physical dimensions can be associated with the resistor value to be generated such that the particular resistor to be generated has access to the predetermined physical dimensions. Thus, once a particular resistor value Rtotal for a particular circuit or project is received, relevant parameters such as Lseg and / or Wseg for this particular resistor can be retrieved, for example, from a known storage location (e.g., from a memory, file, or database).

[0117] In some embodiments, different resistors to be generated for different resistor values ​​may have different corresponding predetermined physical dimensions (e.g., lengths and / or widths). Thus, one resistor to be generated having a first value Rtotal1 may have a first corresponding predetermined length and / or predetermined width, and another resistor to be generated having a second value Rtotal2 may have a second corresponding predetermined length and / or predetermined width. As described above and further exemplified below, incorporating one or more predetermined physical dimensions may be used to improve resistor layout across various resistor value ranges, for example.

[0118] In some embodiments, the resistor specification generator 2212 can further receive, for example, a sheet resistivity.

[0119] The following equations show an exemplary calculation of N and M based on a predetermined length, a predetermined width, and a sheet resistivity: N=The number of resistor segments 2211 in series may be based on the integer portion of Rtotal divided by the segment resistance Rsegment (e.g., Div(Rtotal / Rsegment), ie, the quotient of Rtotal divided by Rsegment). M = The number of resistor segments 2211 in parallel may be based on the remainder of Rtotal divided by the segment resistance Rsegment (e.g., Mod(Rtotal / Rsegment)). In one exemplary embodiment, a maximum number of parallel resistors may be specified, and the value for M is, for example, the number of parallel resistors that results in Rtotal within an acceptable tolerance. Lseg is stored in BIO, and Wseg is calculated from the process design rules.

[0120] The resistance of a segment can be written as: Rseg=ρ(Lseg / Wseg)

[0121] where ρ(rho) is the sheet resistivity (known as "sheet rho," a parameter specified by the particular semiconductor manufacturing process used), Lseg is the segment length, and Wseg is the segment width (e.g., these can be set based on the current density and the particular resistor type used). Thus, the resistance of a resistor segment may be based on its length, width, and / or rho.

[0122] The total resistor value Rtotal can be determined as follows: Rtotal=(Rseg * M) -Series only Rtotal=(Rseg / N) - Parallel only Rtotal=(Rseg * M)+(Rseg / N) - Series and parallel combination

[0123] Features and advantages of certain embodiments may further include generating a schematic diagram for resistor values ​​based on the circuit specification. In this example, the circuit specification 2213 is sent from the generator software system 2202 to the schematic and layout generator software system 2203. The schematic and layout generator software system 2203 may be, for example, the electronic design automation (EDA) software system described above. The software system 2203 may include a schematic generator component 2220 for generating a resistor schematic 2221 from the circuit specification 2213. The schematic generator component 2220 may, for example, receive a netlist and convert it into, for example, schematic symbols and connections between the schematic symbols. However, some schematic generators may not be able to set attributes of components, such as resistors, to specific specified values ​​based on the netlist. Thus, in one exemplary embodiment, the schematic import component 2222 can analyze, for example, the circuit specification 2213 or the generator circuit schematic 2221 and set attributes of components such as resistors therein.

[0124] In one exemplary embodiment, the circuit specification 2213 can specify components that correspond to resistor segments, and the schematic generator 2220 can generate schematic symbols that do not have resistor segments for such components (e.g., a generated symbol can be empty if a component name in the netlist does not exist in the software system 2203 library). Thus, initially, the generated circuit schematic includes multiple empty symbols, with the pins of the symbols connected to each other as specified in the received netlist. The schematic import component 2222 can implement an algorithm for identifying empty components and inserting resistor segments into the symbols. For example, the schematic import component 2222 can automatically insert resistor segments into each empty schematic symbol and connect the terminals of the inserted resistor segments with the pins of the schematic symbol.

[0125] In some embodiments, the schematic import component 2222 may include code for setting attributes of a resistor. For example, attributes for a resistor may include the resistor's physical dimensions, such as length and width. Attributes may include the resistor type (e.g., polysilicon, doped polysilicon, or metal). Attributes of one or more resistors may be passed between software components in various ways. In one embodiment, the specification may include information for setting attributes. For example, attributes may be encoded in an identifier for a component in the circuit 2213 (e.g., encoded in the resistor's name in the netlist). Thus, when a symbol for a component in the netlist is used to generate a symbol, the symbol may include the identifier. The identifier may be read, for example, by the schematic import component 2222 and used to place a resistor into an empty symbol. In other embodiments, attributes may be stored, for example, in a predetermined location and accessible by the schematic import component 2222. A more detailed example technique for passing attributes for a resistor is provided below for illustrative purposes.

[0126] Thus, the diagram generator 2220 can output a resistor diagram 2221. The resistor diagram 2221 can include multiple symbols with pins. Each symbol can have resistor segments embedded therein. As described above, the symbols can be combined with one another in one or more series and / or parallel configurations. For example, combined symbols, each with an internal resistor segment, form a desired total resistor value Rtotal. In some exemplary embodiments, the resistor segments used to form a single total resistor value Rtotal can each have the same length, width, and resistor type.

[0127] Features and advantages of some embodiments of the present disclosure may include automatically generating a resistor layout from a resistor schematic. For example, resistor schematic 2221 may be converted into resistor layout 2224 by layout generator 2223. Layout generator 2223 may, for example, convert resistor segments in a circuit schematic symbol into a plurality of polygons, each polygon having dimensions specified for the corresponding resistor segment. In one embodiment, layout placement instructions 2225 may be executed to place each polygon in the layout, as described in more detail below. Thus, resistor segments forming a total resistor value Rtotal in the schematic may be automatically converted into resistor layout 2224.

[0128] FIG. 23 illustrates a method for generating a resistor according to an embodiment. In one embodiment, the present disclosure includes software that, when executed, performs the method as follows: At 2301, a resistor value to be generated can be received. At 2302, the software can determine at least one number of series-configured resistor segments or at least one number of parallel-configured resistor segments (or both) to generate the received resistor value. At 2303, a circuit specification is generated. The circuit specification can, for example, specify a configuration of multiple components corresponding to the resistor segments. At 2304, a schematic diagram is generated based on the circuit specification. The schematic diagram can include multiple symbols corresponding to multiple components. Each symbol can include, for example, a resistor segment. The symbols are automatically connected to each other based on the circuit specification to provide the resistor value. At 2305, a layout can be generated from the circuit schematic. The layout can include a polygon corresponding to each resistor segment. In one embodiment, the polygons are automatically placed by layout placement instructions.

[0129] 24 illustrates a method for generating a resistor according to another embodiment. In this example, at 2401, a resistor value for a resistor to be generated is received, and at least one physical dimension corresponding to at least one resistor segment is received at 2402. In this example, physical dimensions such as length and / or width can be advantageously used to, for example, optimize the layout of multiple resistor segments from which the resistor value is generated. At 2403, software can determine the number of at least one series-configured resistor segments or the number of at least one parallel-configured resistor segments to generate the received resistor value. At 2404, circuit specifications are generated.

[0130] 25A illustrates a method for generating a resistor according to yet another embodiment. In this example, at 2501, a resistor value for a resistor to be generated is received, and at 2502, a circuit specification is generated. Here, the circuit specification specifies components that correspond to resistor segments. At 2503, a schematic diagram is generated based on the circuit specification. The schematic diagram includes symbols that correspond to components in the circuit specification. In this example, the symbol may not have a resistor segment (e.g., the symbol is empty). Thus, at 2504, a resistor segment is inserted into the symbol. The symbol and the inserted resistor segment can be combined together in the schematic diagram to generate the resistor value.

[0131] FIG. 25B illustrates a method for generating a resistor according to yet another embodiment. In this example, at 2510, resistor values ​​for a resistor to be generated are received, and at 2511, a circuit specification is generated. Here, the circuit specification specifies components corresponding to resistor segments having one or more predetermined physical dimensions. At 2512, a schematic diagram is generated based on the circuit specification. The schematic diagram includes resistor segments (e.g., in series and parallel) configured to generate the resistor values. At 2513, a layout is generated. The layout includes polygons corresponding to the resistor segments. The polygons can be advantageously positioned based on, for example, one or more predetermined physical dimensions of the resistor segments to generate a layout of the resistor.

[0132] FIG. 25C illustrates another embodiment. Various embodiments of the present disclosure can apply some or all of the techniques described herein in various combinations and at various different levels to automate resistor generation. In this example, at 2520, resistor values ​​are determined (e.g., by a circuit generation engine). At 2521, the resistor values ​​can be converted to a circuit schematic (e.g., to an EDA transistor-level schematic in Cadence®). Then, at 2522, the circuit schematic is converted to polygons. At 2523, the polygons for the resistors can be automatically placed by layout placement instructions. For example, a particular circuit being generated can be associated with multiple layout placement instructions that place each of the polygons for the resistors at a specific location in the layout. The layout placement instructions can, for example, place each polygon in a sequence and make connections between the terminals of the polygons to generate the desired resistor value.

[0133] Exemplary Embodiments for Generating Resistors FIG. 26 illustrates an example resistor schematic and layout, according to an embodiment. In this example, resistor schematic 2610 includes N symbols 2611-2613 coupled together in series and M symbols 2614-2616 coupled together in parallel. These symbols may be coupled together, for example, through pins. As shown, the parallel symbols are in series with the series configuration symbols. Example symbol 2620 includes symbol pins 2621 and 2622. Symbol 2620 includes resistor segment 2623 Rseg having first terminal 2624 and second terminal 2625. As noted above, in some embodiments, symbol 2620 can be generated without a resistor segment (e.g., as an empty symbol). Resistor segment Rseg may have been inserted into symbol 2620 by software. Further, the software can, for example, connect resistor terminal 2624 to symbol pin 2621 and associate resistor terminal 2625 with symbol pin 2622. In one embodiment, the software can include scripts (e.g., Skill scripts in Cadence®) that can run, for example, within an electronic design automation (EDA) software system and detect empty symbol instances resulting from, for example, a circuit schematic generated in response to receiving a netlist, and automatically insert resistors. Further, the scripts can set attributes of the inserted resistors with values ​​generated as described above.

[0134] The combined resistance of the resistor segments in symbols 2611-2616 can produce a total resistor value Rtotal to be generated. As mentioned above, in some embodiments, these resistor segments can have, for example, the same resistor segment value Rseg, the same predetermined length Lseg, and the same predetermined width Wseg. Using one or more known lengths and / or widths for the resistor segments can advantageously enable efficient automated layout.

[0135] Example layouts 2690a-2690c illustrate how different resistor values ​​can be automatically generated according to various embodiments. Layout 2690a includes two subcircuits 2650 and 2651 and a resistor including multiple resistor layout segments 2680. Resistor layout segments 2680 can correspond to, for example, multiple polygons in the layout. Resistor layout segments 2680 can be generated from a resistor schematic, such as circuit schematic 2610. Thus, in this example, resistor segment 2623 in symbols 2611-2616 generates corresponding polygon 2680. In other embodiments, for example, a single resistor in a schematic can be converted into multiple polygons and automatically placed as described herein. In this example, each of resistor layout segments 2680 has the same length Lseg and width Wseg. The resistor layout segments 2680 are arranged in parallel (e.g., side by side along the length or width) as shown and can be coupled together (e.g., using metal or poly-Si) in series and / or parallel (e.g., as shown in circuit schematic 2610) so that the total resistance is Rtotal.

[0136] As shown in layouts 2690a-2690c, different numbers of resistor layout segments 2680 can be used to generate different Rtotal values. Some Rtotal values ​​may result in fewer resistor layout segments, while other Rtotal values ​​may result in more resistor layout segments. Layouts 2690b and 2690c illustrate two resistance values ​​for Rtotal. Layout 2690b has fewer resistor layout segments than layout 2690c. However, based on the configuration of parallel and series resistors, the Rtotal value of layout 2690b may be greater or less than the Rtotal value of layout 2690c. Advantageously, the number of resistor layout segments used across different designs for different Rtotal values ​​can be varied by arranging the resistor layout segments side-by-side (e.g., along their lengths) and coupling them together according to different numbers of series and / or parallel combinations, as shown. As described in more detail below, the layout placement instructions can place resistor layout segments in parallel along their lengths in areas reserved for resistor layout segments. In this example, an area 2660 in the layout vertically below layout 2651 for circuit 1 and horizontally close to subcircuit 2650 is reserved for resistor layout segment 2680. The reserved area 2660 in the layout can include a polygon having one dimension (here, reserved height Hr) approximately equal to the resistor segment length (e.g., plus an offset) and a second dimension (here, reserved width Wr) equal to a multiple of the resistor segment width (e.g., plus an offset or spacing between segments) to fit the resistor layout segments across a range of total resistance values ​​Rtotal. In one exemplary embodiment, the reserved width Wr is equal to a multiple of the resistor layout segment width plus an offset that matches the minimum and maximum number of resistor layout segments to generate resistors ranging from a minimum total resistance value Rtotal_min to a maximum total resistance value Rtotal_max.

[0137] FIG. 27A shows an example layout generated for two resistor values ​​used with two different circuits, according to an embodiment. In this example, a first resistor value Rtotal1 for use with a first circuit (Ckt1) can be converted into a layout by layout generator software 2790. In one embodiment, the resistor value (e.g., Rtotal1) is a calculated value for one functional circuit component (e.g., a bias current generator) specified, for example, using parameters as described above. Rtotal1 can be used to generate a schematic diagram including multiple resistor segments, as described above. The resistor segments can have, for example, a first predetermined length Lseg1 associated with Rtotal1 and a corresponding circuit (Ckt1) and can be included in the schematic diagram. The resistor segments in the circuit schematic are converted into resistor layout segments 2710, each having a first predetermined length Lseg1, as shown in layout 2701. Layout 2701 may further include sub-circuits corresponding to, for example, circuit configurations (e.g., current biasing circuit configurations) for the first circuit in which Rtotal1 is used. Generator 2790 may, for example, implement the first circuit as sub-circuit layouts 2751 and 2752.

[0138] A second resistor value Rtotal2 for use in the second circuit (Ckt2) can be converted into a layout by layout generator software 2790, where Rtotal2 is, for example, a calculated value for another functional circuit component (e.g., an oscillator) specified using parameters as described above. Rtotal2 can be used to generate a schematic diagram including multiple resistor segments as described above. The resistor segments can have, for example, a second predetermined length Lseg2 associated with Rtotal2 and the second circuit (Ckt2) and can be included in the schematic diagram. The resistor segments in the circuit schematic are converted into resistor layout segments 2720, each having a second predetermined length Lseg2, as shown in layout 2702. Layout 2702 can further include a subcircuit corresponding to, for example, a circuit configuration for the second circuit (e.g., an oscillator circuit configuration) in which Rtotal2 is used. Generator 2790 may, for example, implement a second circuit as subcircuit layouts 2753 and 2755 .

[0139] The example illustrated in FIG. 27A illustrates that, in some embodiments, resistor values ​​used with different circuits can have different predetermined physical dimensions. In various embodiments of each circuit, more or fewer resistor layout segments 2710 and 2720 can be used for circuits 2751 / 2752 and 2753 / 2754 / 2755 as Rtotal1 and Rtotal2, respectively, change. However, segment lengths Lseg1 and Lseg2 can remain the same. However, as shown in the example below, physical dimensions such as length can be varied to optimize the layout, for example, based on which other subcircuits are included within the circuit.

[0140] FIG. 27B illustrates two resistor values ​​used with the same circuit, according to an embodiment. In this example, two resistor values, Rtotal3 and Rtotal4, for two different resistors to be generated are provided to layout generator software 2790, which generates layout 2703, for example. In this example, a first received resistor value, Rtotal3, corresponding to a first resistor in the circuit is converted into a plurality of resistor layout segments 2730, each having a length, Lseg3. Similarly, a second received resistor value, Rtotal4, corresponding to a second resistor in the circuit is converted into a plurality of resistor layout segments 2740, each having a length, Lseg4. Generator 2790 can generate layouts for the circuit as sub-circuit layouts 2756 and 2757, for example. It is understood that in still other embodiments, Rtotal3 and Rtotal4 can use the same resistor segment length, Lseg, for example.

[0141] FIG. 28 illustrates example layouts generated for resistor values ​​for different subcircuit configurations, according to embodiments. In some embodiments, different physical dimensions may be used for the same resistor value Rtotal 2850 based on other circuit configurations used in the layout. For example, to optimize the resulting layout when the surrounding circuit configuration changes (e.g., when different parameter types or parameter values ​​select different subcircuits), resistor layout segments of different sizes that fit into different available spaces may be used. In this example, a resistor value of Rtotal may be implemented in a resistor layout segment having a length Lseg1 when this resistor is included in a circuit having subcircuits 2810 and 2811, as shown in layout 2801. However, when the resistor is included in a different circuit, for example, having subcircuit 2811, as shown in layouts 2802 and 2803, the resistance value Rtotal may result in resistor layout segments having different lengths or configurations. Layout 2802 shows one example segment length Lseg2 that can be used when only subcircuit 2811 is present therein, and layout 2803 shows another example segment length Lseg3 that can be used when only subcircuit 2811 is present therein. Layout 2804 shows another example segment length Lseg4 that can be used when yet another combination of subcircuits 2810-2812 is present in the same layout as resistor layout segments for Rtotal. As shown in layouts 2801-2804, different layouts with different subcircuits can provide different options for placing resistor segments. For one subcircuit combination, one set of physical dimensions (e.g., Lseg and / or Wseg) can produce a more optimal layout (e.g., one with smaller size or better electrical performance). As the subcircuit combination changes, a different set of physical dimensions for the resistor segments can result in a more optimal layout.In one exemplary embodiment, parameters for one or more functional circuit components can be evaluated and based on these parameters, different predetermined physical dimensions for the resistor segments can be accessed, for example, such that the layout and / or placement of the resistor layout segments therein varies based on other subcircuits within the layout.

[0142] FIG. 29 illustrates an exemplary layout of resistor segments according to an embodiment. Features and advantages of some embodiments of the present disclosure may include, for example, automatically generating resistor layout segments (e.g., polygons) to generate a received resistor value within a software system. FIG. 29 illustrates the placement of multiple resistor layout segments 2950 to generate a resistance value Rtotal. In this example, a first resistor layout segment 2901 having a length Lseg and a width Wseg is placed at coordinate (0,0) on the x and y axes. A second resistor layout segment 2902 having the same length and width is placed in parallel (i.e., side-by-side) along the length of the first resistor layout segment 2901 and is further offset from segment 2901. The resulting placement of segment 2902 is a function of Wseg, e.g., (x=Wseg+offset, y=0). The sum of Wseg and the offset is referred to as a "step" and can be used to iteratively place each segment. Thus, the resistor layout segments 2950 in this example are, for example, Place(i * The resistor layout segments may be arranged according to the formula (step, 0), where "i" equals 0 to (1 - total number of resistor layout segments), and "step" is a placement offset based on Wseg (e.g., Wseg plus an additional design rule check offset "DRC offset" that may be stored and utilized during run-time). In some embodiments, each resistor layout segment may be associated with a unique identifier (e.g., instance name), and the unique identifier may be named to allow for sorting of the resistor layout segments. Thus, the resistor layout segment identifiers may, for example, be sorted (e.g., R1, R2, R3, ..., etc.), and then each resistor layout segment may be arranged in sequence (e.g., in a software loop) to generate a layout of Rtotal.

[0143] 30 illustrates another exemplary layout of resistor segments according to an embodiment. This example illustrates, for example, that layout placement instructions can be used to place resistor layout segments at predetermined locations within a layout, and further illustrates that such placement instructions can be used to rotate the resistor layout segments. For example, here, resistor layout segment 3001 is placed at starting coordinates x1, y1 on the x- and y-axes within the reserved area near (e.g., to the right of) the layout of subcircuit A 3050 and near (e.g., above) the layout of subcircuit B 3051. Furthermore, resistor layout segment 3001 is rotated by, for example, an angle θ=90 degrees.

[0144] Resistor layout segment 3002 is further placed at starting coordinates x1, y1 and offset along the y-axis based on width and other factors (e.g., DRC). As described above, segment 3002 is rotated by an angle θ=90 degrees. In a similar manner, additional resistor layout segments can be placed to generate a total resistor value of Rtotal. Thus, the resistor layout segment shown in FIG. 30 can be placed based on a predetermined physical dimension (e.g., Wseg in this case) according to the formula Place(x1, y1, step, r=90°, p=+), where x1 is the x-axis initial placement coordinate, y1 is the y-axis initial placement coordinate, step is a placement offset based on Wseg (e.g., step=f(Wseg)), "r" is the rotation, and "p" is the polarity of the step (up or down / left or right). Typically, an exemplary embodiment of the present disclosure can include a script that executes layout placement instructions that specify resistor placement, a starting x-coordinate, a starting y-coordinate, an offset based on at least one physical dimension of the resistor segment, a rotation, and a polarity (e.g., p=±). In Figures 29 and 30, the resistor layout segments are placed in series at locations of increasing value along the x-axis (Figure 29) and y-axis (Figure 30) (e.g., positive polarity steps), although it is understood that the polarity of the steps can be, for example, in a negative direction.

[0145] FIG. 31 illustrates passing resistor attributes according to an embodiment. In certain embodiments, it may be advantageous to receive resistor attributes such as length, width, or resistor type for use in a circuit schematic. In one embodiment, a circuit specification is used to generate a schematic that includes symbols for resistors. However, some schematic generators in certain electronic design automation (EDA) software systems may not have the capability to receive a netlist that specifies resistors or values ​​for resistors to be used in a transistor-level schematic. Therefore, in one embodiment, a circuit specification can be generated that has one or more identifiers that can be used to set resistor attributes. For example, one or more resistor values ​​can be encoded in the name of a symbol in the circuit specification. For example, specification 3101 can include an identifier for a component, such as a component name. The component identifier can include one or more encoded resistor attributes 3110. For example, a component in circuit specification 3101 may have the name "rlpp3000rpo5p22u2p5u," where, e.g., "rlpp3000" corresponds to a particular library, rpo corresponds to the resistor type (e.g., poly, poly++, or metal, in this case rpo="poly"), "5p22u" corresponds to a resistor length of 5.22 micrometers, and "2p5u" corresponds to a width of 2.5 micrometers. The following example code shows taking a resistor cell name and splitting it to decode the resistor parameters: if(strncmp(Cname''rlpp3000rpo''10)==0 then rexCompile(''rlpp3000rpo'') newstring=rexReplace(Cname''''1) / / Comment: The string becomes 40p0u2p0u. rexCompile(''p'') newptstring=rexReplace(newstring''.''-1) / / Comment: -1 replaces all ''p'' with ''.'', the string becomes 40.0u2.0u. paramstring=parseString(newptstring''u'') / / Comment: The string is split into (''40.0'' ''2.0''). / / Comment: First the length, then the width l=40.0 w=2.0 length=car(paramstring) width=cadr(paramstring) )

[0146] The circuit specification can be received by a schematic generator component 3121 and converted into a circuit schematic 3122 (e.g., a transistor-level schematic). Initially, the circuit schematic 3122 can include symbols corresponding to resistor components in the circuit specification. However, the symbols corresponding to resistors may initially be empty. The schematic import component 3123 can read the names of the symbols in the schematic and (i) insert the resistor values ​​into the schematic, (ii) connect the resistor terminals to the symbol pins, and (iii) write the resistor attributes based on the encoding name. For example, based on the encoding described above, the schematic import component 3123 can select a polysilicon resistor from the “rlpp3000” library with, for example, Lseg=5.22 um and Wseg=2.5 um and insert it into the symbol.

[0147] Exemplary series and parallel resistors specified in the circuit specification are as follows:

[0148] Example 1: Parallel connected resistor component named "rlpp3000rpo7p5u2p0u" / / Type Poly: 0.20000K ohm resistor module rlpp3000rpo7p5u2p0u(RP,RN); inout RP; inout RN; endmodule rlpp3000rpo7p5u2p0u R0( .RP (RP), .RN (RN), ); rlpp3000rpo7p5u2p0u R1( .RP (RP), .RN (RN), ); rlpp3000rpo7p5u2p0u R2( .RP (RP), .RN (RN), );

[0149] Example 2: Series connected resistor component named "rlpp3000rpo24p8u2p0u" module rlpp3000rpo24p8u2p0u(RP,RN); inout RP; inout RN; endmodule rlpp3000rpo24p8u2p0u R4( .RP (RP), .RN (RP_1), ); rlpp3000rpo24p8u2p0u R5( .RP (RP_1), .RN (RP_2), ); rlpp3000rpo24p8u2p0u R6( .RP (RP_2), .RN (RP_3), );

[0150] In Example 1 above, the first module statement defines a component named "rlpp3000rpo7p5u2p0u" with two terminals RP and RN (e.g., positive and negative). Subsequent statements create three instances of components named R1, R2, and R3, with their positive and negative terminals connected to each other. Similarly, in Example 2 above, the module statement defines a component named "rlpp3000rpo24p8u2p0u," also with two terminals (positive and negative). Subsequent statements create three instances of components named R0, R1, and R2. However, components R4, R5, and R6 are connected in series (e.g., the negative terminal of R0 is assigned to node RP1, the positive terminal of R1 is assigned to RP1, etc.). Thus, receiving instances R1, R2, and R3 into an EDA tool (e.g., as Verilog input) can result in the generation of three component symbols in the transistor-level schematic with symbol names of rlpp3000rpo7p5u2p0u and instance names of R1, R2, and R3. These symbols are coupled in parallel with one another. Similarly, receiving instances R4, R5, and R6 can result in the generation of three component symbols in the transistor-level schematic with symbol names of rlpp3000rpo24p8u2p0u and instance names of R4, R5, and R6. These symbols are coupled in series with one another. In each case, the symbol names can be read, and resistors with encoded attributes can be inserted as described above.

[0151] 32 illustrates passing resistor attributes to a circuit diagram according to another embodiment. In this example, specification 3202 is sent from generator 3201 to circuit diagram generator 3250. Resistor attributes 3203 for one or more resistors to be generated in the circuit diagram can be stored, for example, in a location accessible by circuit diagram import component 3251. In one embodiment, the resistor attributes can be encoded as described above, or alternatively, can be unencoded (e.g., stored as text in a table that can be retrieved from an accessible computer memory location, or in any other manner). Circuit diagram import component 3251 can, for example, read resistor attributes 3203 and write these resistor attributes to the circuit diagram using circuit diagram generator 3250. The resulting circuit diagram 3252 can include, for example, resistors inserted with their attributes in their symbols as described above in the circuit diagram with resistor attributes 3203 written in.

[0152] As mentioned above, in one exemplary embodiment, the generator is an initial program that can receive circuit parameters and generate a specification of the circuit to be generated. This circuit specification can be sent to an electronic design automation (EDA) software system that can include a schematic diagram generator. The schematic diagram import component can include one or more scripts for implementing the techniques described in Figures 31 and 32, for example.

[0153] FIG. 33 illustrates the generation of a resistor specified in a user interface, according to an embodiment. In this example, a user can design a circuit in a design user interface (UI) 3301 (also known as a front end). The design UI 3301 can, for example, perform high-level circuit behavior simulation rather than transistor-level simulation. In this example, the user has already selected a first functional circuit component 3302 (e.g., a comparator or amplifier) ​​and a resistor component 3303. Components 3302 and 3303 are coupled to each other in the design interface. The user can, for example, specify a resistor value for resistor component 3303 in user interface 3304 and enter a desired value for Rtotal. In this example, Rtotal can be in a predetermined range from a minimum value Rmin=100 ohms to a maximum value Rmax=1 megaohm. The functional circuit component 3302 can also have, for example, user-selected parameters, as described above. A circuit schematic 3310 can be generated using the parameters from the UI 3301. The schematic diagram may include one or more subcircuits 3311 that are selected based on parameters received for the functional circuit component 3302. Additionally, the circuit schematic diagram may include a resistor schematic diagram 3313 for Rtotal. The resistor schematic diagram 3313 may include multiple symbols, such as, for example, symbol 3314, configured in series and / or parallel, each including a resistor segment. The combined schematic diagram may produce an approximate Rtotal value entered by the user (e.g., within a degree of error that is acceptable for proper functioning of the circuit).

[0154] FIG. 34 shows an example layout of resistors specified within a user interface. In this example, parameters for functional circuit component 3302 are used to generate subcircuit layout 3401. A user-input value (e.g., Rtotal) for resistor component 3303 is used to generate and place multiple resistor layout segments 3403a-3403n, each having a predetermined segment length and a predetermined segment width, which combine to form Rtotal value 3403, for example. As the user-input Rtotal value changes, the number of resistor layout segments 3403a used to generate Rtotal changes. In this example, for any resistance value Rtotal, the first resistor layout segment may be placed first in the layout at a location adjacent to the layout of subcircuit 3401 (e.g., location (xi, yi) 3450), with subsequent resistor layout segments then being placed at offset locations along the x-axis (e.g., in this illustration, along the negative x-axis so that the segments are configured in parallel along their lengths and spaced apart by an offset).

[0155] FIG. 35 illustrates resistor generation based on circuit parameters specified within a user interface, according to an embodiment. As described above, one or more resistor values ​​Rtotal can be received as a result of calculations by the generator software. In this example, a user can design a circuit within a design user interface (UI) 3501 that includes a first functional circuit component 3502 (e.g., a bias current generator circuit in this case) and one or more other functional circuit components 3503. Components 3502 and 3503 are coupled to each other within the design interface (e.g., a bias current is coupled to one or more of the other functional circuit components). The user can specify parameters for each circuit component, which are sent to the generator software. One or more resistor values ​​can be calculated using the parameters for component 3502 and based on the model. In this example, a user can, for example, enter a desired current for bias current generator circuit 3502 within user interface 3504. The user can, for example, enter a desired value for Ibias into a text field. In this example, Ibias can be in a predetermined range from a minimum value Ibias_min=0.5 uA to a maximum value Ibias_max=5 uA. Other functional circuit components 3503 can also have, for example, user-selected parameters. Parameters from UI 3501 can be used to generate a schematic diagram that can include an Ibias schematic diagram 3510 and subcircuit schematic diagrams 3511 for other functional circuit components 3503. In addition, Ibias schematic diagram 3510 can include a resistor schematic diagram 3514 for Rtotal. Resistor schematic diagram 3514 can include multiple symbols configured in series and / or parallel, each including a resistor segment, as shown in FIG. 33, for example. The combined schematic diagram can approximately produce the Rtotal value calculated by the generator software (e.g., within an acceptable degree of error for proper functioning of the circuit).

[0156] The following example shows one resistor calculation by the generator software in response to receiving parameters for the bias current generator function circuit component 3502. If the user enters an Ibias value between Ibias_min and Ibias_max, then Rbias can be calculated based on the circuit model as follows: Ibias=Vref / Rbias→Rbias=Vref / Ibias

[0157] Here, Vref can be a known parameter, for example, input as part of either functional circuit component 3502 or 3503, yet calculated based on other parameters or automatically set by software based on other parameters (e.g., Vdd). Thus, the above equation for Rbias is an exemplary circuit model that can be used to determine Rbias based on the Ibias value received as a parameter. Thus, a user can, for example, input a single value (e.g., from a continuous range of values) as a parameter, and the generator software can convert this value into a resistor value Rtotal that is implemented as a circuit schematic or layout, or both. As described above, the generator software can access predetermined physical dimensions for the resistor segments and convert Rbias into a series and / or parallel combination of resistors having known segment resistances Rseg, lengths Lseg, and widths Wseg. A schematic for Rbias can be generated, for example, as described above, and combined with the schematics for transistor 3513 and amplifier 3512 to generate Ibias schematic 3510. Although this diagram illustrates calculating resistor values ​​in the context of a bias current generator circuit, it is understood that one skilled in the art of analog / mixed-signal circuit design can calculate resistor values ​​for a wide variety of other analog or mixed-signal circuits.

[0158] FIG. 36 illustrates exemplary layouts of resistors determined from parameters, according to an embodiment. One or more functional circuit components 3503 and corresponding parameters can result in layouts 3601 and 3602. Ibias 3502 and the parameters entered therefor (e.g., from 0.5 uA to 5.0 uA) can result in, for example, layout 3603 corresponding to subcircuits 3512 and 3513 and layout 3604 of resistor layout segments for a calculated value of Rbias. As described above, each resistor layout segment 3605a can have, for example, the same resistor segment value Rseg, length Lseg, and width Wseg. Thus, as the user-entered value for a particular circuit parameter varies across a continuous range of values, the calculated resistor value changes, and so does the resulting number of resistor layout segments required to generate this value. Such exemplary embodiments may advantageously enable the generator software to receive parameters (e.g., from a user) over a continuous range of values ​​and automatically generate analog circuit schematics and / or analog circuit layouts that implement the specified circuit behavior.

[0159] Automatic generation of resistor dividers Features and advantages of some embodiments of the present disclosure may include automatic generation of a resistor divider. FIGS. 37A-37C illustrate generation of a resistor divider according to an embodiment. For example, in various embodiments, a resistor divider function circuit component 3701 may have parameters corresponding to a total resistance, a number of taps, an enable / disable function, and the like. Parameter values ​​3702 for the configured resistor divider function circuit component may be received by generator software 3703, which may include a resistor divider generator component 3705. The parameters may specify the resistor divider to be generated. The resistor divider generator component 3705 may determine multiple resistor values ​​corresponding to resistors between one or more outputs of the resistor divider.

[0160] The resistor divider generator 3705 can generate a wide range of resistor dividers 3706 with different numbers of output taps and different total resistances. An exemplary resistor divider is illustrated in FIG. 37B. The resistor divider 3707 includes two resistors and one output (or tap). The resistor divider 3707 can receive a first voltage reference on the input terminal (top). The top resistor 3710 includes a terminal coupled between the first voltage reference on the input and the output tap, and the bottom resistor 3711 includes a terminal coupled between the output tap and a second voltage reference on the bottom terminal (e.g., ground).

[0161] Resistor divider 3708 includes three resistors and two output taps. Upper resistor 3712 has a terminal coupled to an upper input for receiving a voltage reference and a second terminal coupled to a first tap (Tap 1). Middle resistor 3713 has a first terminal coupled to Tap 1 and a second terminal coupled to a second output tap (Tap 0). Lower resistor 3714 has a first terminal coupled to Tap 0 and a second terminal coupled to a lower terminal (e.g., for receiving a second voltage reference).

[0162] Resistor divider 3709 includes N output taps (where N is an integer) and N+1 resistors including upper resistor 3715, lower resistor 3716, and multiple intermediate resistors and taps (not shown).

[0163] FIG. 37C illustrates that each resistor in the resistor divider generated by resistor divider generator 3705 can be implemented as a plurality of series and / or parallel resistor segments as described above. For example, resistor divider generator 3705 can determine a plurality of resistor segments to approximately generate each of the plurality of resistor values ​​shown in FIG. 37B. Each resistor value described in FIG. 37B can be implemented as a first number of series resistor segments and / or a second number of parallel resistor segments. Resistor divider 3720 illustrates one exemplary implementation of resistor divider 3707. In this example, top resistor 3710 is implemented as a plurality of resistor segments 3723 configured in series and / or parallel to generate a resistance value therefor. Similarly, resistor 3711 is implemented as a plurality of resistor segments 3724 configured in series and / or parallel to generate a resistance value therefor.

[0164] In some embodiments, the resistor divider generator software component 3705 can determine the total resistance (e.g., the sum of the series resistors) for the resistor divider to be generated and the value of each resistor (e.g., based on the tap voltages specified in the parameters) based on the number of taps and the voltage at each tap. For example, if the output taps are specified as a percentage of the input voltage (e.g., Tap1=10%, Tap2=50%, Tap3=70%, etc.), the values ​​for the resistors in the N-tap resistor divider 3709 can be determined as follows: Start with the bottom resistor 3716 and move up through N+1 resistors to the top resistor 3715. Rbottom=R1=Rtotal * tap1 / 100 R2=Rtotal * (Tap2-Tap1) / 100 Ri=Rtotal * (Tap_iTap_i-1) / 100 Rtop=R_N+1 * (1-TapN) / 100

[0165] Thus, in the above example, the resistor value is determined based on the number of taps, the voltage difference between the two input voltages, the tap voltages, and the bottom voltage. The voltage difference can be expressed as an actual voltage or as a percentage of the input voltage as shown in the above example.

[0166] In one embodiment, each resistor value in a resistor divider can be sent to resistor generator software component 3704 as an input to determine values ​​for multiple resistor segments for each resistor in the divider, for example. Thus, each resistor in a resistor divider can be implemented as multiple resistor segments.

[0167] Once the resistor segments have been determined, circuit specifications can be generated. Circuit specifications are generated for configuring each of the resistor segments to form a resistor value. For example, for resistor divider 3707, the circuit specification can configure a first plurality of resistor segments in series and / or parallel to form an upper resistor 3723, and a second plurality of resistor segments in series and / or parallel to form a lower resistor 3724. As described above, the circuit specification can be, for example, a netlist. For resistor divider 3708, the circuit specification can configure a first plurality of resistor segments in series and / or parallel to form an upper resistor 3725, a second plurality of resistor segments in series and / or parallel to form a lower resistor 3727, and a third plurality of resistor segments in series and / or parallel to form a middle resistor 3726 (e.g., where parameters specify two output taps). In resistor divider 3709, the circuit specifications may configure a first plurality of resistor segments in series and / or parallel to form an upper resistor 3728, a second plurality of resistor segments in series and / or parallel to form a lower resistor 3729, and one or more further plurality of resistor segments in series and / or parallel to form a middle resistor (e.g., where the parameters specify more than two output taps).

[0168] The circuit specification for the resistor divider described above can be used to generate a transistor-level schematic diagram that includes resistor segments configured to generate the resistor divider. As described above, a transistor-level schematic symbol can be generated for each resistor segment specified in the circuit specification for the resistor divider, and the resistor can be inserted into the symbol and configured with a resistor value and other attributes (e.g., Runit, Lseg, Wseg). The circuit specification can specify how the resistor segments are connected to each other in the schematic diagram to form the resistor divider. An example resistor divider schematic diagram is shown in FIG. 37C, where resistor divider 3720 includes one output tap, resistor divider 3721 includes two output taps, and resistor divider 3722 includes N output taps.

[0169] FIG. 38A illustrates a method for generating a resistor divider including a subcircuit according to another embodiment. In some embodiments, it may be advantageous to include active circuitry within the resistor divider. For example, parameters 3802 for resistor divider function circuit component 3801 may include a parameter for specifying an enable function (e.g., enable=yes). Thus, resistor divider software component 3805 within generator software 3803 may generate a circuit specification that may specify one or more subcircuit schematics 3807-3809 as part of the resistor divider to generate resistor divider schematic 3810. The specified subcircuit schematic may be configured to receive inputs, for example, to enable or disable the resistor divider. It is understood that other functionality may be incorporated into the resistor divider using other subcircuit schematics.

[0170] In one embodiment, the partial circuit schematic can include a switch for enabling and disabling the resistor divider. FIG. 38B illustrates various embodiments of resistor dividers with different switch configurations. For example, in one embodiment shown in 3820, a switch 3826 is coupled between the resistor divider input and one or more terminals of an upper resistor segment used to generate resistor divider resistance R1 3824. Because each resistor 3824...3825 in divider 3820 includes multiple resistor segments that can be paralleled, a switch can be coupled to a terminal of one segment or to a terminal of multiple parallel segments. Switch 3826 can include an enable input (en) for enabling or disabling the resistor divider. In this example, the switch is a high-voltage switch (HV SW) and can include a transistor capable of withstanding the high input voltage at the top of the divider. In divider 3821, switch 3829 is coupled between the resistor divider's reference input (e.g., ground) and one or more terminals of the lower resistor segment used to generate resistor divider resistance RN+1 3828. Here, switch 3829 may be a low-voltage switch that does not need to withstand the full voltage applied to the divider's input. In divider 3822, switch 3832 may be coupled between one of the resistor divider's output taps (tap 1 in this figure) and one or more terminals of the resistor divider's middle resistor segment (e.g., the resistor segment in RN 3830).

[0171] Automatic generation of capacitors Features and advantages of the present disclosure include automatic generation of capacitors, which in some embodiments can be generated across a range of values ​​for use in, for example, transistor-level circuits and / or layouts.

[0172] FIG. 39 illustrates a computer-implemented system 3901 for automatically generating capacitors according to embodiments. Features and advantages of the present disclosure include, for example, automatically generating a schematic, a layout, or both, including a capacitor based on a specified or calculated capacitor value received by the system. For example, a system according to the present disclosure may receive a capacitor value and automatically generate a schematic for the capacitor, a layout for the capacitor, or both. In this example, the capacitor value Ctotal corresponding to capacitor 3910 would be generated by the capacitor specification generator component 3912 of the generator software 3902. In various embodiments, one or more capacitor values ​​can be specified, for example, by a user, and received as input parameters by the generator software. In other embodiments, one or more capacitor values ​​can be calculated based on, for example, other parameters received by the generator software, as described in more detail below.

[0173] Features and advantages of some embodiments include converting capacitor values ​​into segments, such as series unit capacitor segments to be generated, parallel unit capacitor segments to be generated, or one or more combinations of both series and parallel unit capacitors. For example, the capacitor specification generator 3912 can determine a first number S of capacitor segments to be configured in series and / or a second number P of capacitor segments to be configured in parallel to approximately generate the capacitor value Ctotal. S and P can be integers greater than or equal to 1, for example. S and / or P can alternatively be represented as N. In one embodiment, for example, the capacitances of the unit capacitors can be the same. Once the number S of series capacitors and / or the number P of parallel capacitors have been determined, a circuit specification 3913 (e.g., for Ctotal) can be generated, for example, to generate a schematic diagram, a layout, or both. In this example, capacitor specification generator 3912 may generate circuit specifications 3913 for configuring a first number S of capacitor segments in series, or alternatively a second number P of capacitor segments in parallel (or a combination of both). Although this specification shows one series combination and one parallel combination of capacitors as variations for generating Ctotal, it is understood that multiple combinations of series and parallel capacitors may be used, for example, to achieve Ctotal within an acceptable tolerance.

[0174] In various embodiments, circuit specification 3913 can specify a configuration for multiple components. In this example, the components correspond to unit capacitors (e.g., as represented by capacitor segments 3914-3918), and circuit specification 3913 can specify connections between these capacitor segments. For example, the circuit specification can be a netlist, such as a verilog.v file as described above, where connections between components are based on commonly designated nodes in the netlist.

[0175] Exemplary embodiments of the present disclosure can further receive one or more predetermined physical dimensions for the capacitor segment 3911. The predetermined physical dimensions can be set, for example, to advantageously optimize the layout of different capacitor values, as further illustrated below. For example, the predetermined physical dimensions can be a predetermined maximum length along one dimension of the capacitor segment (e.g., length Lseg) or a predetermined maximum length along another dimension of the capacitor segment (e.g., width Wseg). The predetermined physical dimensions can be associated with a generated capacitor value such that the particular capacitor being generated has access to the predetermined physical dimensions. Thus, once a particular capacitor value Ctotal for a particular circuit or project is received, related parameters such as Lseg and / or Wseg for this particular capacitor can be retrieved, for example, from a known storage location (e.g., from a memory, file, or database).

[0176] Features and advantages of certain embodiments may further include generating a schematic diagram for capacitor values ​​based on the circuit specification. In this example, the circuit specification 3913 is sent from the generator software system 3902 to a schematic and layout generator software system 3903. The schematic and layout generator software system 3903 may be, for example, the electronic design automation (EDA) software system described above. The software system 3903 may include a schematic generator component 3920 for generating a capacitor schematic diagram 3921 from the circuit specification 3913. The schematic generator component 3920 may, for example, receive a netlist and convert it into, for example, schematic symbols and connections between the schematic symbols. However, some schematic generators may not be able to set attributes of components, such as capacitors, to specific specified values ​​based on the netlist. Thus, in one exemplary embodiment, the schematic import component 3922 can analyze, for example, the circuit specification 3913 or the generator circuit schematic 3921 and set attributes of components such as capacitors therein.

[0177] In one exemplary embodiment, the circuit specification 3913 can specify components corresponding to multiple unit capacitors (e.g., in series, in parallel, or both), and the schematic generator 3920 can generate schematic symbols for such components that do not have unit capacitors (e.g., the generated symbol can be empty if the component name in the netlist does not exist in the software system 3903 library). Thus, initially, the generated circuit schematic can include multiple empty symbols, with the pins of the symbols connected to each other as specified in the received netlist. The schematic import component 3922 can implement an algorithm for identifying empty components and inserting capacitors into the symbols. For example, the schematic import component 3922 can automatically insert a capacitor into each empty schematic symbol and connect the terminals of the inserted capacitor with the pins of the schematic symbol.

[0178] In some embodiments, the schematic import component 3922 may include code for setting attributes of a capacitor. For example, attributes for a capacitor may include the capacitor's physical dimensions, such as length and width. Attributes may include the capacitor type (e.g., metal-insulator-metal "mim"). Attributes of one or more capacitors may be passed between software components in various ways. In one embodiment, the specification 3913 may include information for setting attributes. For example, as described above, attributes may be encoded in an identifier for a component in the circuit specification 3913 (e.g., encoded in the capacitor's name in the netlist). Thus, when a symbol for a component in the netlist is used to generate a symbol, the symbol may include the identifier. The identifier may be read, for example, by the schematic import component 3922 and used to place the capacitor into an empty symbol. In other embodiments, attributes may be stored, for example, in a predetermined location and accessible by the schematic import component 3922. A more detailed example technique for passing attributes for a capacitor is provided below for illustrative purposes.

[0179] As described above, the diagram generator 3920 can output a capacitor diagram 3921. The capacitor diagram 3921 can include multiple symbols with pins. Each symbol can have capacitor segments embedded therein. As described above, the symbols can be coupled to one another in one or more series and / or parallel configurations. For example, combined symbols each having an internal capacitor segment form a desired total capacitor value Ctotal. In some exemplary embodiments, the capacitor segments used to form one total capacitor value Ctotal can each have the same length, width, and capacitor type.

[0180] Features and advantages of some embodiments of the present disclosure may include automatically generating a capacitor layout from a capacitor schematic. For example, a capacitor schematic 3921 may be converted into a capacitor layout 3924 by a layout generator 3923. The layout generator 3923 may, for example, convert capacitors in a circuit schematic symbol into a plurality of polygons, each polygon having dimensions specified for a corresponding capacitor segment. In one embodiment, layout placement instructions 3925 may be executed to place each polygon in a layout, as described in more detail below. Thus, capacitor segments forming a total capacitor value Ctotal in a schematic may be automatically converted into a capacitor layout 3924.

[0181] FIG. 40A illustrates a method for generating a capacitor according to an embodiment. In 4001, a capacitance value for a capacitor to be generated is received. The capacitance value can be received, for example, as an input parameter defined by a user in a user interface, or can be received from a software module that determines capacitance values ​​based, for example, on parameters of the circuit to be generated. In 4002, the system determines a number N of unit capacitors having unit capacitance to be combined to form a total capacitance. The number N can alternatively be represented as P (for parallel) capacitor segments configured in parallel or S (for series) capacitor segments configured in series (or a combination of both). In 4003, a transistor-level schematic diagram is generated that includes N unit capacitor schematic diagrams having unit capacitance. The N unit capacitor schematic diagrams are configured to generate a total capacitance for the capacitor to be generated. In 4004, a layout is generated that includes N capacitor layout elements configured to generate the capacitor.

[0182] Figure 40B shows an exemplary technique for determining capacitor dimensions according to an embodiment. At 4010, a capacitor value (e.g., Ctotal = 25 pf) is received. In some embodiments, a capacitor generator software component within the generator software can retrieve predetermined capacitance parameters. For example, a maximum capacitance and a minimum capacitance are stored and can be retrieved for use in generating a capacitor. In some embodiments, different capacitor types can have, for example, different predetermined maximum capacitances and / or minimum capacitances, and the system can select a set of predetermined capacitance parameters based on other information regarding the circuit or capacitor to be generated (e.g., the selection is based on a specified capacitor type or a capacitor type automatically selected for use in a particular analog circuit). In this example, at 4011, the received capacitance Ctotal is compared with the maximum capacitance Cmax. If Ctotal > Cmax, the system can determine, as shown at 4013, the number N (alternatively denoted as P) of unit capacitors Cunit configured in parallel. Cunit can have a capacitance value such that N parallel unit capacitors are combined to form Ctotal. Thus, multiple unit capacitors Cunit can be advantageously used such that the size of each capacitor is less than the predetermined maximum capacitance. If Ctotal < Cmax, at 4012, the received capacitance Ctotal is compared with a predetermined minimum capacitance Cmin. If Ctotal < Cmin, the system can determine, as shown at 4014, the number N (alternatively denoted as S) of unit capacitors Cunit configured in series. Here, Cunit can have a capacitance value such that N series unit capacitors are combined to form Ctotal. Thus, multiple unit capacitors can be advantageously used such that the size of each capacitor is greater than the predetermined maximum capacitance.In this example, when Cmin < Ctotal < Cmax, a single unit capacitor can be used. In some embodiments, a combination of parallel and series capacitors can be used to achieve the capacitor value.

[0183] In 4015, the system can determine the physical dimensions of the unit capacitor Cunit. For example, in one embodiment, the system can store and retrieve a predetermined maximum length along a first dimension. In various embodiments, the system can be configured such that the first length corresponding to the first dimension of N unit capacitors is shorter than or equal to the predetermined maximum length along the first dimension. Further, the system can determine the second length corresponding to the second dimension of N unit capacitors based at least on the unit capacitance Cunit and the first length. In one exemplary embodiment, the unit capacitor Cunit in the wiring diagram can have a length attribute Lseg and a width attribute Wseg. Thus, the first length along the first dimension can correspond to the length attribute Lseg, and the second length along the second dimension can correspond to the width attribute Wseg. Thus, in one embodiment, Lseg can be set to be shorter than or equal to the maximum length Lmax, and the system can determine Wseg such that the unit capacitor value Cunit is achieved. For example, in one embodiment, Lseg can first be set to the predetermined maximum length Lmax. Wseg can be determined as follows: Wseg = Cunit / [Lmax * (capacitance / um 2 )]

[0184] Features and advantages of some embodiments include the ability to set the aspect ratio of the capacitor. A configurable (or programmable) aspect ratio can be advantageous, for example, for optimizing layout to reduce circuit area. In one embodiment, the ratio between the lengths along each dimension of the unit capacitor can be configured to generate a predetermined aspect ratio (e.g., Wseg / Lseg). For example, once Wseg and Lseg have been determined in 4015, the system can compare the aspect ratio of the calculated Wseg / Lseg to a predetermined aspect ratio, which can be defined in code or retrieved from memory, for example. If the aspect ratio is met (e.g., within a specified tolerance) in 4016, the system generates a netlist specification for the unit capacitor in 4017. However, if the aspect ratio is not met in 4016, the system can adjust one of the dimensions (e.g., Wseg or Lseg) in 4018. For example, if the initial Lseg is set to Lmax, the adjusted Wseg can be generated by gradually reducing Lseg until the aspect ratio satisfies a predetermined aspect ratio. Finally, in 4017, information specifying the capacitor can be encoded in an identifier such as a name. For example, the name of N capacitor components in a circuit specification netlist that configures capacitors in series or parallel can be CAP_<cap_type> _ <lseg> _ <wseg>Each capacitor symbol can be, for example, CAP_<cap_type> _ <lseg> _ <wseg>_N, where cap_type is the capacitor type (e.g., "mim"), Lseg is the length attribute, Wseg is the width attribute, and N is the number of capacitors used to generate Ctotal. In various embodiments, components (including capacitors) in a transistor-level schematic can be generated as described above with respect to, for example, FIGS. 31 and 32.

[0185] Exemplary Embodiments for Generating Capacitance 41A-41C illustrate exemplary capacitor diagram generation according to embodiments. FIG. 41A illustrates a capacitor diagram including P symbols 4101A-4101P coupled in parallel. These symbols can be coupled to each other, for example, through pins. FIG. 41B illustrates a capacitor diagram including S symbols 4102A-4102S coupled in series. FIG. 41C illustrates an exemplary symbol 4120 including symbol pins 4121 and 4122. Symbol 4120 includes a transistor-level unit capacitor 4123, Cunit, having a first terminal 4124 and a second terminal 4125. As noted above, in some embodiments, symbol 4120 can be generated without a unit capacitor segment (e.g., as an empty symbol). A unit capacitor segment, Cunit, may already be inserted into symbol 4120 by software. Further, the software may, for example, connect capacitor terminal 4124 to symbol pin 4121 and capacitor terminal 4125 to symbol pin 4122. In one embodiment, the software may include scripts (e.g., Skill scripts in Cadence®) that run, for example, within an electronic design automation (EDA) software system to detect empty symbol instances resulting from, for example, a circuit schematic generated in response to receiving a netlist, and automatically insert capacitors. Further, the scripts may set attributes of the inserted capacitors with values ​​generated as described above.

[0186] The combined capacitance of the capacitor segments in symbols 4101A-4101P or 4102A-4102S can produce a total generated capacitor value Ctotal. As mentioned above, in some embodiments, these unit capacitors can have, for example, the same capacitor value Cunit, the same predetermined length Lseg, and the same predetermined width Wseg. Calculating the length and width of the unit capacitors based on predetermined parameters (e.g., one or more of Cmin, Cmax, Lmax, or a programmed aspect ratio) can advantageously enable efficient automated layout.

[0187] FIG. 42 illustrates example capacitor layouts according to various embodiments. Example layouts 4210-4214 illustrate how capacitor values ​​can be automatically generated in response to different values ​​of Ctotal (the capacitor to be generated). Generator 4201, for example, can receive multiple capacitor values ​​Ctotal1-Ctotal5 and generate layouts 4210-4214 including one or more capacitor layout segments (e.g., 4210 or 4220 / 4221) having lengths along the x-axis and y-axis equal to the attributes for Lseg and Wseg. The capacitor layout segments within each capacitor layout can correspond to multiple polygons, for example. The polygons for each set of capacitor layout segments can have different lengths and widths. The capacitor layout segments can be generated from a capacitor schematic, such as circuit schematic 4110 shown in FIG. 41A. Thus, in this example, the capacitor segments within the symbol generate corresponding polygons for capacitor layouts 4210-4214. In other embodiments, for example, a single capacitor in a schematic diagram can be converted into multiple polygons and automatically placed as described herein. In this example, each of the capacitor layout segments can be arranged in a one- or two-dimensional array (e.g., side-by-side along the length or width) and connected to each other (e.g., using metal or poly-Si) in series and / or parallel (e.g., as shown in the schematic diagrams shown in Figures 41A or 41B) so that the total capacitance is Ctotal. For example, the capacitor layout segments can be arranged in a row until a maximum distance is reached, and then a new row can be started. Alternatively, the capacitor layout segments can be configured in, for example, an N x M array. The capacitor layout segments can be placed on top of other circuit features. The capacitor layout segments can be implemented using metallization layers (e.g., a mim capacitor using metal 3 (M3) and a mim layer between M3 and M4) as known to those skilled in the art.

[0188] As shown in layouts 4210-4214, different numbers of capacitor layout segments having different sizes can be used to generate different Ctotal values. Some Ctotal values ​​may result in fewer capacitor layout segments, whereas other Ctotal values ​​may result in more capacitor layout segments. Advantageously, the number of capacitor layout segments used across different designs for different Ctotal values ​​can be varied by arranging the capacitor layout segments side-by-side (e.g., along their lengths) and coupling them together according to different numbers of series and / or parallel combinations, as shown. As described in more detail below, layout placement instructions can, for example, place the capacitor layout segments in parallel along their lengths in areas reserved for capacitor layout segments (e.g., above areas for subcircuits using metallization).

[0189] FIG. 43 illustrates the generation of a capacitor specified within a user interface according to an embodiment. In this example, a total capacitance is received as a parameter corresponding to a capacitor functional circuit component. For example, a user can design a circuit within a design user interface (UI) 4301 (also known as a front end). The design UI 4301 can perform, for example, high-level circuit behavior simulation rather than transistor-level simulation. In this example, the user has already selected a first functional circuit component 4302 (e.g., a comparator or amplifier) ​​and a capacitor component 4303. Components 4302 and 4303 are coupled to each other within the design interface. The user can, for example, specify a capacitor value for capacitor component 4303 within user interface 4304 and enter a desired value for Ctotal. In this example, Ctotal can be in a predetermined range from a selectable UI minimum value Cmin=100 femtofarads (fF) to a selectable UI maximum value Cmax=50 picofarads (pF). The functional circuit component 4302 can also have, for example, user-selected parameters, as described above. The parameters from the UI 4301 can be used to generate a circuit schematic 4310. The schematic can include one or more subcircuits 4311 selected based on the parameters received for the functional circuit component 4302. Additionally, the circuit schematic can include a capacitor schematic 4312 for Ctotal. The capacitor schematic 4312 can include multiple symbols, such as symbol 4314, configured in series and / or parallel, each including a unit capacitor (Cunit). The combined schematic can approximate the Ctotal value entered by the user (e.g., within a degree of error acceptable for proper functioning of the circuit).

[0190] FIG. 43 shows an example layout of a capacitor specified within a user interface. In this example, parameters for functional circuit component 4302 are used to generate subcircuit layout 4320. User-input values ​​for capacitor component 4303 (e.g., Ctotal) are used to generate and place multiple capacitor layout segments (e.g., capacitor layout segment 4321a), each having the same unit capacitance Cunit, segment length Lseg, and segment width Wseg that combine to form Ctotal value 4321. Varying the user-input Ctotal value changes the number of capacitor layout segments 4321 used to generate Ctotal and the dimensions of such segments (Wseg, Lseg). In this example, the capacitor layout segments are configured in a two-dimensional array (e.g., using different metallization layers for the capacitor plates) above subcircuit layout 4320, spaced apart by an offset.

[0191] In some embodiments, the total capacitance can be generated based on information specifying the circuit to be generated. For example, FIG. 44 illustrates generating a capacitor based on circuit parameters specified in a user interface according to an embodiment. The total capacitance can be generated based on a predetermined circuit model for the circuit to be generated. For example, one or more capacitor values ​​Ctotal can be received as a result of calculations by the generator software. In this example, a user can design a circuit in a design user interface (UI) 4401 that includes a functional circuit component 4402 (e.g., a delay circuit in this case) and one or more other functional circuit components (FCCs) 4403 and 4404. Components 4402, 4403, and 4404 are coupled to each other in the design interface (e.g., the delay circuit receives a signal from FCC 4403 and outputs a signal to FCC 4404). The user can specify parameters for each circuit component. The parameters for component 4402 can be used to calculate one or more capacitor values. In this example, a user can, for example, input a desired time delay for delay circuit 4402 in user interface 4405. The user can, for example, enter a desired value for the time delay in a text field. In this example, the time delay can be in a predetermined range from a minimum value of delay_min=0.5 us to a maximum value of delay_max=200 us. Other functional circuit components 4403 / 4404 can also have, for example, user-selected parameters. Using parameters from UI 4401, a transistor-level schematic can be generated that can include a delay circuit schematic 4410 and subcircuit schematics 4411 and 4412 for the other functional circuit components 4403 and 4404, respectively. Additionally, delay circuit schematic 4410 can include a capacitor schematic 4413 for Ctotal, a bias current schematic (ibias) 4414, and schematics for other circuit configurations (not shown).While this figure shows capacitor 4413 and ibias 4414 symbolically, it is understood that a transistor-level schematic for ibias would be considered to include transistor-level components (e.g., n-type or p-type transistors, resistors, or capacitors). Capacitor schematic 4413 may include multiple symbols, each including a unit capacitor, configured in series and / or parallel, as shown, for example, in Figures 41A and 41B. The combined schematic may approximately produce the Ctotal value calculated by the generator software (e.g., within an acceptable degree of error for proper functioning of the circuit).

[0192] The following example shows one capacitor calculation by the generator software in response to receiving parameters for the delay circuit function circuit component 4402. If the user inputs a delay value between delay_min and delay_max, Ctotal can be calculated (e.g., using a circuit model for the delay circuit). In this example, the delay may be based on the slope of a voltage ramp signal generated into Ctotal by ibias. A waveform for such a circuit is illustrated in 4406. A current Ibias into Ctotal can generate a voltage slope at node A. The voltage slope can be initiated, for example, when an input IN is received. When the voltage slope reaches a certain value, an output is triggered (other circuit configurations not shown). For shorter delays, a steeper voltage slope at node A can be used. For longer delays, the voltage slope can be lower. The voltage slope is given by the following equation: Voltage gradient = dv / dt = ibias / Ctotal, or Ctotal=(Ibias * delay) / Vth

[0193] Here, Vth can be, for example, the threshold voltage at node A at which the output is triggered. Thus, the above equation for Ctotal is an exemplary circuit model that can be used to determine Ctotal based on a delay value received as a parameter. Thus, a user can, for example, input a single value (e.g., from a continuous range of values) as a parameter, and the generator software can convert this value into a capacitor value Ctotal that is implemented as a schematic, layout, or both. As described above, the generator software can access predetermined physical dimensions for unit capacitors to convert Ctotal into series and / or parallel combinations of capacitors. A schematic for Ctotal can be generated, for example, as described above, and combined with the schematic for Ibias 4414 (and other delay circuit schematics) to generate delay circuit schematic 4410. While this diagram illustrates calculating capacitor values ​​in the context of a delay circuit, it should be understood that one skilled in the art of analog / mixed-signal circuit design can calculate capacitor values ​​for a wide variety of other analog or mixed-signal circuits.

[0194] FIG. 44 further illustrates exemplary layouts of capacitors determined from parameters according to embodiments. One or more functional circuit components 4402-4404 and corresponding parameters can result in layouts 4420-4422. Delay 4402 and associated input parameters (e.g., from 0.5 us to 200 us) can result in layout 4420, corresponding to, for example, a subcircuit for Ibias 4414 and other delay subcircuits (not shown), and layout 4423 of capacitor layout segments for a calculated value of Ctotal. As described above, each capacitor layout segment (e.g., capacitor layout segment 4423a) can have, for example, the same unit capacitor value Cunit, length Lseg, and width Wseg, which combine to form Ctotal. Thus, as a user-entered value for a particular circuit parameter varies across a continuous range of values, the calculated capacitor value changes, and the resulting number of capacitor layout segments required to generate this value changes. Such exemplary embodiments may advantageously enable the generator software to receive parameters (e.g., from a user) over a continuous range of values ​​and automatically generate analog circuit schematics and / or analog circuit layouts that implement the specified circuit behavior.

[0195] Automatic generation of transistors Features and advantages of various embodiments of the present disclosure may further include, for example, automatic generation of transistors such as field effect transistors (FETs).

[0196] FIG. 45 illustrates the automatic generation of a transistor, such as a field effect transistor (FET), according to an embodiment. In this example, generator software 4504 can receive information as parameters 4502 specifying the transistor to be generated. The transistor to be generated can be, for example, a signal FET or a power FET. A power FET refers to a transistor configured to deliver power, typically in the form of a large current, while a signal FET is a transistor configured to couple signals between various nodes of a circuit. In some embodiments, parameters can be generated from a user-configured FET functional circuit component 4501, where a user inputs desired characteristics for the FET, and such characteristics are embodied in parameters 4502 and sent to generator software 4504. Generator software 4504 can automatically generate transistors with, for example, different dopant types (e.g., n-type or p-type), maximum voltages (e.g., maximum drain-to-source voltage Vds_max or maximum gate-to-source voltage Vgs_max). Various embodiments described herein can, for example, automatically generate transistors with replica devices and / or Kelvin connections. Based on received information specifying the transistors to be generated, generator software 4504 can generate circuit specification 4505. Circuit specification 4505 can be, for example, a netlist specifying one or more of the specific transistors (e.g., n-type, p-type, Vds_max, Vgs_max) and can further specify additional connections and elements to form, for example, replica transistors or Kelvin connections.

[0197] The circuit specification 4505 can be used to generate transistor schematics. As mentioned above, in some embodiments, the circuit specification 4505 can be received by, for example, electronic design automation (EDA) software and converted into transistor-level schematics that can be simulated at the device level. In this example, N different combinations of parameter values ​​(e.g., params_1,..., params_N, where N is an integer) can result in N different FET transistor schematics 4530-4532. The transistor schematics 4530-4532 can be converted into FET layouts 4540-4542.

[0198] FIG. 46 shows a flow diagram for automatically generating a transistor according to an embodiment. In 4601, information specifying a transistor to be generated is received (e.g., by generator software 104). In 4602, transistor attributes can be determined from this information. Attributes can include n-type or p-type device, maximum voltage, replica device, or Kelvin connection, as described above. In some embodiments, a user can specify on-resistance (e.g., drain-to-source on-resistance “Rds_on” or simply “Ron”), and other attributes can be automatically determined, such as the width divided by length ratio (W / L), number of fingers, and number of device cells, as described in more detail below. In some embodiments, for example, known layout parameters for a particular transistor configuration can be retrieved and used to determine one or more attributes (e.g., gate width or aspect ratio) of the transistor to be generated. In 4603, a circuit specification is generated. The circuit specification can include one or more devices configured to generate the specified transistor to be generated. At 4604, a transistor level schematic is generated from the circuit specification, and at 4605, a layout for the specified transistors is generated.

[0199] 47A-47E illustrate example transistors generated with different parameters according to various embodiments. In FIG. 47A, a first parameter set (params_1) results in a circuit specification including one FET device M1 coupled to nodes a, b, and c. Furthermore, device M1 may be associated with, for example, an n-type 6 volt device. The received parameters may include, for example, Rds_on, which may be used to determine a first gate width w=W1, a gate length l=L1, a specific number of fingers F=F1, and a multiplier attribute (M) (where M=1), where, for example, W1 and L1 are values ​​(e.g., W1=2.8 um and L1=200.0 nm) and F1 is an integer (e.g., F1=2). The multiplier attribute (M) is one technique that may be used to specify, for example, the number of device cells. Typically, in the following examples, the W 、L , and F represent different values ​​for width, length, and fingers, respectively. In this example, circuit specification parameters are used to generate a transistor-level schematic for NMOS transistor 4701. This circuit specification can be used to select a 6v n-type transistor 4701 (e.g., from a transistor library), which is then configured with attributes including, for example, gate width w=W1, gate length l=L1, number of fingers F=F1, and multiplier attribute M=1. Transistor 4701 can be placed in the schematic and coupled to other circuit configurations as described herein.

[0200] FIG. 47B shows a second parameter set (params_2) resulting in a circuit specification including one FET device M1 coupled to nodes a, b, and c. Device M1 may be associated with, for example, an n-type Vds_max=6 volt device. The received parameters may include, for example, a different Rds_on that can be used to determine a second gate width w=W2, a gate length l=L1 (which may be the same minimum gate length, for example), the same number of fingers F=F1, and a multiplier attribute M=1. This circuit specification may be used to select a 6v n-type transistor 4702, which is then configured and placed in a transistor-level schematic using the attributes shown in FIG. 47B and described above.

[0201] FIG. 47C shows a third parameter set (params_3) resulting in a circuit specification including one FET device M1 coupled to nodes a, b, and c. Device M1 may be associated with, for example, an n-type Vds_max=6 volt device. The receive parameters may include, for example, additional values ​​for Rds_on that may be used to determine a third gate width w=W3, the same gate length l=L1, a different number of fingers F=F2, and a multiplier attribute M=1. This circuit specification may be used to select a 6v n-type transistor 4703, which is then configured and placed in a transistor-level schematic using the attributes shown in FIG. 47C and described above.

[0202] Figure 47D shows a fourth set of parameters (params_4) that generates specifications for device M4 associated with an n-type Vds_max = 6 volt device. The received parameters may include, for example, additional values ​​for Rds_on that may be used to determine a fourth gate width w = W4, the same gate length l = L1, the same number of fingers F = F2 as device M3, and a multiplier attribute M = 1. This circuit specification may be used to select a 6v n-type transistor 4704, which is then configured and placed in a transistor-level schematic using the attributes shown in Figure 47D and described above.

[0203] From the above examples, it can be seen that a wide range of devices can be generated having different combinations of width and finger count based on different parameter values.

[0204] FIG. 47E shows another example transistor generated from a fifth parameter set (params_5a). In some embodiments with larger gate widths, it may be desirable to generate multiple device cells. In one example embodiment, params_5a can generate a circuit specification for an n-type MOS transistor having Vds_max=6 volts, a gate width w=W4 (e.g., transistor unit gate width Wunit), a gate length l=L1, a number of fingers F=F3, and a multiplier attribute (M=P1, where P1 is an integer value greater than 1 that specifies the number of device cells). When this circuit specification is converted into a transistor schematic, the result is transistor 4705 having a width W4, F3 fingers configured in parallel, and a multiplier M=P1. The drain is coupled to node a, the gate is coupled to node b, and the source is coupled to node c.

[0205] Figure 47F shows another parameter set (params_5b) that results in a circuit specification for a p-type MOS transistor having a gate width W1, length L1, number of fingers F2, and a multiplier M = P1. This circuit specification is used to generate a transistor-level schematic diagram for a PMOS transistor 4706 having the attributes specified in the circuit specification shown in Figure 47F.

[0206] FIG. 48A shows another example transistor generated from another set of parameter values ​​(e.g., params_6). FIG. 48A illustrates an alternative technique for generating multiple device cells. For example, rather than setting M>1 in the attributes of a single transistor to achieve multiple device cells, the transistor to be generated can be implemented as P (an integer) transistors in parallel based on param_6. For example, a circuit specification may specify P MOSFET transistors, M1, M2, ..., MP, with M coupled to nodes a, b, and c. These transistors may be n-type, Vds_max=6v, unit gate width w=W6, gate length l=L1, and number of fingers F=F6. The multiplier M attribute of each transistor is set to 1 in this example. When the circuit specification is converted to a transistor-level schematic, P (an integer) n-type MOS transistors 4820(1) through 4820(P) having Vds_max=6v, width=W6, length=L1, number of fingers F=F6, and multiplier M=1 are selected and configured in parallel. For each device, the drain is coupled to node a, the gate is coupled to node b, and the source is coupled to node c. Each transistor can be configured, for example, within one of symbols 4810(1) through 4810(P), which can be embedded, for example, within symbol 4800 for a composite transistor having specified characteristics.

[0207] FIG. 48B shows another example transistor generated from another set of parameter values ​​(e.g., params_7). In this example, params_7 results in a circuit specification specifying P (integer) p-type MOSFET transistors M1, M2, ..., MP coupled to nodes a, b, and c, with Vds_max=12v, unit gate width w=W7, gate length l=L1, number of fingers F=F7, and multiplier attribute M=1. When the circuit specification is converted to a transistor schematic, P (integer) Vds_max=12v p-type MOS transistors 4821(1) through 4821(P) are selected and configured in parallel with attributes set to width w=W7, length l=L1, number of fingers F=F7, and M=1. For each device 4821(1) through 4821(P), the drain is coupled to node c, the gate is coupled to node b, and the source is coupled to node a. Each transistor may be configured, for example, within one of symbols 4811(1)-4811(P), which may be embedded, for example, within symbol 4801 for a composite transistor having specified characteristics.

[0208] FIG. 49A shows an exemplary method for generating a transistor according to another embodiment. In 4901, information specifying the transistor to be generated is received by generator software executing on a computer system. This information may include parameters describing characteristics of the MOS transistor to be generated, such as n-type or p-type, Vds_max (e.g., 2v, 6v, 12v, 20v, 24v, 30v), Vgs_max (e.g., 2v, 6v), on-resistance (Ron), Kelvin (yes / no), replica (yes / no), or test (yes / no). In 4902, a total width (Wtotal) for the transistor to be generated is determined. The gate length can be retrieved (e.g., from memory, a database, or a file), for example. One exemplary technique for determining the width of the transistor is described below in FIG. 49B.

[0209] In one exemplary embodiment, a transistor having a unit width Wunit can be generated, where the transistor can have a plurality of fingers and / or some device cells (P) as described above (e.g., based on a plurality of attributes M or parallel devices). In 4903, the unit width Wunit, the number of fingers F, and the number of device cells P configured in parallel can be determined. For example, in one embodiment, the maximum width (Wmax), the maximum number of fingers (Fmax), and the maximum number of device cells (P) can be determined from the total width. For example, when the total width is 200,000 um, Fmax = 120, and Wmax = 200 um, P = 9 is considered to generate the following number of fingers (F): F = Wtotal / (Wmax * P) = 200Kum / (200um * 9) = 111

[0210] The generator software can sequentially determine different values of F over different values of P, for example, until values of F and P are found that result in F < Fmax. In one particular exemplary embodiment, P is set to a perfect square (i.e., the square root of P is a positive integer), which advantageously achieves an N×N array of device cells in the layout, as will be described in more detail below.

[0211] Features and advantages of the present disclosure may further include setting the unit width so that a plurality of transistor device cells have a rectangular area. The ratio of the x dimension to the y dimension (e.g., X / Y or Y / X, where X is the length of the cell in the x direction and Y is the length of the cell in the y direction) may be, for example, between about two-thirds and about three-quarters, providing a rectangular layout structure that is advantageous for arranging layout structures and optimizing the area of ​​the semiconductor circuit. In one exemplary embodiment, X / Y=0.75. The Y and X of the transistor may be determined from layout parameters, where, for example, X is a function of the number of fingers, X=f1(F), and Y is a function of the unit width, Y=f2(Wunit). In this example, the number of fingers, F, can be achieved from Wtotal, Wmax, and P (above), so the unit width, Wunit, can be expressed as follows: Wunit=f2 -1 (Y)=f2 -1 (X / 0.75)=f2 -1 (f1(F) / 0.75)

[0212] X=f1(F) and Y=f2(Wunit) are predetermined functions based on predetermined transistor layout parameters, which can be different for different transistors. Thus, the generator software running on the computer system can select different formulas for X=f1(F) and Y=f2(Wunit) based on information specifying the transistor to be generated (e.g., n-type or p-type, Vds_max, Vgs_max, or parameters for a particular transistor from a library of transistors used in a particular circuit specification). Exemplary formulas X=f1(F) and Y=f2(Wunit) for n-type and p-type transistors are illustrated below:

[0213] Thus, using the techniques described above, the transistor attributes W, L, and F to be generated can be achieved. The number of device cells P can be configured, for example, either as M=P or as P transistors configured in parallel. Thus, at 4904, a circuit specification can be generated. At 4905, the circuit specification can be used to generate a schematic diagram, and at 4906, a layout is generated from the circuit schematic diagram.

[0214] Features and advantages of the present disclosure include receiving a value for on-resistance (Ron) and using Ron to determine a gate width (e.g., Wtotal) for a transistor. In one exemplary embodiment, the relationship between Ron and Wtotal can be determined by generating simulated experimental data for a particular transistor (e.g., Vds_max=6v NMOS or Vds=24v PMOS) that compares Ron with different values ​​of gate-to-source voltage (Vgs), gate width (w), and temperature (T), thereby generating data points corresponding to a particular curve for such a particular transistor. For example, an equation for this curve can be obtained by a curve-fitting algorithm, such as a regression algorithm. In one embodiment, regression of a data set including Ron values ​​across different values ​​for Vgs, w, and T can result in the following coefficients for the curve: Ron=Vgs k1* w k2* T k3* C

[0215] For a given Ron, the required transistor width can be obtained as follows: JPEG2024170423000002.jpg20150

[0216] The above formula can use, for example, a predetermined gate length. In one embodiment, a width of one device cell (e.g., M=1) can be used (e.g., w=200 um), and the data set can use different values ​​of M (e.g., sweeping Vgs, M, and T versus Ron).

[0217] FIG. 49B illustrates an exemplary method for converting a specified value of on-resistance (Ron) to gate width (e.g., Wtotal) according to an embodiment. At 4910, data sets are generated for different gate width values ​​(w) that result in different values ​​of Ron for multiple transistor types. For example, various embodiments may determine values ​​of Ron across gate width and other transistor operating parameters, such as gate-to-source voltage (Vgs) and / or temperature (T). Thus, different transistor types may have corresponding different data sets. For example, different transistor types (e.g., p-type, n-type, signal FET, or power FET) having different drain-to-source maximum voltages (Vds_max) and different gate-to-source maximum voltages (Vgs_max) may have corresponding different data sets. At 4911, multiple regression coefficients are generated for each transistor type. In one exemplary embodiment described above, the regression coefficients may include a Vgs coefficient (k1), a gate width coefficient (k2), a temperature coefficient (k3), and a constant (C). In some embodiments, the same regression equation and corresponding coefficients can be used, for example, across multiple transistor types. At 4912, a Ron value is received along with information specifying a transistor type. For example, the generator software component can receive a value for Ron, a value for Vds_max, and a value for Vgs_max. The values ​​for Vds_max and Vgs_max can be used to select a particular transistor type (e.g., a 6v NMOS transistor) from a transistor library, which can have a Ron vs. width data set and coefficients as described above. At 4913, regression coefficients can be selected based on the specified transistor type. At 4914, a transistor gate width can be determined based on the received Ron value and the selected regression coefficients. The resulting gate width can be, for example, a total gate width Wtotal.

[0218] FIG. 50 illustrates generation of a transistor with a replica device 5001 according to an embodiment. In this example, a value for a parameter (e.g., params_8) can specify that the transistor to be generated will include a replica transistor (e.g., replica=yes). In this example, the generator receives params_8 and generates a circuit specification including one Vds_max=6v NMOS transistor 5002 (e.g., “ntype_6v”) M1 with width w=W4, length l=L1, number of fingers F=F3, and multiplier M=1. The circuit specification configures M1 to have its drain coupled to node a, its gate coupled to node b, and its source coupled to node c. When generating a replica device, the circuit specification further includes a replica transistor MR5001, which in this example is the same device type as M1 (Vds_max=6v NMOS, here “ntype_6v”). The length can be the same (l=L1), but the width and number of fingers can be different. In this example, the width is w=WR, the number of fingers is F=1, and the multiplier is M=1. In one exemplary embodiment, the parameters can specify the replica gain. Thus, the generator can set values ​​for the widths of the replica transistors, for example, to obtain the gain specified by the parameters. For example, if the replica gain is set to 1000:1, the ratio of the total width of M1 to the width of MR is Wtotal / Wreplica=1000 / 1.

[0219] FIG. 51 illustrates generation of a transistor with a Kelvin connection according to an embodiment. In this example, a value for a parameter (e.g., params_9) can specify that the transistor to be generated is to include a Kelvin connection (e.g., Kelvin=Yes). In this example, the generator receives params_9 and generates a circuit specification including one Vds_max=6v NMOS transistor (e.g., “n-type_6v”) M1 with width w=W4, length l=L1, number of fingers F=F3, and multiplier M=1. The circuit specification configures M1 to couple its drain to node D (e.g., (D)rain), its gate to node G (e.g., (G)ate), and its source to node S (e.g., (S)source). Additionally, the circuit specification is configured to generate additional terminals (e.g., (D)rain_(K)elvin “DK” and / or (S)source_(K)elvin “SK”) coupled to the drain and / or source along secondary conduction paths from points within the integrated circuit near the drain and / or source, respectively. The secondary conductive path may draw a very weak current compared to the current flowing along the primary conductive path (e.g., the path between the drain and the circuitry connected to the D terminal, or the path between the source and the circuitry connected to the S terminal). Thus, the DK and SK terminals may sense voltage while minimizing the current-related voltage drop experienced along the primary conductive path, for example, between the drain and / or source and the S and D terminals. In one exemplary embodiment, the generator may further include resistors in the secondary conductive path (e.g., to reduce the current flowing in the secondary conductive path). Thus, in this example, the circuit specification includes a first resistor R1=100 mOhm coupled between nodes D and DK, and a second resistor R2=100 mOhm coupled between nodes S and SK. The circuit specification may be converted into a transistor schematic 5100 including an NMOS transistor 5101 and resistors 5102 and 5103 configured as shown. From this transistor schematic a layout can be generated where the secondary path is coupled to the transistor, for example, immediately adjacent to either the drain or the source.

[0220] FIG. 52A shows an example of automatically generating a transistor layout according to an embodiment. FIG. 52A shows alternative layouts 5200(1) through 5200(N) of transistors with different numbers of fingers F. Transistor layout 5200(1) includes two fingers, in this case two gates 5201 and 5202, each having a width w. Transistor layout 5200(1) also includes two sources 5203 and 5204 and a single drain 5205. FIG. 52A illustrates that as the number of fingers varies, the length of the transistor's x-dimension (e.g., horizontal) can change, but the length of the y-dimension (e.g., vertical) can remain the same. The overall y-axis length of the transistor can be set by the transistor gate width w and the upper and lower edges of the gate, source, and / or drain structures. In this example, lengths C (above the gate / source / drain) and D (below the gate / source / drain), together with width w, set the overall y-axis length Y. The number of fingers and other x-axis lengths can set the total x-axis length X.

[0221] For example, if F=4 fingers, additional gate, drain, gate, and source segments may be added, the additions change the length along the x-axis, but the length along the y-axis remains the same. For example, the x-axis length can be a function of a first length A, a second length (or pitch) p, and a third length B (e.g., X=[(F / 2) * (p)itch]+xoffset, where xoffset=A+B). The y-axis length can be a function of the unit gate width Wunit and the lengths C and D (e.g., Y=w+yoffset, where yoffset=C+D). In one exemplary embodiment, the layout parameters for a Vds_max=6v NMOS transistor can be (p)itch=3.3um, xoffset=2.33um, and yoffset=8.33um. As Vds_max increases, xoffset and yoffset can remain the same, but the pitch can increase. For example, the following are exemplary (Vds_max,P(pitch)) tuples for other NMOS transistors: [(12v,4.1um), (20v,4.9um), (24v,5.3um), (40v,7.9um)]. Length A can include various layout structures related to the first edge of the transistor, such as bulk material, a first source configured along the first edge of the transistor, and other layout structures. Length B can include various layout structures related to the second edge of the transistor, such as bulk material and other layout structures. Lengths C and D can include various layout structures, such as bulk material and process-specific setbacks. Length (p)itch can include layout structures that repeat when additional fingers are included in the circuit. For example, when F=4, an additional segment 5210 can be included to generate layout 5200(2) including a second gate / drain / gate / source. The x-axis length can increase by another amount p, but A and B can remain constant. As shown in layout 5200(N), for F=N, A and B remain constant and there are N (p)itch lengths. It is to be understood that the layout structure may be different for different transistors, and therefore A, B, (p)itch, xoffset, and yoffset may be different for different transistors.However, the same type of transistors (e.g., n-type, MOSFET, Vds_max = 6V, Vgs_max = 6V) can have the same layout structure and the same values for A, B, (p)itch, xoffset, and yoffset in different instances of the transistors. The example described in FIG. 52A shows, for example, the variation of the x-axis length versus F for one y-axis length corresponding to the same gate width w for layouts 5200(1) to 5200(N).

[0222] FIG. 52A is advantageous in showing how the attributes of the transistors in the transistor-level connection diagram can be determined. When the unit width and the number of fingers change, composite transistors can be formed using different numbers of device cells (P) (e.g., 5200(1) to 5200(N)). In one exemplary embodiment, using the total width Wtotal calculated from the specified Ron, the number of fingers F can be determined with respect to a given maximum unit width Wunit_max, the maximum number of fingers Fmax, and P (the number of device cells). For example, the number of fingers F can be calculated based on Wtotal, P = 1, Fmax, and Wunit_max. If no solution is obtainable, P can be increased. The number of device cells can be incremented iteratively and sequentially to a larger number of device cells until a solution for F is found. The number of device cells can be limited to values that can form a two-dimensional array having a combined aspect ratio (e.g., rectangular) between 0.5 and 1. In one embodiment, the number of device cells can be advantageously set to perfect squares (e.g., 1, 4, 9, 16,...). When the number of fingers F (F < Fmax) and the number of device cells P are found for a given Wtotal and Wunit_max, for example, the final width of each transistor with respect to a specified ratio (X / Y or Y / X) can be determined.

[0223] In one embodiment, the unit gate width (Wunit), the number of fingers (F), and the number of device cells (P) can be determined based on the maximum width and the maximum number of fingers. The maximum width (Wmax) and the maximum number of fingers (Fmax) can be predetermined values ​​included in the generator software or stored in and received from an external storage location (e.g., a file or database). In one embodiment, the generator software can determine the number of device cells (P) and the number of fingers (F) based on each successive increment of the current number of device cells (P), the maximum width (Wmax), and the maximum number of fingers (Fmax) by increasing the number of device cells (P) through multiple increments to determine the number of available fingers (F). This approach can advantageously result in a minimum number of device cells (P) and a small circuit area.

[0224] For example, starting with a total width (Wtotal), the generator software can iteratively increase the number of device cells (P) through multiple values. For P=perfect square, P can be iteratively set to 1, 4, 9, etc. At each current value of P, the system can determine whether the total width (Wtotal) is available given the current value of P, the maximum width (Wmax), and the maximum number of fingers (Fmax). For example, with Wtotal=200,000 um, Wmax=200 um, and Fmax=120, P=1 results in F=Wtotal / (Wmax*P)=1000, which is greater than Fmax. Therefore, this total width is not obtainable from the current value of P, Wmax, and Fmax. Therefore, P is incremented to the next value (here, 4). With P=4, F=250, still greater than Fmax. Therefore, P is incremented to the next value (here, 9). When P=9, F=111, which is smaller than Fmax. Therefore, from P=9, F=111, and Wmax=200 um, Wtotal=200,000 um is available, and these values ​​can be used to set the transistor attributes.

[0225] Features and advantages of the present disclosure may further include setting transistor attributes based on one or more layout parameters. For example, as described above, a configurable aspect ratio of a device cell may be used to set the x- and y-axis lengths of the device cell, which may set, for example, a unit gate width, Wunit. For example, the length X along the x-dimension of the device cell may be determined by the number of fingers (F) and a predetermined offset value (e.g., layout parameters related to P (pitch) and xoffset) - X = ((F / 2) * As mentioned above, the predetermined offset value can be selected based on the transistor type (e.g., one or more of dopant type, p / n type, Vdsmax, Vgsmax), e.g., different transistor types can have different layout parameter values ​​for pitch, xoffset, and yoffset. Next, the length X and the aspect ratio (Y=AR * A length Y along the y-dimension of the device cell may be determined based on the total width and total length and a predetermined offset value yoffset-Y=Wunit+yoffset. In some embodiments, the generator software may compare the area calculated based on the total width and total length to the area calculated based on the final unit gate width (Wunit), the number of device cells (P), and the number of fingers (F). For example, if the area is within an acceptable error tolerance, the design and various layout parameters may be considered valid.

[0226] FIG. 52B illustrates that increasing the number of fingers can change the aspect ratio of a transistor layout. In one exemplary embodiment, varying the number of fingers can result in a change in transistor device cell width to maintain the aspect ratio (e.g., either constant or within a range). Here, a device cell layout instance 5250 is generated for a first device cell having F=F1 fingers and a width w=W1, resulting in a Y / X ratio of 0.75. Another device cell layout instance 5251 can be generated with number of fingers F=F2, width=W2, and a Y / X ratio of 0.75. Yet another device cell layout instance 5252 can be generated with number of fingers F=F3 and width=W3 while maintaining a Y / X ratio of 0.75. Finally, yet another device cell layout instance 5253 can be generated with number of fingers F=F4, width=W4, and a Y / X ratio of 0.75. As discussed above, the number of fingers can be used to determine the width of the transistor. Thus, in some exemplary embodiments, as the number of fingers increases, the transistor width may also increase. Transistor device cells 5250-5253 are successively larger. For a given transistor type, additional fingers can generate a larger gate width to maintain the aspect ratio at a particular value or range. For example, while this figure shows an aspect ratio of 0.75, it is understood that other rectangular aspect ratios can be used. In some embodiments, the aspect ratio can be programmable, for example. Various exemplary embodiments can include aspect ratios greater than or equal to 0.5 (≧0.5) and less than 1. Some embodiments can include aspect ratios from about two-thirds to about three-quarters, for example. Furthermore, while FIG. 52B shows a Y / X aspect ratio, it is understood that an X / Y aspect ratio can be used.For example, a rectangular aspect ratio (e.g., X<>Y) may be advantageous to allow the layout routine to manipulate one or more transistors to reduce the area of ​​the semiconductor circuit, optimizing placement by allowing the system to rotate the transistor layout to fit into different available spaces on the layout.

[0227] 53A-53B illustrate an array of transistor device cell layout instances configured to form a transistor according to an embodiment. As described above, for example, the transistor device cell layout instances shown in FIG. 52A can be combined in an M×N array (where M and N are integers) to form a single composite device (e.g., using P parallel transistors with multiplier attributes M=P>1 or M=1). FIG. 53A illustrates, for example, a 3×4 array with a ratio Y / X of two-thirds (drawing not to scale). The device cell layout instances can be spaced apart in equal steps Sx along the x-axis and equal steps Sy along the y-axis. In some embodiments, Sx and Sy can be the same.

[0228] Figure 53B illustrates an array of transistor device cell layout instances configured to form a transistor according to another embodiment. Figure 53B illustrates an example in which the device cell count is set to perfect squares (e.g., 1, 4, 9, 16, 25, 36, ...) to generate an N x N array. In this example, nine device cell layout instances 5302 are configured into a 3 x 3 array with a ratio Y / X of, for example, 3 / 4 = 0.75 (drawing not to scale). The cells may be spaced apart in equal steps Sx along the x axis and in equal steps Sy along the y axis, where Sx and Sy may be the same as described above.

[0229] The following are example layout placement instructions for placing a device cell layout to form a transistor: placeFET xy xstep ystep #columns #rows

[0230] Here, for example, each transistor type can have unique layout parameter values ​​that are used in the above-mentioned layout placement instructions. The x and y in the above-mentioned layout placement instructions are the locations where the first device cell layout instance will be placed. Furthermore, "xstep" and "ystep" indicate offsets to the location of the next layout instance along the x and y axes. Finally, the number of columns and rows can be specified. Based on the above disclosure, the xstep, ystep, #columns, and #rows can be calculated and received by the layout placement instructions, for example, during execution.

[0231] FIG. 54 illustrates generation of a layout for transistors according to an embodiment. In this example, received parameters are used to generate a circuit specification including four device cells (P=4), each of which is an n-type Vds_max=6v MOS transistor with gate length w=W1, length l=L1, number of fingers F=F1, and multiplier M=1. The circuit specification is used to generate a transistor-level schematic including transistors 5401-5404 configured in parallel. This schematic is used to generate a layout. Each transistor 5401-5404 can be automatically converted into, for example, a device cell layout instance 5410. The device cell layout instances are automatically placed using layout placement instructions. For example, a first device cell layout instance can be placed at a starting location (e.g., location x=0, y=0 in the layout environment). The device cell layout instances can be placed serially along the x and y axes based on x-steps and y-steps. The x step is based on the x axis length X plus the x cell offset ("xcell_offset"), and the y step is based on the y axis length Y plus the y cell offset ("ycell_offset").

[0232] FIG. 55 illustrates generation of a layout for a transistor according to an embodiment. In this example, received parameters are used to generate a circuit specification including an n-type Vds_max=6v MOS transistor (also known as P=25 device cells) with gate length w=W2, length l=L1, number of fingers F=F2, and multiplier M=25. The circuit specification is used to generate a transistor-level schematic diagram including transistor 5501. This schematic diagram is used to generate a layout. Transistor 5501 can be automatically converted into, for example, 25 device cell layout instances 5510. The device cell layout instances are automatically placed using layout placement instructions. For example, a first device cell layout instance can be placed at a starting location (e.g., location x=0, y=0 in the layout environment). The device cells can be placed serially along the x and y axes based on x-steps and y-steps. The x step is based on the x axis length X plus the x cell offset ("xcell_offset"), and the y step is based on the y axis length Y plus the y cell offset ("ycell_offset").

[0233] 54 and 55 show an example where the number P is set to a perfect square as described above.

[0234] Features and advantages of some embodiments of the present disclosure may include automated placement of layout instances (e.g., polygons) to form a transistor layout. For example, FIG. 56A illustrates automated placement of layout instances to form a MOS transistor. In this example, the number of device cells P is equal to 4, and the resulting layout includes a 2×2 array of transistor device cell layout instances 5650-5653. Each of cells 5650-5653 includes multiple source(s) (e.g., source 5602), gate(g) (e.g., gate 5601), and drain(d) (e.g., drain 5603) arranged in parallel as vertical strips. The automated placement of device cell layout instances used to form the complete layout of the transistor may be based on multiple parameters, some of which may be selected based on transistor type and others that may be calculated. For example, different transistor types may select different stored parameters for performing the automated layout using layout placement instructions. For example, automatic layout for an NMOS transistor with Vgs_max=6v and Vds_max=12v may be performed by, for example, selecting different stored layout parameters, performing different placement calculations, and using a different layout algorithm than for an NMOS transistor with Vgs_max=6v and Vds_max=6v. Thus, automatic layout of a transistor may include selecting layout parameters based on the transistor type. Once the layout parameters are selected, additional parameters may be calculated by executing a customization script for the transistor type. To dynamically configure a particular transistor, the selected and calculated parameters may be included as parameters to the layout placement instructions. For example, source, drain, and gate dimensions and placement locations may be determined from transistor attributes (e.g., the w, l, F, and M described above), and layout elements (e.g., polygons) may be automatically placed in the layout based on, for example, the selected and calculated parameters.As illustrated in FIG. 56A and described above, the selection parameters may include multiple offsets for placing a particular layout element at a predetermined position, such as the initial position or the initial position adjusted by a pitch.

[0235] FIG. 56A illustrates an automated layout of metal layers according to an embodiment. This example illustrates stored and calculated parameters according to an embodiment. In this example, multiple metal layers are composed of horizontal strips covering an array of device cell layout instances, such as horizontal metal layers 5620 and 5621. Metal layers 5620-5621 are sometimes referred to as "Metal 2," which may be, for example, a second layer of metal above a polysilicon layer. The metal layers may have widths set to a stored parameter for the maximum width of Metal 2 ("M2wmax"). Some processes may require the insertion of slots when the metallization width exceeds a predetermined value (e.g., to relieve stress). The M2wmax width may be set slightly smaller than the required width of the slot. In another embodiment, the slot width may be stored, and M2wmax may be calculated, for example, by a customized layout placement script, as the slot width less any predetermined amount. Furthermore, the layout placement script may determine the number of horizontal metal strips that can fit across a particular row of cells based, for example, on the gate width of the transistors. An initial M2 strip can be placed at an offset M2os (or equivalent initial reference) below the top edge of the cell, and a calculated number of horizontal M2 strips having a width M2wmax can be placed in series (e.g., spaced apart by a predetermined gap, which can be a process-dependent stored parameter). Figure 56A further illustrates gate metallization 5625 configured between rows of device cells. The device cells can be separated by another stored parameter, "ygap," and M2 gate metal 5625 can be configured, for example, in the center of the gap. Embodiments of the present disclosure can further illustrate automatic placement of vias (e.g., via 5610) that associate M2 with underlying structures in the layout, according to embodiments. In this example, source, drain, and gate vias into the M2 strips can be automatically placed based on one or more of the stored parameters for the transistor, transistor attributes (e.g., gate width), and / or offsets.For example, one or more initial source vias 5610 can be placed based on a source y-axis offset (Syos) and a source x-axis offset (Sxos). Additional source vias can be placed at predetermined steps (e.g., x-axis pitch length and y-axis pitch length based on M2wmax) from their initial placement locations. Similarly, one or more initial drain vias 5611 can be placed based on a drain y-axis offset (Dyos) and a drain x-axis offset (Dxos). Additional drain vias can be placed at predetermined steps from their initial placement locations. Similarly, gate vias can couple gate 5601 to M2 gate metal 5625 according to the gate steps. In this example, the gate-to-gate pitch (Pgg), gate-source-gate pitch (Pgsg), and drain-to-drain pitch (Pdd) can be stored parameters. In this example, the source between the gate pair can have a larger x-axis length, and thus, for example, the Pgsg dimension can be used to properly place transistor layout elements. As can be seen, source vias start at an initial value (e.g., based on Sxos and Syos) and repeat along the x- and y-axes across each cell. Similarly, drain vias start at an initial value (e.g., based on Dxos and Dyos) and repeat along the x- and y-axes across each cell. For example, a devStep parameter can be stored and retrieved for a particular transistor type to set the x-axis distance between the last source 5622 in one cell and the first source 5623 in an adjacent cell so that the layout element can repeat across cells along the x-axis. Similarly, the position of the layout element can be offset across cells along the y-axis using, for example, the y-gap and device width. Figure 56A also illustrates that multiple vias can be placed for each connection point 5610. As shown in 5650, M2wmax can be used to calculate the number of vias that can be automatically placed, for example, at the intersection of an M2 strip with a source, gate, or drain.In one embodiment, the horizontal edges of the M2 strips and the vertical edges of the source, gate, or drain may have a setback process parameter, for example, M2wmax=2. * This can be the remaining distance minus the setback and is used to calculate the number of vias that can be placed in series as shown at 5650. Finally, Figure 56B shows a vertical strip 5690 of metal layer 3 that is above M2 and can be used to connect the M2 source, M2 drain, and M2 gate, for example.

[0236] Automated integrated circuit layout Features and advantages of various embodiments of the present disclosure may further include the automated generation of layouts for integrated circuits. In some exemplary embodiments, a transistor-level schematic diagram may have an associated layout script. When the schematic diagram is converted to a layout (e.g., in an EDA tool), the layout script associated with the circuit schematic diagram may be used to position the layout instance generated from the circuit schematic. Exemplary embodiments of the present disclosure may include a layout script customized for each transistor-level schematic diagram to automatically generate a concise and efficient layout for the circuit.

[0237] FIG. 57 illustrates layout generation according to an embodiment. In this figure, layout generator software component 5700 converts circuit diagram 5701 into multiple layout instances (e.g., instances 5710, 5711, 5712, 5713) to form circuit layout 5703. Circuit diagram 5701 may define a transistor-level circuit for, for example, an analog circuit or a mixed-signal circuit. Layout generator 5700 may generate layout instances (e.g., polygons) for various circuit components within circuit diagram 5701. Initially, the layout instances may be cluttered and not optimally configured based on connectivity, circuit performance, and area conservation, for example. Advantageously, layout generator 5700 may receive a layout script 5702 for circuit diagram 5701. In one embodiment, layout script 5702 may be customized and predetermined for a particular circuit diagram to, for example, optimize the layout. As described in more detail below, layout script 5702 may include a set of instructions for automatically arranging layout instances generated from circuit schematic 5701. As shown in layout 5703, execution of layout script 5702 (e.g., by a computer system) may result in the positioning of multiple layout instances (e.g., instances 5710, 5711, 5712, 5713) to generate circuit layout 5703.

[0238] In various embodiments, for example, the layout instances can correspond to various components from the circuit schematic, and in some cases, additional structures are added to the layout that can be useful for the operation of the circuit when implemented in semiconductor. In one exemplary embodiment, the layout instances can be predetermined layouts for subcircuit schematics, as described above (e.g., predetermined layouts associated with transistor layouts such as comparators, amplifiers, oscillators, bandgap circuits, current mirrors, signal FETs, or power FETs, or a wide variety of other analog or mixed-signal circuits). Accordingly, the layout script can include a reference (e.g., a library name) to a library in which one or more layout instances are stored (e.g., a library in which one or more predetermined layouts for the circuit schematic are stored). In other exemplary embodiments, the layout instances can be passive layout components, such as resistor layout components or capacitor layout components. Advantageously, in certain exemplary embodiments, the layout script generates a specific placement for each of multiple layout instances generated from the circuit schematic 5701 and can further incorporate and automatically place additional layout structures (e.g., vias, guard rings, bulk connections). Thus, in some exemplary embodiments, all layout instances (eg, masks) used to form the circuit layout can be automatically positioned to generate the circuit layout.

[0239] FIG. 58 illustrates an exemplary system including an automatic layout generator according to an embodiment. In this diagram, functional circuitry 5801 can be configured to generate multiple circuit schematics implementing a common circuit function. For example, functional circuitry 5801 can be used to generate circuit configurations for a comparator, oscillator, amplifier, current mirror, gm circuit, voltage-to-current converter, voltage buffer, or any one of a wide variety of other analog or mixed-signal circuit functions. A particular functional circuitry 5801 can implement a particular function (e.g., a voltage-to-current converter) subject to various parameters (e.g., input device type, gain, clamping, etc.). Generator software 5800 can receive parameter values ​​and generate a netlist for generating circuit schematic 5802(1) as described above. Generator 5800 can generate different circuit schematics 5802(1)-5802(N), for example, in response to receiving various combinations of parameter values. Based on different parameter values, the functional circuitry can generate schematics for oscillators, amplifiers, etc., with different characteristics. As described above, circuit diagrams 5802(1)-5802(N) can be generated from predetermined sub-circuit diagrams, which can be stored in library 5805. Library 5805 can store, for example, sub-circuit diagrams and sub-circuit layouts for generating circuit diagrams and layouts for functional circuit component 5801 across different parameter values.

[0240] Features and advantages of some embodiments of the present disclosure further include generator 5800 generating layout script 5803. Layout script 5803 may be associated with one or more of multiple circuit diagrams 5802(1)-5802(N), which may perform common functions and be generated from different values ​​of the same parameters. In some embodiments, layout script 5803 is configured to position layout instances for each of the multiple circuit diagrams. For example, in FIG. 58, a single layout script 5803 is configured to generate layouts for multiple circuit diagrams 5802(1)-5802(N). In some embodiments, the layout script may perform multiple placement operations on layout instances from different circuit diagrams (e.g., a placement operation on a layout instance from diagram 5802(1) and other placement operations on other layout instances from diagrams 5802(2)-5802(N)). As described in various examples below, placement operations may be performed on a layout instance corresponding to circuit diagram 5802(1) (e.g., when circuit diagram 5802(1) is generated and converted to a layout), while placement operations may not be performed on layout instances corresponding to other circuit diagrams (e.g., when circuit diagram 5802(1) is generated and converted to a layout). By way of example only, if a particular diagram is converted to provide layout instance XU1 and another diagram is converted to provide layout instance XU2, the layout script may include placement operations for both XU1 and XU2, but the placement operations may be performed on this layout instance only when the layout instance is present on the layout canvas. Thus, in some embodiments, a single layout script may include placement operations that are executed only when, for example, a particular diagram is being converted to a layout.

[0241] Layout generator 5806 can receive layout script 5803 and any of circuit diagrams 5802(1) to 5802(N) and generate a corresponding layout. In this figure, layout generator 5806 receives layout script 5803 and circuit diagram 5802(1) and generates layout 5808. Similarly, layout generator 5806 receives layout script 5803 and circuit diagram 5802(N) and generates layout 5809. For example, a layout for any of circuit diagrams 5802(1) to 5802(N) can also be generated automatically.

[0242] The automatic layout techniques described in this description may be applied to the system described in FIG. 58 and other portions of this disclosure, but it is understood that these techniques may be used, for example, to convert a schematic diagram to a layout within an EDA environment using an EDA tool.

[0243] FIG. 59 illustrates the conversion of a circuit schematic into layout instances and the generation of layouts according to an embodiment. In this example, in 5902, circuit schematic 5901 is converted into layout instances 5910-5913. In various embodiments, the layout instances can correspond to different components within the schematic. For example, the layout instances can correspond to passive layout components, such as resistor layout components or capacitor layout components. In this example, layout instances 5913a-5913d can be, for example, resistor layout segments within circuit 5901, corresponding to multiple resistor segments configured to generate a single total resistance value Rtotal. In another example described below, the layout instances can be, for example, capacitor layout segments within the schematic, corresponding to multiple unit capacitors configured to generate a single total capacitance value Ctotal. As described above, different parameterized instances of circuit schematic 5901 can include different predetermined sub-circuit schematics. In this example, layout instances 5910, 5911, and 5912 are three predetermined partial circuit schematic layouts. It is understood that any one or more components in circuit schematic 5901 can be converted into a layout instance and placed according to the techniques described herein.

[0244] Initially, layout instances may be placed in a non-optimal manner within the layout environment (e.g., scattered across the canvas). Layout script 5902 can place layout instances in specific locations to generate a more optimal layout. In this example, layout script 5902 places layout instances in specific locations in 5914 to generate layout 5930. Advantageously, layout script 5902 can be customized to automatically place each layout instance from one or more corresponding circuit schematics in any location to generate an optimal layout, for example.

[0245] Although the example shown in FIG. 59 and further examples below show layout instances initially placed on the layout canvas prior to final positioning by the layout script, it is understood that the layout instance can be placed directly in its final customized position by the layout script without such initial placement on the canvas.

[0246] FIG. 60 illustrates a layout script according to an embodiment. Features and advantages of some embodiments may include a layout script including multiple layout placement instructions. The layout placement instructions may specify placement locations (e.g., within a layout environment) for one or more corresponding layout instances. Thus, the layout placement instructions may be advantageously used to position one or more of the layout instances. In this example, a layout script 6000 includes multiple layout instructions 6001-6003. The layout placement instructions 6001-6003 may include code for performing a specific function corresponding to each layout placement instruction. The code may be implemented as a script, for example, a script within an EDA environment (e.g., SkillScript within Cadence®). In this example, the layout placement instructions may operate on one or more instances. Furthermore, the layout placement instructions may receive layout parameters, for example, to control various operations performed on the layout instances.

[0247] In various embodiments, the script 6000 can include multiple layout placement instructions 6001-6003, and a subset of the layout placement instructions can include references to specific layout instances. As shown in various examples below, in some embodiments, the references are cell names (e.g., place<cell_name> In other embodiments, the reference is an instance name (e.g., place<instance_name> In some applications, multiple layout instances may have the same cell name but different instance names. Therefore, layout placement instructions can be advantageously configured to make cell name-based placement or instance name-based placement more efficient for different scenarios.

[0248] Various exemplary layout placement instructions are presented in more detail below.

[0249] FIG. 61 illustrates an example placement operation of a layout placement instruction, according to an embodiment. In some embodiments, one or more layout placement instructions specify a particular layout instance and x-axis and y-axis coordinates for placing it. In this example, layout instance 6101 is placed at (x,y) coordinates (0,0) as shown in 6101A (e.g., "place").<cell_name> Alternatively, the layout instance 6101 can be placed at another (x,y) coordinate (x1,y1) as shown in 6101B (e.g., "place<cell_name> x1 y1", where x1 can be a first specified value and y1 can be a second specified value. Figure 61 also illustrates another feature of some embodiments in which one or more layout placement instructions further specify a rotation of a particular layout instance. In this example, the layout placement instruction may rotate layout instance 6101B by 90 degrees (e.g., place<cell_name> x1 y1 90). In some embodiments, it may be advantageous for the layout placement instruction to further specify the name of a library that stores a particular layout instance. For example, the library that stores the predetermined partial circuit layout instance may be included as a parameter in the layout placement instruction (e.g., "place<library_name><cell_name> "0 0 0" allows a specific cell from a specific library to be placed at (x,y)=(0,0) with 0 rotation).

[0250] FIG. 62 shows yet another example of layout generation according to yet another embodiment. In some embodiments, a layout placement instruction can position multiple layout instances. The example shown in FIG. 62 is illustrative. Here, multiple layout instances for the same type of cell (e.g., having different instance names) can be placed using a single layout placement instruction. In this example, layout instances 6201a-6201b correspond to a first layout instance type (e.g., one predetermined sub-circuit layout or passive component), layout instances 6202a-6202d correspond to a second layout instance type (e.g., resistor layout components), and layout instances 6203a-6203c correspond to a third layout instance type (e.g., capacitor layout components).

[0251] In one embodiment, layout instances 6201a-6201b can be placed using a single layout placement command. For example, "placeSTEP<cell_name> The instruction "xy step step direction rotation" can position both layout instances by placing them starting at a starting position and then placing them at another position defined by the step. This example layout placement instruction illustrates several features that can be included in various embodiments. First, the first layout instance<cell_name> can be located at specific (x,y) coordinates, e.g., the same<cell_name> Subsequent layout instances with "placeSTEP" will be placed at a position offset from the specified (x,y) coordinates by the amount "step". Additionally, a step direction (e.g., +x, -x, +y, or -y) can be specified within the layout placement instruction. Finally, rotation is included within this example layout placement instruction. Thus, "placeSTEP"<cell_name_6201> 0 0<cell_width_6201> Execution of the layout placement command "x 90" causes the layout instances 6201a to 6201b to be first placed at the point (0,0), and then moved along the +x direction to "0+<cell_width> ", where<cell_name_6201> is the cell name,<cell_width_6201> is the width (here, the length along the x-axis) of layout instances 6201a-6201b. Similarly, layout instances 6202a-6202d may be placed in series starting at point (x1,0) using a single layout placement instruction, and 6203a-6203c may be placed in series starting at point (0,y1) using a single layout placement instruction. In some exemplary embodiments, resistors may have dedicated layout placement instructions (e.g., placeRES) and capacitors may have dedicated layout placement instructions (e.g., placeCAP), both of which are described in more detail below.

[0252] FIG. 63A illustrates exemplary types of steps that can be used in various layout placement instructions according to various embodiments. FIG. 63A illustrates that layout instances 6301a-6301d can be stepped differently from layout instances 6302a-6302d. For example, in one embodiment, the step can specify the distance between adjacent boundaries of the layout instances. This is illustrated in 6300a, where layout instances 6302a-6302d are positioned along the +x-axis, starting at (0,0), by the distance, or step, between the vertical sidewall boundaries of each layout instance. Here, the layout placement instruction can position each layout instance based on the step value specified therein plus the length of the layout instance along one axis (e.g., the x-axis in this case). Specifying the distance between adjacent layout instances can be advantageous for layout instances that may have different sizes, such as for resistor layout components or capacitor layout components.

[0253] Alternatively, the step can specify a pitch, where subsequent placements are the initial position plus the pitch (e.g., x = xinit + (i * The layout placement instructions are positioned at a step (pitch). Thus, some layout placement instructions can set the step to be greater than or equal to the length of the boundary along the first axis of the subset of layout instances being positioned. In FIG. 63A, layout instances 6301a-6301d have their step set to their length along the x-axis, and each layout instance is positioned so that adjacent vertical boundaries touch. This step type can also be used, for example, to set the spacing between each layout instance.

[0254] FIG. 63B illustrates additional parameters used by some layout placement instructions, according to embodiments. In some embodiments, a single layout placement instruction can be used to place multiple layout instance groups (e.g., multiple resistor layout component subgroups). In this example, the layout placement instruction includes at least a first layout placement instruction subgroup 6303a-6303d and a second layout placement instruction subgroup 6304a-6304d. The layout placement instruction can specify a step between layout instances in the first and second subgroups. In some embodiments, for example, the subgroups can have different names (e.g., resistor layout instance names or cell names), and the layout placement instruction can place layout instances in the same group using a first spacing (or step), and two subgroups can be placed such that there is a second spacing (or step) between them. In this example, the layout placement instruction can place layout instances 6303a-6303d in series, starting at (0,0), separated by a "step" along the x-axis. The layout instances 6304a-6304d are placed in series starting at a location separated along the x-axis by the "group step" from the adjacent boundary of the last layout instance of the group 6303a-6303d. The layout instances 6304a-6304d are then placed in series separated by the "step". An example layout placement instruction for positioning the resistor layout instances is "placeRES xy step_btwn_same_name_res step_btwn_diff_name_res rotation directionx directiony distance". The "distance" feature is discussed in more detail below with respect to Figure 63C.

[0255] In some embodiments, one layout placement instruction can follow another. The subsequent layout placement instruction can position one or more layout instances starting from the end position of the previous layout placement instruction. This placement can be advantageous, for example, to place a different layout instance serially relative to a previously placed layout instance. Figure 63C shows two different examples. For example, in layout 6300c, layout instances 6306a-6306d are placed serially using a first layout placement instruction (e.g., placeSTEP), and layout instances 6305a-6305d are placed serially continuing from where the previous layout placement instruction ended using a second layout placement instruction (e.g., placeSTEPCONTINUE). In some embodiments, the second layout placement instruction can include layout placement parameters for step direction and rotation as described above. Layout 6300d, for example, shows where a second layout placement instruction rotates -90 degrees from where the previous layout placement instruction ended and continues along the -y direction to place layout instances 6305a-6305d in series, such that in this example the layout instances are placed around the perimeter of occupied region 6390. The following example is an example of a layout placement instruction that can follow a previous layout placement instruction and maintain the x,y coordinates of the previous layout placement instruction, according to an embodiment: "placeSTEPcell libraryname cellname rotation" / / Places the layout instance for "cellname" from "libraryname" (which is not converted from a circuit diagram and may not exist on the layout canvas) into the next step xy (which may follow placeSTEP) from the preceding instruction. placeSTEPcontinue libraryname cellname stepdirection stepdistance rotation / / Places the layout instance at the next step xy location from the previous instruction (which can follow placeSTEP).

[0256] Figure 64 illustrates another parameter used in some layout placement instructions according to various embodiments. Here, the layout placement instructions further specify a distance. The distance can specify a maximum distance along one axis (e.g., the x-axis), where layout instances greater than this distance are placed starting at a different position along the other axis (e.g., the y-axis) and progressing along the first axis (e.g., the x-axis) until this distance is reached. Thus, layout instances can be placed serially along the first axis from a starting position to a second position based on the distance. When a first portion of the layout instance spans the space between the starting position and the second position, a second portion of the layout instance is placed serially along the first axis between a third position offset from this final position along the second axis and a fourth position based on this distance. Figure 64 illustrates different layouts of layout instances 6401a-6401c and 6402a-6402g for different distance parameter values.

[0257] Layout 6400a illustrates that d1 can be set as a parameter for the first distance. Thus, layout instances 6401a-6401c are placed serially along the x-axis, starting from (0,0). With instance 6401c placed, there is room for instance 6402a, for example, within distance d1. With layout instances 6401a-6401c and 6402a spanning distance d1, the next location for placement is moved along the y-axis from the final location of instance 6402a to a new location offset along the y-axis by an amount equal to the thickness of instances 6401a-6401c or 6402a (where these instances have the same thickness), and then resumes along the x-axis in the negative x-direction. In this example, all remaining instances of 6402 are placed. However, if additional instances are placed, placement will increment the y-axis each time distance d1 is occupied. This is illustrated in 6400b, where the last two layout instances 6402g-6402f, by a distance d2 less than d1, are folded back onto the x-axis to form a third row along the y-axis. In various embodiments, the automatic meandering ("back and forth" or "alternating") arrangement of layout segments can advantageously shorten the length of connections between segments in some example applications.

[0258] Layouts 6400c-6400d illustrate another feature of some embodiments. In layout 6400c, if a layout instance cannot fit within the remaining distance d3, the layout instance is offset (up the y-axis in this illustration) and its starting position is at distance d3. Alternatively, in 6400d, the layout instance can be left-justified relative to x=0.

[0259] 6400e-6400f illustrate another feature of some embodiments. This example illustrates another parameter that can specify "strict" or "loose" adherence to the distance parameter. For example, as shown in layout 6400e, in some situations it may be advantageous to allow some small extension greater than distance d4 before continuing placement at an offset location. As shown in layout 6400f, the system applies "strict" to distance d4 as a maximum, and layout instance 6401c is placed on a new line up the y-axis so as not to exceed distance d4.

[0260] Layout 6400g illustrates another parameter of a layout placement instruction, according to an embodiment. In one embodiment, the layout placement instruction can associate a distance with one of the layout instances. In this example, the distance is set equal to d5, the length of the longest resistor layout component. Thus, one instance of the longest resistor layout component is placed, and its next location is moved to the next location (up the y-axis in this illustration). Subsequent layout segments are placed as described above until, for example, all resistor layout components have been placed to form layout 6400g.

[0261] Features and advantages of some embodiments may further include layout placement instructions that include conditional statements. Figure 65 shows steps for conditional layout placement instructions. At 6501, a condition for the layout placement instruction is evaluated. A layout placement instruction may have associated with it a variety of conditions, including expressions (logical or mathematical) or conditions based on factors related to the layout itself, examples of which are provided below. At 6502, the condition may be evaluated. If the condition is true, then one or more layout placement instructions may be executed at 6503. If the condition is false, then other layout placement instructions may be executed at 6504. While Figure 65 shows executing alternative layout placement instructions (e.g., "IF<condition=true> then<layout placement instruction 1> , else<layout placement instruction 2> "), the layout placement instruction can be executed only if the condition is true or false, otherwise the conditional statement is terminated (e.g., "IF<condition=true> then<layout placement instruction> , else continue" or "IF<condition=false> then<layout placement instruction> , else continue”).

[0262] In one embodiment, a conditional layout placement instruction determines whether a location is occupied. In some applications, a layout script can be used for multiple circuits of the same type (or family, e.g., the same functional circuit component with different parameters). For some parameters, a particular layout instance can occupy space on the layout. Thus, determining whether a particular location is occupied can advantageously indicate which circuit within the family is being generated. Thus, different layout instances and / or different locations can be specified based on whether a location is occupied, which can result in, for example, the execution of different layout placement instructions with different parameters for the same type of circuit configuration. For example, an exemplary layout placement instruction "placeTAP xy" can determine whether a layout instance exists at a particular location. If the location (x, y) is occupied, the instruction can execute the layout placement instruction following "placeTAP." Alternatively, if the location is unoccupied, the instruction can execute a different layout placement instruction (e.g., by skipping the line following "placeTAP"). The following conditional layout placement command instead places "cellname1" or "cellname2" in different locations based on whether position (x,y)=(10,10) is occupied: placeTAP 10 10 place cellname1 0 5.5 R0 place cellname2 4.9 5.5 R0

[0263] As mentioned above, "cellname1" can be used for a circuit with one parameter set (e.g., a circuit with high-voltage switches), and "cellname2" can be used for a circuit with a different parameter set (e.g., the same circuit with low-voltage switches). Because different circuits can have different layout spacing, different cells can be advantageously positioned in different locations.

[0264] Another exemplary conditional layout placement command can evaluate the attributes of a layout instance and execute different layout placement commands based on the result. For...

Claims

1. 1. A computer-implemented method for generating a circuit, comprising: receiving parameters specifying the circuit to be created; selecting predetermined sub-circuit schematics to be included in the circuit based on the parameters; determining connections between the predetermined partial circuit diagrams based on the parameters; generating a circuit specification for the circuit to be generated, the circuit specification specifying the sub-circuit schematics and connections between the predetermined sub-circuit schematics; and generating a layout script associated with the circuit to be generated; generating a circuit specification, selecting a predetermined partial circuit diagram specified in the circuit specification; connecting said predetermined sub-circuit diagrams to form said circuit diagram; converting the circuit diagram into a number of layout instances; and positioning the layout instance based on the layout script associated with the circuit to be generated to generate the circuit layout; converting the circuit specification into a circuit schematic and a circuit layout; 4. A computer-implemented method comprising:

2. The method of claim 1 , wherein the predetermined sub-circuit schematic comprises a predetermined analog sub-circuit schematic.

3. the parameters specify one or more functional circuit components; the one or more functional circuit components have corresponding predetermined subcircuit schematics; The method according to claim 1 .

4. generating one or more symbols corresponding to the one or more functional circuit components; the symbol encapsulates the selected predetermined subcircuit schematic; The method according to claim 3 .

5. The method of claim 1 , wherein the layout script comprises a plurality of layout placement instructions.

6. The method of claim 1 , wherein the layout script is configured to position layout instances from multiple circuit schematics.

7. The method of claim 6 , wherein the multiple circuit schematics are associated with a same functional circuit component.

8. 2. The method of claim 1, wherein the step of generating a circuit specification is performed on a first software system and the step of converting the circuit specification to a circuit schematic and a circuit layout is performed on a second software system.

9. The method of claim 8 , wherein the second software system is an electronic design automation software system.

10. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, receiving parameters specifying the circuit to be created; selecting predetermined sub-circuit schematics to be included in the circuit based on the parameters; determining connections between the predetermined partial circuit diagrams based on the parameters; generating a circuit specification for the circuit to be generated, the circuit specification specifying the sub-circuit schematics and connections between the predetermined sub-circuit schematics; and generating a layout script associated with the circuit to be generated; generating a circuit specification, selecting a predetermined partial circuit diagram specified in the circuit specification; connecting said predetermined sub-circuit diagrams to form said circuit diagram; converting the circuit diagram into a number of layout instances; and positioning the layout instance based on the layout script associated with the circuit to be generated to generate the circuit layout; converting the circuit specification into a circuit schematic and a circuit layout; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

11. When executed by a computer system, the computer system receiving parameters specifying the circuit to be generated; selecting a predetermined sub-circuit schematic to be included in the circuit based on the parameters; determining connections between the predetermined partial circuit diagrams based on the parameters; generating a circuit specification for the circuit to be generated that specifies the sub-circuit schematics and the connections between the predetermined sub-circuit schematics; and generating a layout script associated with the circuit to be generated; generating a circuit specification, Select a predetermined partial circuit diagram designated in the circuit specification; connecting the predetermined sub-circuit diagrams to form the circuit diagram; converting the circuit diagram into a number of layout instances; and positioning the layout instance based on the layout script associated with the circuit to be generated to generate the circuit layout; converting the circuit specification into a circuit schematic and a circuit layout; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

12. 1. A computer-implemented method for generating a circuit, comprising: receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; selecting, by the at least one software system, a plurality of sub-circuit schematics based on the circuit specification parameters; combining, by the at least one software system, the sub-circuit schematics to form a circuit schematic for the at least one functional circuit component; 4. A computer-implemented method comprising:

13. The method of claim 12 , wherein the at least one functional circuit component is an analog functional circuit component.

14. The method of claim 12 , wherein the sub-circuit schematic comprises an analog sub-circuit schematic.

15. The method of claim 12 , wherein the sub-circuit schematic comprises a predetermined analog sub-circuit schematic.

16. 16. The method of claim 15, wherein the selected plurality of sub-circuit schematics is a subset of a second plurality of predetermined analog sub-circuit schematics.

17. 20. The method of claim 16, wherein the second plurality of predetermined analog subcircuit schematics correspond to the at least one functional analog circuit component.

18. 17. The method of claim 16, wherein the plurality of sub-circuit schematics includes alternative sub-circuit schematics for implementing the same functionality using different circuits.

19. 13. The method of claim 12, wherein the sub-circuit schematic includes a plurality of analog pins having different electrical characteristics.

20. 20. The method of claim 19, wherein the different electrical properties are different voltage or current operating ranges.

21. 13. The method of claim 12, wherein the sub-circuit schematic includes a plurality of pins, and the combining step includes mapping the pins of the sub-circuit schematic.

22. 22. The method of claim 21, wherein one or more pins of the plurality of pins are analog pins.

23. The method of claim 21 , wherein the mapping is based on at least one pin map.

24. 24. The method of claim 23, wherein different pin maps specify connections between the plurality of sub-circuit schematic pins for different combinations of selected sub-circuit schematics.

25. 24. The method of claim 23, wherein the at least one pin map is based on the selected subcircuit schematic.

26. 24. The method of claim 23, wherein the pin map specifies connections between pins of the sub-circuit schematic.

27. 24. The method of claim 23, wherein the pin map specifies connections between pins of the sub-circuit schematic and inputs or outputs of the circuit schematic.

28. 22. The method of claim 21, wherein the connected pins have a predetermined compatibility.

29. 22. The method of claim 21, wherein mapping the pins comprises connecting the pins in the circuit schematic.

30. 22. The method of claim 21, wherein said mapping step is performed automatically by said at least one software system based on a plurality of predetermined rules.

31. 13. The method of claim 12, wherein different values ​​for the circuit specification parameters generate different analog circuit schematics having different characteristics for the at least one functional circuit component.

32. The method of claim 12 , wherein different sets of circuit specification parameters for different corresponding functional circuit components have different corresponding sets of predetermined sub-circuit schematic diagrams.

33. 33. The method of claim 32, wherein different values ​​for different sets of circuit specification parameters select different subsets of predefined sub-circuit schematics from one of a plurality of sets of predefined sub-circuit schematics corresponding to different functional circuit components.

34. The method of claim 12 , wherein the plurality of circuit specification parameters includes one or more of parameters specifying physical attributes or parameters specifying electrical attributes.

35. 13. The method of claim 12, further comprising generating a netlist specifying the selected subcircuit.

36. 36. The method of claim 35, wherein the netlist is a verilog file.

37. 13. The method of claim 12, wherein the sub-circuit diagrams are combined according to a rule set associated with the at least one functional circuit component to form the circuit diagram for the at least one functional circuit component.

38. The method of claim 12 , wherein different circuit specification parameters corresponding to different functional circuit components are processed using different association rule sets for combining different sets of sub-circuit schematic diagrams.

39. The method of claim 12 , wherein different functional circuit components have corresponding unique sets of predetermined sub-circuit schematics.

40. 40. The method of claim 39, wherein each unique set of predetermined sub-circuit schematics includes one or more unique predetermined analog sub-circuit schematics used only for the corresponding functional circuit component.

41. 40. The method of claim 39, wherein each unique set of predetermined sub-circuit schematics includes one or more predetermined analog sub-circuit schematics used for multiple corresponding functional circuit components.

42. The method of claim 12 , wherein the circuit specification parameters include variables and corresponding values.

43. 43. The method of claim 42, wherein the variables and the values ​​are received as text.

44. The method of claim 12 , wherein the circuit specification parameters include codes that specify characteristics of the circuit schematic.

45. 45. The method of claim 44, wherein different values ​​of the code select different sub-circuit schematics.

46. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; selecting, by the at least one software system, a plurality of sub-circuit schematics based on the circuit specification parameters; combining, by the at least one software system, the sub-circuit schematics to form a circuit schematic for the at least one functional circuit component; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

47. When executed by a computer system, the computer system receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; causing said at least one software system to select a plurality of sub-circuit schematics based on said circuit specification parameters; and combining, by said at least one software system, said sub-circuit schematics to form a circuit schematic for said at least one functional circuit component; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

48. 1. A system for generating a circuit, comprising: means for receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; means for selecting, by said at least one software system, a plurality of sub-circuit schematics based on said circuit specification parameters; means for combining, by said at least one software system, said sub-circuit schematics to form a circuit schematic for said at least one functional circuit component; Including, the system.

49. 1. A computer-implemented method for generating a circuit, comprising: receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; combining, with the at least one software system, a plurality of sub-circuit layouts based on the circuit specification parameters to form a circuit layout for the at least one functional circuit component; 4. A computer-implemented method comprising:

50. 50. The method of claim 49, wherein the sub-circuit layout is an analog sub-circuit layout.

51. 50. The method of claim 49, wherein the sub-circuit layout is a predetermined analog sub-circuit layout.

52. 52. The method of claim 51, wherein a subset of the plurality of predetermined analog sub-circuit layouts corresponds to the at least one functional analog circuit component.

53. 50. The method of claim 49, wherein the plurality of sub-circuit layouts include alternative sub-circuit layouts for implementing the same function with different circuits.

54. 50. The method of claim 49, wherein different values ​​for the circuit specification parameters generate different analog circuit layouts having different characteristics for the at least one functional circuit component.

55. 50. The method of claim 49, wherein different circuit specification parameter sets for different corresponding functional circuit components have different corresponding predetermined sub-circuit layout sets.

56. 56. The method of claim 55, wherein different values ​​for each circuit specification parameter set combine different subsets of predefined sub-circuit layouts from one of a plurality of predefined sub-circuit layout sets corresponding to different functional circuit components.

57. 50. The method of claim 49, wherein the plurality of circuit specification parameters includes one or more of parameters specifying physical attributes or parameters specifying electrical attributes.

58. 50. The method of claim 49, wherein the circuit specification parameters include variables and corresponding values.

59. 60. The method of claim 58, wherein the circuit specification parameters include variables and values ​​are received as text.

60. 50. The method of claim 49, wherein the circuit specification parameters include codes that specify characteristics of the circuit layout.

61. 61. The method of claim 60, wherein different values ​​of the code select different sub-circuit layouts.

62. 50. The method of claim 49, wherein the combining is based on a plurality of layout placement instructions for placing the sub-circuit layouts into the circuit layout.

63. 63. The method of claim 62, wherein at least one of the sub-circuit layouts has a first height and a first width, and at least one of the other sub-circuit layouts has a second height different from the first height and a second width different from the second width.

64. 63. The method of claim 62, wherein the layout placement instructions are predetermined.

65. 63. The method of claim 62, wherein the layout placement instructions access placement data from an external data record.

66. 63. The method of claim 62, wherein the layout placement instructions are predetermined in an external data record.

67. 63. The method of claim 62, wherein the layout placement instructions place the sub-circuit layout according to an x,y coordinate system.

68. 63. The method of claim 62, wherein different circuit layouts can be formed from different sub-circuit layout sets associated with different corresponding layout placement instructions.

69. 63. The method of claim 62, wherein the plurality of layout placement instructions includes one or more layout placement instructions for placing one or more sub-circuit layouts at particular coordinates.

70. 63. The method of claim 62, wherein the plurality of layout placement instructions includes one or more layout placement instructions that rotate one or more sub-circuit layouts.

71. the plurality of layout arrangement instructions are in a sequence; a particular sub-circuit layout is serially placed based on said sequence of said layout placement instructions; 63. The method of claim 62.

72. 63. The method of claim 62, wherein the plurality of layout placement instructions comprises executable instructions that access data specifying the placement of the sub-circuit layout.

73. 73. The method of claim 72, wherein the data specifies one or more layout placement instructions to be executed for each sub-circuit layout.

74. 73. The method of claim 72, wherein the data specifies x-axis and y-axis coordinates for placing a plurality of the sub-circuit layouts.

75. 73. The method of claim 72, wherein the data specifies a rotation for one or more of the sub-circuit layouts.

76. different values ​​for the circuit specification parameters combine different sub-circuit layouts with corresponding layout placement instructions; The particular layout placement instructions executed are specific to the particular analog circuit layout generated from the particular circuit specification parameter values; 63. The method of claim 62.

77. executing one of a plurality of sets of layout placement instructions based on a particular combination of sub-circuit layouts to generate the circuit layout; Different combinations of sub-circuit layouts have corresponding different layout placement instructions; 63. The method of claim 62.

78. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; combining, with at least one software system, a plurality of sub-circuit layouts based on the circuit specification parameters to form a circuit layout for the at least one functional circuit component; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

79. When executed by a computer system, the computer system receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; and combining, with at least one software system, a plurality of sub-circuit layouts based on the circuit specification parameters to form a circuit layout for the at least one functional circuit component. A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

80. 1. A system for generating a circuit, comprising: means for receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; means for combining, by at least one software system, a plurality of sub-circuit layouts based on the circuit specification parameters to form a circuit layout for the at least one functional circuit component; Including, the system.

81. 1. A computer-implemented method for generating a circuit, comprising: generating a first model of the circuit to be generated; generating circuit specification parameters corresponding to the first model; selecting a plurality of sub-circuit schematics based on the circuit specification parameters; combining the sub-circuit schematics to form a circuit schematic for the circuit to be generated; Including, the combined partial circuit diagram forms a transistor level model corresponding to the first model. , computer-implemented method.

82. 82. The method of claim 81 , wherein the first model is a behavioral model.

83. 82. The method of claim 81, wherein a plurality of behavioral level simulations of the first model substantially match a corresponding plurality of transistor level simulations for the transistor level model.

84. the first model is configurable based on the circuit specification parameters to generate a plurality of behaviors for the first model; a simulation of the first model and the transistor-level model substantially matches when the first model and the transistor-level model have the same parameters; 82. The method of claim 81 .

85. 82. The method of claim 81, wherein a plurality of behavioral level simulations of the first model are matched to a corresponding plurality of transistor level simulations for the transistor level model.

86. 82. The method of claim 81, wherein the sub-circuit schematic comprises a predetermined analog sub-circuit schematic.

87. converting the circuit schematic into a plurality of layout instances; positioning the layout instances based on a layout script to generate a circuit layout; 82. The method of claim 81, further comprising:

88. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, generating a first model of the circuit to be generated; generating circuit specification parameters corresponding to the first model; selecting a plurality of sub-circuit schematics based on the circuit specification parameters; and combining the sub-circuit schematics to form a circuit schematic for the circuit to be created; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising: Including, the combined partial circuit diagram forms a transistor level model corresponding to the first model. , computer systems.

89. When executed by a computer system, the computer system generating a first model of a circuit to be generated; generating circuit specification parameters corresponding to the first model; selecting a plurality of sub-circuit schematics based on the circuit specification parameters; combining the sub-circuit schematics to form a circuit schematic for the circuit to be generated; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon for causing a the combined partial circuit diagram forms a transistor level model corresponding to the first model. , a non-transitory computer-readable storage medium.

90. 1. A system for generating a circuit, comprising: means for generating a first model of a circuit to be generated; means for generating circuit specification parameters corresponding to the first model; means for selecting a plurality of sub-circuit schematics based on the circuit specification parameters; means for combining the sub-circuit schematics to form a circuit schematic for the circuit to be generated; Including, the combined partial circuit diagram forms a transistor level model corresponding to the first model. ,system.

91. 1. A computer-implemented method for generating a circuit, comprising: receiving information specifying a circuit to be created; selecting one or more pin lists corresponding to one or more sub-circuit diagrams based on the information, each pin list including sub-circuit diagram pins for a corresponding sub-circuit diagram; selecting a subset of a plurality of predetermined pins for at least one symbology based on said information; establishing connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; a partial circuit diagram pin from the one or more pin lists corresponding to one or more partial circuit diagrams; the subset of the plurality of predetermined pins for the at least one symbol; and the connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; generating a circuit specification including:

4. A computer-implemented method comprising:

92. 92. The method of claim 91, further comprising processing the circuit specification in an EDA tool to generate a circuit schematic diagram.

93. 92. The method of claim 91, wherein the pin list and symbol correspond to a first functional circuit component.

94. 94. The method of claim 93, wherein different functional circuit components have different associated subcircuit schematic pin lists and predetermined pins to functional circuit component symbols.

95. 92. The method of claim 91, further comprising retrieving a layout script based on the information, the layout script configured to automatically position a layout instance for a circuit generated from the circuit specification.

96. 92. The method of claim 91, wherein the information includes a parameter.

97. deriving parameter limits; comparing said parameter to said parameter limits to validate said parameter; 97. The method of claim 96, further comprising:

98. determining component values; encoding the component values ​​within an identifier associated with a plurality of component symbols; Further comprising: the circuit specification further includes the plurality of component symbols; 92. The method of claim 91.

99. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, receiving information specifying a circuit to be created; selecting one or more pin lists corresponding to one or more sub-circuit diagrams based on the information, each pin list including sub-circuit diagram pins for a corresponding sub-circuit diagram; selecting a subset of a plurality of predetermined pins for at least one symbol based on said information; establishing connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; and a partial circuit diagram pin from the one or more pin lists corresponding to one or more partial circuit diagrams; the subset of the plurality of predetermined pins for the at least one symbol; and the connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; generating a circuit specification including: A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

100. When executed by a computer system, the computer system receiving information specifying a circuit to be generated; selecting one or more pin lists corresponding to one or more sub-circuit diagrams based on the information, each pin list including sub-circuit diagram pins for a corresponding sub-circuit diagram; selecting a subset of a plurality of predetermined pins for at least one symbology based on the information; establishing connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; a partial circuit diagram pin from the one or more pin lists corresponding to one or more partial circuit diagrams; the subset of the plurality of predetermined pins for the at least one symbol; and the connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; generating a circuit specification including: A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

101. 1. A system for generating a circuit, comprising: means for receiving information specifying a circuit to be generated; means for selecting, based on the information, one or more pin lists corresponding to one or more sub-circuit diagrams, each pin list including sub-circuit diagram pins for a corresponding sub-circuit diagram; means for selecting a subset of a plurality of predetermined pins for at least one symbol based on said information; means for establishing connections between the sub-circuit diagram pins and the subset of the plurality of predetermined pins for the at least one symbol; a partial circuit diagram pin from the one or more pin lists corresponding to one or more partial circuit diagrams; the subset of the plurality of predetermined pins for the at least one symbol; and the connections between the sub-circuit schematic pins and the subset of the plurality of predetermined pins for the at least one symbol; means for generating a circuit specification including: Including, the system.

102. 1. A computer-implemented method for generating circuit components, comprising: receiving a total attribute value of a component to be created; determining a second attribute value for the to-be-created entity based at least on the total attribute value; determining a number N of at least one of the components having the second attribute value that will be combined to form the component having the total attribute value; generating a transistor level schematic diagram including a plurality of components configured using the second attribute values; generating a layout including N layout instances corresponding to the components configured to generate the total attribute value; 4. A computer-implemented method comprising:

103. 103. The method of claim 102, wherein the component to be generated is one of a transistor, a resistor, or a capacitor.

104. generating a circuit specification that specifies a configuration of the N components to generate the total attribute value; the transistor level schematic is generated based on the circuit specifications; The method of claim 102.

105. The method further includes receiving at least one layout parameter; the second attribute value for the to-be-created component is determined based on the at least one layout parameter. The method of claim 102.

106. 106. The method of claim 105, wherein layout parameters specify a length along at least one dimension of the components to be generated.

107. 106. The method of claim 105, wherein the layout parameters specify resistor layout segment lengths.

108. 106. The method of claim 105, wherein the layout parameters specify a predetermined maximum length along a first dimension of the unit capacitor.

109. 103. The method of claim 102, wherein the total attribute value is a total resistance for a resistor to be created.

110. 103. The method of claim 102, wherein the total attribute value is a total capacitance for a capacitor to be created.

111. 103. The method of claim 102, wherein the total attribute value is a total gate width determined based on an on-resistance for a transistor to be created.

112. 1. A computer system for generating circuit components, comprising: one or more processors; When executed by a computer system, receiving a total attribute value of the components to be generated; determining a second attribute value for the to-be-created entity based at least on the total attribute value; determining a number N of at least one of said components having said second attribute value that will be combined to form said component having said total attribute value; generating a transistor level schematic including a plurality of components configured using the second attribute values; and generating a layout including N layout instances corresponding to the components configured to generate the total attribute value; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

113. When executed by a computer system, the computer system receiving a total attribute value of a component to be generated; determining a second attribute value for the to-be-created entity based at least on the total attribute value; determining a number N of at least one of the components having the second attribute value that will be combined to form the component having the total attribute value; generating a transistor level schematic diagram including a plurality of components configured using the second attribute values; generating a layout including N layout instances corresponding to the components configured to generate the total attribute value; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

114. 1. A system for generating circuit components, comprising: means for receiving a total attribute value of the components to be generated; means for determining a second attribute value for the to-be-created entity based on at least the total attribute value; means for determining a number N of at least one of the components having the second attribute value that will be combined to form the component having the total attribute value; means for generating a transistor level schematic including a plurality of components configured using the second attribute values; means for generating a layout including N layout instances corresponding to the components configured to generate the total attribute value; Including, the system.

115. 1. A computer-implemented method for generating a circuit, comprising: receiving information specifying analog circuitry to be created; deriving layout parameters based at least in part on said information; determining attributes of the to-be-created analog circuit components based on the information and the layout parameters; generating a transistor level schematic diagram of the analog circuit including one or more of the analog circuit components configured using the attributes; generating a layout from the transistor level schematic, the layout including a plurality of layout instances corresponding to the one or more analog circuit components, each layout instance being automatically positioned in the layout by a layout script based on the attributes of the analog circuit components; 4. A computer-implemented method comprising:

116. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, receiving information specifying analog circuit components to be created; deriving layout parameters based at least in part on said information; determining attributes of the to-be-created analog circuit components based on the information and the layout parameters; generating a transistor level schematic diagram of the analog circuit including one or more of the analog circuit components configured using the attributes; and generating a layout from the transistor level schematic, the layout including a plurality of layout instances corresponding to the one or more analog circuit components, each layout instance being automatically positioned in the layout by a layout script based on the attributes of the analog circuit components; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

117. When executed by a computer system, the computer system receiving information specifying analog circuitry to be created; deriving layout parameters based at least in part on said information; determining attributes of the to-be-created analog circuit components based on the information and the layout parameters; generating a transistor level schematic diagram of the analog circuit including one or more of the analog circuit components configured using the attributes; generating a layout from the transistor-level schematic, the layout including a plurality of layout instances corresponding to the one or more analog circuit components, each layout instance being automatically positioned in the layout by a layout script based on the attributes of the analog circuit components; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

118. 1. A system for generating a circuit, comprising: means for receiving information specifying analog circuitry to be created; means for deriving layout parameters based at least in part on said information; means for determining attributes of the analog circuit components to be generated based on the information and the layout parameters; means for generating a transistor level schematic diagram of the analog circuit including one or more of the analog circuit components configured using the attributes; means for generating a layout from the transistor level schematic, the layout including a plurality of layout instances corresponding to the one or more analog circuit components, each layout instance being automatically positioned in the layout by a layout script based on the attributes of the analog circuit components; Including, the system.

119. 1. A computer-implemented method for generating an electronic component schematic diagram, comprising: receiving information specifying an electronic circuit to be created; determining a component value for at least one component of the electronic circuit based on the information; generating a plurality of component symbols; encoding said component values ​​in identifiers associated with each of said component symbols; establishing connections between said constituent symbols; generating a circuit specification for configuring said component symbols in series or in parallel; 4. A computer-implemented method comprising:

120. 120. The method of claim 119, wherein the identifier comprises a symbolic name.

121. the component is a resistor; The component values ​​include resistance. The method of claim 119.

122. the component is a capacitor; The component values ​​include capacitance. The method of claim 119.

123. the component is a transistor; the component values ​​include a gate width; The method of claim 119.

124. 124. The method of claim 123, wherein the component values ​​further include a number of fingers.

125. 1. A computer system for generating electronic component schematics, comprising: one or more processors; When executed by a computer system, receiving information specifying an electronic circuit to be created; determining a component value for at least one component of the electronic circuit based on the information; generating a plurality of component symbols; encoding said component values ​​in identifiers associated with each of said component symbols; establishing connections between said constituent symbols; and generating a circuit specification for configuring said component symbols in series or in parallel; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

126. When executed by a computer system, the computer system receiving information specifying an electronic circuit to be generated; determining a component value for at least one component of the electronic circuit based on the information; generating a plurality of component symbols; encoding said component values ​​in identifiers associated with each of said component symbols; establishing connections between said constituent symbols; and generating a circuit specification for configuring said component symbols in series or in parallel; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

127. 1. A system for generating electronic component schematics, comprising: means for receiving information specifying an electronic circuit to be generated; means for determining a component value for at least one component of the electronic circuit based on the information; means for generating a plurality of component symbols; means for encoding said component values ​​within an identifier associated with each of said component symbols; means for establishing connections between said constituent symbols; means for generating a circuit specification for configuring said component symbols in series or in parallel; Including, the system.

128. 1. A computer-implemented method for generating an electronic component schematic diagram, comprising: receiving a circuit specification specifying one or more components including one or more corresponding identifiers; generating one or more schematic symbols for the one or more components, the one or more schematic symbols being associated with the one or more corresponding identifiers; reading the identifier associated with the one or more symbols; inserting a schematic representation for the one or more components into a corresponding symbol, wherein one or more attributes of the schematic representation for the component are set based on the identifier associated with the symbol; 4. A computer-implemented method comprising:

129. 129. The method of claim 128, wherein the identifier encodes an attribute value.

130. 129. The method of claim 128, wherein the identifier comprises a symbolic name.

131. 131. The method of claim 130, wherein the symbolic name encodes one or more attribute values.

132. the component is a resistor; the one or more attributes include resistance; The method of claim 128.

133. the component is a capacitor; the one or more attributes include capacitance; The method of claim 128.

134. the component is a transistor; the one or more attributes include a gate width; The method of claim 128.

135. 135. The method of claim 134, wherein the one or more attributes further include a number of fingers.

136. 1. A computer system for generating electronic component schematics, comprising: one or more processors; When executed by a computer system, receiving a circuit specification specifying one or more components including one or more corresponding identifiers; generating one or more schematic symbols for the one or more components, the one or more schematic symbols being associated with the one or more corresponding identifiers; reading the identifier associated with the one or more symbols; and inserting a schematic representation for the one or more components into a corresponding symbol, wherein one or more attributes of the schematic representation for the component are set based on the identifier associated with the symbol; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

137. When executed by a computer system, the computer system receiving a circuit specification specifying one or more components including one or more corresponding identifiers; generating one or more schematic symbols for the one or more components, the one or more schematic symbols being associated with the one or more corresponding identifiers; reading the identifier associated with the one or more symbols; and inserting into a corresponding symbol a schematic representation for the one or more components, wherein one or more attributes of the schematic representation for the one or more components are set based on the identifier associated with the symbol; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

138. 1. A system for generating electronic component schematics, comprising: means for receiving a circuit specification specifying one or more components including one or more corresponding identifiers; means for generating one or more schematic symbols for the one or more components, the one or more schematic symbols being associated with the one or more corresponding identifiers; means for reading the identifier associated with the one or more symbols; means for inserting a schematic representation for the one or more components into a corresponding symbol, the inserting means setting one or more attributes of the schematic representation for the component based on the identifier associated with the symbol; Including, the system.

139. 1. A computer-implemented method for generating a resistor, comprising the steps of: receiving a first resistor value; converting the resistor values ​​into a plurality of resistor layout segments; automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value; 4. A computer-implemented method comprising:

140. 140. The method of claim 139, wherein a first resistor layout segment is placed in an initial position and another resistor layout segment is placed in a position offset from the initial position.

141. 141. The method of claim 140, wherein the offset is based on a width of each resistor layout segment.

142. 142. The method of claim 141, wherein the offset is further based on a predetermined separation between adjacent layout segments.

143. 143. The method of claim 142, wherein the predetermined separation is based on design rule check (DRC) values.

144. 141. The method of claim 140, wherein the resistor layout segments are arranged in parallel along a length of each resistor layout segment.

145. 141. The method of claim 140, wherein resistor layout segments are rotated by an amount specified in the one or more layout placement instructions.

146. 141. The method of claim 140, wherein resistor layout segments are arranged consecutively along an axis according to a polarity specified in the one or more layout placement instructions.

147. Each resistor layout segment has a unique identifier; the method further comprising: selecting the resistor layout segments based on the unique identifier; and sequentially arranging each resistor layout segment. The method of claim 139.

148. 140. The method of claim 139, wherein a first portion of the resistor layout segments are configured in series and a second portion of the resistor layout segments are configured in parallel.

149. 140. The method of claim 139, wherein at least a first plurality of the resistor layout segments have the same length and width.

150. 1. A computer system for generating a resistor, comprising: one or more processors; When executed by a computer system, receiving a first resistor value; converting the resistor values ​​into a plurality of resistor layout segments; and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

151. When executed by a computer system, the computer system receiving a first resistor value; Transforming the resistor values ​​into a plurality of resistor layout segments; and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value. A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

152. 1. A system for generating a resistor, comprising: means for receiving a first resistor value; means for converting the resistor values ​​into a plurality of resistor layout segments; means for automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value; Including, the system.

153. 1. A computer-implemented method for generating a resistor, comprising the steps of: receiving a first resistor value; To approximately generate the first resistor value: a first number designating a first plurality of resistor segments to be configured in series; and a second number designating a second plurality of the resistor segments to be configured in parallel; determining one or both of: generating a circuit specification for configuring the first number of resistor segments in series and / or the second number of resistor segments in parallel; 4. A computer-implemented method comprising:

154. 154. The method of claim 153, wherein the first resistor value varies over a range of values.

155. 154. The method of claim 153, wherein the first resistor value is received as a parameter having an associated resistor component type.

156. receiving at least one predetermined physical dimension for the resistor segments; the first and second pluralities of resistor segments each having the at least one predetermined physical dimension; determining the first number of resistor segments to be configured in series and the second number of resistor segments to be configured in parallel is based on the at least one predetermined physical dimension. The method of claim 153.

157. 157. The method of claim 156, wherein the at least one predetermined physical dimension comprises a predetermined resistor segment length.

158. 158. The method of claim 157, wherein the at least one predetermined physical dimension comprises a predetermined resistor segment width.

159. 157. The method of claim 156, wherein the at least one predetermined physical dimension for the resistor segments is associated with the first resistor value.

160. 154. The method of claim 153, wherein different resistors having different resistor values ​​have different corresponding predetermined resistor segment lengths.

161. receiving a resistivity associated with the first resistor value; determining the first number of resistor segments to be configured in series and the second number of resistor segments to be configured in parallel is based on the resistivity. The method of claim 153.

162. 154. The method of claim 153, wherein the first resistor value is specified by a user.

163. receiving one or more parameters; the first resistor value is determined based on the parameter. The method of claim 153.

164. 154. The method of claim 153, wherein the circuit specification specifies a plurality of components corresponding to the plurality of resistor segments and connections between the plurality of components.

165. 165. The method of claim 164, wherein the circuit specification is a netlist.

166. 154. The method of claim 153, further comprising the step of transmitting the circuit specification from a first software system to a second software system that generates a schematic diagram based on the circuit specification.

167. 167. The method of claim 166, further comprising receiving, by the second software system, predetermined lengths and predetermined widths for the plurality of resistor segments encoded within identifiers for components corresponding to the resistor segments in the circuit specification.

168. 168. The method of claim 167, wherein the identifier is a symbolic name.

169. 168. The method of claim 167, wherein the identifier further encodes a resistor type.

170. 167. The method of claim 166, further comprising receiving, by the second software system, predetermined lengths and predetermined widths for the plurality of resistor segments from a first storage location.

171. 154. The method of claim 153, further comprising generating a schematic diagram based on the circuit specification, the schematic diagram including schematic symbols for the first and second numbers of resistor segments.

172. the wiring diagram symbol is an empty wiring diagram symbol including a plurality of pins, the method further comprising the step of automatically inserting resistors into each of the schematic symbols and connecting terminals of the resistors with the pins of the schematic symbols. The method of claim 171.

173. 172. The method of claim 171, further comprising mapping a schematic symbol name to an attribute of the resistor.

174. 154. The method of claim 153, further comprising: generating a layout including a plurality of polygons for the first number of resistor segments in series and the second number of resistor segments in parallel.

175. 175. The method of claim 174, further comprising executing a plurality of predetermined layout placement instructions to position the polygon in the layout.

176. 1. A computer system for generating a resistor, comprising: one or more processors; When executed by a computer system, receiving a first resistor value; To approximately generate the first resistor value: a first number designating a first plurality of resistor segments to be configured in series; and a second number designating a second plurality of the resistor segments to be configured in parallel; determining one or both of generating a circuit specification for configuring the first number of resistor segments in series and / or the second number of resistor segments in parallel; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

177. When executed by a computer system, the computer system receiving a first resistor value; To approximately generate the first resistor value: a first number designating a first plurality of resistor segments to be configured in series; and a second number designating a second plurality of the resistor segments to be configured in parallel; and generating circuit specifications for configuring the first number of resistor segments in series and / or the second number of resistor segments in parallel; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

178. 1. A system for generating a resistor, comprising: means for receiving a first resistor value; To approximately generate the first resistor value: a first number designating a first plurality of resistor segments to be configured in series; and a second number designating a second plurality of the resistor segments to be configured in parallel; and means for determining one or both of means for generating a circuit specification for configuring the first number of resistor segments in series and / or the second number of resistor segments in parallel; Including, the system.

179. 1. A computer-implemented method for generating a resistor, comprising the steps of: receiving a resistor value; generating a circuit specification that specifies a configuration of a plurality of components; generating, based on the circuit specification, a plurality of schematic symbols corresponding to the plurality of components coupled together based on the circuit specification, the plurality of schematic symbols being generated without resistor segments; automatically inserting resistor segments into each of said schematic symbols and connecting terminals of said resistors with pins of said schematic symbols; Including, the plurality of components and inserted resistor segments form a wiring diagram for a resistor network having the resistor values. , computer-implemented method.

180. 180. The method of claim 179, wherein the symbol is generated as an empty symbol in response to the circuit specification.

181. 180. The method of claim 179, further comprising the step of assigning attributes to the resistors.

182. 182. The method of claim 181, wherein attributes for the resistors are encoded within the circuit specification.

183. 182. The method of claim 181, wherein attributes for the resistor are retrieved from a storage location.

184. 180. The method of claim 179, wherein the circuit specification is generated by a first software system and the wiring diagram is generated by a second software system.

185. 185. The method of claim 184, wherein the second software system is an electronic design automation software system.

186. 1. A computer system for generating a resistor, comprising: one or more processors; When executed by a computer system, receiving a resistor value; generating a circuit specification that specifies a configuration of a plurality of components; generating, based on the circuit specification, a plurality of schematic symbols corresponding to the plurality of components coupled together based on the circuit specification, the plurality of schematic symbols being generated without resistor segments; and automatically inserting resistor segments into each of said schematic symbols and connecting terminals of said resistors with pins of said schematic symbols; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising: Including, the plurality of components and inserted resistor segments form a wiring diagram for a resistor network having the resistor values. , computer systems.

187. When executed by a computer system, the computer system Receive resistor values, generating a circuit specification that specifies a configuration of a plurality of components; generating, based on the circuit specification, a plurality of schematic symbols corresponding to the plurality of components coupled together based on the circuit specification, the plurality of schematic symbols being generated without resistor segments; automatically inserting resistor segments into each of said schematic symbols and connecting terminals of said resistors with pins of said schematic symbols; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon for causing a the plurality of components and inserted resistor segments form a wiring diagram for a resistor network having the resistor values. , a non-transitory computer-readable storage medium.

188. 1. A system for generating a resistor, comprising: means for receiving a resistor value; means for generating a circuit specification that specifies a configuration of a plurality of components; means for generating, based on the circuit specification, a plurality of wiring diagram symbols corresponding to the plurality of components coupled together based on the circuit specification, the plurality of wiring diagram symbols being generated without resistor segments; means for automatically inserting resistor segments into each of said schematic symbols and connecting terminals of said resistors with pins of said schematic symbols; Including, the plurality of components and inserted resistor segments form a wiring diagram for a resistor network having the resistor values. ,system.

189. 1. A computer-implemented method for generating a resistor, comprising the steps of: receiving a first resistor value; generating a circuit specification specifying a configuration of a plurality of components corresponding to resistor segments having at least one predetermined physical dimension; generating a schematic diagram based on the circuit specification, the schematic diagram including resistor segments corresponding to the plurality of components coupled together based on the circuit specification to generate the first resistor value; generating a layout based on the schematic diagram, the layout including a plurality of polygons corresponding to the resistor segments, the plurality of polygons being automatically positioned in the layout based on the at least one predetermined physical dimension of the resistor segments; 4. A computer-implemented method comprising:

190. 1. A computer system for generating a resistor, comprising: one or more processors; When executed by a computer system, receiving a first resistor value; generating a circuit specification specifying a configuration of a plurality of components corresponding to resistor segments having at least one predetermined physical dimension; generating, based on the circuit specification, a schematic diagram including the resistor segments corresponding to the plurality of components coupled together based on the circuit specification to generate the first resistor value; generating a layout based on the schematic diagram including a plurality of polygons corresponding to the resistor segments, the plurality of polygons being automatically positioned in the layout based on the at least one predetermined physical dimension of the resistor segments; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

191. When executed by a computer system, the computer system Receiving a first resistor value; generating a circuit specification specifying a configuration of a plurality of components corresponding to resistor segments having at least one predetermined physical dimension; generating a wiring diagram based on the circuit specification, the wiring diagram including resistor segments corresponding to the plurality of components coupled together based on the circuit specification to generate the first resistor value; generating a layout based on the schematic, the layout including a plurality of polygons corresponding to the resistor segments, the plurality of polygons being automatically positioned in the layout based on the at least one predetermined physical dimension of the resistor segments; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

192. 1. A system for generating a resistor, comprising: means for receiving a first resistor value; means for generating a circuit specification that specifies a configuration of a plurality of components corresponding to resistor segments having at least one predetermined physical dimension; means for generating, based on the circuit specification, a wiring diagram including the resistor segments corresponding to the plurality of components coupled together based on the circuit specification to generate the first resistor value; means for generating a layout based on the schematic, the layout including a plurality of polygons corresponding to the resistor segments, the plurality of polygons being automatically positioned in the layout based on the at least one predetermined physical dimension of the resistor segments; Including, the system.

193. 1. A computer-implemented method for generating a capacitor, comprising the steps of: receiving a total capacitance for a capacitor to be created; determining a number N of unit capacitors having unit capacitances that will be combined to form the total capacitance; generating a transistor level schematic including N unit capacitor schematics having the unit capacitance, the N unit capacitor schematics being configured to generate the total capacitance; generating a layout including N capacitor layout elements configured to generate the capacitor; 4. A computer-implemented method comprising:

194. 200. The method of claim 193, wherein the total capacitance is generated based on information specifying a circuit to be generated.

195. 200. The method of claim 194, wherein the total capacitance is generated based on a predetermined circuit model for the circuit to be generated.

196. 200. The method of claim 193, wherein the total capacitance is received as a parameter corresponding to a capacitor functional circuit component.

197. comparing the total capacitance to a predetermined maximum capacitance; The N unit capacitor wiring diagrams are configured in parallel when the total capacitance is greater than the predetermined maximum capacitance. The method of claim 193.

198. comparing the total capacitance to a predetermined minimum capacitance; The N unit capacitors are configured in series when the total capacitance is less than the predetermined minimum capacitance. The method of claim 193.

199. 200. The method of claim 193, wherein the number N of unit capacitors is an integer greater than or equal to one (1).

200. configuring a first length corresponding to a first dimension of the N unit capacitors to be less than or equal to a predetermined maximum length along the first dimension; determining a second length corresponding to a second dimension of the N unit capacitors based on at least the unit capacitance and the first length; 194. The method of claim 193, further comprising:

201. 201. The method of claim 200, wherein the first length is set to the predetermined maximum length along the first dimension.

202. 201. The method of claim 200, wherein the first length and the second length are configured to produce a predetermined aspect ratio of the first length and the second length.

203. 201. The method of claim 200, further comprising the step of iteratively adjusting the first length to produce an adjusted second length until an aspect ratio of the first length and the second length satisfies a predetermined aspect ratio.

204. 204. The method of claim 203, wherein the first length is initially the predetermined maximum length, and the first length is iteratively shortened.

205. 201. The method of claim 200, further comprising generating a circuit specification including N components corresponding to the N unit capacitors.

206. 206. The method of claim 205, wherein the circuit specification is a netlist.

207. 206. The method of claim 205, wherein one or more attributes of the N unit capacitors are encoded within the circuit specification.

208. 201. The method of claim 200, wherein the N unit capacitor schematics have a first attribute set to the first length and a second attribute set to the second length.

209. 201. The method of claim 200, wherein the N capacitor layout elements comprise a polygon having a first dimension equal to the first length and a second dimension equal to the second length.

210. The step of generating a transistor level schematic diagram comprises: generating N circuit diagram symbols; automatically inserting a capacitor symbol component into each of said N schematic symbols; Including, The method of claim 193.

211. 1. A computer system for generating a capacitor, comprising: one or more processors; When executed by a computer system, receiving a total capacitance for a capacitor to be created; determining a number N of unit capacitors having unit capacitances that will be combined to form the total capacitance; generating a transistor level schematic including N unit capacitor schematics configured to have the unit capacitances to generate the total capacitance; and generating a layout including N capacitor layout elements configured to generate the capacitor; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

212. When executed by a computer system, the computer system receiving a total capacitance for a capacitor to be created; determining a number N of unit capacitors having unit capacitances that will be combined to form the total capacitance; generating a transistor level schematic including N unit capacitor schematics configured to have the unit capacitances to generate the total capacitance; generating a layout including N capacitor layout elements configured to generate the capacitor; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

213. 1. A system for generating a capacitor, comprising: means for receiving a total capacitance for the capacitor to be created; means for determining a number N of unit capacitors having unit capacitances that will be combined to form said total capacitance; means for generating a transistor level schematic including N unit capacitor schematics configured to have the unit capacitances to generate the total capacitance; means for generating a layout including N capacitor layout elements configured to generate the capacitor; Including, the system.

214. 1. A computer-implemented method for generating a resistor divider, comprising the steps of: receiving parameters specifying a resistor divider to be generated; determining a plurality of resistor values ​​corresponding to resistors between one or more output taps of the resistor divider; for each resistor value, determining a number of resistor segments to generate each of the plurality of resistor values; generating a circuit specification for configuring each of the plurality of resistor segments to form the plurality of resistor values; generating a transistor level schematic including the plurality of resistor segments to generate the resistor divider; 4. A computer-implemented method comprising:

215. 215. The method of claim 214, wherein determining the plurality of resistor segments includes determining at least one first number designating a first plurality of ones of the resistor segments to be configured in series.

216. 215. The method of claim 214, wherein determining the plurality of resistor segments includes determining at least a first number designating a first plurality of ones of the resistor segments to be configured in parallel.

217. 215. The method of claim 214, wherein determining the plurality of resistor segments includes determining at least one first number designating a first plurality of ones of the resistor segments to be configured in series and at least one second number designating a second plurality of ones of the resistor segments to be configured in parallel.

218. the parameter specifies the total resistance of the resistor divider; the plurality of resistor values ​​are determined based on the total resistance of the resistor divider. The method of claim 214.

219. The parameters specify one or more output taps; the plurality of resistor values ​​being equal to the number of output taps plus one (1); The method of claim 214.

220. The parameters specify the voltage at each output tap; the plurality of resistor values ​​are determined based on a number of output taps and the voltage at each output tap. The method of claim 219.

221. the parameters specify the voltage at each output tap as one or more percentages; the plurality of resistor values ​​are determined based on a number of output taps and a percentage difference across two of the input, the plurality of output taps, and the lower portion. The method of claim 219.

222. The parameter specifies enable, the method further comprising specifying one or more sub-circuit schematics within the circuit specification; the specified subcircuit schematic is configured to receive an input for enabling or disabling the resistor divider; The method of claim 214.

223. 223. The method of claim 222, wherein the sub-circuit schematic includes a switch.

224. 224. The method of claim 223, wherein the switch is coupled between an input of the resistor divider and one or more terminals of an upper resistor segment of the resistor divider.

225. 224. The method of claim 223, wherein the switch is coupled between a reference input of the resistor divider and one or more terminals of a lower resistor segment of the resistor divider.

226. 224. The method of claim 223, wherein the switch is coupled between an output tap of the resistive divider and one or more terminals of a middle resistor segment of the resistive divider.

227. 1. A computer system for generating a resistor divider, comprising: one or more processors; When executed by a computer system, receiving parameters specifying a resistor divider to be generated; determining a plurality of resistor values ​​corresponding to resistors between one or more output taps of the resistor divider; for each resistor value, determining a plurality of resistor segments to generate each of said plurality of resistor values; generating a circuit specification for configuring each of the plurality of resistor segments to form the plurality of resistor values; and generating a transistor level schematic including the plurality of resistor segments to generate the resistor divider; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

228. When executed by a computer system, the computer system receiving parameters specifying a resistor divider to be generated; determining a plurality of resistor values ​​corresponding to resistors between one or more output taps of the resistor divider; for each resistor value, determining a number of resistor segments to generate each of the plurality of resistor values; generating a circuit specification for configuring each of the plurality of resistor segments to form the plurality of resistor values; generating a transistor level schematic including the plurality of resistor segments to generate the resistor divider; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

229. 1. A system for generating a resistor divider, comprising: means for receiving parameters specifying a resistor divider to be generated; means for determining a plurality of resistor values ​​corresponding to resistors between one or more output taps of the resistor divider, and for each resistor value determining a plurality of resistor segments to generate each of the plurality of resistor values; means for generating a circuit specification for configuring each of the plurality of resistor segments to form the plurality of resistor values; means for generating a transistor level schematic including the plurality of resistor segments to generate the resistor divider; Including, the system.

230. 1. A computer-implemented method for generating a transistor, comprising the steps of: receiving information specifying a transistor to be created and including an on-resistance of the transistor to be created; determining a total gate width of the to-be-created transistor based at least on the on-resistance; determining a first width, a number of fingers (F), and a number of device cells (P) based on the total width; generating a transistor level schematic including one or more transistors configured using the first width and the number of fingers (F); generating a layout including P device cells, each device cell including a number of gates corresponding to the number of fingers (F), each gate having the first width, the device cells being arranged in a two-dimensional array; 4. A computer-implemented method comprising:

231. 231. The method of claim 230, wherein the transistor level schematic includes one transistor having a multiplier attribute (M) equal to the number (P) of device cells.

232. 231. The method of claim 230, wherein the transistor level schematic comprises P transistors configured in parallel.

233. 231. The method of claim 230, wherein the P device cells have a programmable aspect ratio.

234. 234. The method of claim 233, wherein the aspect ratio is greater than 0.5 and less than 1.

235. 234. The method of claim 233, wherein the aspect ratio is between about two-thirds and about three-quarters.

236. 231. The method of claim 230, wherein the two-dimensional array includes an equal number of rows and columns of device cells.

237. 231. The method of claim 230, wherein the number (P) of device cells is a perfect square.

238. 231. The method of claim 230, wherein the first width, the first number of fingers, and the number of device cells (P) are determined based on a maximum width and a maximum number of fingers.

239. 239. The method of claim 238, further comprising determining the number of device cells (P) and the number of fingers (F) by increasing the number of device cells (P) over a number of increments to determine the number of fingers (F) obtainable based on a current number of device cells, the maximum width, and the maximum number of fingers.

240. iteratively increasing the number (P) of device cells over a number of values; determining whether the total width is obtainable from a current value of P, the maximum width, and the maximum number of fingers; if the total width is not obtainable from the current value of P, the maximum width, and the maximum number of fingers, increasing the value of P and repeating the determining step; if the total width is obtainable from the current value of P, the maximum width, and the maximum number of fingers, setting the number of device cells (P) to the current value of P and setting the number of fingers (F) based on the maximum width and the current value of P; The method of claim 238, further comprising:

241. 240. The method of claim 239, further comprising determining a first length along a first dimension of a device cell based on the number of fingers (F) and a first plurality of predetermined offset values.

242. 242. The method of claim 241, wherein the plurality of predetermined offset values ​​are selected based on transistor type.

243. 242. The method of claim 241, further comprising determining a second length of the device cell based on the first length and a predetermined aspect ratio.

244. 244. The method of claim 243, wherein the aspect ratio is programmable.

245. 244. The method of claim 243, further comprising determining the first width based on the second length and at least one second predetermined offset value.

246. 239. The method of claim 238, wherein the maximum width and maximum number of fingers are predetermined values.

247. generating a circuit specification specifying one or more transistors having the first width and the number of fingers (F); the circuit specification is used to generate the transistor level schematic; The method of claim 230.

248. The information specifying the transistor to be generated specifies a device type; the circuit specification specifies one or more p-type or n-type transistors based on the device type; The method of claim 247.

249. The information specifying the transistor to be created specifies a maximum drain-to-source voltage; the circuit specification specifies one of a plurality of transistors based on the maximum drain-to-source voltage. The method of claim 247.

250. The information specifying the transistor to be created specifies a maximum gate-to-source voltage; the circuit specification specifies one of a plurality of transistors based on the maximum gate-to-source voltage. The method of claim 247.

251. determining the total width of the gates of the to-be-created transistor based at least on the on-resistance, selecting a set of a plurality of sets of regression coefficients based on a transistor type of the transistor to be generated; determining the total width based on the on-resistance and the selected set of regression coefficients; Including, The method of claim 230.

252. 252. The method of claim 251, wherein the transistor type is a power transistor.

253. 252. The method of claim 251, wherein the transistor type is a signal transistor.

254. The information specifying transistors to be generated specifies replica transistors; the transistor level schematic includes a replica transistor having a gate coupled to one or more gates of the one or more transistors and a drain coupled to one or more drains of the one or more transistors; The method of claim 230.

255. The information specifying the transistor to be generated specifies a replica gain; a width of the replica transistor is determined based on the total width of the to-be-created transistors; The method of claim 254.

256. The information specifying the transistor to be created specifies a Kelvin connection; the transistor level schematic includes a Kelvin source terminal coupled to one or more sources of the one or more transistors and a Kelvin drain terminal coupled to one or more drains of the one or more transistors. The method of claim 230.

257. 257. The method of claim 256, wherein the transistor level schematic further includes a first resistor configured between the Kelvin source terminal and the one or more source terminals of the one or more transistors, and a second resistor configured between the Kelvin drain terminal and the one or more drains of the one or more transistors.

258. generating a layout includes executing one or more layout placement instructions; the layout placement instructions successively place the P device cells at an initial location and P-1 other locations offset from the initial location by integer numbers of x-axis and y-axis offsets; The method of claim 230.

259. 259. The method of claim 258, wherein the performed layout placement instructions are performed based on transistor type.

260. 259. The method of claim 258, wherein the x-axis offset and y-axis offset are calculated based on the first width and the number of fingers (F).

261. 260. The method of claim 258, wherein the generating a layout further comprises automatically placing a plurality of metallization strips across the two-dimensional array of device cells.

262. 262. The method of claim 261, wherein a number of metallization strips across each device cell is determined based on the first width and a predetermined maximum strip width.

263. 262. The method of claim 261, wherein the metallization strips are placed based on a predetermined offset selected based on a transistor type of the transistor to be created.

264. 1. A computer system for generating a transistor, comprising: one or more processors; When executed by a computer system, receiving information specifying a transistor to be created and including an on-resistance of the transistor to be created; determining a total gate width of the to-be-created transistor based at least on the on-resistance; determining a first width, a number of fingers (F), and a number of device cells (P) based on the total width; generating a transistor level schematic including one or more transistors configured using the first width and the number of fingers (F); and generating a layout including P device cells, each device cell including a number of gates corresponding to the number of fingers (F), each gate having the first width, the device cells being arranged in a two-dimensional array; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

265. When executed by a computer system, the computer system receiving information specifying a transistor to be created and including an on-resistance of the transistor to be created; determining a total gate width of the to-be-created transistor based at least on the on-resistance; determining a first width, a number of fingers (F), and a number of device cells (P) based on the total width; generating a transistor level schematic including one or more transistors configured using the first width and the number of fingers (F); generating a layout including P device cells, each device cell including a number of gates corresponding to the number of fingers (F), each gate having the first width, the device cells being arranged in a two dimensional array; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a

266. 1. A system for producing a transistor, comprising: means for receiving information specifying a transistor to be created and including an on-resistance of the transistor to be created; means for determining a total gate width of the transistor to be generated based at least on the on-resistance; means for determining a first width, a number of fingers (F), and a number of device cells (P) based on the total width; means for generating a transistor level schematic including one or more transistors configured with said first width and said number of fingers (F); a means for generating a layout, the layout including P device cells, each device cell including a number of gates corresponding to the number of fingers (F), each gate having the first width, the device cells being arranged in a two dimensional array; Including, the system.

267. 1. A computer-implemented method for generating a transistor, comprising the steps of: receiving information specifying a transistor to be created and including an on-resistance; calculating an area from the on-resistance; determining a total width based on the area and a predetermined length; determining a number of device cells (P) and a number of fingers (F) based on the total width, a predetermined maximum width, and a predetermined maximum number of fingers; determining a first length along a first dimension of a device cell based on the number of fingers (F); determining a second length along a second dimension of the device cell based on a programmed ratio of the first length to the second length; determining a first gate width based on the second dimension; configuring one or more transistors in a transistor level schematic using the first gate width and the number of fingers (F); 4. A computer-implemented method comprising:

268. 268. The method of claim 267, wherein the transistor level schematic includes one transistor having a multiplier attribute (M) equal to the number (P) of device cells.

269. 268. The method of claim 267, wherein the transistor level schematic includes P transistors configured in parallel.

270. 268. The method of claim 267, wherein the number (P) of device cells is a perfect square.

271. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, receiving information specifying a transistor to be generated and including at least an on-resistance; Calculating the area from the on-resistance; determining a total width based on the area and a predetermined length; determining a number of device cells (P) and a number of fingers (F) based on the total width, a predetermined maximum width, and a predetermined maximum number of fingers; determining a first length along a first dimension of a device cell based on the number of fingers (F); determining a second length along a second dimension of the device cell based on a programmed ratio of the first length to the second length; determining a first gate width based on the second dimension; and configuring one or more transistors in a transistor level schematic using the first gate width and the number of fingers (F); A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

272. When executed by a computer system, the computer system receiving information specifying a transistor to be generated and including at least an on-resistance; Calculate the area from the on-resistance, determining a total width based on the area and a predetermined length; determining a number of device cells (P) and a number of fingers (F) based on the total width, a predetermined maximum width, and a predetermined maximum number of fingers; determining a first length along a first dimension of the device cell based on the number of fingers (F); determining a second length along a second dimension of the device cell based on a programmed ratio of the first length to the second length; determining a first gate width based on the second dimension; and configuring one or more transistors in a transistor level schematic using the first gate width and the number of fingers (F); A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

273. 1. A system for producing a transistor, comprising: means for receiving information specifying a transistor to be generated and including an on-resistance; A means for calculating an area from an on-resistance; means for determining a total width based on the area and a predetermined length; means for determining a number of device cells (P) and a number of fingers (F) based on the total width, a predetermined maximum width, and a predetermined maximum number of fingers; means for determining a first length along a first dimension of a device cell based on the number of fingers (F); means for determining a second length along a second dimension of the device cell based on a programmed ratio of the first length to the second length; means for determining a first gate width based on the second dimension; means for configuring one or more transistors in a transistor level schematic using said first gate width and said number of fingers (F); Including, the system.

274. generating a plurality of data sets for a plurality of transistors, each data set including on-resistance values ​​obtained for a plurality of gate widths for a particular transistor of the plurality of transistors; generating a plurality of coefficient sets, the plurality of coefficient sets including one or more regression coefficients, based on a regression equation applied to each of the plurality of data sets; receiving information specifying an on-resistance and a transistor of the plurality of transistors; selecting one of the plurality of coefficient sets based on a designated transistor of the plurality of transistors; determining a gate width based on the on-resistance and the selected set of coefficients; 4. A computer-implemented method comprising:

275. 1. A computer system for generating a circuit, comprising: one or more processors; When executed by a computer system, generating a plurality of data sets for a plurality of transistors, each data set including on-resistance values ​​obtained for a plurality of gate widths for a particular transistor of the plurality of transistors; generating a plurality of coefficient sets, including one or more regression coefficients, based on the regression equation applied to each of the plurality of data sets; receiving information specifying an on-resistance and a transistor of the plurality of transistors; selecting a coefficient set from the plurality of coefficient sets based on a designated transistor from the plurality of transistors; and determining a gate width based on the on-resistance and the selected set of coefficients; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

276. When executed by a computer system, the computer system generating a plurality of data sets for a plurality of transistors, each data set including values ​​of on-resistance obtained for a plurality of gate widths for a particular transistor of the plurality of transistors; generating a plurality of coefficient sets including one or more regression coefficients based on the regression equation applied to each of the plurality of data sets; receiving information specifying an on-resistance and a transistor of the plurality of transistors; selecting a coefficient set from the plurality of coefficient sets based on a designated transistor from the plurality of transistors; and determining a gate width based on the on-resistance and the selected set of coefficients; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

277. 1. A system for generating a circuit, comprising: means for generating a plurality of data sets for a plurality of transistors, each data set including on-resistance values ​​obtained for a plurality of gate widths for a particular transistor of the plurality of transistors; means for generating a plurality of coefficient sets, the plurality of coefficient sets including one or more regression coefficients, based on a regression equation applied to each of the plurality of data sets; means for receiving information specifying an on-resistance and a transistor of the plurality of transistors; means for selecting one of the plurality of coefficient sets based on the designated transistor of the plurality of transistors; means for determining a gate width based on the on-resistance and the selected set of coefficients; Including, the system.

278. 1. A computer-implemented method for generating a transistor, comprising the steps of: receiving information specifying a transistor to be created; deriving predetermined layout parameters based at least in part on said information; determining attributes of the to-be-created transistor including width, number of fingers, and number of device cells based on the information and the layout parameters; generating a transistor level schematic diagram for the to-be-generated transistor including one or more transistor schematic diagrams configured based on the attributes; generating a layout of the to-be-generated transistor from the transistor level schematic, the layout including the number of device cells, each device cell being automatically positioned within the layout by layout placement instructions based on the attributes; 4. A computer-implemented method comprising:

279. 1. A computer system for generating a transistor, comprising: one or more processors; When executed by a computer system, receiving information specifying a transistor to be created; deriving predetermined layout parameters based at least in part on said information; determining attributes of the to-be-created transistor including width, number of fingers, and number of device cells based on the information and the layout parameters; generating a transistor level schematic diagram for the to-be-generated transistor, the transistor schematic diagram including one or more transistor schematic diagrams configured based on the attributes; and generating a layout of the to-be-generated transistor from the transistor level schematic, the layout including the number of device cells, each device cell being automatically positioned within the layout by layout placement instructions based on the attributes; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

280. When executed by a computer system, the computer system receiving information specifying a transistor to be produced; deriving predetermined layout parameters based at least in part on said information; determining attributes of the to-be-created transistor including width, number of fingers, and number of device cells based on the information and the layout parameters; generating a transistor level schematic diagram for the to-be-generated transistor including one or more transistor schematic diagrams configured based on the attributes; and generating a layout of the to-be-generated transistors from the transistor-level schematic, the layout including the number of device cells, each device cell being automatically positioned within the layout by layout placement instructions based on the attributes; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

281. 1. A system for producing a transistor, comprising: means for receiving information specifying a transistor to be produced; means for deriving predetermined layout parameters based at least in part on said information; means for determining attributes of the to-be-created transistor based on the information and the layout parameters, the attributes including width, number of fingers, and number of device cells; means for generating a transistor level schematic diagram for the to-be-generated transistor, the transistor schematic diagram including one or more transistor schematic diagrams configured based on the attributes; means for generating a layout of the to-be-generated transistor from the transistor level schematic, the layout including the number of device cells, each device cell being automatically positioned within the layout by layout placement instructions based on the attributes; Including, the system.

282. 1. A computer-implemented method for generating a transistor layout, comprising: transforming one or more transistors into a plurality of layout instances based on attributes of the transistors; executing a predetermined layout script that positions the plurality of layout instances as a two-dimensional array to form a layout for the transistor; 4. A computer-implemented method comprising:

283. 283. The method of claim 282, wherein the layout script is associated with a circuit schematic that includes the transistor.

284. 283. The method of claim 282, wherein the transistor is a field effect transistor.

285. 285. The method of claim 284, wherein the transistor is a power field effect transistor.

286. 283. The method of claim 282, further comprising determining a first gate width based on the total gate width for the transistor, a number of fingers (F), and a number of device cells (P).

287. the one or more transistors are a plurality of transistors having the same attributes and arranged in parallel, Each transistor has a multiplier attribute equal to 1, The method of claim 282.

288. 283. The method of claim 282, wherein the one or more transistors is a single transistor having a multiplier attribute greater than one.

289. 283. The method of claim 282, wherein the number (P) of layout instances is a perfect square.

290. 283. The method of claim 282, wherein the aspect ratio of the layout instance is programmable.

291. 283. The method of claim 282, wherein the layout script includes at least one layout placement instruction that specifies an initial position for a first layout instance.

292. 300. The method of claim 291, wherein a single layout arrangement instruction arranges the multiple layout instances.

293. 300. The method of claim 291, wherein the at least one layout placement instruction specifies an x ​​step and a y step between the layout instances.

294. 300. The method of claim 291, wherein the at least one layout placement instruction specifies a number of columns and a number of rows for the two-dimensional array.

295. 1. A computer system for generating a transistor layout, comprising: one or more processors; When executed by a computer system, Transforming one or more transistors into a plurality of layout instances based on attributes of the transistors; and executing a predetermined layout script that positions the plurality of layout instances as a two-dimensional array to form a layout for the transistor; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

296. When executed by a computer system, the computer system Transforming one or more transistors into a plurality of layout instances based on attributes of the transistors; and executing a predetermined layout script that positions the plurality of layout instances as a two-dimensional array to form a layout for the transistor; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

297. 1. A computer system for generating a transistor layout, comprising: means for transforming one or more transistors into a plurality of layout instances based on attributes of the transistors; means for executing a predetermined layout script that positions the plurality of layout instances as a two-dimensional array to form a layout for the transistor; 2. A computer system comprising:

298. 1. A computer-implemented method for generating a circuit layout, comprising: specifying a circuit schematic to be converted into said circuit layout; receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic; converting the circuit diagram into the plurality of layout instances; positioning the plurality of layout instances based on the layout script to generate the circuit layout; 4. A computer-implemented method comprising:

299. 300. The method of claim 298, wherein the circuit schematic is a transistor level schematic for an analog or mixed signal circuit.

300. 300. The method of claim 298, wherein one or more of the plurality of layout instances is a predetermined layout for a sub-circuit schematic diagram.

301. 301. The method of claim 300, wherein the layout script includes a reference to a library in which a particular layout instance is stored.

302. 300. The method of claim 298, wherein a first subset of the plurality of layout instances corresponds to a plurality of resistors.

303. 300. The method of claim 298, wherein a first subset of the plurality of layout instances corresponds to a plurality of capacitors.

304. 300. The method of claim 298, wherein the layout script specifies a particular placement for each of the multiple layout instances.

305. the circuit diagram corresponds to a first circuit diagram among a plurality of circuit diagrams; the layout script is configured to position a layout instance for each of the plurality of circuit schematics; The method of claim 298.

306. 306. The method of claim 305, wherein the plurality of circuit schematics implement a first function.

307. the layout script performs a plurality of placement operations on layout instances from different circuit schematics; A placement operation is performed on a layout instance corresponding to the first circuit diagram, and a placement operation is not performed on layout instances corresponding to other circuit diagrams; The method of claim 305.

308. 300. The method of claim 298, wherein the layout script includes a plurality of layout placement instructions for positioning one or more of the layout instances.

309. 309. The method of claim 308, wherein the plurality of layout placement instructions includes corresponding code for performing a placement operation corresponding to each layout placement instruction.

310. 310. The method of claim 309, wherein the code is a layout placement instruction script.

311. 309. The method of claim 308, wherein the layout placement instructions receive positioning parameters that specify a placement of the one or more layout instances.

312. 309. The method of claim 308, wherein the subset of layout placement instructions includes a reference to a particular layout instance of the plurality of layout instances.

313. 313. The method of claim 312, wherein the reference is a cell name.

314. 313. The method of claim 312, wherein the reference is an instance name.

315. 309. The method of claim 308, wherein one or more layout placement instructions specify a placement location for one or more corresponding layout instances of the plurality of layout instances.

316. 309. The method of claim 308, wherein the one or more layout placement instructions specify a particular layout instance and x-axis and y-axis coordinates for positioning the particular layout instance.

317. 317. The method of claim 316, wherein the one or more layout placement instructions further specify a library name in which the particular layout instance is stored.

318. 317. The method of claim 316, wherein the one or more layout placement instructions further specify a rotation of the particular layout instance.

319. 309. The method of claim 308, wherein a first layout placement instruction of the plurality of layout placement instructions positions a first subset of the plurality of layout instances.

320. 320. The method of claim 319, wherein the first subset of the plurality of layout instances is a predetermined layout for a sub-circuit schematic.

321. 320. The method of claim 319, wherein the first subset of the plurality of layout instances are passive layout components.

322. 322. The method of claim 321, wherein the plurality of passive layout components are resistor layout components.

323. 322. The method of claim 321, wherein the plurality of passive components are capacitor layout components.

324. 320. The method of claim 319, wherein the first layout placement instructions specify a step direction along one of a plurality of axes.

325. 320. A method as recited in claim 319, wherein the first layout placement instructions specify a starting position and a step between the first subset of layout instances.

326. 326. A method as recited in claim 325, wherein said step of specifying a distance between adjacent boundaries of the first subset of layout instances.

327. 326. A method as recited in claim 325, wherein the step is greater than or equal to a length of a boundary along a first axis of the first subset of layout instances.

328. 320. The method of claim 319, wherein the first layout placement instructions further specify a maximum distance for consecutively placing layout instances along an axis.

329. 329. The method of claim 328, wherein the maximum distance is associated with a length of one of the plurality of layout instances.

330. 329. The method of claim 328, wherein the layout instances are successively positioned along a first axis from the starting position to a second position based on the distance, and wherein as the first portion of the layout instances spans a space between the starting position and the second position, the second portion of the layout instances is successively positioned along the first axis between a third position offset from the starting position along the second axis and a fourth position based on the distance.

331. the first subset of layout arrangement instances includes at least a first subgroup of layout arrangement instances and a second subgroup of layout arrangement instances; the first layout placement instructions further specify a step between a first subgroup and a second subgroup of layout instances; The method of claim 319.

332. 320. The method of claim 319, wherein a second layout placement instruction following the first layout placement instruction places one or more layout instances of the plurality of layout instances at one or more positions starting from a final position of the first layout placement instruction.

333. 309. The method of claim 308, wherein one or more of the layout placement instructions includes a conditional statement.

334. 334. The method of claim 333, wherein at least one layout placement instruction determines whether a position is occupied.

335. 335. A method as recited in claim 334, wherein one or more first layout placement instructions are executed if the location is occupied.

336. 335. A method as recited in claim 334, wherein one or more first layout placement instructions are executed if the location is unoccupied.

337. At least one layout placement instruction determines whether one or more specified layout instances are included in the layout; one or more first layout placement instructions are executed if the specified instance is included in the layout; one or more second layout placement instructions are executed if the one or more specified layout instances are not present in the layout. The method of claim 333.

338. 1. A computer system for generating a circuit layout, comprising: one or more processors; When executed by a computer system, specifying a circuit schematic to be converted into said circuit layout; receiving a layout script associated with the circuit diagram, the layout script being configured to position a plurality of layout instances generated from the circuit diagram; converting the circuit diagram into the plurality of layout instances; and positioning the plurality of layout instances based on the layout script to generate the circuit layout; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

339. When executed by a computer system, the computer system Specifying a circuit diagram to be converted into the circuit layout; receiving a layout script associated with the circuit diagram configured to position a plurality of layout instances generated from the circuit diagram; Transforming the circuit diagram into the plurality of layout instances; and positioning the plurality of layout instances based on the layout script to generate the circuit layout; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

340. 1. A computer system for generating a circuit layout, comprising: means for specifying a circuit diagram to be converted into said circuit layout; means for receiving a layout script associated with the circuit diagram, the layout script being configured to position a plurality of layout instances generated from the circuit diagram; means for converting the circuit diagram into the plurality of layout instances; means for positioning the plurality of layout instances based on the layout script to generate the circuit layout; 2. A computer system comprising:

341. 1. A computer-implemented method for generating a circuit layout, comprising: receiving a plurality of layout instances generated from the wiring diagram into a layout canvas; receiving a layout script associated with the wiring diagram, the layout script including a plurality of layout placement instructions for placing a plurality of layout instances generated from the wiring diagram; positioning the layout instances using the layout placement instructions; 4. A computer-implemented method comprising:

342. 1. A computer system for generating a circuit layout, comprising: one or more processors; When executed by a computer system, receiving a plurality of layout instances generated from the wiring diagram into a layout canvas; receiving a layout script associated with the wiring diagram, the layout script including a plurality of layout placement instructions for placing a plurality of layout instances generated from the wiring diagram; and positioning the layout instances using the layout placement instructions; A non-transitory computer-readable storage medium having stored thereon computer-executable instructions for causing a computer system to perform a method comprising:

2. A computer system comprising:

343. When executed by a computer system, the computer system Receive multiple layout instances generated from a wiring diagram into the layout canvas, receiving a layout script associated with the circuit diagram, the layout script including a plurality of layout placement instructions for placing a plurality of layout instances generated from the circuit diagram; and positioning the layout instances using the layout placement instructions; A non-transitory computer-readable storage medium having computer-executable instructions stored thereon.

344. 1. A system for generating a circuit layout, comprising: means for receiving into a layout canvas a plurality of layout instances generated from a wiring diagram; means for receiving a layout script associated with the wiring diagram, the layout script including a plurality of layout placement instructions for placing a plurality of layout instances generated from the wiring diagram; means for positioning the layout instances using the layout placement instructions; Including, the system.

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