Semiconductor device

Abstract

To provide a semiconductor device suitable for miniaturization.SOLUTION: A semiconductor device comprises a first transistor, a second transistor located above the first transistor, a barrier layer located between the first and second transistors, a first electrode located between the first transistor and the barrier layer, and a second electrode being located between the barrier layer and the second transistor, and superposed on the first electrode while interposing the barrier layer therebetween. The gate electrode, the first electrode of the first transistor, and one of the source electrode and the drain electrode of the second transistor are connected electrically, the first transistor has a channel formed in a first semiconductor layer containing a single crystal semiconductor, and the second transistor has a channel formed in a second semiconductor layer containing an oxide semiconductor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a manufacturing method of a semiconductor device. One embodiment of the present invention relates to a method for driving a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to a process, a machine, or a method of manufacture. , manufacture, or composition of matter. More specifically, the technical field of one embodiment of the present invention disclosed in this specification is a semiconductor device, Examples of the display device, the light-emitting device, the lighting device, the driving method thereof, or the manufacturing method thereof are as follows. These can be listed as:

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Devices, storage devices, imaging devices, electro-optical devices, power generation devices (thin-film solar cells, organic thin-film solar cells etc.), and electronic devices may include semiconductor devices. [Background technology]

[0004] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials that can be used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating a transistor using this method have been disclosed (see Patent Documents 1 and 2).

[0006] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. 2. Description of the Related Art There is an increasing demand for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device that is suitable for miniaturization.

[0009] Another object is to provide a semiconductor device with good electrical characteristics. Another object of the present invention is to provide a semiconductor device having a novel structure. One of the objectives is to provide the following.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor located above the first transistor. a barrier layer located between the first transistor and the second transistor; a first electrode located between the first transistor and the barrier layer; and a second electrode located between the barrier layer and the second transistor. a second electrode located between the first electrode and the transistor and overlapping the first electrode with a barrier layer interposed therebetween; The first transistor has a channel formed in a first semiconductor layer including a single crystal semiconductor, The second transistor is a semiconductor transistor in which a channel is formed in a second semiconductor layer including an oxide semiconductor. It is a semiconductor device.

[0012] Another embodiment of the present invention is a semiconductor device including a first transistor and a semiconductor device disposed above the first transistor. a second transistor disposed between the first transistor and the second transistor; a barrier layer formed on the first transistor; a first electrode located between the first transistor and the barrier layer; and a barrier layer a second transistor that is located between the first electrode and the second transistor and overlaps with the first electrode with a barrier layer interposed therebetween; a gate electrode of the first transistor, a first electrode, and a second transistor One of the source electrode and the drain electrode of the first transistor is electrically connected to each other. In the first transistor, a channel is formed in a first semiconductor layer including a single crystal semiconductor, and the second transistor is The semiconductor device has a channel formed in a second semiconductor layer including an oxide semiconductor.

[0013] Another embodiment of the present invention is a semiconductor device including a first transistor and a semiconductor device disposed above the first transistor. a second transistor disposed between the first transistor and the second transistor; a barrier layer formed on the first transistor; a first electrode located between the first transistor and the barrier layer; and a barrier layer a second transistor that is located between the first electrode and the second transistor and overlaps with the first electrode with a barrier layer interposed therebetween; a gate electrode of the first transistor, a second electrode, and a second transistor One of the source electrode and the drain electrode of the first transistor is electrically connected to each other. In the first transistor, a channel is formed in a first semiconductor layer including a single crystal semiconductor, and the second transistor is The semiconductor device has a channel formed in a second semiconductor layer including an oxide semiconductor.

[0014] Another embodiment of the present invention is a semiconductor device including a first transistor and a semiconductor device disposed above the first transistor. a second transistor disposed between the first transistor and the second transistor; a barrier layer formed on the first transistor; a first electrode located between the first transistor and the barrier layer; and a barrier layer a second transistor that is located between the first electrode and the second transistor and overlaps with the first electrode with a barrier layer interposed therebetween; a gate electrode of the first transistor, a first electrode, and a second transistor The source electrode or the drain electrode of the second electrode is electrically connected to the second electrode of the second The first transistor includes a channel formation region overlapping with the channel formation region of the second transistor. A channel is formed in a first semiconductor layer including an oxide semiconductor. The semiconductor device has a channel formed in the semiconductor layer 2.

[0015] The barrier layer may be made of silicon nitride, silicon oxynitride, aluminum oxide, or oxynitride. Aluminum oxide, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride It is preferable that the oxide contains at least one of hafnium, hafnium oxide, and hafnium oxynitride. stomach.

[0016] Further, an insulating layer containing an oxide is provided between the second transistor and the barrier layer. The layer preferably has regions containing more than stoichiometric oxygen. .

[0017] The insulating layer contains hydrogen at a concentration of 5×10 18 cm -3 Being less than preferable.

[0018] The second semiconductor layer contains hydrogen at a concentration of 5×10 18 cm -3 Less than is preferred.

[0019] The gate insulating layer of the second transistor contains hydrogen at a concentration of 5×10 1 8 cm -3 It is preferable that it is less than 1000 .mu.m.

[0020] Moreover, the second electrode preferably contains a conductive metal oxide.

[0021] Also, a third electrode containing the same material as the second electrode is provided on the same plane as the second electrode. It is preferable that the third electrode overlaps with a channel formation region of the second transistor. is preferred.

[0022] The second transistor has an S value of 60 mV / dec. or more and 100 mV / dec. or more. c. It is preferable that: Effect of the Invention

[0023] According to one embodiment of the present invention, a semiconductor device suitable for miniaturization can be provided.

[0024] Alternatively, it is possible to impart good electrical characteristics to the semiconductor device. It is possible to provide a semiconductor device. Alternatively, it is possible to provide a semiconductor device having a novel configuration. The description of these effects does not preclude the existence of other effects. An embodiment of the invention does not necessarily have to have all of these effects. The effects of the above are self-evident from the description, drawings, claims, etc. Other effects can be extracted from descriptions in the specification, drawings, claims, etc. [Brief description of the drawings]

[0025] [Figure 1] 1A to 1C are diagrams illustrating a stacked structure included in a semiconductor device according to an embodiment; [Diagram 2] 1A to 1C are circuit diagrams and configuration examples of a semiconductor device according to an embodiment. [Diagram 3] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 4] 1 shows a configuration example of a semiconductor device according to an embodiment. [Diagram 5] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 6] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 7] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 8] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 9] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 10] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 11] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 12] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 13] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 14]1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 15] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 16] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 17] 1A to 1C are circuit diagrams and configuration examples of a semiconductor device according to an embodiment. [Figure 18] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 19] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 20] 1A to 1C are circuit diagrams and configuration examples of a semiconductor device according to an embodiment. [Figure 21] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 22] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 23] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 24] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 25] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 26] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 27] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 28] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 29] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 30] 1A to 1C are diagrams illustrating a band structure according to an embodiment. [Diagram 31] High-resolution TEM image and local Fourier transform image of a cross section of an oxide semiconductor. [Diagram 32] 1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. [Diagram 33]An example of structural analysis using transmission electron diffraction measurements, and a high-resolution TEM image in a plan view. [Diagram 34] FIG. [Diagram 35] 3 shows an example of the configuration of an RFID tag according to the embodiment. [Diagram 36] 3 shows an example of the configuration of a CPU according to the embodiment. [Figure 37] 1 is a circuit diagram of a memory element according to an embodiment. [Figure 38] 1 is a circuit diagram of a display device according to an embodiment. [Figure 39] 1 is an electronic device according to an embodiment. [Diagram 40] 1 shows an example of how RFID is used in accordance with an embodiment of the present invention. [Diagram 41] FIG. 13 shows electrical characteristics of a transistor. [Diagram 42] FIG. 2 is a top view showing a peripheral structure of a transistor. [Diagram 43] FIG. 13 shows electrical characteristics of a transistor. [Diagram 44] 13A and 13B are diagrams showing variations in electrical characteristics of transistors. [Diagram 45] FIG. 13 is a graph showing the relationship between the voltage applied to the second gate electrode and the ideal drain current of a transistor when the voltage of the first gate electrode is 0 V. [Diagram 46] FIG. 2 is a schematic cross-sectional view of a transistor according to an embodiment of the present invention. [Figure 47] FIG. 13 is a graph showing Vg-Id characteristics of a transistor in an ideal state. [Figure 48] FIG. 4 is a circuit diagram showing an example of a measurement system. [Figure 49] FIG. 4 is a timing chart showing potentials related to the operation of the measurement system. [Figure 50] 13A and 13B are diagrams illustrating measurement results of off-state current. [Figure 51] 13A and 13B are diagrams illustrating measurement results of off-state current. [Figure 52] FIG. 2 is an Arrhenius plot diagram for explaining an off-state current. [Figure 53] 1A and 1B are diagrams for explaining measurement results of off-state current and Arrhenius plot diagrams. [Figure 54] The required lifetime of each device and the target leakage current of the transistors. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0027] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be used.

[0028] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0029] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0030] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0031] (Embodiment 1) [Example of laminated structure] An example of a stacked structure that can be applied to a semiconductor device of one embodiment of the present invention will be described below. FIG 1 is a schematic cross-sectional view of a laminate structure 10 as described below.

[0032] The laminate structure 10 includes a first layer 11 including a first transistor, a first insulating layer 21, a first The wiring layer 31, the barrier layer 41, the second wiring layer 32, the second insulating layer 22, and the second transistor The second layer 12 including the stanchion has a laminated structure in which the first layer 12 and the second layer 12 are laminated in order.

[0033] The first transistor included in the first layer 11 is configured to include a first semiconductor material. The second transistor included in the second layer 12 is made of a second semiconductor material. The first and second semiconductor materials may be the same material, but may be different materials. The first transistor and the second transistor are preferably made of a semiconductor material. The semiconductor layer, the gate electrode, the gate insulating layer, the source electrode and the drain electrode (or In addition, the semiconductor device has a source region and a drain region.

[0034] For example, a semiconductor that can be used as the first semiconductor material or the second semiconductor material Examples of the semiconductor materials include silicon and germanium. Compound semiconductor materials containing gallium, arsenic, aluminum, etc., organic semiconductor materials, or Examples of the material include an oxide semiconductor material.

[0035] Here, single crystal silicon is used as the first semiconductor material and oxide is used as the second semiconductor material. The case where a semiconductor is used will be described.

[0036] The barrier layer 41 has a function of suppressing the diffusion of water and hydrogen from the layers below it to the layers above it. The barrier layer 41 is a layer having an upper electrode or wiring and a lower electrode or wiring. The insulating layer may have an opening or a plug for electrically connecting the insulating layer to an electrode or wiring provided on the insulating layer. For example, the wiring or electrodes included in the first wiring layer 31 and the wiring or electrodes included in the second wiring layer 32 may be The semiconductor device has a plug for electrically connecting to a wiring or electrode.

[0037] The first wiring layer 31 and the second wiring layer 32 are provided so as to sandwich the barrier layer 41 therebetween. The first wiring layer 31 has at least a first electrode, and the second wiring layer 32 has at least a first The first electrode, the barrier layer 41 and the second electrode are overlapped by a second electrode. More capacitance can be formed.

[0038] As a material used for the wiring or electrodes included in the first wiring layer 31 and the second wiring layer 32, In addition to metal or alloy materials, conductive metal oxides can be used. A layer containing such a material may be used as a single layer, or two or more layers may be laminated.

[0039] The first insulating layer 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. In addition, the first insulating layer 21 includes the first transistor, the electrodes, and the like included in the first layer 11. and an opening for electrically connecting the electrodes or wiring included in the first wiring layer 31. It may have a port or plug.

[0040] The second insulating layer 22 has a function of electrically insulating the second layer 12 and the second wiring layer 32. In addition, the second insulating layer 22 is provided with a second transistor and an electrode included in the second layer 12. or for electrically connecting the wiring to the electrodes or wiring included in the second wiring layer 32. It may have an opening or a plug.

[0041] The second insulating layer 22 preferably contains an oxide. Preferably, the oxide material contains oxygen that is desorbed from the oxide. It is preferable to use an oxide containing more oxygen than the first semiconductor material. When a conductor is used, oxygen desorbed from the second insulating layer 22 is supplied to the oxide semiconductor, and the oxide This makes it possible to reduce oxygen vacancies in the semiconductor. As a result, the current of the second transistor is This suppresses fluctuations in electrical characteristics and improves reliability.

[0042] Here, hydrogen, water, etc. should be reduced as much as possible below the barrier layer 41. Hydrogen and water can cause fluctuations in the electrical characteristics of oxide semiconductors. In addition, the barrier layer 41 prevents hydrogen and water from diffusing from the lower layer to the upper layer. However, hydrogen and water may enter the upper layer through openings or plugs provided in the barrier layer 41. It may spread.

[0043] In order to reduce hydrogen and water contained in each layer located below the barrier layer 41, Before forming layer 41 or immediately after forming an opening in barrier layer 41 for forming a plug In addition, a heat treatment may be performed to remove hydrogen and water contained in the layer below the barrier layer 41. In the heat treatment, while taking into consideration the heat resistance of a conductive film or the like that constitutes a semiconductor device, As long as the electrical characteristics of the transistor are not deteriorated, the temperature of the heat treatment is preferably as high as possible. Specifically, for example, 450° C. or higher, preferably 490° C. or higher, more preferably 530° C. The temperature should be 650°C or higher, but it may be 650°C or higher. Heat treatment in a pressurized atmosphere for 1 hour or more, preferably 5 hours or more, more preferably 10 hours or more. In addition, the temperature of the heat treatment is set to the temperature of the first layer 11 and the first wiring layer 31. The heat resistance of the material of the wiring or electrode to be formed and the material of the plug to be formed in the first insulating layer 21 is For example, if the material has low heat resistance, the temperature should be set to 550℃ or lower. The heating may be performed at a temperature of 600° C. or less, 650° C. or less, or 800° C. or less. Such a heat treatment may be carried out at least once, but it is more preferable to carry out the heat treatment a plurality of times.

[0044] The insulating film provided under the barrier layer 41 is analyzed by thermal desorption spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C, as measured by the ° C., the amount of hydrogen molecules released is preferably 130% or less, and more preferably 110% or less. Or, the amount of hydrogen molecules desorbed when the substrate surface temperature is 450°C, as measured by TDS analysis. is preferably 130% or less, more preferably 110% or less, of the amount desorbed at 350°C. .

[0045] In addition, it is preferable that the water and hydrogen contained in the barrier layer 41 itself is reduced. For example, The barrier layer 41 is formed by applying a thermal desorption spectroscopy (TDS) to the substrate surface at a temperature ranging from 20° C. to 600° C. The amount of hydrogen molecules (M / z=2) desorbed in the range of 2×10 15 pieces / cm 2 Less than, good Preferably 1×1015 pieces / cm 2 less than 5×10 14 pieces / cm 2 Less than It is preferable to use a material having a high thermal conductivity as the barrier layer 41. The amount of water molecules (M / z=18) desorbed when the substrate surface temperature was in the range of 20°C to 600°C was , 1×10 16 pieces / cm 2 Less than 5 x 10 15 pieces / cm 2 Less than, more preferably is 2 × 10 12 pieces / cm 2 It is preferred to use a material for the barrier layer 41 that has a viscosity of less than 100 .mu.m.

[0046] In addition, the semiconductor layer of the first transistor included in the first layer 11 is made of single crystal silicon. In this case, the heat treatment breaks down the dangling bonds of silicon. This can also serve as a process for terminating the substrate with hydrogen (also called hydrogenation). As a result, some of the hydrogen contained in the first layer 11 and the insulating layer 21 is released, forming the first transistor. The first transistor is formed by diffusing into the semiconductor layer and terminating the dangling bonds in the silicon. This can improve the reliability of the transistor.

[0047] Materials that can be used for the barrier layer 41 include silicon nitride, silicon oxynitride, Aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide Examples include thorium, yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride. In particular, aluminum oxide is preferable because it has excellent barrier properties against water and hydrogen.

[0048] The barrier layer 41 is made of a layer of a material that is difficult for water and hydrogen to permeate, and a layer containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing metal oxide, A layer containing a fluorine compound may be laminated.

[0049] In addition, it is preferable that the barrier layer 41 is made of a material that is difficult for oxygen to permeate. The material has excellent barrier properties against oxygen as well as hydrogen and water. By this, oxygen released when the second insulating layer 22 is heated is directed to a layer below the barrier layer 41. As a result, the diffusion of the ions from the second insulating layer 22 to the first insulating layer 23 can be suppressed. Increasing the amount of oxygen available to the semiconductor layer of the second transistor in layer 12 of FIG. can be done.

[0050] The barrier layer 41 can also function as a dielectric layer for the capacitor. If a material with a high dielectric constant (also called a high-k material) is used as 41, the This is preferable because it is possible to increase the capacitance value of the capacitor. This is preferable because it is possible to reduce the leakage current of the capacitor.

[0051] In this way, in one embodiment of the present invention, the layers located below the barrier layer 41 The concentration of hydrogen and water is reduced or removed, and the barrier layer 41 is formed to prevent hydrogen and water from entering the gas. The second insulating layer 22 and the second layer 12 are prevented from diffusing into each other. The hydrogen and water contents in each layer constituting the second transistor included in 12 are For example, the second insulating layer 22, the semiconductor layer of the second transistor, The hydrogen concentration in the gate insulating layer is set to 5×10 18 cm -3 Less than, preferably 1×10 18 cm -3 less than 3×10 17 cm -3 Reduce to less than It is possible.

[0052] By applying the stacked layer structure 10 to the semiconductor device according to one embodiment of the present invention, the first layer 1 The first transistor included in the first layer 11 and the second transistor included in the second layer 12 Even in these cases, it is possible to achieve high reliability, resulting in an extremely reliable semiconductor device. This can be achieved.

[0053] [Configuration example 1] FIG. 2A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a first transistor 110, a second transistor 100, and a capacitor 130. , a wiring BL, a wiring WL, a wiring CL, and a wiring BG.

[0054] The first transistor 110 has a source or a drain electrically connected to a wiring BL. The other end is electrically connected to a wiring SL, and the gate is the source or is electrically connected to one of the drains and one of the electrodes of the capacitor 130. 100 is a transistor in which the other of the source and drain is electrically connected to a wiring BL and the gate is connected to a wiring WL. The other electrode of the capacitor 130 is electrically connected to the wiring CL. The line BG is electrically connected to the second gate of the second transistor 100. The gate of the second transistor 110 and either the source or the drain of the second transistor 100 and one electrode of the capacitor 130 is called a node FN.

[0055] In the semiconductor device illustrated in FIG. 2A, the second transistor 100 is in a conductive state (on state). At this time, a potential corresponding to the potential of the wiring BL is applied to the node FN. When MOSFET 00 is in a non-conducting state (off state), the potential of node FN is maintained. That is, the semiconductor device shown in FIG. 2A functions as a memory cell of a memory device. In addition, the liquid crystal element and organic EL (Electroluminescence) When the semiconductor device in FIG. 2A has a display element such as a display screen element, It can also function as a pixel.

[0056] The conductive state or non-conductive state of the second transistor 100 is selected by the wiring WL or the wiring BG The potential applied to the wiring WL or the wiring BG can be used to control the The threshold voltage of the second transistor 100 can be controlled by By using a transistor with a small off-state current as the transistor 100, The potential of the node FN in the semiconductor device can be maintained for a long period of time. This reduces the refresh frequency of the device, making it possible to manufacture a semiconductor device with low power consumption. As an example of a transistor with low off-state current, Examples of such transistors include those using semiconductors.

[0057] A constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent current of the second transistor 100 is changed by the potential of the node FN. The apparent threshold voltage fluctuates. This fluctuation in the apparent threshold voltage causes the first transistor 11 0, the conductive state and non-conductive state of the node FN are changed, and the potential information stored in the node FN is can be read out as data.

[0058] The potential held at node FN is 3.15×10 8 seconds) In order to maintain the capacitance, the off-state current per 1 μF of capacitance and per 1 μm of transistor channel width is The current value is 4.3yA (1yA is 10 -24 A) is preferably less than At this time, it is preferable that the allowable fluctuation in the potential of the node FN is within 0.5 V. Alternatively, the off-state current is preferably less than 1.5 yA at 95° C. In the semiconductor device according to the present invention, the hydrogen concentration in the layer below the barrier layer is sufficiently reduced. As a result, the transistor using an oxide semiconductor as the upper layer has such an extremely low onset voltage. A floating current can be realized.

[0059] In addition, the S value (subthreshold value) of a transistor using an oxide semiconductor is 66m V / dec. or more, preferably 60mV / dec. or more, more preferably 50mV / dec. or more. c. or more, and 200 mV / dec. or less, preferably 150 mV / dec. or less, More preferably, it is 100 mV / dec. or less, and further preferably, it is 80 mV / dec. or less. The smaller the S value, the greater the off-state current at a specific voltage at which the transistor is turned off. The current can be reduced.

[0060] By arranging the semiconductor device shown in FIG. 2A in a matrix, a memory device (memory cell It is possible to configure a

[0061] FIG. 2B shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG. vinegar.

[0062] The semiconductor device includes a first transistor 110, a second transistor 100, and a capacitor 13. 0. The second transistor 100 is provided above the first transistor 110, A barrier layer 120 is provided between the first transistor 110 and the second transistor 100. It is being done.

[0063] [First layer] The first transistor 110 is provided on a semiconductor substrate 111. The semiconductor layer 112, the gate insulating layer 114, the gate electrode 115, and the source region The gate electrode 113 has a low resistance layer 113a and a low resistance layer 113b which function as a drain region.

[0064] The first transistor 110 may be either a p-channel type or an n-channel type. Appropriate transistors may be used depending on the configuration and driving method.

[0065] The region in which the channel of the semiconductor layer 112 is formed and the region in the vicinity thereof, the source region or the drain region In the low resistance layer 113a and the low resistance layer 113b which become the drain region, a silicon-based semiconductor Preferably, the semiconductor includes a semiconductor such as silicon, and more preferably, the semiconductor includes single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). A structure using strained silicon for the crystal may be used. Alternatively, GaAs and AlGaAs, etc. By using the above, the first transistor 110 can be a HEMT (High Electron Transistor). Mobility Transistor).

[0066] The low resistance layer 113a and the low resistance layer 113b are formed of a semiconductor material applied to the semiconductor layer 112. In addition, elements that impart n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, are added. Contains elements that

[0067] The gate electrode 115 is made of an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon that contain elements that impart electrical conductivity of the type, metal materials, alloy materials, For the material, conductive materials such as metal oxide materials can be used. In particular, It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use a ten.

[0068] Here, the configuration including the first transistor 110 is the first layer 11 in the above-mentioned laminated structure. Corresponds to.

[0069] Here, the first transistor 110 is replaced with a transistor 16 as shown in FIG. 0 may be used. A cross section of a transistor 160 in the channel length direction is shown on the left side of FIG. The right side shows a cross section in the channel width direction. The semiconductor layer 112 (part of the semiconductor substrate) to be formed has a convex shape, and the side and top surfaces of the convex shape are A gate insulating layer 114 and a gate electrode 115 are provided. The transistor 160 is also called a FIN type transistor because it uses the protruding portion of the semiconductor substrate. In addition, an insulating layer is provided in contact with the upper portion of the protrusion and functions as a mask for forming the protrusion. In addition, the case where a protrusion is formed by processing a part of a semiconductor substrate is shown here. However, a semiconductor layer having a convex shape may be formed by processing an SOI substrate.

[0070] [First insulating layer] The first transistor 110 is covered with an insulating layer 121, an insulating layer 122, and an insulating layer 123. are stacked in order.

[0071] Insulating layer 121 is formed by insulating low-resistance layer 113a and low-resistance layer 113 during the manufacturing process of the semiconductor device. It functions as a protective film during heat treatment to activate the conductive elements added to b. If the insulating layer 121 is unnecessary, it does not have to be provided.

[0072] When the semiconductor layer 112 is made of a silicon-based semiconductor material, the insulating layer 122 is made of an insulating material containing hydrogen. The insulating layer 122 containing hydrogen is provided on the first transistor 110. By performing heat treatment, dangling of the semiconductor layer 112 is prevented by hydrogen in the insulating layer 122. The bonds are terminated, which can improve the reliability of the first transistor 110.

[0073] The insulating layer 123 is a step formed by the first transistor 110 and the like provided below. The upper surface of the insulating layer 123 functions as a planarizing layer that flattens the difference between the upper surface and the lower surface. Chemical Mechanical Polishing (CMP) method The surface may be planarized by a planarization process using a polishing agent or the like.

[0074] In addition, the insulating layers 121, 122, and 123 are provided with low resistance layers 113a and 113b. 13b, etc., and the gate electrode 11 of the first transistor 110. 5 and the like are embedded therein.

[0075] The structure including the insulating layer 121, the insulating layer 122, and the insulating layer 123 is the first in the above-mentioned laminated structure. This corresponds to the insulating layer 21.

[0076] [First wiring layer] On the upper portion of the insulating layer 123, a wiring 131, a wiring 132, a wiring 133, a wiring 134, etc. are provided. It is being done.

[0077] The wiring 131 is electrically connected to the plug 161. The wiring 133 is electrically connected to the plug 162. a portion of which also serves as a first electrode of the capacitor 130.

[0078] In this specification, the electrodes and the wiring electrically connected to the electrodes are integrated. That is, a part of the wiring may function as an electrode, or a part of the electrode may function as a wiring. In some cases, it may be possible.

[0079] Here, the configuration including the wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. is It corresponds to the first wiring layer 31 in the layer structure.

[0080] The material of the wiring 131, the wiring 132, the wiring 133, and the wiring 134 may be a metal material, an alloy material, or the like. A conductive material such as a gold material or a metal oxide material can be used. It is preferable to use high melting point materials such as tungsten and molybdenum, which have both high thermal conductivity and excellent thermal conductivity. It is preferable to use tungsten, particularly.

[0081] The wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. are embedded in the insulating layer 124. The insulating layer 124 is provided so as to be embedded in the wiring 131, the wiring 132, the wiring 133, and the wiring 1 The upper surface of each of 34 etc. is preferably planarized.

[0082] [Barrier Layer] The barrier layer 120 includes an insulating layer 124, a wiring 131, a wiring 132, a wiring 133, and a wiring 134. The barrier layer 120 is provided to cover the upper surfaces of the barrier layers 121 and 122 in the laminated structure. The material of the barrier layer 120 corresponds to the material of the barrier layer 41. Can be used.

[0083] The barrier layer 120 is a capacitance layer in the region where the wiring 133 and the wiring 142 (described later) overlap each other. It also functions as the dielectric layer of 130 .

[0084] The barrier layer 120 is an opening for electrically connecting the wiring 132 to a wiring 141 to be described later. and an opening for electrically connecting the wiring 134 to a wiring 142 described later. .

[0085] [Second wiring layer] On the barrier layer 120, a wiring 141, a wiring 142, etc. are provided. The configuration including 142 etc. corresponds to the second wiring layer 32 in the above-mentioned laminated structure.

[0086] The wiring 141 is electrically connected to the wiring 132 through an opening provided in the barrier layer 120. Part of the wiring 141 overlaps with a channel formation region of a second transistor 100 to be described later. The second gate electrode 110 functions as a second gate electrode of the second transistor 100 .

[0087] As shown in FIG. 4B, the second gate electrode of the second transistor 100 is Alternatively, a structure using wiring 132 may be used.

[0088] The wiring 142 is electrically connected to the wiring 134 through an opening provided in the barrier layer 120. The wiring 142 partially overlaps with the wiring 133 and functions as a second electrode of the capacitor 130. do.

[0089] Here, the materials constituting the wiring 141, wiring 142, etc. may be metal materials, alloy materials, or Conductive materials such as metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum for the conductive layer. Considering this, it is preferable to use a metal material or alloy material having a low resistance. , chromium, copper, tantalum, titanium, or other metal materials, or alloy materials containing such metal materials. They may be used in a single layer or in a laminated form.

[0090] In addition, the materials constituting the wiring 141, wiring 142, etc. include phosphorus, boron, carbon, nitrogen, Alternatively, it is preferable to use a metal oxide containing an element other than the main component, such as a transition metal element. Such metal oxides can achieve high electrical conductivity. For example, In-Ga oxides, In -Zn-based oxides, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, C Materials with enhanced electrical conductivity that contain the above elements in metal oxides such as Nd, Hf, etc. Furthermore, such metal oxides are difficult to permeate oxygen, so they can be used as a barrier. Covering the openings in the layer 120 with wiring 141, wiring 142, etc., including such a material. When the insulating layer 125 is heat-treated, the oxygen released from the insulating layer 125 is absorbed by the barrier layer 120. As a result, the diffusion of the ions from the insulating layer 125 downward can be suppressed. The amount of oxygen that can be supplied to the semiconductor layer of the second transistor 100 can be increased. .

[0091] As shown in FIG. 4A, the wiring 141 and the wiring 142 are formed at the same time. The wiring 141a and the wiring 141b may be provided by etching. 1b is connected to wiring 131, wiring 133, and the like.

[0092] The wiring 142 may not be connected to the wiring 134 but may be connected to another wiring. For example, as shown in FIG. 4B, the wiring 142 is connected to the electrodes 103a and 103b. It may be connected to the wiring 103c which is formed at the same time and etched at the same time.

[0093] [Second insulating layer] An insulating layer 125 is provided to cover the barrier layer 120, the wiring 141, the wiring 142, etc. Here, the region including the insulating layer 125 corresponds to the second insulating layer 22 in the above-mentioned laminated structure.

[0094] The upper surface of the insulating layer 125 is preferably planarized by the above-mentioned planarization treatment.

[0095] The insulating layer 125 is preferably made of an oxide material from which oxygen is partially released by heating. .

[0096] As an oxide material that releases oxygen by heating, It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When an oxide film containing oxygen is heated, some of the oxygen is released. The oxide film containing more oxygen than the The oxygen in terms of oxygen atoms was analyzed by Esorption Spectroscopy. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 at oms / cm 3 The oxide film is as above. Note that the surface temperature of the film during the TDS analysis was The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0097] For example, such a material may include silicon oxide or silicon oxynitride. It is preferable to use a metal oxide. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0098] [Second layer] A second transistor 100 is provided on top of the insulating layer 125. The configuration including the resistor 100 corresponds to the second layer 12 in the above-mentioned laminated structure.

[0099] The second transistor 100 includes a first oxide layer 101a in contact with the upper surface of the insulating layer 125 and The semiconductor layer 102 is in contact with the upper surface of the first oxide layer 101a, and the semiconductor layer 102 is in contact with the upper surface of the semiconductor layer 102. The electrodes 103a and 103b are spaced apart from each other in the region where they overlap the semiconductor layer 102, and the semiconductor layer A second oxide layer 101b is in contact with the upper surface of the second oxide layer 101b, and a gate insulating layer is formed on the second oxide layer 101b. The semiconductor layer 102 is connected to the edge layer 104 via the gate insulating layer 104 and the second oxide layer 101b. and a gate electrode 105 overlapping the second transistor 100. A layer 107, an insulating layer 108, and an insulating layer 126 are provided.

[0100] At least a part (or the whole) of the electrode 103a (and / or the electrode 103b) , the surface, side, etc. of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a) The surface is provided on at least a portion (or all) of the face, upper face, and / or lower face.

[0101] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a), In contact with at least a portion (or all) of the side, top, and / or bottom surfaces; or At least a part (or the whole) of the electrode 103a (and / or the electrode 103b) is a semiconductor. At least a portion of the semiconductor layer, such as the oxide layer 102 (and / or the first oxide layer 101a) or all of the above.

[0102] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a), Electrically connected to at least a part (or the whole) of the side, top, and / or bottom surfaces Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) ) is a part ( or all of the components.

[0103] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a), Located adjacent to at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) ) is a part ( or all of the above.

[0104] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a), It is disposed laterally on at least a portion (or all) of the side, top, and / or bottom surfaces. Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) , a part of the semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a) (or All are located to the side.

[0105] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a), The side, top, and / or bottom surface are at least partially (or entirely) arranged diagonally above the Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) ) is a part ( or all of them).

[0106] Or, at least a part (or all) of the electrode 103a (and / or the electrode 103b) The surface of a semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a), It is disposed on at least a portion (or all) of the side, top, and / or bottom surface. Alternatively, at least a part (or all) of the electrode 103a (and / or the electrode 103b) , a part of the semiconductor layer such as the semiconductor layer 102 (and / or the first oxide layer 101a) (or It is located at the top of all

[0107] The semiconductor layer 102 is made of a semiconductor such as a silicon-based semiconductor in a region where a channel is formed. In particular, the semiconductor layer 102 may include a material having a band gap larger than that of silicon. It is preferable that the semiconductor layer 102 contains an oxide semiconductor. A semiconductor material with a wider band gap and lower carrier density than silicon is called The use of such a compound is preferable because it can reduce the current in the off state of the transistor.

[0108] For example, the oxide semiconductor may contain at least indium (In) or zinc (Zn It is preferable that the oxide contains In-M-Zn (wherein M is Al, Ti, Metals such as Ga, Ge, Y, Zr, Sn, La, Ce or Hf) are included. nothing.

[0109] In particular, the semiconductor layer has a plurality of crystal parts, and the crystal parts have a c-axis aligned with a surface on which the semiconductor layer is formed. or oriented perpendicular to the upper surface of the semiconductor layer and having no grain boundaries between adjacent crystal portions. An oxide semiconductor film is preferably used.

[0110] By using such materials for the semiconductor layer, the fluctuation of electrical characteristics is suppressed, and reliability is improved. This allows for high-performance transistors.

[0111] Regarding preferred forms of oxide semiconductors applicable to the semiconductor layer and methods for forming the same, This will be explained in detail in a later embodiment.

[0112] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer and an insulating layer overlapping the oxide semiconductor layer. At least one metal element among metal elements constituting the oxide semiconductor layer is included between the It is preferable that the oxide semiconductor layer and the oxide layer contain the element. Therefore, it is possible to suppress the formation of trap levels at the interface between the semiconductor layer and the insulating layer that overlaps the semiconductor layer. Cut.

[0113] That is, one embodiment of the present invention is a method for forming an oxide semiconductor layer having a channel formation region The top and bottom surfaces function as barrier films for preventing the formation of interface states in the oxide semiconductor layer. It is preferable that the oxide layer is in contact with the oxide layer. The generation of oxygen vacancies and impurities that cause carrier generation in semiconductor layers and interfaces Since contamination can be suppressed, the oxide semiconductor layer can be made highly purified and intrinsic. The term "highly purified intrinsic" refers to making an oxide semiconductor layer intrinsic or substantially intrinsic. Therefore, a change in the electrical characteristics of a transistor including the oxide semiconductor layer can be suppressed, and a highly reliable semiconductor device can be obtained. It is thus possible to provide a conductor device.

[0114] Note that in the case of being substantially intrinsic in this specification and the like, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 By making the oxide semiconductor layer highly intrinsic, the transistor has stable electrical characteristics. It is possible to give the

[0115] The first oxide layer 101 a is provided between the insulating layer 125 and the semiconductor layer 102 .

[0116] The second oxide layer 101b is provided between the semiconductor layer 102 and the gate insulating layer 104. More specifically, the second oxide layer 101b has an upper surface that is in contact with the lower surface of the gate insulating layer 104. The lower surface of the electrode is in contact with the upper surfaces of the first electrode 103a and the second electrode 103b. It is set up as follows.

[0117] The first oxide layer 101a and the second oxide layer 101b are the same as the semiconductor layer 102. It includes oxides containing one or more metal elements.

[0118] The boundary between the semiconductor layer 102 and the first oxide layer 101a and the boundary between the semiconductor layer 102 and the second oxide layer 101b are The boundary of the oxide layer 101b may be unclear.

[0119] For example, the first oxide layer 101a and the second oxide layer 101b may be made of In or Ga. Representative examples include In-Ga oxide, In-Zn oxide, and In-M-Zn oxide. (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) and is a semiconductor A material having a conduction band lower end energy closer to the vacuum level than the semiconductor layer 102 is used. , the energy of the bottom of the conduction band of the first oxide layer 101a or the second oxide layer 101b. The difference between the energy of the conduction band of the semiconductor layer 102 and the energy of the bottom of the conduction band of the semiconductor layer 102 is 0.05 eV or more and 0.07 eV or more. V or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0. It is preferably 5 eV or less, or 0.4 eV or less.

[0120] A first oxide layer 101a and a second oxide layer 102 are provided to sandwich the semiconductor layer 102. The oxide layer 101b has a higher Ga content than the semiconductor layer 102 and functions as a stabilizer. By using the oxide, release of oxygen from the semiconductor layer 102 can be suppressed.

[0121] The semiconductor layer 102 is, for example, a layer of In:Ga:Zn=1:1:1 or 3:1:2. When an In-Ga-Zn oxide having a numerical ratio is used, the first oxide layer 101a or the second oxide layer The compound layer 101b may be, for example, In:Ga:Zn=1:3:2, 1:3:4, or 1:3:6. , 1:6:4, 1:6:8, 1:6:10, or 1:9:6 atomic ratios of In-G The semiconductor layer 102 and the first oxide layer 101 can be made of a-Zn oxide. The atomic ratios of the first oxide layer 101a and the second oxide layer 101b are calculated by subtracting the above atomic ratios from the atomic ratios as errors. The variation of the first oxide layer 101a and the second oxide layer 10 For 1b, materials having the same composition may be used, or materials having different compositions may be used.

[0122] In addition, when an In-M-Zn oxide is used as the semiconductor layer 102, the semiconductor layer 102 and The target used for forming the semiconductor film is a metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is 1 / 3 or less. z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, It is preferable to use an oxide having an atomic ratio of 1 to 6. In addition, when z1 / y1 is 6 or less, This makes it easier to form the CAAC-OS film described later. Representative examples of atomic ratios include In:M:Zn=1:1:1 and 3:1:2.

[0123] The first oxide layer 101a and the second oxide layer 101b are made of In-M-Zn oxide. When a material such as a fluorine-containing oxide is used, oxide films that become the first oxide layer 101a and the second oxide layer 101b are formed. The target used for forming the film has an atomic ratio of metal elements contained in the target of In: When M:Zn=x2:y2:z2, x2 / y2 <x1 / y1であり、z2 / y2 It is preferable to use an oxide having an atomic ratio of 1 / 3 to 6, preferably 1 to 6. It is preferable that the ratio z2 / y2 is 6 or less. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn=1: Examples include 3:4, 1:3:6, 1:3:8, etc.

[0124] In addition, the first oxide layer 101a and the second oxide layer 101b have a higher conductivity than the semiconductor layer 102. By using materials whose conduction band minimum energy is close to the vacuum level, the semiconductor layer 10 A channel is mainly formed in the semiconductor layer 2, and the semiconductor layer 102 becomes the main current path. The semiconductor layer 102 in which the channel is to be formed is covered with a first oxide layer 101a containing the same metal element and By sandwiching the first oxide layer 101b and the second oxide layer 101c, the generation of these interface states is suppressed. This improves the reliability of the electrical characteristics of the transistor.

[0125] However, the present invention is not limited to this, and the semiconductor characteristics and electrical characteristics (field effect The appropriate composition should be used depending on the required properties (mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the semiconductor layer 102, the first oxide layer 101a, and the The carrier density, impurity concentration, defect density, number of metal elements and oxygen atoms of the oxide layer 101b of 2 It is preferable to set the ratio, interatomic distance, density, etc. appropriately.

[0126] Here, the first oxide layer 101a is disposed between the first oxide layer 101a and the semiconductor layer 102. In some cases, the semiconductor layer 102 may have a mixed region of the second acid a and the semiconductor layer 102. Between the first oxide layer 101b and the second oxide layer 101b, there is a mixed region of the semiconductor layer 102 and the second oxide layer 101b. The mixed region has a low interface state density. The laminate of the semiconductor layer 102 and the second oxide layer 101b has a structure in the vicinity of the interface between the semiconductor layer 102 and the second oxide layer 101b. In this case, a band structure is formed in which the energy changes continuously (also called a continuous junction).

[0127] Here, the band structure will be described. For ease of understanding, the band structure is shown as follows: 25, the first oxide layer 101a, the semiconductor layer 102, the second oxide layer 101b and the gate The energy (Ec) of the conduction band minimum of the insulating layer 104 is shown.

[0128] As shown in FIG. 30(A) and FIG. 30(B), the first oxide layer 101a, the semiconductor layer 102 In the second oxide layer 101b, the energy of the conduction band minimum changes continuously. are elements constituting the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b. This is also because oxygen easily diffuses between the two materials due to their common properties. The first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b are stacked layers with different compositions. Although it is a layered structure, it can also be said to be physically continuous.

[0129] The oxide films that are laminated with the same main component are not simply laminated, but are bonded continuously ( Here, we specifically focus on a U-shaped well structure in which the energy of the conduction band edge changes continuously between layers. In other words, the layers are fabricated so that trap centers and recombination centers are formed at the interfaces of the layers. The stacked structure is formed so that there are no impurities that would create a defect level. When impurities are present between the layers of a multilayer film, the continuity of the energy bands is lost, and the boundaries At this surface, carriers disappear due to trapping or recombination.

[0130] In FIG. 30A, the Ec of the first oxide layer 101a and the second oxide layer 101b is Although the cases are similar, they may be different. For example, the first oxidation When the Ec of the second oxide layer 101b is higher than that of the oxide layer 101a, A part of the structure is shown in FIG.

[0131] As shown in FIG. 30(A) and FIG. 30(B), the semiconductor layer 102 serves as a well, and In the first embodiment, a channel is formed in the semiconductor layer 102. The oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b have an energy level at the bottom of the conduction band. Since the shape of the well changes continuously, it is also called a U-shaped well. In addition, a channel formed in this manner is also called a buried channel. can.

[0132] The first oxide layer 101a and the second oxide layer 101b are made of a silicon oxide film or the like. In the vicinity of the interface with the insulating film, trap levels due to impurities or defects can be formed. The first oxide layer 101a and the second oxide layer 101b form a semiconductor layer 102 and However, the first oxide layer 101a or the first oxide layer 101b can be separated from the trap level. When the energy difference between Ec of the oxide layer 101b of No. 2 and Ec of the semiconductor layer 102 is small, Electrons in the semiconductor layer 102 may exceed the energy difference and reach the trap level. When electrons that become the charge of the transistor are captured by the trap level, the threshold voltage of the transistor shifts in the positive direction.

[0133] Therefore, to reduce the variation in the threshold voltage of the transistor, the first oxide layer 10 An energy difference is set between Ec of the first oxide layer 101a and the second oxide layer 101b and the semiconductor layer 102. The respective energy differences are preferably 0.1 eV or more, and 0 .15 eV or higher is more preferred.

[0134] The first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 101b are made of crystalline In particular, the use of crystals oriented along the c-axis provides a stable transistor. It is possible to impart the desired electrical properties.

[0135] In addition, in the band structure shown in FIG. 30(B), the second oxide layer 101b is provided. First, an In-Ga oxide (for example, an In-Ga oxide having an atomic ratio of 100:1 or less) is formed between the semiconductor layer 102 and the gate insulating layer 104. In this case, In:Ga=7:93) may be used.

[0136] The semiconductor layer 102 has a higher electron density than the first oxide layer 101a and the second oxide layer 101b. For example, the semiconductor layer 102 is made of a first oxide layer 101. a and the second oxide layer 101b have an electron affinity of 0.07 eV or more and 1.3 eV or less; Preferably, the voltage is 0.1 eV or more and 0.7 eV or less, and more preferably, the voltage is 0.15 eV or more and 0.4 eV or less. V or less. The electron affinity is the energy between the vacuum level and the bottom of the conduction band. This is the difference between...

[0137] Here, the thickness of the semiconductor layer 102 is formed to be at least thicker than that of the first oxide layer 101a. It is preferable that the semiconductor layer 102 is thicker. In addition, the first oxide layer 101a can suppress the generation of an interface state of the semiconductor layer 102. For example, the thickness of the semiconductor layer 102 is set to be equal to or larger than the first thickness. The thickness of the oxide layer 101a is more than 1 time, preferably 2 times or more, and more preferably The on-state current of the transistor is preferably set to be 4 times or more, more preferably 6 times or more. However, this is not the case when it is not necessary to increase the thickness of the first oxide layer 101a. The thickness may be greater than or equal to that of 102 .

[0138] In addition, the second oxide layer 101b is also a semiconductor layer 102, similar to the first oxide layer 101a. It is sufficient if the thickness is such that the effect of suppressing the generation of interface states is not lost. For example, The thickness of the second oxide layer 101b may be equal to or less than that of the second oxide layer 101a. Otherwise, the electric field from the gate electrode 105 may not reach the semiconductor layer 102 easily. It is preferable that the second oxide layer 101b is formed thin. For example, the thickness of the semiconductor layer 102 is However, the thickness of the second oxide layer 101b is not limited to this, and the thickness of the second oxide layer 101b may be smaller than the gate insulating layer. Taking into consideration the withstand voltage of the insulating layer 104, the voltage at which the transistor is driven may be appropriately set. stomach.

[0139] Here, for example, the semiconductor layer 102 is an insulating layer having a different constituent element (for example, a silicon oxide film). When a semiconductor comes into contact with a material such as an insulating layer containing a metal, an interface state is formed at the interface between the material and the material. In such a case, a second transistor with a different threshold voltage may be formed. appears, and the apparent threshold voltage of the transistor may vary. In the transistor of this configuration, the semiconductor layer 102 contains one or more metal elements. Since the first oxide layer 101a is formed in the semiconductor layer 102, the first oxide layer 101a and the semiconductor layer 102 Therefore, by providing the first oxide layer 101a, it becomes difficult to form an interface state at the interface with the first oxide layer 101a. This makes it possible to reduce variations and fluctuations in the electrical characteristics of transistors, such as their threshold voltages. Cut.

[0140] In addition, when a channel is formed at the interface between the gate insulating layer 104 and the semiconductor layer 102, the Interface scattering can occur at the interface, reducing the field effect mobility of the transistor. However, in the transistor of this configuration, the semiconductor layer 102 is made of one or more metal elements. Since the second oxide layer 101b is formed on the semiconductor layer 102, the semiconductor layer 102 and the second oxide layer 101b are not uniform. Carrier scattering is less likely to occur at the interface with 01b, improving the field-effect mobility of the transistor. It can be made easier.

[0141] One of the electrodes 103a and 103b functions as a source electrode and the other functions as a drain electrode. It functions as a pole.

[0142] The electrode 103 a is connected to the wiring 13 through an opening provided in the insulating layer 125 and the barrier layer 120 . 1. The electrode 103b is electrically connected to the wiring 133 through a similar opening. Connect.

[0143] In FIG. 2B, the electrode 103a and the wiring 131, and the electrode 103b and the wiring 133 are connected in series. 3B, the insulating layer 125 and the barrier layer 12 The structure is such that the plugs 165 and 166 embedded in the . It may also be composed of.

[0144] The electrodes 103a and 103b are made of aluminum, titanium, chromium, nickel, copper, or indium. A metal consisting of tritium, zirconium, molybdenum, silver, tantalum, or tungsten. A single-layer or multi-layer structure is used, for example, of a solid metal or an alloy containing this metal as the main component. A single layer structure of aluminum film containing silicon, and a double layer structure of aluminum film laminated on titanium film A two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium-aluminum film, Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, A two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride film, and the titanium An aluminum film or a copper film is laminated on the silicon film or the titanium nitride film, and then an aluminum film or a copper film is laminated on the aluminum film or the copper film. Three-layer structure forming titanium film or titanium nitride film, molybdenum film or molybdenum nitride film Then, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There are three-layer structures, such as a layer of a molybdenum nitride film on top of the layer of a molybdenum nitride film. A transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0145] The gate insulating layer 104 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminate or a single layer.

[0146] The gate insulating layer 104 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), hafnium aluminium doped with nitrogen Luminate (HfAl x O y N z), using high-k materials such as yttrium oxide Good too.

[0147] Similarly to the insulating layer 125, the gate insulating layer 104 is made of an oxide having a stoichiometric composition. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0148] In addition, when a specific material is used for the gate insulating layer, electrons are captured in the gate insulating layer under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. For example, hafnium oxide, aluminum oxide, and oxide are mixed in the gate insulating layer. By using a material with many electron capture levels, such as tantalum, and by using a material that can withstand higher temperatures (the operating temperature of semiconductor devices), Or higher than the storage temperature, or 125°C to 450°C, typically 1 At a temperature of 50°C or higher and 300°C or lower, the potential of the gate electrode is set to the potential of the source electrode or drain electrode. By maintaining the higher temperature for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move toward the pole, some of which are captured by the electron capture level.

[0149] In this way, a transistor that has captured the necessary number of electrons at the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The treatment for adding the conductive layer may be performed during the manufacturing process of a transistor.

[0150] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After, or after the completion of the pre-process (wafer processing), or after the wafer dicing process It is advisable to carry out the inspection at any stage before shipment from the factory, after packaging, etc. It is preferred that the subsequent exposure to temperatures above 125° C. is not to be allowed for more than 1 hour.

[0151] The gate electrode 105 may be made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide The gate electrode 105 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a silicon layer on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride Two-layer structure with tungsten film laminated on the film, tantalum nitride film or tungsten nitride film A two-layer structure with a tungsten film laminated on top of the titanium film and an aluminum film on top of the titanium film. There are three-layer structures, such as a titanium film on top of the laminated aluminum. Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film made of one or more of the above metals or a nitride film may be used.

[0152] The gate electrode 105 is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0153] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 105 and the gate insulating layer 104. Conductor film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may have a thermal conductivity of 5 eV or more, preferably 5.5 eV or more. Since the work function of the oxide semiconductor is higher than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the FET can be shifted to the positive side, For example, an In-Ga-Zn oxynitride semiconductor can be used. When a semiconductor film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 102, specifically, 7 atomic % or more. The above In-Ga-Zn-based oxynitride semiconductor film is used.

[0154] The insulating layer 107, like the barrier layer 120, may be made of a material that is difficult for water and hydrogen to diffuse into. In particular, it is preferable to use a material that is difficult for oxygen to permeate as the insulating layer 107. It is nice.

[0155] By covering the semiconductor layer 102 with the insulating layer 107 containing a material that is difficult for oxygen to permeate, the semiconductor layer This can prevent oxygen from being released from 102 above the insulating layer 107. Furthermore, oxygen desorbed from the insulating layer 125 can be confined below the insulating layer 107. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 102 can be increased.

[0156] In addition, the insulating layer 107, which is difficult for water and hydrogen to permeate, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and the electrical characteristics of the second transistor 100 can be improved. This suppresses fluctuations in the capacitance, thereby achieving a highly reliable transistor.

[0157] In addition, below the insulating layer 107, there is a layer that, like the insulating layer 125, from which oxygen is desorbed by heating. An insulating layer is provided, and oxygen is supplied from the upper side of the semiconductor layer 102 through the gate insulating layer 104. This may also be configured.

[0158] Here, other configuration examples of a transistor applicable to the second transistor 100 will be described. Figure 5(A) is a schematic top view of the transistor shown below, and Figure 5(B) and Figure 5(C) are schematic top views of the transistor shown below. C) are cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in FIG. 5(A), respectively. FIG. 5(B) corresponds to a cross section in the channel length direction of a transistor, and FIG. C) corresponds to a cross section in the channel width direction of a transistor.

[0159] In FIG. 5, the gate insulating layer 1 is formed on the second transistor 100 shown in FIG. 04 and the top surface shape of the second oxide layer 101b approximately corresponds to the top surface shape of the gate electrode 105. 1 shows an example in which the same photomask is used for processing so that

[0160] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0161] As shown in FIG. 5C, in a cross section in the channel width direction of the transistor, The contact electrode 105 is provided on the upper surface and the side surface of the semiconductor layer 102, The channel is formed not only near the top surface of 2 but also near the side surface, increasing the effective channel width. In addition, the current in the on-state (on-state current) can be increased. The width is extremely small (e.g., 50 nm or less, preferably 30 nm or less, more preferably 20 nm or less), the region in which the channel is formed extends into the semiconductor layer 102. Therefore, the contribution to the on-current increases as the size decreases.

[0162] The transistors shown in FIGS. 6A and 6B have the following features in comparison with the transistor shown in FIG. A second oxide layer 101b is provided in contact with the lower surfaces of the electrodes 103a and 103b. The main difference is in one point.

[0163] With this structure, the first oxide layer 101a, the semiconductor layer 102, and the second oxide layer 103 are During the deposition of each film constituting the oxide layer 101b, the films were continuously deposited without being exposed to the air. Since the films can be formed successively, defects at the interfaces can be reduced.

[0164] In the above, the first oxide layer 101a and the second oxide layer 102 are in contact with the semiconductor layer 102. The configuration in which the first oxide layer 101a or the second oxide layer 101b is provided has been described. One or both of 1b may be omitted.

[0165] In FIGS. 7(A) and 7(B), the first oxide layer 101a and the second oxide layer 101b are not provided. 8A and 8B show an example in which the first oxide layer 101a is not provided. 9A and 9B show an example in which the second oxide layer 101b is not provided. 1 shows an example in which the second oxide layer 101b is provided and the first oxide layer 101a is not provided. is.

[0166] In the configurations shown in FIGS. 5 to 9, the upper surface shape of the gate insulating layer 104 is the gate electrode This shows the case where the part is processed so as to roughly match 105, but this is not limited to this. At least in the region overlapping with the semiconductor layer 102, the gate electrode 1 is located inside the gate insulating layer 104. Even when the second oxide layer 101b is provided, The second oxide layer 101b has a different top surface shape from that of the gate electrode 105 and the gate insulating layer 104. Examples of such a case are shown in Figures 10, 11, and 12.

[0167] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum value, minimum value, and The value is the average value.

[0168] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the gate electrode (where the current flows) or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum value, minimum value, and maximum value in the region where the channel is formed. The value is the average value.

[0169] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0170] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0171] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is defined as the "surrounded channel width (SCW)". In this specification, when it is simply referred to as the channel width, In some cases, this refers to the enclosed channel width or apparent channel width. In the detailed description, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, enclosure The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. , values ​​can be determined.

[0172] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0173] The above is the description of the second transistor 100.

[0174] In FIG. 2B etc., the insulating layer 126 covering the second transistor 100 is The insulating layer 108 functions as a planarizing layer that covers the convex shape. The insulating layer 108 may have a function as a protective film when the insulating layer 108 is formed. Good too.

[0175] The insulating layer 107, the insulating layer 108, and the insulating layer 126 are electrically connected to the electrode 103a. A plug 163 and a plug 164 electrically connected to the gate electrode 105 are buried. .

[0176] On the upper portion of the insulating layer 126, a wiring 151 electrically connected to the plug 163 and a plug 164 are provided. Wiring 152 and the like are provided for electrically connecting to the above.

[0177] Here, in FIG. 2B, the wiring 151 corresponds to the wiring BL shown in FIG. Similarly, the wiring 152 corresponds to the wiring WL, the wiring 134 corresponds to the wiring CL, and the wiring 132 corresponds to the wiring WL. The gate electrode 115 of the first transistor 110 and the first the wiring 133 which functions as an electrode of the second transistor 100 and the electrode 103b of the second transistor 100 The node corresponds to node FN shown in FIG.

[0178] A semiconductor device according to one embodiment of the present invention includes a first transistor 110 and Since the second transistor 100 is located above the first transistor 100, these are stacked. This allows the area occupied by the element to be reduced. The barrier layer 120 provided between the first transistor 100 and the second transistor 100 prevents the This can prevent impurities such as water and hydrogen present in the second transistor 100 from diffusing to the second transistor 100 side. Furthermore, a wiring 133, a part of which functions as a first electrode, is disposed across the barrier layer 120. A wiring 142, a part of which functions as a second electrode, is provided to form a capacitor 130. The volume 130 can be easily produced without adding a separate process for producing the volume 130. can be done.

[0179] As shown in FIG. 3C, a hydrogen-containing insulating layer 122 is formed on the insulating layer 122 in the same manner as the barrier layer 120. The insulating layer 140 may be formed by using the above-mentioned material. The upward diffusion of water and hydrogen remaining in the insulating layer 122 containing silicon is effectively suppressed. In this case, the insulating layer 140 may be formed before and after the insulating layer 140 is formed. Before forming the barrier layer 120, a heat treatment for removing water and hydrogen is performed twice in total. It is preferable to carry out the above steps.

[0180] The above is a description of configuration example 1.

[0181] [Configuration example 2] Below, a configuration example partially different from the above-mentioned configuration example 1 will be described with reference to the drawings. In the following, explanations of parts that overlap with those described above may be omitted.

[0182] FIG. 13 shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG.

[0183] The semiconductor device shown in FIG. 13 includes a first transistor 110, a second transistor 100, and a capacitance 130. The second transistor 100 is disposed above the first transistor 110. A barrier layer 1 is provided between the first transistor 110 and the second transistor 100. 20 are provided.

[0184] The semiconductor device shown in FIG. 13 has a capacitance of 130 μm compared to the semiconductor device shown in FIG. The main difference is that the configuration of the wiring 133 is different. The wiring 134 functions as one of a pair of electrodes of the capacitor 130. The wiring 133 and the wiring 142 are electrically connected to each other through openings provided in the layer 125. The wiring 134 and the wiring 142 have an overlapping area, and a capacitance 130 is formed. is.

[0185] That is, in the configuration illustrated in FIG. 2B, the barrier layer of the pair of electrodes of the capacitor 130 The wiring (wiring 133) arranged below 120 (on the first transistor 110 side) is 13, the barrier layer 120 is a part of the barrier FN. The wiring (wiring 142) arranged on the upper side (the second transistor 100 side) is a node FN. The main difference between the two is in the way they are structured.

[0186] As shown in FIG. 14A, the wiring 141 and the wiring 142 are formed at the same time. Alternatively, wiring 141a and wiring 141b may be provided, which are etched in the direction perpendicular to the surface of the substrate 141. 41b is connected to the wiring 131, the wiring 133, and the like.

[0187] As shown in FIG. 14B, the second gate electrode of the second transistor 100 is In addition, as shown in FIG. 14B, the electrode 103 may be provided. Alternatively, b may be connected to the wiring 134 instead of the wiring 142 .

[0188] In FIG. 13, the electrode 103a and the wiring 131, the electrode 103b and the wiring 133, and the electrode In the illustrated embodiment, the wiring 142 and the 103b are in contact with each other. The plugs 165 and 166 embedded in the insulating layer 125 and the barrier layer 120 167 or the like may be used to electrically connect them.

[0189] A semiconductor device according to one embodiment of the present invention includes a first transistor 110 and Since the second transistor 100 is located above the first transistor 100, these are stacked. This allows the area occupied by the element to be reduced. The barrier layer 120 provided between the first transistor 100 and the second transistor 100 prevents the This can prevent impurities such as water and hydrogen present in the second transistor 100 from diffusing to the second transistor 100 side. Furthermore, a wiring 134, a part of which functions as a first electrode, is disposed across the barrier layer 120. A wiring 142, a part of which functions as a second electrode, is provided to form a capacitor 130. The volume 130 can be easily produced without adding a separate process for producing the volume 130. can be done.

[0190] As shown in FIG. 15B, a hydrogen-containing insulating layer 122 is formed on the barrier layer 120. Alternatively, an insulating layer 140 containing a material similar to that described above may be provided. The upward diffusion of water and hydrogen remaining in the insulating layer 122 containing hydrogen is effectively suppressed. In this case, the insulating layer 140 may be formed before and after the insulating layer 140 is formed. Before forming the barrier layer 120, a total of two heat treatments were performed to remove water and hydrogen. It is preferable to carry out the above process at least once.

[0191] FIG. 16 is a schematic cross-sectional view of a semiconductor device having a configuration partially different from that of FIG. 13. In the semiconductor device, a part of the wiring 142 is connected to the wiring 13 through an opening provided in the barrier layer 120. 3. The electrode 103b of the second transistor 100 is electrically connected to the wiring 133. The insulating layer 125 is electrically connected to the wiring 142 through an opening in the insulating layer 125 provided in the area where the insulating layer 125 overlaps the wiring 142. That is, the electrode 103b and the wiring 103a are formed in a region overlapping one of the openings provided in the insulating layer 125. The wire 142 and the wiring 133 are electrically connected to each other. This makes it possible to reduce the number of openings to be formed in the insulating layer 125, thereby reducing the occupation area of ​​the semiconductor device. The area can be further reduced.

[0192] The above is an explanation of configuration example 2.

[0193] [Configuration example 3] The following describes a configuration example of a semiconductor device that is partially different from the above configuration examples 1 and 2. The following description will be given with reference to the drawings. Note that the following description will be omitted for the parts that overlap with the above description. It may be omitted.

[0194] FIG. 17A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device shown in FIG. 2A has a second transistor 10. The difference is that the second gate of 0 is electrically connected to the wiring CL instead of the wiring BG. do.

[0195] FIG. 17B shows an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. Shows.

[0196] The semiconductor device shown in FIG. 17B includes a first transistor 110 and a second transistor 1 00, and a capacitance 130. The second transistor 100 is connected to the first transistor 110. A variance is provided between the first transistor 110 and the second transistor 100. A layer 120 is provided.

[0197] The semiconductor device shown in FIG. 17B has a capacitance smaller than that of the semiconductor device shown in FIG. The main difference is that the configuration of the wiring 130 and its surroundings is different. The wiring 133 and the wiring 141 are not provided. The barrier layer 120 has an overlapping area, forming a capacitance 130. In the area where the corresponding wiring 141 overlaps, the insulating layer 142 also functions as a dielectric layer for the capacitor 130 .

[0198] That is, the capacitor 130 overlaps with the second transistor 100 and is provided below it. Specifically, at least the channel formation of the semiconductor layer 102 of the second transistor 100 A wiring 133 that overlaps the region and functions as a first electrode of the capacitor 130 and a capacitor 13 The barrier layer 120 is sandwiched between the wiring 141 and the second electrode 142. The capacitor 130 and the second transistor 10 are connected to each other. By providing overlapping 0, it is possible to effectively reduce the area occupied by the semiconductor device. do.

[0199] Here, in FIG. 17B, the wiring 151 corresponds to the wiring BL shown in FIG. Similarly, the wiring 152 corresponds to the wiring WL, and the wiring 132 corresponds to the wiring CL. A gate electrode 115 of the transistor 110 and a wiring 1 functioning as a first electrode of the capacitor 130 33, and a node including the electrode 103b of the second transistor 100 is shown in FIG. This corresponds to node FN.

[0200] A semiconductor device according to one embodiment of the present invention includes a first transistor 110 and Since the second transistor 100 is located above the first transistor 100, these are stacked. This allows the area occupied by the element to be reduced. The barrier layer 120 provided between the first transistor 100 and the second transistor 100 prevents the This can prevent impurities such as water and hydrogen present in the second transistor 100 from diffusing to the second transistor 100 side. Furthermore, a wiring 133, a part of which functions as a first electrode, is disposed across the barrier layer 120. A wiring 141, a part of which functions as a second electrode, is provided to form a capacitor 130. The volume 130 can be easily produced without adding a separate process for producing the volume 130. can be done.

[0201] As shown in FIG. 18, the wiring 141 and the insulating film 142 are formed and etched at the same time. Wiring 141a and wiring 141b may be provided. 1, and is connected to wiring 133, etc.

[0202] In FIG. 17B, the electrode 103a and the wiring 131, and the electrode 103b and the wiring 133 are 19A, the insulating layer 125 and the barrier layer 126 are in contact with each other. 120, plugs 165 and 166 are embedded in the The configuration may be such that:

[0203] 19B, a hydrogen-containing insulating layer 122 is formed on the barrier layer 120. Alternatively, an insulating layer 140 containing a material similar to that described above may be provided. The upward diffusion of water and hydrogen remaining in the insulating layer 122 containing hydrogen is effectively suppressed. In this case, the insulating layer 140 may be formed before and after the insulating layer 140 is formed. Before forming the barrier layer 120, a total of two heat treatments were performed to remove water and hydrogen. It is preferable to carry out the above process at least once.

[0204] FIG. 20A shows a circuit diagram of a semiconductor device having a structure partially different from that of FIG.

[0205] The semiconductor device shown in FIG. 20A has a third transistor 180. The wiring BL1 and the wiring BL2 are included instead of the wiring BL, and the wiring W is included instead of the wiring WL. The main difference is that it has wiring L1 and wiring WL2.

[0206] The third transistor 180 has a gate electrically connected to the wiring WL2 and a source or drain One of the drains is electrically connected to the other of the source or drain of the first transistor 110. The other of the source and the drain is electrically connected to the wiring BL2. 100 is a gate that is electrically connected to the wiring WL1 instead of the wiring WL, and a source or drain The other one is electrically connected to the wiring BL1 instead of the wiring BL.

[0207] FIG. 20B is a schematic cross-sectional view of a semiconductor device that can be applied to the circuit of FIG. 20A. In FIG. 20B, the third transistor 180 is the same as the first transistor 110. In addition, compared to the configuration of FIG. 17(B), the second transistor The difference is that the electrode 103a of the transistor 100 is not electrically connected to the wiring 131. .

[0208] In the semiconductor device shown in FIG. 20B, the wiring 152 corresponds to the wiring WL1, and the wiring 15 The wiring 131 corresponds to the wiring BL2. A gate electrode 180 or a wiring (not shown) electrically connected to the gate electrode is provided. Corresponds to line WL2.

[0209] With this structure, part of the wiring 141 is connected to the second It is used as a gate to provide a potential for controlling the threshold voltage of the second transistor 100. In this case, the influence of the potential on the wiring 141 is larger than the influence of the potential on the wiring BL2 for reading data. It is possible to suppress the influence on the position.

[0210] The above is an explanation of configuration example 3.

[0211] [Production method example 1] An example of a method for manufacturing the semiconductor device shown in the above Configuration Example 1 will be described below with reference to FIGS. This will be explained using 23.

[0212] First, a semiconductor substrate 111 is prepared. The semiconductor substrate 111 is, for example, a single crystal silicon. Silicon substrates (including p-type semiconductor substrates and n-type semiconductor substrates), silicon carbide and gallium nitride A compound semiconductor substrate made of silicon can be used. In the following description, a single crystal silicon substrate is used as the semiconductor substrate 111. The case where the above formula is used will be described.

[0213] Next, an element isolation layer (not shown) is formed on the semiconductor substrate 111. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh The insulating layer 11 may be formed by using a method such as a trench isolation method.

[0214] When forming p-type transistors and n-type transistors on the same substrate, the semiconductor substrate 1 An n-well or p-well may be formed in a part of the semiconductor substrate 11. For example, 1 is doped with impurity elements such as boron that give it p-type conductivity to form a p-well, An n-type transistor and a p-type transistor may be formed on the substrate.

[0215] Next, an insulating film that will become the gate insulating layer 114 is formed on the semiconductor substrate 111. For example, The surface of the semiconductor substrate 111 is oxidized to form a silicon oxide film. After the silicon oxide film is formed, a nitriding process is performed to nitride the surface of the silicon oxide film. In this way, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed. Alternatively, silicon oxide, silicon oxynitride, or high-dielectric-constant materials (also called high-k materials) Tantalum oxide, hafnium oxide, hafnium silicate oxide, zirconium oxide, Metal oxides such as aluminum oxide, titanium oxide, or rare earth oxides such as lanthanum oxide Objects etc. may also be used.

[0216] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition) sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) method Alternatively, the film may be formed by a film formation method such as a (ion) method.

[0217] Next, a conductive film that will become the gate electrode 115 is formed. Metals selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. The polycrystalline silicon to which the impurity is added can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. This can improve adhesion and prevent peeling.

[0218] Conductive films are formed by sputtering, deposition, CVD (thermal CVD, MOCVD, PEC It is possible to form a film by a method such as VD method. It also reduces damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferable.

[0219] Next, a resist mask is formed on the conductive film by photolithography or the like. The unnecessary portion of the conductive film is removed. Then, the resist mask is removed to reveal the gate. A contact electrode 115 can be formed.

[0220] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, A method of slimming the resist mask may be used. A dummy pattern was formed by a raffin method or the like, and a sidewall was formed on the dummy pattern. After that, the dummy pattern is removed, and the remaining sidewall is used as a resist mask. The film to be processed may be etched. In addition, the etching of the film to be processed may be performed using a method for etching a film having a high aspect ratio. In order to achieve this, it is preferable to use anisotropic dry etching. Alternatively, a hard mask made of a metal film may be used.

[0221] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6 nm), H-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Also, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Instead of light for exposure, electron beams can be used. Extreme ultraviolet light, X-rays, or The use of an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0222] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. The organic resin film may be, for example, By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce the variation in thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is required to have a high resistance to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0223] After the gate electrode 115 is formed, a sidewall is formed to cover the side surface of the gate electrode 115. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 115, and then Anisotropic etching is performed to leave the insulating film only on the side of the gate electrode 115. It can be formed by:

[0224] When the sidewalls are formed, the insulating film that will become the gate insulating layer 114 is also etched at the same time. As a result, a gate insulating layer 114 is formed under the gate electrode 115 and the sidewalls. Alternatively, after the gate electrode 115 is formed, the gate electrode 115 or the gate electrode 11 The insulating film is etched using a resist mask for processing 5 as an etching mask. Alternatively, the insulating film may be etched to form the gate insulating layer 114. Alternatively, the gate insulating layer 114 may be directly used without being subjected to a etching process.

[0225] Next, the gate electrode 115 (and sidewalls) of the semiconductor substrate 111 are provided. In the area where there is no n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, is added. The element to be added is added. The cross-sectional schematic diagram at this stage corresponds to Figure 21(A).

[0226] Next, after forming the insulating layer 121, the above-mentioned element for imparting conductivity is activated. A first heat treatment is carried out.

[0227] The insulating layer 121 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Silicon, Aluminum Oxide, Aluminum Oxynitride, Aluminum Oxide Nitride, Aluminum Nitride The insulating layer 121 is formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by using a PLD method or the like. In particular, the insulating film can be formed by using a CVD method, preferably Alternatively, it is preferable to form the film by a plasma CVD method, since the coating property can be improved. In order to reduce damage caused by plasma, it is necessary to use thermal CVD, MOCVD or A The LD method is preferred.

[0228] The first heat treatment is performed under an inert gas atmosphere such as a rare gas or nitrogen gas, or under a reduced pressure atmosphere. The heating can be performed at a temperature of, for example, 400° C. or higher but below the strain point of the substrate.

[0229] At this stage the first transistor 110 is formed.

[0230] Subsequently, the insulating layer 122 and the insulating layer 123 are formed.

[0231] The insulating layer 122 may be made of a material that can be used for the insulating layer 121, or a nitrogen-containing material that contains oxygen and hydrogen. By using silicon oxynitride (SiNOH), the amount of hydrogen released by heating can be increased. In addition, the insulating layer 123 is preferably made of a material that can be used for the insulating layer 121. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or Silicon oxide with good step coverage formed by reacting silane with oxygen or nitrous oxide. It is preferable to use the element.

[0232] The insulating layer 122 and the insulating layer 123 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, (including MOCVD, PECVD, etc.), MBE, ALD, or PLD methods, etc. In particular, the insulating layer can be formed by a CVD method, preferably a plasma CVD method. Therefore, it is preferable to form a film by using plasma, since the covering property can be improved. To reduce damage, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

[0233] Then, the upper surface of the insulating layer 123 is planarized by using a CMP method or the like.

[0234] Then, the dangling bonds in the semiconductor layer 112 are desorbed from the insulating layer 122 by hydrogen. The second heat treatment is then performed to terminate the layers. By desorbing the water and hydrogen contained in the fuel, the water and hydrogen contents can be reduced.

[0235] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above.

[0236] Next, the low resistance layer 113a and the low resistance layer 113b are formed on the insulating layer 121, the insulating layer 122, and the insulating layer 123. An opening is formed that reaches the layer 113b and the gate electrode 115. Then, a A conductive film is formed on the insulating layer 123, and a planarization treatment is performed on the conductive film so that the upper surface of the insulating layer 123 is exposed. By this, plugs 161 and 162 are formed. The conductive film is formed by, for example, sputtering. deposition method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method The film can be formed by using an ALD method, a PLD method, or the like.

[0237] Next, a conductive film is formed on the insulating layer 123. After that, a resist is formed by the same method as above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the quartz, wiring 131, wiring 132, wiring 133, wiring 134, etc. are formed. It is possible.

[0238] Next, an insulating film is formed to cover the wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. Then, a flattening process is performed so that the upper surfaces of the wirings are exposed, thereby forming an insulating layer 124. The schematic cross-sectional view at this stage corresponds to FIG.

[0239] The insulating film that becomes the insulating layer 124 is formed from the same material and by the same method as the insulating layer 121, etc. This can be done.

[0240] After the insulating layer 124 is formed, a third heat treatment is preferably performed. This allows the water and hydrogen contained in each layer to be desorbed, thereby reducing the water and hydrogen content. A third heat treatment is performed immediately before forming the barrier layer 120 described later, and the barrier layer After thoroughly removing hydrogen and water contained in the layers below 120, the barrier layer 120 is formed. By doing so, water and hydrogen will not diffuse again below the barrier layer 120 in a later process. can be suppressed.

[0241] The third heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above.

[0242] Next, a barrier layer is formed on the insulating layer 124, the wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. The rear layer 120 is formed (FIG. 21(C)).

[0243] The barrier layer 120 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, (including PECVD, etc.), MBE, ALD, PLD, etc. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. This is preferable because it can improve the coating property. In addition, it is possible to reduce damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferable.

[0244] After the barrier layer 120 is formed, a process for removing water and hydrogen contained in the barrier layer 120 is performed. A heat treatment may be carried out.

[0245] Next, a resist mask is formed on the barrier layer 120 by the same method as described above. The unnecessary portions of the photoresist layer 120 are removed by etching. The resist mask is then removed. As a result, openings reaching the wiring 132 and the wiring 134 are formed.

[0246] Next, a conductive film is formed on the barrier layer 120, and then a resist mask is formed on the conductive film by the same method as described above. Then, a resist mask is formed and unnecessary portions of the conductive film are removed by etching. By removing the wiring 141 and the wiring 142, etc. can be formed (FIG. 21( D)).

[0247] At this stage, the capacitor 130 is formed. The capacitor 130 has a portion that functions as a first electrode. A wiring 133 that functions as a second electrode, a wiring 142 that functions as a second electrode, and a barrier sandwiched between them. It is composed of a rear layer 120 .

[0248] Next, the insulating layer 125 is formed.

[0249] The insulating layer 125 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using methods such as ECVD, MBE, ALD, or PLD. In particular, the insulating layer can be formed by a CVD method, preferably a plasma CVD method. This is preferable because it can improve the coverage and reduce damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferred.

[0250] In order to make the insulating layer 125 contain excess oxygen, for example, the insulating layer 125 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating layer 125 after the film formation to make the insulating layer 125 contain excess oxygen. Alternatively, a region having either of these may be formed, or both approaches may be combined.

[0251] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen ions) may be added to the insulating layer 125 after the film formation. A region containing excess oxygen is formed by introducing oxygen into the film. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0252] In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas.

[0253] After the insulating layer 125 is formed, the CMP method or the like is used to improve the flatness of the upper surface. A flattening process may also be performed.

[0254] Next, an oxide film that will become the first oxide layer 101a and a semiconductor film that will become the semiconductor layer 102 are The oxide film and the semiconductor film are formed in succession without being exposed to the air. It is preferable.

[0255] After the oxide film and the semiconductor film are formed, a fourth heat treatment is preferably performed. At a temperature of 250°C to 650°C, preferably 300°C to 500°C, inert gas The treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The heat treatment atmosphere is an inert gas atmosphere, and then oxygen is added to replenish the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more. The process may be performed immediately after the semiconductor film is processed to form the island-shaped semiconductor layer 102. By the heat treatment, oxygen is supplied from the insulating layer 125 or the oxide film to the semiconductor film, and the semiconductor The oxygen vacancies in the conductive film can be reduced.

[0256] After that, a resist mask is formed on the semiconductor film by the same method as above, and the semiconductor film and the acid are The unnecessary portions of the oxide film are removed by etching. The resist mask is then removed. As a result, a laminated structure of island-shaped first oxide layers 101a and island-shaped semiconductor layers 102 is formed. This can be done (Figure 22(A)).

[0257] As shown in FIG. 22A, when the oxide film and the semiconductor film are etched, the insulating layer A part of 125 is etched and covered with the first oxide layer 101a and the semiconductor layer 102. The insulating layer 125 may thin in the areas where the etching is not performed. In order to prevent the insulating layer 125 from disappearing due to the heat, it is preferable to form the insulating layer 125 thick in advance. It is nice.

[0258] Next, the wiring 131 and the barrier layer 120 are formed on the insulating layer 125 and the barrier layer 120 in the same manner as described above. An opening reaching the wiring 133 and the like is formed.

[0259] Next, a conductive film is formed, and a resist mask is formed on the conductive film by the same method as described above. Then, unnecessary portions of the conductive film are removed by etching. Then, the resist mask is removed. In this way, the electrodes 103a and 103b can be formed (FIG. 22B).

[0260] The conductive film is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using methods such as ECVD, MBE, ALD, or PLD. In particular, the conductive film is formed by a CVD method, preferably a plasma CVD method. This is preferable because it can improve the coverage and reduce damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferred.

[0261] Here, when the conductive film is etched, a part of the upper part of the semiconductor layer 102 and the insulating layer 125 is etched. The portions not overlapping with the electrodes 103a and 103b may become thin. Therefore, the thickness of the semiconductor film or the like that will become the semiconductor layer 102 is determined in consideration of the etching depth. It is preferable to form the insulating layer 11 thick in advance.

[0262] Next, an oxide film, an insulating film, and a conductive film are sequentially laminated. A resist mask is formed on the conductive film by a method, and unnecessary portions of the conductive film are removed. The gate electrode 105 can be formed by removing the resist mask. A resist mask is similarly formed on the gate electrode 105 and the insulating film, and the insulating film and the oxide The unnecessary parts of the film are removed by etching, and the resist mask is removed to reveal the gate insulating film. The edge layer 104 and the second oxide layer 101b may be formed simultaneously.

[0263] As shown in FIG. 5, the upper surface of the gate insulating layer 104 and the second oxide layer 101b When the shape is formed so as to substantially match the top surface shape of the gate electrode 105, The insulating film and the oxide film are etched using a resist mask for forming the electrode 105. Alternatively, after forming the gate electrode 105 and removing the resist mask, the gate electrode 1 The insulating film and the oxide film can be etched using 05 as a hard mask.

[0264] At this stage the second transistor 100 is formed.

[0265] Next, the insulating layer 107 is formed (FIG. 22(C)). The insulating layer 107 is formed by, for example, sputtering. Ring method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, The insulating film can be formed by using the ALD method or the PLD method. When the film is formed by a method, preferably a plasma CVD method, the covering property can be improved. In order to reduce damage caused by plasma, thermal CVD, MOCVD, etc. Alternatively, the ALD method is preferred.

[0266] After the insulating layer 107 is formed, a fifth heat treatment is preferably performed. The oxygen is supplied to the semiconductor layer 102 from the layer 125, etc., to reduce oxygen vacancies in the semiconductor layer 102. At this time, the oxygen desorbed from the insulating layer 125 is absorbed into the barrier layer 120. and the insulating layer 107 , and the barrier layer 120 is below the insulating layer 107 . Since the oxygen does not diffuse to the upper layer, the oxygen can be effectively trapped. The amount of oxygen that can be supplied to the conductor layer 102 can be increased, and oxygen deficiency in the semiconductor layer 102 can be reduced. The loss can be effectively reduced.

[0267] Next, the insulating layer 108 and the insulating layer 126 are formed in this order (FIG. 23(A)). 8 and the insulating layer 126 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method) The method may be, for example, a PECVD method, an MBE method, an ALD method, or a PLD method. In particular, the insulating layer 107 can be formed by a CVD method, preferably a plasma CVD method. This is preferable because it is possible to improve the coating properties. To reduce the damage, the thermal CVD method, MOCVD method or ALD method is preferable. When organic insulating material such as organic resin is used as 126, a coating method such as spin coating is used. Alternatively, after the insulating layer 126 is formed, a planarization method may be used. It is preferable to carry out the treatment.

[0268] Next, in the same manner as above, the insulating layer 126, the insulating layer 108, and the insulating layer 107 are A plug 163 reaching the electrode 103a, a plug 164 reaching the gate electrode 105, etc. are formed. do.

[0269] Next, a conductive film is formed on the insulating layer 126. After that, a resist is formed by the same method as above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the pits, the wiring 151, the wiring 152, etc. can be formed (FIG. 23( B).

[0270] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0271] [Production method example 2] An example of a method for manufacturing the semiconductor device shown in the above Configuration Example 2 will be described below with reference to FIGS. 26. Note that the explanation of the same parts as in the above-mentioned Preparation Method Example 1 will be omitted. This may be the case.

[0272] First, an element isolation layer is formed on the semiconductor substrate 111. Then, the same method as above is used to A semiconductor layer 112, a gate insulating layer 114, and a gate electrode 115 are formed (FIG. 24(A)).

[0273] Next, after forming the insulating layer 121, a first heat treatment for activation is performed. The low resistance layers 113a and 113b are formed, thereby forming the first transistor 1. 10 is formed.

[0274] Next, the insulating layer 122 and the insulating layer 123 are formed, and the upper surface of the insulating layer 123 is polished by a CMP method or the like. Then, a second heat treatment is performed.

[0275] Next, the low resistance layer 113a and the low resistance layer 113b are formed on the insulating layer 121, the insulating layer 122, and the insulating layer 123. An opening reaching the layer 113b and the gate electrode 115 is formed, and then the plug 161 and the plug Next, the wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. are formed. After forming the insulating layer 124, the insulating layer 124 is formed (FIG. 24(B)). It is preferable to carry out the heat treatment of 3.

[0276] Next, a barrier layer is formed on the insulating layer 124, the wiring 131, the wiring 132, the wiring 133, the wiring 134, etc. After the barrier layer 120 is formed, the barrier layer 1 Heat treatment may be carried out to remove water and hydrogen contained in 20.

[0277] Next, an opening is formed in the barrier layer 120, which reaches the wiring 132, etc. Wiring 141, wiring 142, etc. are formed on the insulating film 10 (FIG. 24(D)).

[0278] At this stage, the capacitor 130 is formed. The capacitor 130 has a portion that functions as a first electrode. A wiring 134 is connected to the first electrode 132, a part of which functions as a second electrode 142 is connected to the second electrode 132, and a barrier 143 is sandwiched between the wiring 134 and the first electrode 142. It is composed of a rear layer 120 .

[0279] Subsequently, the insulating layer 125 is formed. After the insulating layer 125 is formed, the flatness of the upper surface of the insulating layer 125 is improved. In order to achieve this, a planarization process using a CMP method or the like may be performed.

[0280] Next, a laminate structure of an island-shaped first oxide layer 101a and an island-shaped semiconductor layer 102 is formed. (FIG. 25(A)). After the conductive film is formed, a fourth heat treatment is preferably performed.

[0281] Next, the wiring 131, the wiring 133, and the wiring 14 are formed on the insulating layer 125 and the barrier layer 120. Then, the electrodes 103a and 103b are formed (FIG. 2). 5(B)).

[0282] Next, the gate electrode 105, the gate insulating layer 104, and the second oxide layer 101b are formed. At this stage, the second transistor 100 is formed.

[0283] Next, the insulating layer 107 is formed (FIG. 25(C)). After the insulating layer 107 is formed, a fifth process is performed. It is preferable to carry out a heat treatment.

[0284] Next, the insulating layer 108 and the insulating layer 126 are formed in this order (FIG. 26(A)). After the layer 126 is formed, it is preferable to perform a planarization process on the upper surface. A plug 163 reaching the electrode 103a is formed in the edge layer 126, the insulating layer 108 and the insulating layer 107. A plug 164 reaching the port electrode 105 and the like are formed.

[0285] Next, the wiring 151, the wiring 152, etc. are formed (FIG. 26(B)).

[0286] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0287] [Production method example 3] An example of a method for manufacturing the semiconductor device shown in the above Configuration Example 2 will be described below with reference to FIGS. 29. Note that the same parts as those in the above-mentioned Preparation Method Example 1 and Preparation Method Example 2 will be described. In some cases, explanations may be omitted.

[0288] First, an element isolation layer is formed on the semiconductor substrate 111. Then, the same method as above is used to A semiconductor layer 112, a gate insulating layer 114, and a gate electrode 115 are formed (FIG. 27(A)).

[0289] Next, after forming the insulating layer 121, a first heat treatment for activation is performed. The low resistance layers 113a and 113b are formed, thereby forming the first transistor 1. 10 is formed.

[0290] Next, the insulating layer 122 and the insulating layer 123 are formed, and the upper surface of the insulating layer 123 is polished by a CMP method or the like. Then, a second heat treatment is performed.

[0291] Next, the low resistance layer 113a and the low resistance layer 113b are formed on the insulating layer 121, the insulating layer 122, and the insulating layer 123. An opening reaching the layer 113b and the gate electrode 115 is formed, and then the plug 161 and the plug Then, the wiring 131, the wiring 132, the wiring 133, etc. are formed. After that, the insulating layer 124 is formed (FIG. 27(B)). After the insulating layer 124 is formed, a third heat treatment is performed. It is preferable to carry out the above process.

[0292] Next, a barrier layer 12 is formed on the insulating layer 124, the wiring 131, the wiring 132, the wiring 133, etc. 0 is formed (FIG. 27(C)). After the barrier layer 120 is formed, A heat treatment may be carried out to remove water and hydrogen that are present in the mixture.

[0293] Next, an opening is formed in the barrier layer 120, which reaches the wiring 132, etc. Wiring 141 and the like are formed on the substrate 10 (FIG. 27(D)).

[0294] At this stage, the capacitor 130 is formed. The capacitor 130 has a portion that functions as a first electrode. A wiring 133 that functions as a second electrode, a wiring 141 that functions as a second electrode, and a barrier sandwiched between them. It is composed of a rear layer 120 .

[0295] Subsequently, the insulating layer 125 is formed. After the insulating layer 125 is formed, the flatness of the upper surface of the insulating layer 125 is improved. In order to achieve this, a planarization process using a CMP method or the like may be performed.

[0296] Next, a laminate structure of an island-shaped first oxide layer 101a and an island-shaped semiconductor layer 102 is formed. (FIG. 28(A)). An oxide film that becomes the first oxide layer 101a and a semiconductor film that becomes the semiconductor layer 102 are After the conductive film is formed, a fourth heat treatment is preferably performed.

[0297] Next, the insulating layer 125 and the barrier layer 120 are covered with the wiring 131 and the wiring 133. An opening is formed, and then the electrodes 103a and 103b are formed (FIG. 28(B)).

[0298] Next, the gate electrode 105, the gate insulating layer 104, and the second oxide layer 101b are formed. At this stage, the second transistor 100 is formed.

[0299] Next, the insulating layer 107 is formed (FIG. 28(C)). After the insulating layer 107 is formed, a fifth process is performed. It is preferable to carry out a heat treatment.

[0300] Next, the insulating layer 108 and the insulating layer 126 are formed in this order (FIG. 29(A)). After the layer 126 is formed, it is preferable to perform a planarization process on the upper surface. A plug 163 reaching the electrode 103a is formed in the edge layer 126, the insulating layer 108 and the insulating layer 107. A plug 164 reaching the port electrode 105 and the like are formed.

[0301] Next, the wiring 151, the wiring 152, etc. are formed (FIG. 29(B)).

[0302] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0303] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0304] (Embodiment 2) In this embodiment, a semiconductor layer of a semiconductor device according to one embodiment of the present invention can be preferably used. The oxide semiconductor will be described.

[0305] Oxide semiconductors have a large energy gap of 3.0 eV or more, making them suitable for The oxide semiconductor film obtained by processing the oxide semiconductor film under suitable conditions and sufficiently reducing the carrier density is applied. In a transistor with a low resistance, the leakage current between the source and drain in the off state (off current) can be made extremely low compared to conventional silicon-based transistors. .

[0306] The applicable oxide semiconductors include at least indium (In) or zinc (Zn It is particularly preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (e.g. , cerium (Ce), neodymium (Nd), gadolinium (Gd), or It is preferable that one or more kinds of the amine compound are contained.

[0307] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxides, In-Zr-Zn-based oxides, In-Ti-Zn-based oxides, In-Sc-Zn In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, I n-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga- Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, I An n-Hf-Al-Zn oxide can be used.

[0308] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0309] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer In addition, M is selected from Ga, Fe, Mn, and Co. A metal element or elements, or the above-mentioned stabilizer elements. In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0310] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A Or, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=2:1:3 and its composition It is preferable to use an oxide in the vicinity of the above.

[0311] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. This causes a transistor Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove the impurities to obtain a high purity so that the impurities are not included as much as possible.

[0312] Note that the oxide semiconductor film is dehydrated (dehydrogenated) to At the same time, oxygen may also decrease. A process to add oxygen to an oxide semiconductor to compensate for oxygen vacancies increased by the oxidation process. In this specification and the like, the case where oxygen is supplied to the oxide semiconductor film is preferably performed by heating. This may be referred to as oxygenation treatment, or oxygen contained in an oxide semiconductor film may be reduced to a value lower than the stoichiometric composition. When more oxygen is added, it is sometimes referred to as hyperoxygenation treatment.

[0313] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that the number of carriers derived from donors in the oxide semiconductor film is extremely small. (close to zero), carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below It says something.

[0314] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 85 1×10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V, 2V, or 3V less than the threshold voltage, , the transistor is turned off.

[0315] The structure of the oxide semiconductor film will be described below.

[0316] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal-Oxide Semiconductor Film). (stalline oxide semiconductor) film, polycrystalline oxide semiconductor The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0317] First, we will explain the CAAC-OS film.

[0318] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0319] Transmission Electron Microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of the CAAC-OS film was obtained by a microscope. (also called high-resolution TEM image) allows multiple crystals to be identified. On the other hand, the high-resolution TEM image also clearly shows the boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur.

[0320] A high-resolution TEM image of the cross section of the CAAC-OS film is observed from a direction roughly parallel to the sample surface. It can be seen that the metal atoms are arranged in layers in the crystal part. reflects the unevenness of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed) or the top surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0321] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. It was confirmed that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0322] FIG. 31(a) is a high-resolution TEM image of the cross section of the CAAC-OS film. b) is a high-resolution TEM image of a cross section of Fig. 31(a) enlarged for easier understanding. The atomic arrangement is highlighted to facilitate understanding.

[0323] Figure 31(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 31(a). From Fig. 31(c), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between the A-O and O-A' sections, so the different graphs are formed. The c-axis angles between the AOs are 14.3° and 16. 6°, 26.4°, and so on. Similarly, OA Between these, the c-axis angle gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0324] In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright points) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm is observed on the top surface of the CAAC-OS film. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See Figure 32(A)).

[0325] The high-resolution TEM images of the cross section and the plane show that the CAAC-OS film is crystalline. It can be seen that the part has orientation.

[0326] Most of the crystals in the CAAC-OS film are cubic with a side length of less than 100 nm. The size is small enough to fit inside the body. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This includes sizes that fit within a cube of less than 3 nm, 5 nm, or 5 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a high-resolution TEM image of a plane, 2 Below Top, 5μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0327] X-ray diffraction (XRD) of CAAC-OS film When the structure was analyzed using the device, for example, CAAC-OS with InGaZnO4 crystals was In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0328] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0329] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, it is clear that the direction of the lattice is the same as that confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in a layered fashion is parallel to the ab plane of the crystal.

[0330] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. For example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the face or top surface normal vector.

[0331] In addition, the distribution of the c-axis oriented crystal parts in the CAAC-OS film may not be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. The proportion of the impurity part may be increased. The region where the ZnO was added was altered, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0332] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0333] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor film. The elements that bond to oxygen stronger than the metal elements that form the oxide semiconductor film, such as Zn, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Since the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor film, the oxide semiconductor film The impurities contained in the oxide semiconductor film are disturbed, which causes a decrease in crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0334] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0335] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small carrier generation source, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) in which the threshold voltage is negative. It is also called "marine". It is rare for it to become "high purity genuine" or "substantially high purity". The intrinsic oxide semiconductor film has few carrier traps. Transistors using the film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it were a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There may be cases where this occurs.

[0336] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0337] Next, the polycrystalline oxide semiconductor film will be described.

[0338] In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in a high-resolution TEM image. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, 2 nm or more in a high-resolution TEM image. 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the case of a polycrystalline oxide semiconductor film, the crystal grain boundaries can be confirmed in a high-resolution TEM image. There are cases.

[0339] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, the positions of the crystals in the polycrystalline oxide semiconductor film may differ from each other. When structural analysis was performed, for example, the ou of a polycrystalline oxide semiconductor film having InGaZnO4 crystals was In the t-of-plane analysis, there was a peak at 2θ near 31° and a peak at 2θ near 36°. or other peaks may appear.

[0340] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at crystal grain boundaries. The grain boundaries of the polycrystalline oxide semiconductor film become defect states. Since the oxide semiconductor film may become a carrier trap or a carrier generation source, The transistors using the CAAC-OS film showed a small change in electrical characteristics compared to the transistors using the CAAC-OS film. may result in a transistor with low reliability.

[0341] Next, a microcrystalline oxide semiconductor film will be described.

[0342] In the microcrystalline oxide semiconductor film, crystal parts can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor has a region where a crystal part is not clearly observed, and a region where a crystal part is not clearly observed. The crystal parts contained in the film are large, with sizes ranging from 1 nm to 100 nm, or from 1 nm to 10 nm. In particular, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is c-OS(nanocrystalline oxide semiconductor In addition, the nc-OS film is called a crystalline structure. For example, in a high-resolution TEM image, the grain boundaries are clearly visible. It may not be possible to verify.

[0343] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that in the crystalline region. Electron diffraction (also called selected area electron diffraction) is performed using an electron beam (e.g., 50 nm or larger). On the other hand, for the nc-OS film, Nanobeam electron circuit using an electron beam with a probe diameter close to or smaller than the size of the crystal part. In addition, nanobeam electron diffraction was performed on the nc-OS film. When the image is taken, a circular (ring-shaped) area of ​​high brightness may be observed. When nanobeam electron diffraction was performed on the c-OS film, multiple spots were observed within the ring-shaped region. In some cases, it may be measured (see FIG. 32(B)).

[0344] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, the crystal orientation is not regular between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0345] Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film having a high carrier density may have high electron mobility. In some cases, a transistor using an nc-OS film has high field-effect mobility. The nc-OS film has a higher defect density than the CAAC-OS film, which leads to carrier transport. Therefore, the transistor using the nc-OS film is Compared to transistors using OS films, the electrical characteristics fluctuate greatly and the reliability is low. However, the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, it is easier to form than the CAAC-OS film, and is preferably used depending on the application. Therefore, a semiconductor having a transistor using an nc-OS film can be The devices may be capable of being manufactured productively.

[0346] Next, the amorphous oxide semiconductor film will be described.

[0347] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state like quartz.

[0348] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image. .

[0349] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of- In the plane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is observed. is observed.

[0350] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. In addition, the amorphous oxide semiconductor film has a high density of defect states.

[0351] An oxide semiconductor film having a high impurity concentration and a high density of defect states has carrier traps and The oxide semiconductor film is the most common source of CO2 generation.

[0352] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film may have a normally Therefore, it is difficult to obtain normally-on electrical characteristics from transistors that require normally-on electrical characteristics. The amorphous oxide semiconductor film may be preferably used as a photoresist. Therefore, the number of carrier traps may increase due to the high temperature. The transistors using the CAAC-OS film and the nc-OS film had the following characteristics: This results in a transistor with large fluctuations in electrical characteristics and low reliability.

[0353] Next, a single crystal oxide semiconductor film will be described.

[0354] A single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). ) an oxide semiconductor film. Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0355] Note that the oxide semiconductor film has a high density when the number of defects is small. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of the single crystal oxide semiconductor film is higher than that of the CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0356] Note that the oxide semiconductor film has a structure that exhibits physical properties intermediate between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly in the case of an amorphous like oxide film. Compound semiconductor (amorphous-like OS: amorphous-like O This is called a xide semiconductor film.

[0357] The amorphous-like OS membrane appears as a void in high-resolution TEM images. In addition, crystals may be clearly identified in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The rphous-like OS film can be observed by irradiating it with a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of good quality, For example, crystallization is hardly observed due to minute electron irradiation, on the level observed by TEM.

[0358] The size of the crystals in the amorphous-like OS film and the nc-OS film was Measurements can be performed using high-resolution TEM images. For example, the crystal of InGaZnO4 has a layered structure, with two Ga-Zn-O layers between In-O layers. The unit cell of the crystal of 4 has three In-O layers and six Ga-Zn-O layers. The structure has nine layers stacked in the c-axis direction. Therefore, the spacing between adjacent layers is is approximately the same as the lattice spacing (also called d value) of the (009) plane, and this is confirmed by crystal structure analysis. The value of 0.29 nm has been determined. Therefore, the lattice fringes in the high-resolution TEM image In particular, in the areas where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes are considered to correspond to the ab plane of the InGaZnO4 crystal. The maximum length of the region observed in the amorphous-like and nc-OS membranes was The size of the crystal part is used. Note that the size of the crystal part is selected to be 0.8 nm or more. do.

[0359] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of AAC-OS films.

[0360] When an oxide semiconductor film has multiple structures, the structures can be resolved by using nanobeam electron diffraction. In some cases, analysis may be possible.

[0361] FIG. 32C shows an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, and an optical system 613 below the electron gun chamber 610. 12, a sample chamber 614, an optical system 616, and a viewfinder 616. An observation room 620, a camera 618 installed in the observation room 620, and a film below the observation room 620. The transmission electron diffraction measurement apparatus has a chamber 622. The camera 618 is located inside the observation chamber 620. The film chamber 622 does not necessarily have to be provided.

[0362] FIG. 32(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 32(C). In the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 610 are The electrons are irradiated via an optical system 612 onto a substance 628 placed in a sample chamber 614. The electrons passing through 28 are guided to a fluorescent screen 63 installed inside an observation chamber 620 via an optical system 616. 2. On the fluorescent screen 632, a pattern appears according to the intensity of the incident electrons. A transmission electron diffraction pattern can be measured.

[0363] The camera 618 is installed facing the fluorescent screen 632 and captures the pattern that appears on the fluorescent screen 632. The center of the lens of the camera 618 and the center of the fluorescent screen 632 can be used to capture the image. The angle between the straight line passing through the center and the upper surface of the fluorescent screen 632 is, for example, 15° to 80°. , 30° to 75° or 45° to 70°. The smaller the angle, the Transmission electron diffraction patterns taken with MERA 618 are highly distorted. If the angle is known, it is possible to correct distortions in the obtained transmission electron diffraction pattern. There are cases where the camera 618 may be installed in the film chamber 622. For example, The camera 618 is installed in the film chamber 622 so as to face the direction of incidence of the electrons 624. In this case, a transmission electron diffraction pattern with little distortion is captured from the rear surface of the fluorescent screen 632. It is possible.

[0364] In the sample chamber 614, a holder for fixing a substance 628 which is a sample is installed. The holder is constructed to be transparent to electrons passing through the material 628. For example, the holder may have a function of moving the substance 628 in the X-axis, Y-axis, Z-axis, etc. The movement function may be, for example, 1 nm to 10 nm, 5 nm to 50 nm, or 10 nm or more. In ranges such as 100nm or less, 50nm to 500nm, 100nm to 1μm, etc. The ranges are determined by the structure of the material 628. Just set it as:

[0365] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0366] For example, as shown in FIG. 32(D), the irradiation position of the electron 624, which is a nanobeam, in the material By changing the position (scanning), it is possible to observe how the structure of a material changes. In this case, if the substance 628 is a CAAC-OS film, as shown in FIG. If the material 628 is an nc-OS film, the diffraction pattern shown in FIG. A diffraction pattern like that shown in B) is observed.

[0367] By the way, even if the material 628 is a CAAC-OS film, it is partially an nc-OS film. Therefore, the quality of the CAAC-OS film can be evaluated. is the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CA For example, a good quality CAAC-OS film can be expressed as If so, the CAAC ratio is 50% or more, preferably 80% or more, and more preferably 90% or more. % or more, and more preferably 95% or more. The area where CAAC is observed is denoted as the non-CAAC rate.

[0368] As an example, the film is formed immediately after (denoted as-sputtered) or in an atmosphere containing oxygen. The top surface of each sample with CAAC-OS film after the heat treatment at 450 °C in air was scanned. Transmission electron diffraction patterns were obtained while scanning the sample at a speed of 5 nm / s for 60 s. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as still images every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the A nano-beam electron beam of 1.5 m was used. The same measurements were performed on six samples. The AC conversion rate was calculated using the average value for six samples.

[0369] The CAAC ratio in each sample is shown in FIG. The AAC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC ratio is reduced by heat treatment at a high temperature (e.g., 400°C or higher). In addition, the CAAC content is increased when the temperature is heated below 500°C. It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained even with

[0370] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The pattern was a folded pattern. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment could not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the neighboring domains influences the rearrangement of the CAAC domain. .

[0371] 33(B) and 33(C) show the CAAC- A high-resolution TEM image of the OS film in the plane. Compare Fig. 33(B) with Fig. 33(C). It can be seen that the CAAC-OS film after the 450℃ heat treatment has a more homogeneous film quality. That is, the quality of the CAAC-OS film is improved by heat treatment at high temperatures. I understand.

[0372] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0373] The CAAC-OS film can be formed, for example, by the following method.

[0374] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The film is formed by sputtering.

[0375] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is suppressed. Specifically, the substrate temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or lower. The film is formed at a temperature of 500°C or less. By increasing the substrate temperature during film formation, flat or pellet-shaped films can be formed. When sputtered particles reach the substrate, migration occurs on the substrate, The flat surface of the sputtered particles adheres to the substrate. At this time, the sputtered particles are positively charged. By applying an electric current, the sputtering particles repel each other while adhering to the substrate. The CAAC-OS film is formed with uniform thickness without unevenly overlapping the coating particles. It is possible.

[0376] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0377] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. Expressed as volume percent.

[0378] Alternatively, the CAAC-OS film is formed by the following method.

[0379] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher. The temperature is set to 500° C. or less, preferably 150° C. to 450° C., and the oxygen ratio in the deposition gas is set to 30 % by volume or more, preferably 100% by volume.

[0380] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be performed at 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor film from the first oxide semiconductor film may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0381] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0382] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more. The second oxide semiconductor film is formed to a thickness of 0 nm or less by a sputtering method. Specifically, the substrate temperature is set to 100° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower. The oxygen ratio in the deposition gas is set to 30% by volume or more, preferably 100% by volume. To film.

[0383] Next, heat treatment is performed to grow a second oxide semiconductor film from the first CAAC-OS film through solid phase epitaxial growth. The second CAAC-OS film is formed with high crystallinity by the heat treatment at a temperature of 350 The temperature is from 450°C to 650°C, preferably from 450°C to 650°C. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After that, a heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the heat treatment. The oxygen vacancies can be reduced by heat treatment in a reactive atmosphere. The pressure may be reduced to 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration in the second oxide semiconductor film can be reduced in a shorter time. Cut.

[0384] In this manner, a CAAC-OS film having a total thickness of 10 nm or more is formed. can be done.

[0385] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0386] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to FIG. This will be described with reference to the following.

[0387] [Circuit configuration example] In the configuration shown in the first embodiment, the transistors, wiring, and electrode connection configuration are changed. By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0388] [CMOS Circuits] The circuit diagram shown in FIG. 34A includes a p-channel transistor 2200 and an n-channel The transistors 2100 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. Note that in the figure, the transistors to which the second semiconductor material is applied are is indicated with the symbol "OS."

[0389] [Analog Switch] The circuit diagram shown in FIG. 34B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0390] [Example of storage device] By using a transistor according to one embodiment of the present invention, the contents of the memory can be read even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written is shown in Figure 3. 4(C).

[0391] The semiconductor device shown in FIG. 34C includes a transistor 3200 using a first semiconductor material and The semiconductor device includes a transistor 3300 using a second semiconductor material and a capacitor 3400 . Note that the transistor 3300 is any of the transistors described in the above embodiments. It is possible.

[0392] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The off-state current of the transistor 3300 is small, so that the transistor 3300 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. To provide a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0393] In FIG. 34C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is a capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. and is electrically connected to

[0394] In the semiconductor device shown in FIG. 34C, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0395] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is Then, a certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By setting the transistor 3300 in the off state, the The charge applied to the gate electrode is retained (retention).

[0396] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrodes is maintained for a long period of time.

[0397] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_ HThe figure shows the state when a low-level charge is applied to the gate electrode of the transistor 3200. Threshold V th_L The apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". If the potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0398] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0399] The semiconductor device shown in FIG. 34D is different from the semiconductor device shown in FIG. 3 mainly in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and hold information. It is possible to create

[0400] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The change in the potential of the third wiring 3003 is proportional to the change in the potential of one electrode of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0401] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one electrode of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0402] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0403] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor in which a second semiconductor material is applied is used as the transistor 3300. The transistor may be laminated on the driver circuit.

[0404] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0405] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating layer does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0406] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0407] (Embodiment 4) In this embodiment, a R The FID tag will be explained with reference to FIG.

[0408] The RFID tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RFID tags can identify objects by reading their individual information. It can be used for individual authentication systems that distinguish between people. To achieve this, extremely high reliability is required.

[0409] The structure of the RFID tag will be described with reference to Fig. 35. Fig. 35 shows the structure of the RFID tag. FIG. 1 is a block diagram illustrating an example.

[0410] As shown in FIG. 35, an RFID tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RFID tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, A demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811 are included. In addition, a reverse current is applied to a transistor having a rectifying effect included in the demodulation circuit 807. A material capable of sufficiently suppressing the noise, for example, an oxide semiconductor, may be used. This suppresses the degradation of the rectification caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit with respect to the input of the demodulation circuit is made nearly linear. The data transmission format is a pair of coils arranged facing each other and using mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses electromagnetic fields to communicate, and the The RFID tag 800 shown in this embodiment is The present invention can be applied to any of the above methods.

[0411] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential. A limiter circuit may be provided on the output side or on the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0412] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0413] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0414] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0415] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0416] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when the power supply is cut off. The memory circuit according to one embodiment of the present invention can be suitably used for an RFID tag. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance when reading and writing data. Furthermore, it is possible to prevent malfunctions or erroneous writing caused by insufficient power when writing data. It is possible.

[0417] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, so that users cannot freely rewrite it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RFID tag produced, This means that unique numbers can only be assigned to products that have been shipped, and the unique numbers of the products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0418] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0419] (Embodiment 5) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the above embodiment will be described.

[0420] FIG. 36 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 2 is a block diagram showing an example of a configuration.

[0421] The CPU shown in FIG. 36 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 36 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 36 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0422] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0423] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0424] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0425] In the CPU shown in FIG. 36, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0426] In the CPU shown in FIG. 36, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0427] FIG. 37 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. It may further include other elements such as a converter.

[0428] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0429] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0430] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply voltage The other is electrically connected to a wiring (e.g., a GND line) that can supply a switch voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (the first terminal of the transistor 1214) is electrically connected to the The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) a first terminal of the switch 1204 (one of the source and drain of the transistor 1214) one of a pair of electrodes of a capacitor 1207, and an input terminal of a logic element 1206. , are electrically connected. Here, the connection point is designated as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. For example, It can be configured so that the power supply potential (GND, etc.) or high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a power supply that can supply a low power potential. The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND A power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.) can be input to the capacitance element 12. The other of the pair of electrodes of 08 is a wiring that can supply a low power supply potential (for example, GN D line).

[0431] The capacitors 1207 and 1208 are parasitic capacitances of transistors and wirings, etc. It is also possible to omit it by making active use of the above.

[0432] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive or non-conductive state between the first and second terminals, and When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch and There is no electrical continuity between the second terminals.

[0433] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 37, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0434] In FIG. 37, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the drain (the other drain) is passed through the logic element 1206 and the circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the circuit 1201. The signal output from the other terminal of the transistor 1213 (the other of the source and drain of the transistor 1213) is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0435] In addition, in FIG. 37, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed in oxide semiconductor layers. Alternatively, the memory element 1200 may include a transistor 1209 or In addition, a transistor in which a channel is formed in an oxide semiconductor layer may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0436] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0437] In the semiconductor device according to one embodiment of the present invention, a power supply voltage is not supplied to the memory element 1200. During this period, data stored in the circuit 1201 is transferred to the capacitor 12 in the circuit 1202. It can be retained by 08.

[0438] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents ( It is possible to retain the data.

[0439] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operations, after the power supply voltage is resumed, the circuit 1201 This can shorten the time it takes to restore the original data.

[0440] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0441] Such a memory element 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0442] In the present embodiment, the memory element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, Also applicable to RFID (Radio Frequency Identification) It is possible.

[0443] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0444] (Embodiment 6) In this embodiment, a structure example of a display panel according to one embodiment of the present invention will be described.

[0445] [Configuration example] FIG. 38A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 38C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0446] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. In addition, since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be composed of a transistor of the same type as the transistor of the pixel part. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the above-mentioned capacitor, a highly reliable display device can be provided.

[0447] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 includes a signal line driver circuit 703 and a signal line driver circuit 704. A first scanning line driving circuit 702 and a second scanning line driving circuit 704 are arranged to extend from the first scanning line driving circuit 702 and a second scanning line driving circuit 704. The second scanning line driving circuit 703 is extended from the second scanning line driving circuit 703. In each region, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection part. do.

[0448] In FIG. 38A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel section 701. The number of components such as the drive circuits to be provided is reduced, which contributes to cost reduction. 700 If a driving circuit is provided externally, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0449] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 38(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0450] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of the multi-domain design to be The signals applied to the electrode layers can be controlled independently.

[0451] A gate wiring 712 of a transistor 716 and a gate wiring 713 of a transistor 717 The data lines are separated so that different gate signals can be applied. The source electrode layer or drain electrode layer 714 functioning as a transistor 716 is Transistors 716 and 717 are used in common in the above embodiment. The transistor described in the above embodiment can be appropriately used. A liquid crystal display panel can be provided.

[0452] A first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the pixel electrode layer is separated by slits. The first pixel electrode layer spreads in a V shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0453] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the transistor 717 The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the thickness, the alignment of the liquid crystal can be controlled.

[0454] In addition, the capacitance wiring 710, the gate insulating film functioning as a dielectric, and the first pixel electrode layer Alternatively, a storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0455] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0456] Note that the pixel circuit shown in FIG. 38(B) is not limited to this. A switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be newly added to the pixel shown in FIG. etc. may be added.

[0457] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0458] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0459] FIG. 38C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0460] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain this in more detail.

[0461] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting The switching transistor 721 has a gate element 724 and a capacitor element 723. The first electrode (one of the source and drain electrode layers) is connected to the scan line 726. The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725. It is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. It is electrically connected to a common potential line formed thereon.

[0462] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. This allows the transistors described in 2. to be used appropriately. A display panel can be provided.

[0463] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727. For example, D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0464] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode layer and the gate electrode layer.

[0465] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A gate electrode layer of the transistor 722 is connected to a signal line 725. A voltage equal to or greater than the threshold voltage Vth of the driving transistor 722 is applied.

[0466] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 7 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. This causes a current to flow through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed to the light emitting element 724. Moreover, analog gray scale driving can be performed.

[0467] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. The pixel circuit shown in 8(C) is provided with a switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0468] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0469] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0470] (Embodiment 7) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, Image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) (car audio, digital audio player), navigation systems, audio playback devices Layers, etc.), copiers, facsimiles, printers, printer-combinations, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 39. .

[0471] FIG. 39A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 39(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0472] FIG. 39(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The first display unit 913 and the second display unit 914 may be switched according to the angle between the first display unit 913 and the second display unit 914. At least one of the first display unit 912 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be achieved by touching the display device. The position input function can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0473] FIG. 39C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0474] FIG. 39(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0475] FIG. 39E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0476] FIG. 39(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0477] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0478] (Embodiment 8) In this embodiment, a usage example of an RFID according to one aspect of the present invention will be described with reference to FIG. RFID has a wide range of uses, including banknotes, coins, securities, and unregistered securities. Bonds, certificates (driver's licenses, resident's certificates, etc., see Figure 40(A)), packaging containers (wrapping paper bottles, etc., see Fig. 40(C), recording media (DVD software, video tapes, etc., see Fig. 40( B), vehicles (bicycles, etc., see Figure 40(D)), personal belongings (bags, glasses, etc.), food products, plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronics Equipment (liquid crystal display devices, EL display devices, television sets, or mobile phones) and other items, Or, it is used by attaching it to a tag (see Figure 40 (E) and Figure 40 (F)) to each article. It is possible.

[0479] The RFID 4000 according to one embodiment of the present invention can be attached to or embedded in a surface, It is fixed to the object. For example, in a book, it is embedded in the paper and the packaging is made of organic resin. If the RFI is used, it is embedded in the organic resin and fixed to each article. The D4000 is small, thin, and lightweight, so even after it is attached to an object, it retains the data of the object itself. In addition, the design of banknotes, coins, securities, bearer bonds, or certificates is not affected. By providing an RFID 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RFID tag according to one embodiment, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RFID tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0480] As described above, the RFID according to one aspect of the present invention can be used for each of the applications described in this embodiment. This reduces the power consumption during operation, including writing and reading information, and therefore the maximum communication distance It is also possible to store information for a very long time even when the power is cut off. Since the data can be stored for a long period of time, it can be used for applications where the frequency of writing and reading is low. can.

[0481] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. EXAMPLES

[0482] In this embodiment, a transistor using single crystal silicon and a semiconductor device stacked on the transistor are used. A semiconductor device including a transistor using an oxide semiconductor and The electrical properties of the transistor were evaluated.

[0483] [Sample description] The method for preparing the samples will be described below.

[0484] First, an SOI substrate having a single crystal silicon film with a thickness of 52 nm was prepared. .

[0485] Next, a portion of the single crystal silicon film is etched by photolithography to form a single crystal The silicon film was formed in an island shape.

[0486] Next, the single crystal silicon film was oxidized from the surface using microwave CVD to a thickness of 1 A silicon oxide film with a thickness of 0 nm was formed. The microwave CVD method was a high-density plasma CVD method. This is also called the D method. Next, heat treatment is performed at 950°C for 1 hour in a nitrogen atmosphere. Thus, a gate insulating film was formed.

[0487] Next, to form a p-channel transistor, phosphorus is added to a part of the single crystal silicon film. The phosphorus ions were implanted using an ion implanter (with mass separation function). The acceleration voltage was 18 kV, and the 11 ions / cm 2 The experiment was carried out at a concentration of .

[0488] Next, to form an n-channel transistor, boron is added to a part of the single crystal silicon film. Boron ions were implanted using an ion implanter at an acceleration voltage of 14 kV. As a result, 3.0 × 10 12 ions / cm 2 The experiment was carried out at a concentration of .

[0489] Next, a tantalum nitride film with a thickness of 30 nm and a tantalum nitride film with a thickness of 170 nm were deposited by sputtering. Next, a tungsten film with a thickness of 1 nm was formed on the tungsten nitride film by photolithography. The aluminum film and the tungsten film were partly etched to form a gate electrode.

[0490] Next, a gate electrode is formed on the region of the single crystal silicon film that will become a p-channel transistor. Using this as a mask, boron ions were implanted. The boron ions were implanted using an ion implanter. The acceleration voltage was 9 kV, and the 13 ions / cm 2 The experiment was carried out at a concentration of .

[0491] Next, a gate electrode is formed on the region of the single crystal silicon film that will become an n-channel transistor. The phosphorus ions were implanted using the mask. The phosphorus ions were implanted using an ion implanter with accelerated At a voltage of 9 kV, it is 1.0 x 10 13 ions / cm 2 The experiment was carried out at a concentration of .

[0492] Next, a silicon oxynitride film having a thickness of 300 nm is formed using a plasma CVD method. By performing anisotropic etching, the insulating film in contact with the side of the gate electrode (sidewall insulating film or sub-insulating film) is A part of the gate insulating film was formed using this oxynitride. As a result, the single crystal silicon film is etched at the same time as the etching of the silicon nitride film. The part is exposed.

[0493] Next, a gate electrode is formed on the region of the single crystal silicon film that will become a p-channel transistor. Boron ions were implanted using the sidewall insulating film as a mask. Using a doping device (without mass separation function), set the acceleration voltage to 10 kV, 1. 5×10 16 ions / cm 2 The boron ion implanted area is a p-type It also functions as the source or drain region of the channel transistor. The region of the single crystal silicon film directly below the film is the channel formation region formed by the above-mentioned process. , and the carrier density in the source region or drain region is intermediate, so that LDD(L The slits function as a lightly doped drain area.

[0494] Next, a gate electrode is formed on the region of the single crystal silicon film that will become an n-channel transistor. Using the sidewall insulating film as a mask, phosphorus ions were implanted. The accelerating voltage was set to 10 kV, and the 15 ions / cm 2 Concentration The phosphorus ion implanted region was located in the source region of the n-channel transistor. The region of the single crystal silicon film directly below the sidewall insulating film functions as a drain region. The channel forming region and the source or drain region formed by the above-mentioned process are Since it has a carrier density intermediate between the LDD region and the LDD region, it functions as an LDD region.

[0495] Next, a silicon oxynitride film was formed to a thickness of 50 nm by using a plasma CVD method.

[0496] Next, heat treatment was performed at 550° C. for 1 hour in a nitrogen atmosphere.

[0497] Next, a silicon oxynitride film with a thickness of 280 nm was formed using the plasma CVD method. The silicon nitride oxide film is also called a SiNOH film because it contains a large amount of hydrogen. .

[0498] Next, a silicon oxynitride film was formed to a thickness of 300 nm by thermal CVD.

[0499] Next, heat treatment was performed at 490° C. for 1 hour in a nitrogen atmosphere. The hydrogen is released from the SiNOH film. The released hydrogen reaches the single crystal silicon film. This terminates the dangling bonds of the single crystal silicon film. This is called hydrotreating.

[0500] Next, a silicon oxynitride film having a thickness of 50 nm and a silicon nitride oxide film having a thickness of 280 nm are The source region and the silicon oxide film having a thickness of 300 nm are partially etched. Openings reaching the drain region, gate electrode, etc. were formed.

[0501] Next, a tungsten film was formed to a thickness of 150 nm by sputtering.

[0502] Next, a part of the tungsten film is etched by photolithography to form a first wiring. A line layer was formed.

[0503] Next, a silicon oxide film was formed to a thickness of 900 nm by using a plasma CVD method.

[0504] Next, the thickness of the silicon oxide film is reduced to 400 mm by CMP processing from the top surface of the silicon oxide film. The thickness was flattened from about 100 nm to about 500 nm.

[0505] Next, the sample was heat-treated in a nitrogen atmosphere at 490°C for 10 hours. Sample 2 was subjected to a heat treatment at 450°C for 5 hours. The hydrogenation process does not cause out-diffusion or utilization for terminating dangling bonds. This process is called dehydrogenation because it causes the hydrogen remaining in each layer to diffuse outward. The higher the temperature and the longer the time, the more effective it is. Therefore, compared to sample 2, This can be said to be a sample with a small amount of remaining hydrogen.

[0506] Next, a part of the silicon oxide film, which is about 400 nm to 500 nm thick, is etched. In this way, an opening reaching the first wiring layer and the like was formed.

[0507] Next, a tungsten film was formed to a thickness of 150 nm by sputtering.

[0508] Next, a portion of the tungsten film is etched away by photolithography to expose a second A conductive film 220 having a function as a gate electrode and a conductive film 221 having a function as a second wiring layer A conductive film 174 was formed.

[0509] Next, a silicon oxide film was formed to a thickness of 500 nm by using a plasma CVD method.

[0510] Next, the thickness of the silicon oxide film is reduced to 0 nm by CMP processing from the top surface of the silicon oxide film. The upper surface of the tungsten film was then exposed by planarizing it to a thickness of about 50 nm.

[0511] Next, a silicon oxide film having a thickness of 100 nm was formed by using a plasma CVD method.

[0512] Next, the sample was subjected to a heat treatment in a nitrogen atmosphere at 490°C for 10 hours. Sample 2 was subjected to a heat treatment at 450°C for 1 hour. Then, further dehydrogenation treatment was carried out.

[0513] Next, an aluminum oxide film was formed to a thickness of 50 nm by sputtering. The aluminum oxide film has a function of blocking oxygen, hydrogen, etc. By providing an aluminum nitride film, a transistor using single crystal silicon and Hydrogen released from the insulating and conductive films around the device will be absorbed into the oxide semiconductor that will be fabricated later. This can prevent the semiconductor device from being mixed into a transistor using the semiconductor device.

[0514] Next, a silicon oxynitride film with excess oxygen of 100 nm was formed by plasma CVD. The silicon oxynitride film was formed by the subsequent heat treatment, etc. The released oxygen reduces oxygen vacancies in the oxide semiconductor. It is used to improve the electrical characteristics and reliability of transistors. When the released oxygen reaches the single crystal silicon, it degrades the electrical characteristics and reliability of the transistor. The aluminum oxide film described above has a function of preventing oxygen from being mixed into single crystal silicon. Therefore, even if a silicon oxynitride film containing excess oxygen is provided, the electrical characteristics and the reliability are not deteriorated. It is possible to manufacture highly reliable transistors using single crystal silicon.

[0515] Next, as Sample 1, a first oxide semiconductor film having a thickness of 20 nm was formed by a sputtering method. A first oxide semiconductor film having a thickness of 20 nm and a second oxide semiconductor film having a thickness of 20 nm were formed in this order. A first oxide semiconductor film having a thickness of 20 nm and a second oxide semiconductor film having a thickness of 15 nm were formed by a quenching method. The first oxide semiconductor film was deposited in this order. The atomic ratio of the second oxide semiconductor was 1:3:2. A target with an atomic ratio of In:Ga:Zn=1:1:1 was used for depositing the film. The first oxide semiconductor film and the second oxide semiconductor film are collectively referred to as oxide semiconductor film 2. Let's call it 06.

[0516] Next, the specimen was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then heated in an oxygen atmosphere. Then, heat treatment was performed at 450° C. for 1 hour.

[0517] Next, part of the oxide semiconductor film 206 is etched by photolithography. The nitride semiconductor film 206 was formed in an island shape.

[0518] Next, a part of the silicon oxynitride film having excess oxygen, a part of the aluminum oxide film, and By etching a part of the silicon oxide film, the conductive film 220, the conductive film 174, etc. are reached. Openings (such as opening 260) were formed through the openings.

[0519] Next, a tungsten film was formed to a thickness of 100 nm by sputtering.

[0520] Next, a portion of the tungsten film is etched away by photolithography to form an oxide semiconductor. A conductive film that functions as a source electrode or a drain electrode of a transistor using a conductor A conductive film 216a and a conductive film 216b were formed.

[0521] Next, a third oxide semiconductor film was formed to a thickness of 5 nm by a sputtering method. The third oxide semiconductor film was formed using a tantalum oxide semiconductor layer having an atomic ratio of In:Ga:Zn=1:3:2. A target was used.

[0522] Next, a silicon oxynitride film was formed to a thickness of 20 nm by using a plasma CVD method.

[0523] Next, a titanium nitride film with a thickness of 30 nm and a titanium nitride film with a thickness of 135 nm were deposited by sputtering. Then, a tungsten film of 300 nm was deposited on the substrate.

[0524] Next, the titanium nitride film and a part of the tungsten film are etched away by photolithography. Then, the gate electrode 204 was formed.

[0525] Next, a third oxide semiconductor film and a silicon oxynitride film are formed by photolithography. The silicon oxynitride film is a second oxide film which is a channel formation region. Since it is disposed between the semiconductor film and the gate electrode 204, it functions as a gate insulating film. do.

[0526] Next, an aluminum oxide film was formed to a thickness of 150 nm by sputtering. The aluminum oxide film has a function of blocking oxygen, hydrogen, etc. By providing an aluminum nitride film, a transistor using single crystal silicon and Hydrogen released from insulating films and conductive films provided around the device and hydrogen mixed in from outside the device This can prevent hydrogen from entering a transistor including an oxide semiconductor. The oxygen released from the silicon oxynitride film containing excess oxygen is prevented from diffusing outward, Oxygen can be efficiently used to reduce oxygen vacancies in oxide semiconductors. .

[0527] Next, heat treatment was performed at 400° C. for 1 hour in an oxygen atmosphere. A part of the oxygen contained in the silicon oxynitride film having excess oxygen is released, and the first The supplied oxygen flows in a domino effect through the first oxide semiconductor film. Therefore, oxygen is apparently supplied to the second oxide semiconductor film. By this method, oxygen vacancies in the second oxide semiconductor film, which is a channel formation region, can be reduced. At this time, an aluminum oxide film is disposed around the second oxide semiconductor film. Therefore, the oxygen released from the silicon oxynitride film having excess oxygen is It is understood that the oxygen vacancies in the oxide semiconductor film can be effectively reduced.

[0528] Next, a silicon oxynitride film was formed to a thickness of 300 nm by using a plasma CVD method.

[0529] Next, a part of the silicon oxynitride film and the aluminum oxide film is etched. Openings reaching the conductive film 216a, the conductive film 216b, and the like were formed.

[0530] Next, a titanium film with a thickness of 50 nm and an alumina film with a thickness of 200 nm were deposited by sputtering. An aluminum film and a titanium film having a thickness of 50 nm were formed in this order.

[0531] Next, the titanium film, the aluminum film and the titanium film are photolithographically formed. A part of the wiring layer was then etched to form a second wiring layer.

[0532] In the above manner, a transistor using single crystal silicon and a transistor using an oxide semiconductor were fabricated. Samples 1 and 2, which are semiconductor devices having a transistor, were fabricated.

[0533] [measurement] Next, transistors using single crystal silicon included in Sample 1 and Sample 2 were fabricated. The electrical characteristics of the transistor including the oxide semiconductor were measured.

[0534] The only difference between Sample 1 and Sample 2 is the conditions for the two dehydrogenation treatments. Sample 1 was dehydrogenated for the first time at 490°C for 10 hours in a nitrogen atmosphere. The second dehydrogenation treatment was performed at 490°C for 10 hours in a nitrogen atmosphere. For sample 2, the first dehydrogenation treatment was performed in a nitrogen atmosphere. The second dehydrogenation treatment was performed in a nitrogen atmosphere. The resulting mixture was then heat-treated at 450° C. for 1 hour.

[0535] FIG. 41 shows the Vg-Id characteristics of a transistor using single crystal silicon. The characteristics were measured with a drain voltage (Vd) of 0.1 V or 1.8 V, and the n-channel transistor For the transistor, the gate voltage (Vg) is set to -1.8V to 3.3V in 0.1V increments. The drain current (Id) was measured when the voltage was swept at . In the case of a transistor, the gate voltage (Vg) is set from 1.8V to -3.3V, The drain current (Id) was measured when the transistor was swept at intervals. The design values ​​of the channel length and width of the MOSFET were 0.35 μm and 1.6 μm, respectively. The measurements were performed on 25 transistors evenly arranged on a 126.6 mm square substrate. Ta.

[0536] As shown in Figure 41, the electrical characteristics of the transistors using single crystal silicon in Sample 1 and Sample 2 are Almost no difference was observed. Specifically, the n-channel transistor in sample 1 The threshold voltage is 0.47V and the subthreshold swing value (also called S value) is 6 The n-channel transistor in sample 2 had a The threshold voltage was 0.51 V and the S value was 67.6 mV / dec. The p-channel transistor has a threshold voltage of -0.59V and an S value of 69.0mV / d The threshold voltage of the p-channel transistor in Sample 2 was - The threshold voltage was 0.55V and the S value was 71.6mV / dec. The S value was derived from the Vg-Id characteristics at a drain voltage of 1.8 V. This was done based on the Vg-Id characteristics at 0.1V.

[0537] When hydrogen terminating the dangling bonds of single crystal silicon is released, However, as shown in Figure 41, the electrical characteristics of the transistors in the sample 1 and sample 2. Almost no difference was observed in the electrical characteristics of the transistors using single crystal silicon. Therefore, even under conditions where hydrogen desorption is more likely to occur, such as in sample 1, in this example, There is almost no desorption of hydrogen terminating the dangling bonds of crystalline silicon. It can be seen that.

[0538] Next, the Vg-Id characteristics of the transistor including an oxide semiconductor were measured. In order to evaluate the effect of the openings in each layer around the transistor, the Vg-Id The characteristics of a transistor using an oxide semiconductor and its surroundings are measured. FIG.

[0539] FIG. 42A shows a structure that does not have a conductive film 174 and an opening 260 (referred to as structure 1). 42B shows a conductive film 174, a conductive film 216a, and a conductive film 216. a) and b) have one opening 260 between them (hereinafter referred to as structure 2). FIG. 42C shows the area between the conductive film 174 and the conductive film 216a, and the area between the conductive film 174 and the conductive film 216b. Each of the films 216b has one opening 260, and the surrounding wiring layer, etc. However, it is a structure that has an opening (referred to as Structure 3).

[0540] FIG. 43 shows the Vg- Id characteristics are shown. The Vg-Id characteristics are measured by setting the drain voltage (Vd) to 0.1V or 2. When the gate voltage (Vg) is swept from -3V to 3V at 0.1V intervals with the voltage set to 7V, The drain current (Id) was measured. The transistor was designed to have a channel The length of the channel was 0.8 μm and the width of the channel was 0.8 μm. Measurements were performed on 25 transistors evenly spaced within the chip.

[0541] As shown in FIG. 43, in the structure 1, the transistor using the oxide semiconductor is different between the sample 1 and the sample 2. There was almost no difference in the electrical properties of the two samples. The input current is 1×10 -12 The gate voltage at A is defined as the shift value. The peak current was 0.44V and the S value was 90.7mV / dec. The shift value was 0.34V and the S value was 98.4mV / dec. The shift value was derived as follows: The Vg-Id characteristics were calculated at a drain voltage of 2.7 V. The S value was also calculated at The Vg-Id characteristics were measured at a voltage of 0.1 V.

[0542] In addition, as shown in FIG. 43, in the structure 2, the oxide semiconductor-based transistors in the samples 1 and 2 are The difference in the electrical characteristics of the transistors was observed. Specifically, the shift value of sample 1 was 0.47 V, S The value was 95.3 mV / dec, while sample 2 had a shift value of 0.28 V and an S value of 132. In structure 2, sample 2 has a larger S value than structure 1. On the other hand, sample 1 had a similar S value to structure 1, and structure 2 also had good electrical properties. It was found that.

[0543] In addition, as shown in FIG. 43, in the structure 3, the oxide semiconductor-based transistors in the samples 1 and 2 are A significant difference was observed in the electrical characteristics of the transistors. Specifically, sample 1 had a shift value of 0.24 Although the V and S values ​​were 98.1 mV / dec, sample 2 did not exhibit switching characteristics. From the above results, it was found that Sample 1 had an S value similar to that of Structures 1 and 2, and Structure 3 had an S value similar to that of Structures 2 and 3. It was found that the SiO2-based ...

[0544] The difference between the structures 1, 2, and 3 is that the presence or absence of an opening in sample 2 is due to the oxide semiconductor. It was suggested that this contributes to the superiority or inferiority of the electrical characteristics of transistors using conductors. It was found that the more openings there are around the transistor, the more the electrical characteristics deteriorate. In Sample 1, the electrical characteristics of the transistor are not as great as those of Sample 2 depending on the presence or absence of an opening. This is because the dehydrogenation treatment of sample 2 is more effective than that of sample 1. Therefore, hydrogen moves to a transistor using an oxide semiconductor through the opening. On the other hand, in sample 1, the dehydrogenation treatment was sufficient, so the hydrogen-induced This is thought to be because almost no deterioration occurred. However, even in sample 1, Since a slight deterioration in electrical properties was observed, the dehydrogenation treatment conditions were further strengthened. This is expected to lead to further improvements in characteristics.

[0545] The total shift value derived from the Vg-Id characteristics shown in Figure 43 is plotted in Figure 44. The 3σ shift value of material 1 is 0.05 V for structure 1, 0.07 V for structure 2, and 0.21 V for structure 3. On the other hand, the 3σ shift value of sample 2 was 0.05 V for structure 1 and 0.16 V for structure 2. V, structure 3 was not measurable.

[0546] Therefore, the variation in Vg-Id characteristics due to the difference in structure is smaller in sample 1 than in sample 2. It was found that the

[0547] Compared to Structure 1, Structures 2 and 3 have more openings and are closer to highly integrated semiconductor devices. Therefore, even structures with many openings such as Structure 2 and Structure 3 have excellent electrical conductivity. The ability to realize high-temperature characteristics is important for manufacturing highly integrated semiconductor devices with high yields. It can be seen that.

[0548] In this example, by strengthening the conditions of the dehydrogenation treatment, it was possible to obtain a traction using single crystal silicon. While maintaining the electrical characteristics of transistors, transistors using oxide semiconductors with various structures are being developed. It was found that the deterioration of the electrical properties of the sintered body could be suppressed. By strengthening the oxide semiconductor, deterioration of the electrical characteristics of a transistor using an oxide semiconductor can be further suppressed. This suggests the possibility of controlling EXAMPLES

[0549] In this embodiment, the difference in the dehydrogenation process and the thickness of the silicon oxynitride film having excess oxygen are How do the electrical characteristics of a transistor using an oxide semiconductor change depending on the thickness? We evaluated whether this was the case.

[0550] [Sample description] The methods for preparing Samples 3 and 4 are described below.

[0551] The thickness of the second oxide semiconductor film in Sample 3 is 15 nm larger than that in Sample 1 shown in Example 1. The samples were prepared under the same conditions except for the above. Sample 3 and Sample 1 were prepared under the same conditions as the second oxide semiconductor. The only difference is the thickness of the membrane. For other conditions, please refer to the explanation for sample 1. In other words, Sample 3 was subjected to enhanced dehydrogenation treatment conditions.

[0552] Sample 4 is a silicon oxynitride film having excess oxygen compared to Sample 2 shown in Example 1. The samples were prepared under the same conditions except that the thickness was set to 300 nm. Since the only difference is the thickness of the silicon oxynitride film containing excess oxygen, other conditions are not affected. For details, please refer to the explanation for Sample 2. Note that the oxynitride silicon having excess oxygen in Sample 3 The thickness of the silicon film is 100 nm.

[0553] [measurement] Next, the Vg-Id characteristics of Sample 3 and Sample 4 were measured. The measurement was performed on the structure 1 shown in Example 1. The Vg-Id characteristics were measured at room temperature (25° C.). Or at 85°C, the drain voltage (Vd) is 1.8V and the gate voltage (Vg) is - Measure the drain current (Id) when sweeping from 3V to 3V in 0.1V intervals. This measurement was performed at a voltage (Vbg The test was repeated several times while changing the voltage from 0V to -20V. The design values ​​of the channel length and width were 0.8 μm and 0.8 μm, respectively. Measurements were performed on 13 transistors evenly spaced within a 26.6 mm square substrate.

[0554] Then, the S value was calculated from the obtained Vg-Id characteristics, and the drain current at a gate voltage of 0 V was calculated. The in-phase current was derived by extrapolation. The results are shown in Figure 45. Figure 45(A) shows the in-phase current at room temperature. The relationship between the voltage applied to the conductive film 220 and the drain current when the gate voltage is 0 V is shown. FIG. 45(B) shows the relationship between the voltage applied to the conductive film 220 at 85° C. and the gate 13 is a graph showing the relationship between the drain current and the gate voltage of 0 V.

[0555] As shown in Figure 45, sample 3, which had stronger dehydrogenation conditions, had an overall lower drain rate than sample 4. It was also found that the thickness of the silicon oxynitride film having excess oxygen was Because the conductive film 220 is thin, the voltage applied to the conductive film 220 that functions as the second gate electrode can be reduced. It was found that the drain current reduction effect was large for the conductive film 220. It was found that the drain current can be reduced more effectively even if the absolute value of the applied voltage is small. I did.

[0556] In addition, as shown in FIG. 45, by strengthening the conditions of the dehydrogenation treatment, the voltage applied to the gate electrode The drain current in the OFF state (sometimes referred to as the off current) is 1×10 -22 A to 1×10 -35 It was suggested that the acid concentration could be reduced to about A. When manufacturing a semiconductor device that utilizes the extremely small off-current of a transistor using a nitride semiconductor, It is clear that it is important to strengthen the dehydrogenation treatment conditions in this case.

[0557] Note that the drain current derived by extrapolation may differ from the actual value. For example, When hydrogen is mixed into a transistor using a semiconductor, the drain current is higher than that obtained by extrapolation. The actual drain current may become large. The thorough reduction of hydrogen, which may lead to the development of transistors using oxide semiconductors, is essential. It is clear that this is important for improving the characteristics. EXAMPLES

[0558] In this embodiment, an ideal system without leakage current, trap levels, parasitic resistance, etc. in the gate insulating film is used. The off-state current of the assumed transistor was calculated and evaluated.

[0559] First, the structure of a transistor will be described.

[0560] FIG. 46 is a cross-sectional view of a transistor in the channel length direction. The n-type region (also called the low resistance region) adjacent to the drain electrode is the source electrode and the drain electrode. The second insulating film is provided over the entire oxide semiconductor film S2 that overlaps the second insulating film S1. The length L is 0.8 μm, the channel width W is 1 nm, and the gate electrode and the source electrode or the drain electrode The overlapping width Lov between the poles was set to 0.2 μm.

[0561] Next, the calculation conditions will be described.

[0562] The calculations were performed using Synopsys' Sentaurus under the conditions shown in Table 1. went.

[0563] [Table 1]

[0564] In the table, GI represents a gate insulating film, S3 represents an oxide film, and S2 represents an oxide semiconductor film. S1 represents the oxide film, GE represents the gate electrode, and S / D represents the source and drain electrodes. Represents the n electrode.

[0565] Next, FIG. 47 shows the Vg-Id characteristics and the S value when the drain voltage Vd is 1.8 V.

[0566] As shown in FIG. 47, a transistor using IGZO(111) for the oxide semiconductor film S2 and an oxide In the ideal system, the off-current of both transistors using IGZO(312) for the semiconductor film S2 is calculated as The limit of possible values ​​is 1 × 10 -35 It was confirmed that the resistance was reduced to about A / μm. The S value was estimated to be 66mV / dec. for each transistor. EXAMPLES

[0567] Example 1 In this example, electrical characteristics of a transistor which is one embodiment of the present invention will be described.

[0568] [sample] Sample 5 used in the evaluation will be described below.

[0569] Sample 5 is a sample having excess oxygen in the preparation method of Sample 1 and Sample 2 shown in Example 1. A silicon oxynitride film is formed on a single crystal substrate using the same process as that of the silicon oxynitride film. A transistor was fabricated using the above.

[0570] Also, the difference from the preparation method shown in Example 1 is that in Sample 5, The thickness of the silicon oxynitride film is 300 nm, and the thickness of the second oxide semiconductor film is 15 nm, and the thickness of the silicon oxynitride film that functions as the gate insulating film is 10 nm. The difference is that the thickness of the aluminum oxide film is 70 nm.

[0571] [Off-state current measurement] Next, the measurement method and results of the off-state current of Sample 5 fabricated above will be described with reference to FIGS. This will be explained using Figure 51.

[0572] [Measurement system] The measurement system shown in FIG. 48 includes a capacitance element 400, a transistor 401, a transistor 402, The transistor 403 and the transistor 404 are included. Here, the transistor 403 is The transistor 403 is a transistor for charge injection, and the transistor 404 is a transistor for evaluating leakage current. The transistor 401 and the transistor 402 constitute an output circuit 406. In addition, the source terminal (or drain terminal) of the transistor 403 and the transistor 404 the drain terminal (or source terminal) of the capacitance element 400, the first terminal of the transistor 4 The connection point with the gate terminal of 01 is called node A.

[0573] By providing a transistor for charge injection and a transistor for evaluation separately, During charge injection, the evaluation transistor can be kept in the off state at all times. If no transistor for evaluation is provided, the evaluation transistor is turned on once during charge injection. However, it takes time to reach a steady state from the on state to the off state. For such devices, it takes time to measure. Since there is no need to use the MOSFET, some of the charge in the channel region flows into node A. There is no effect of potential fluctuations on node A.

[0574] The channel width W of the evaluation transistor is set to the channel width W of the charge injection transistor. It is preferable to set the channel width W of the evaluation transistor to be larger than the By making it larger than the channel width W of the transistor, the leakage current of the evaluation transistor As a result, the leakage current component other than the current can be made relatively small. The leakage current of a transistor can be measured with high accuracy.

[0575] The measurement system shown in FIG. 48 includes a source terminal (or drain terminal) of a transistor 403, The drain terminal (or source terminal) of the transistor 404 and the first terminal of the capacitive element 400 is connected to the gate terminal of the transistor 401. The terminal and the source terminal (or drain terminal) of the transistor 404 are connected The drain terminal (or source terminal) of the transistor 401 is connected to a power supply. The source terminal (or drain terminal) of the transistor 402 is connected to the power supply. The drain terminal (or source terminal) of the transistor 403 is connected to a power supply.

[0576] In addition, the measurement system shown in FIG. 48 is a measurement system for measuring the drain terminal (or source terminal) of the transistor 403. ) is supplied with V3 from the power supply, and the source terminal (or drain terminal) of the transistor 404 A potential V4 is applied to the drain terminal ( or source terminal) is supplied with V1 from the power supply, and the source terminal ( The power supply V2 is applied to the drain terminal of the transistor 401. the drain terminal (or source terminal) of the transistor 402 terminal), which corresponds to the output terminal of the output circuit 406, outputs an output potential Vout will be output.

[0577] In the above, the gate terminal of the transistor 402 is connected to a voltage adjusting circuit 406. The gate terminal of the transistor 403 is supplied with a potential Vext_a. A potential Vext_c is supplied to control the on / off state of the transistor 404. A potential Vext_b that controls the state of the evaluation transistor is supplied to the output terminal.

[0578] In FIG. 48, the capacitance element 400 may not be provided. In this case, the node A is The gate terminal of the transistor 401 and the source terminal (or drain terminal) of the transistor 403 404 and the drain terminal (or source terminal) of the transistor 404.

[0579] <Current measurement method> Next, an example of a current measuring method using the above-mentioned measuring system will be described with reference to FIG.

[0580] First, the outline of the write period during which a potential difference is applied to measure the off-state current is shown in FIG. Explain using (A).

[0581] In the write period, a voltage is applied to the drain terminal (or source terminal) of the transistor 403. After inputting the potential V3, a voltage Vout is applied to the gate terminal of the transistor 403 to turn the transistor 403 on. A potential Vext_c is input to the drain terminal (or source) of the transistor 404. A potential V3 is applied to a node A connected to the transistor 402 (transistor terminal). A potential Vext_a is input to turn on the transistor 402. A potential Vext_b that turns off the transistor 404 is input, and the transistor 404 is turned off. This is the state.

[0582] Here, the potential V3 is a high potential (H1), and the potential Vext_c is a high potential (H2). Potential V1 is high potential (H3). Potential Vext_a is low potential (L4), and potential V2 is low potential. (L5), the potential Vext_b is set to a low potential (L2), and the potential V4 is set to Vss.

[0583] Thereafter, a potential Vext_a that turns off the transistor 402 is input. The potential V2 is set to a high potential (H4), and the potential V1 is set to a low potential (L 3). Here, the potential V2 is set to the same potential as the potential V1. Next, the potential V3 is set to a low potential ( L) to the gate terminal of the transistor 403, the transistor 403 is turned off. A potential Vext_c is input to turn off the transistor 403 .

[0584] Here, the potential Vext_c is a low potential (L2), the potential Vext_a is a high potential (H4), Let potential V3 be low potential (L1), potential V1 be low potential (L3), and potential V2 be high potential (H4). The potential Vext_b is set to a low potential (L2), and the potential V4 is set to Vss.

[0585] With the above, the write period ends. When the write period ends, the transistor 4 04 is in an off state, but the node A and the source terminal (drain terminal) of the transistor 404 Since a potential difference occurs between Therefore, an off-current (i.e., a leakage current) occurs.

[0586] Next comes the readout period. During the readout period, the amount of charge held by node A changes. The amount of change in the potential of node A caused by the above is measured. This will be explained with reference to FIG.

[0587] When the read period starts, the capacitance connected to node A is held over time. The amount of charge changes, and the potential of node A changes accordingly. This means that the potential of the output terminal fluctuates over time, so the output of the output circuit 406 The potential of the terminals also fluctuates.

[0588] In the readout period, the measurement period M of the change in the potential of node A and the charge of node A are It is preferable to repeat the accumulation period S and the measurement of the amount of change in the potential of the node A. By repeatedly storing and storing a load, it is possible to confirm that the measured voltage value is the value in a steady state. In other words, the current I flowing through node A is A Of these, the transient current As a result, it is possible to eliminate the current component that decreases over time after the start of measurement. As a result, the leakage current can be measured with higher accuracy.

[0589] In advance, the potential of node A, V A By determining the relationship between the output potential Vout and The output potential Vout to the potential V at node A A In general, it is possible to obtain the Potential V A can be expressed as a function of the output potential Vout as follows:

[0590]

number

[0591] In addition, the charge Q of the capacitance connected to node A A is the potential V of node A. A , connected to node A The capacity C A , using a constant (const), it is expressed as follows. Here, Capacitance C connected to A A is the capacitance of the capacitive element 400 and other capacitances (the input capacitance of the output circuit 406). It is the sum of several quantities.

[0592]

number

[0593] Current I at node A A is the charge flowing into (or out of) node A Since this is the time derivative of the current I Ais expressed as follows:

[0594]

number

[0595] In this way, the capacitance C connected to node A A , and the output potential Vout of the output circuit 406. From the time change Δt, the current I A can be sought.

[0596] In addition, the current I A is the current I flowing through transistor 404 dev and other current components I le ak Therefore, the current I flowing through the transistor 404 is dev To get the value accurately, The current I flowing through transistor 404 dev For other current components I leak Small enough It is desirable to measure the current component I leak Quote , current I A The current I flowing through transistor 404 is subtracted from dev Even if we improve the accuracy of good.

[0597] Here, in the measurement period M, the potential V2 is set to a low potential (L5) and the potential Vext_a is set to a low potential (L6). The transistor 402 is turned on as the output terminal (L4). In order to achieve the on state, the low potential of the potential Vext_a (L4) is lower than the low potential of the potential V2 (L5). The potential V1 is a high potential (H3). The potential Vext_c is a low potential (L2). The potential V3 is a low potential (L1). The potential Vext_b is a low potential (L2), and the potential V4 Let be Vss.

[0598] In addition, during the accumulation period S, the potential V2 is set to a high potential (H4), and the potential Vext_a is set to a high potential ( The potential V1 is set to a low potential (L3) to turn off the transistor 402. However, the potential V1, the potential V2, and the potential Vext_a are the same potential. _c is a low potential (L2), and the potential V3 is a low potential (L1). The potential (L2) and the potential V4 are set to Vss.

[0599] By the above-described method, it is possible to measure the minute current flowing through the transistor 404. do.

[0600] In this embodiment, the transistor 401 and the transistor 402 have a channel length L=3 μm. The channel width W=100 μm, and the transistor 403 has a channel length L=10 μm and a channel width W = 10 μm, and the transistor 404 has a channel length L = 0.8 μm and a channel width W = 1000 Each transistor was formed under the same conditions as those for Sample 1.

[0601] Next, the measurement sequence will be explained. There are two types of measurement sequences: A constant sequence was used.

[0602] The first measurement sequence begins with the measurement temperature set to 125° C., and the current flowing through the transistor is The Δt used to calculate I is 1 hour, and the cycle in which the writing period is set every Δt is 10 Next, the measurement temperature was set to 85°C, Δt was set to 6 hours, and the writing period was set to 1000 times for each Δt. The cycle of providing the above was repeated four times.

[0603] The second measurement sequence begins with a measurement temperature of 150°C, Δt of 1 hour, and The cycle of setting a writing period between each was repeated 10 times. Then, the measurement temperature was set to 125°C, Δt was set to 1 hour, and the cycle of setting a writing period every Δt was repeated 10 times. The measurement temperature is 85°C, Δt is 6 hours, and a write period is set every Δt. This was repeated four times. Next, the measurement temperature was set to 85°C, Δt was set to 12 hours, and data was written for each Δt. The cycle of setting a cooling period was repeated three times. Next, the measurement temperature was set to 60°C, and Δt was set to 60 The time was set to 100 s, and a cycle in which a writing period was provided every Δt was performed once.

[0604] In this embodiment, during the write period, the high potential (H1) of the potential V3 is set to 2V and the potential V The low potential (L1) of 3 was set to 1 V. The high potential (H2) of the potential Vext_c was set to 5 V, and the low potential ( The high potential (H3) of the potential V1 was set to 3 V, and the low potential (L3) was set to 1.5 V. The high potential (H4) of the potential Vext_a was set to 1.5 V, and the low potential (L4) was set to -1 V. The high potential (H4) of the potential V2 was set to 1.5 V, and the low potential (L5) was set to -2 V. b is set to −3 V, the transistor 404 is turned off, and the potential V4 is set to 1 V. , 2V was applied to node A.

[0605] In addition, during the readout period, the measurement period M is 10 seconds and the hold period S is 290 seconds. The read operation was repeated and the output potential Vout was measured.

[0606] In this embodiment, during the readout period, the high potential (H1) of the potential V1 is set to 5 V, and the low potential (H2) is set to 1 V. The high potential (H4) of the potential Vext_a was set to 1.5 V, and the low potential ( L4) was set to -1V. The high potential (H4) of potential V2 was set to 1.5V and the low potential (L5) was set to -2V. The low potential (L2) of the potential V3 was set to 1 V. The low potential (L2) of the potential Vext_c was set to The potential Vext_b is set to −3 V, the transistor 404 is turned off, and the potential Position V4 was set to 1V.

[0607] As an example of the measurement data, FIG. 50 shows the elapsed time and the output in the second measurement sequence. 50 shows the relationship between the output potential Vout of the circuit 406 and the output potential Vout of the circuit 406. You can see the change in potential.

[0608] Figure 51 shows the leakage current calculated by measuring the output potential Vout. Figure 51(A) shows FIG. 51(B) shows the results of the measurement in the first measurement sequence, and FIG. 51(B) shows the results of the measurement in the second measurement sequence. The results are shown in Fig. 51 (A) and (B). 13 is a diagram showing the relationship between the capacitance and the leakage current flowing between the gate electrodes.

[0609] In Figures 51(A) and (B), the leakage current measured immediately after the start of measurement gradually It was found that the temperature tends to decrease and converge to a certain value. In the highest condition, the lowest measured leakage current is taken as the leakage current at that temperature. did.

[0610] From Figure 51(A), the leakage current is 5×10 when the measurement temperature is 125°C. -21 A / μm (5zA / μm) or less, and 1×10 -22 A / μm(10 0yA / μm (Yoctoampere: 1yA is 10 -24 A) was less than 100%.

[0611] Also, from Figure 51(B), the leakage current is 1.5×10 -20 A / μm (15zA / μm (zeptoampere: 1zA is 10 -21 A) Less than, When the constant temperature is 125°C, it is 2×10 -21 A / μm (2zA / μm) or less, measurement temperature At 85°C, it is 5×10 -23 A / μm (50yA / μm (yoctoampere: 1yA is 10 -24 A)) is less than 6 x 10 when the measurement temperature is 60°C. -24 A / μm(6yA / The grain size was less than 1 μm.

[0612] From the above results, it is clear that the influence of transient current changes can be reduced by increasing the measurement temperature at the start of the measurement. It was found that this effectively suppresses the leakage current inherent to transistors and allows the measurement of the leakage current. .

[0613] As described above, according to this embodiment, a transistor using an oxide semiconductor that is highly purified and has a suppressed oxygen vacancy was obtained. It was confirmed that the off-current of the transistor was sufficiently small.

[0614] Next, the Arrhenius plot of the leakage current shown in FIG. 51(B) is shown in FIG. As shown in the figure, the temperature dependence of the leakage current measured above is linear, and the activation energy Since it is almost constant, it was confirmed that there is nothing unnatural in the measured values. EXAMPLES

[0615] In this example, the off-state current of Sample 6, which was fabricated in the same manner as Sample 1 in Example 1, was Measured.

[0616] The off-state current was measured in the same manner as in Example 4. The measurement sequence used was as follows: This is a first measurement sequence.

[0617] FIG. 53(A) shows the leakage current calculated by measuring the output potential Vout. FIG. 53(B) shows an Arrhenius plot of the leakage current shown in FIG. 53(A). ), (B) shows that the leakage current is 1×10 when the measurement temperature is 125°C. -20 A / μm (10zA / μm) or less, and 2×10 when the measurement temperature is 85°C -22 A / μm(200 The electrical conductivity was less than yA / μm.

[0618] As described above, the semiconductor device according to one embodiment of the present invention has a lower layer of a transistor including an oxide semiconductor. Even in a structure in which a transistor including a single crystal semiconductor is provided, a transistor including an oxide semiconductor It was confirmed that the off-state current of the transistor was sufficiently small.

[0619] <Reference example> As a reference example, the required retention time and the target (required) leakage current at 85°C for each device are A note about the flow.

[0620] Using Figure 54, we explain the required retention period for each device and the target leakage current at 85°C. do.

[0621] The semiconductor device shown in FIG. 34B is a DOSRAM (Dynamic Oxide Se It is called an oxidized microconductor random access memory (RAM). The transistors using solid semiconductors are used as the selection transistors (switching elements) of memory cells. It is a memory device that uses 1000 times as much transistors as possible.

[0622] When the minimum processing dimension is F, the area occupied by one memory cell is 8F 2 As D OSRAM has set a target current of less than 100aA / μm and a retention time of 1 hour. For this period, the storage capacitance is 30 fF and the allowable threshold fluctuation is 0.3 V.

[0623] In the normally-off CPU shown in FIG. 36 and FIG. 37, the target current of the transistor is 3 Less than zA / μm, retention time is more than 1 day, retention capacitance is 184fF, and allowable threshold fluctuation is 0.1V It is.

[0624] The semiconductor device shown in FIG. 2 is a non-volatile oxide random access memory (NOSRAM). It is called Semiconductor Random Access Memory (SRAM). The target current for small-scale NOSRAM transistors is less than 93yA / μm, and the retention time is More than 10 years, retention capacitance is 21fF, and allowable threshold drift is 0.5V. Also, two-level NOS The target current of the RAM transistor is less than 1.5yA / μm, the retention time is more than 10 years, The capacitance is 39aF and the allowable threshold voltage variation is 0.5V. The target current of the resistor is less than 0.02yA / μm, the retention time is more than 10 years, and the retention capacity is 39 aF, the allowable threshold variation is 0.1V.

[0625] The target current of FPGA transistors is less than 44yA / μm, and the retention time is more than 10 years. The storage capacitance is 184fF and the allowable threshold variation is 0.3V. [Explanation of symbols]

[0626] 10 Laminated structure 11 layers 12 layers 21 Insulating layer 22 Insulating layer 24 electronic 31 Wiring layer 32 wiring layer 41 Barrier Layer 100 transistors 101a Oxide layer 101b Oxide layer 102 Semiconductor layer 103a electrode 103b electrode 104 Gate insulation layer 105 Gate electrode 107 Insulating layer 108 Insulating layer 110 Transistor 111 Semiconductor substrate 112 Semiconductor layer 113a Low resistance layer 113b Low resistance layer 114 Gate Insulation Layer 115 Gate electrode 120 Barrier Layer 121 Insulating layer 122 Insulating layer 123 Insulating Layer 124 Insulating Layer 125 Insulating layer 126 Insulating Layer 130 capacity 131 Wiring 132 Wiring 133 Wiring 134 Wiring 140 Insulating layer 141 Wiring 142 Wiring 151 Wiring 152 Wiring 160 Transistors 161 Plug 162 Plug 163 Plug 164 Plug 165 Plug 166 Plug 167 Plug 174 Conductive Film 180 Transistors 204 Gate electrode 206 Oxide Semiconductor Film 216a Conductive film 216b Conductive film 220 Conductive Film 260 Opening 400 Capacitive element 401 Transistor 402 Transistor 403 Transistor 404 Transistor 406 Output circuit 610 Electron Gun Room 612 Optical system 614 Sample Room 616 Optical system 618 Camera 620 Observation Room 622 Film Room 624 electronic 628 Substance 632 Fluorescent Screen 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal line driver circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RFID Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RFID

Claims

1. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitance element; a second insulating layer having a region overlying the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source and a drain of the second transistor; a fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor; a fifth conductive layer having a region located above the fourth insulating layer and functioning as a second gate electrode of the second transistor; the third conductive layer is always electrically connected to a gate of the first transistor through a first opening provided in the second insulating layer; the fourth conductive layer is always electrically connected to one of the source and the drain of the first transistor through a second opening provided in the second insulating layer; the first conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the second conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween.

2. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitance element; a second insulating layer having a region overlying the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source and a drain of the second transistor; a fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor; a fifth conductive layer having a region located above the fourth insulating layer and functioning as a second gate electrode of the second transistor; the third conductive layer is always electrically connected to a gate of the first transistor through a first opening provided in the second insulating layer; the fourth conductive layer is always electrically connected to one of the source and the drain of the first transistor through a second opening provided in the second insulating layer; the first conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the second conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the oxide semiconductor layer contains In, Ga, and Zn; The second insulating layer comprises nitrogen and silicon.

3. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitance element; a second insulating layer having a region overlying the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source and a drain of the second transistor; a fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor; a fifth conductive layer having a region located above the fourth insulating layer and functioning as a second gate electrode of the second transistor; the third conductive layer is always electrically connected to a gate of the first transistor through a first opening provided in the second insulating layer; the fourth conductive layer is always electrically connected to one of the source and the drain of the first transistor through a second opening provided in the second insulating layer; the first conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the second conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the first conductive layer comprises molybdenum; The second conductive layer comprises molybdenum.

4. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one of the electrodes of the capacitance element; a second insulating layer having a region overlying the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and having a channel formation region of the second transistor; a third conductive layer having a region in contact with the oxide semiconductor layer and functioning as one of a source and a drain of the second transistor; a fourth conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor; a fifth conductive layer having a region located above the fourth insulating layer and functioning as a second gate electrode of the second transistor; the third conductive layer is always electrically connected to a gate of the first transistor through a first opening provided in the second insulating layer; the fourth conductive layer is always electrically connected to one of the source and the drain of the first transistor through a second opening provided in the second insulating layer; the first conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the second conductive layer has a region overlapping with the oxide semiconductor layer with the third insulating layer interposed therebetween and a region overlapping with the third conductive layer with the third insulating layer interposed therebetween; the oxide semiconductor layer contains In, Ga, and Zn; the second insulating layer comprises nitrogen and silicon; the first conductive layer comprises molybdenum; The second conductive layer comprises molybdenum.

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