Gate drive circuit, power conversion device, and gate drive method

Abstract

To provide a gate drive circuit capable of preventing deviation in the on / off timing of each semiconductor switching element.SOLUTION: A gate drive circuit includes an input unit 20 for a main gate signal for controlling the switching operation of first and second semiconductor switching elements 11, 12 connected in parallel, drive units 31, 32 for driving the first and second semiconductor switching elements 11, 1 on the basis of the main gate signal, a first source resistor 51 of the first semiconductor switching element 11, a second source resistor 52 of the second semiconductor switching element 12, a first voltage sensor 41 for detecting a voltage across the first source resistor 51, a second voltage sensor 42 for detecting a voltage across the second source resistor 52, and correction units 21, 22 for correcting the timing of the switching operation of the first and second semiconductor switching elements 11, 12 on the basis of the detection results of the first and second voltage sensors 41, 42, respectively.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a gate drive circuit, a power conversion device incorporating the gate drive circuit, and a gate drive method. [Background technology]

[0002] Voltage-driven power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are often used in power conversion devices for electric vehicles and railways. In order to increase the power capacity of power conversion devices and broaden the range of applications, the application of power conversion devices in which multiple semiconductor switching elements are connected in parallel has been considered.

[0003] In such a power conversion device, it is known that the wiring inductance between the semiconductor switching elements is adjusted in order to equalize the currents flowing through the semiconductor switching elements connected in parallel (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-17655 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, even if the wiring inductance is adjusted, if there is a mismatch in the on / off timing of each semiconductor switching element, an excessive current may flow through the semiconductor switching element in which the mismatch occurs, possibly damaging the semiconductor switching element.

[0006] An object of the present invention is to provide a gate drive circuit, a power conversion device, and a gate drive method that can prevent deviations in the on / off timing of each semiconductor switching element connected in parallel. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, a gate drive circuit according to one aspect of the present invention includes an input unit that inputs a main gate signal for controlling switching operation of first and second semiconductor switching elements connected in parallel to simultaneously turn them into a conductive state / non-conductive state; a drive unit that is connected to the gate terminals and source terminals of each of the first and second semiconductor switching elements and changes a gate voltage applied to each of the gate terminals of the first and second semiconductor switching elements based on the main gate signal; a first source resistor connected in series between the source terminal of the first semiconductor switching element and the drive unit, and a second source resistor connected in series between the source terminal of the second semiconductor switching element and the drive unit; a first voltage sensor that detects a voltage across the first source resistor, a second voltage sensor that detects a voltage across the second source resistor, and a correction unit that corrects the timing of the switching operation of each of the first and second semiconductor switching elements based on the detection results of the first and second voltage sensors, respectively.

[0008] Moreover, a power conversion device according to an aspect of the present invention includes the gate drive circuit according to any one of claims 1 to 9 mounted thereon.

[0009] Furthermore, a gate driving method according to one aspect of the present invention includes the steps of: inputting a main gate signal for controlling a switching operation for simultaneously turning first and second semiconductor switching elements connected in parallel into a conductive state / non-conductive state; correcting the main gate signal with a stored output timing; changing a gate voltage applied to each of the gate terminals of the first and second semiconductor switching elements based on the corrected main gate signal; detecting a voltage across a source resistor connected in series to the source terminal of the first semiconductor switching element, detecting a voltage across a source resistor connected in series to the source terminal of the second semiconductor switching element; determining whether the voltage across the source resistor exceeds a threshold; and not updating the stored output timing if the voltage does not exceed the threshold. and updating the stored output timing when the voltage across the source resistor exceeds a threshold value. Effect of the Invention

[0010] According to one aspect of the present invention, it is possible to prevent deviation in the on / off timing of each semiconductor switching element connected in parallel. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic configuration diagram of MOSFET elements and a gate drive circuit connected in parallel in a first embodiment of the present invention. [Diagram 2] FIG. 1 is an equivalent circuit diagram including main circuit wiring inductance of MOSFET elements connected in parallel. [Diagram 3] This is an equivalent circuit diagram including the gate-source parasitic capacitance of a single MOSFET element, and the wiring inductance of the gate terminal and auxiliary source terminal. [Figure 4] This shows a comparison diagram of the current waveforms flowing through the auxiliary source terminal when there is variation in wiring inductance. [Diagram 5]The diagram shows the current waveforms of the current flowing through the auxiliary source terminal at turn-on and turn-off when the main currents flowing through the MOSFET elements are unbalanced. [Figure 6] In the first embodiment of the present invention, the internal configuration of a gate signal correction circuit that corrects the rise and fall times of the gate signal of a MOSFET element using the voltage across a source resistor and a master gate signal is shown. [Figure 7] FIG. 11 is a schematic configuration diagram of MOSFET elements connected in parallel and a gate drive circuit in a second embodiment of the present invention. [Figure 8] FIG. 11 is a schematic configuration diagram of MOSFET elements connected in parallel and a gate drive circuit in a third embodiment of the present invention. [Figure 9] 13 is a flowchart showing a control process procedure of a gate drive circuit in a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Each embodiment of the present invention is an example of an apparatus or method for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the material, shape, structure, arrangement, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the embodiment, a switching circuit in which three MOSFET (metal-oxide-semiconductor) elements are connected in parallel will be described as an example, but the present invention can be applied to any circuit configuration in which multiple power semiconductor elements are connected in parallel.

[0014] <First embodiment> 1 shows a schematic configuration diagram of MOSFET elements 11, 12, and 13 connected in parallel and a gate drive circuit 1A in the first embodiment of the present invention. The MOSFET elements 11, 12, and 13 respectively have drain terminals 111, 121, and 131 through which a main current flows, source terminals 112, 122, and 132, gate terminals 113, 123, and 132 connected to the gate drive circuit 1A, and auxiliary source terminals 114, 124, and 134 connected to the gate drive circuit 1A. The object to be driven by the gate drive circuit 1A is not limited to MOSFET elements, and may be, for example, an insulated gate bipolar transistor (IGBT) as a semiconductor switching element.

[0015] The gate drive circuit 1A is composed of a master gate signal (an example of a main gate signal) for controlling the switching operation of simultaneously turning the MOSFET elements 11, 12, and 13 into a conductive state (on state) / non-conductive state (off state), specifically, a master gate signal input section (an example of an input section) 20 for inputting a master gate signal for controlling the entire switching circuit, gate signal correction circuits (an example of first and second gate signal correction sections) 21, 22, and 23 for controlling the current balance between the MOSFET elements 11, 12, and 13, and drive circuits (an example of first and second element drive sections) 31, 32, and 33 for controlling the gate-source voltage of each MOSFET element 11, 12, and 13.

[0016] The gate drive circuit 1A also includes source resistors 51, 52, 53 connected in series to auxiliary source terminals 114, 124, 134 of the MOSFET elements 11, 12, 13, and voltage sensors 41, 42, 43 for detecting voltages across the source resistors 51, 52, 53. Specifically, the drive circuits 31, 32, 33 generate gate drive signals for changing the gate voltages applied to the gate terminals 113, 123, 133 of the MOSFET elements 11, 12, 13, based on the master gate signal sent from the master gate signal input unit 20 via the gate signal correction circuits 21, 22, 23.

[0017] Voltage sensors 41, 42, 43 detect the voltages across source resistors 51, 52, 53 and input the obtained voltage information to gate signal correction circuits 21, 22, 23. The gate signal correction circuits 21, 22, 23 use the master gate signal and voltage information input to master gate signal input section 20 to correct the turn-on and turn-off timing of each MOSFET element 11, 12, 13 and balance the main currents. The corrected master gate signal is input to drive circuits 31, 32, 33 for each MOSFET element 11, 12, 13.

[0018] Freewheel diodes 61, 62, 63 connected in anti-parallel are connected to the MOSFET elements 11, 12, 13, respectively. Specifically, drain terminals 111, 121, 131 of the MOSFET elements 11, 12, 13 are connected to cathode terminals provided on the freewheel diodes 61, 62, 63. Source terminals 112, 122, 132 of the MOSFET elements 11, 12, 13 are connected to anode terminals provided on the freewheel diodes 61, 62, 63. The freewheeling diodes 61, 62, and 63 may be replaced with body diodes of the MOSFET elements 11, 12, and 13, respectively.

[0019] The drain terminals 111, 121, 131 of the MOSFET elements 11, 12, 13 and the cathode terminals of the freewheeling diodes 61, 62, 63 are connected to a high potential supply terminal Thp to which a high potential is supplied. For example, when the MOSFET elements 11, 12, 13 are applied to semiconductor switching elements for an upper arm of an inverter circuit (an example of a power conversion device), the high potential supply terminal Thp becomes a terminal to which a positive DC power source is supplied or a connection part to be connected to a positive side line to which the DC power source is supplied. When the MOSFET elements 11, 12, 13 are applied to semiconductor switching elements for a lower arm of an inverter circuit (an example of a power conversion device), the high potential supply terminal Thp becomes an AC output terminal.

[0020] The source terminals 112, 122, 132 of the MOSFET elements 11, 12, 13 and the anode terminals of the freewheeling diodes 61, 62, 63 are connected to a low potential supply terminal Tlp to which a low potential is supplied. For example, when the MOSFET elements 11, 12, 13 are applied to semiconductor switching elements for an upper arm of an inverter circuit (an example of a power conversion device), the low potential supply terminal Tlp becomes an AC output terminal. When the MOSFET elements 11, 12, 13 are applied to semiconductor switching elements for a lower arm of an inverter circuit (an example of a power conversion device), the low potential supply terminal Tlp becomes a ground terminal or a terminal to which a negative-side DC power supply is supplied, or a connection part to be connected to a negative-side line to which the DC power supply is supplied.

[0021] 2 shows an equivalent circuit diagram including the main circuit wiring inductance of the parallel-connected MOSFET elements 11, 12, and 13. It is assumed that the source terminals 112, 122, and 132 of the MOSFET elements 11, 12, and 13 have wiring inductances Ls1, Ls2, and Ls3. During switching operation, the di / dt of the main currents id1, id2, and id3 flowing through the MOSFET elements 11, 12, and 13 increases, and voltages Vs1, Vs2, and Vs3 are generated in the wiring inductances. For example, when the wiring inductances Ls1, Ls2, Ls3 or the di / dt of the main currents id1, id2, id3 and both are inconsistent and Vs1 is greater than Vs2, Vs3, a voltage difference occurs between the auxiliary source terminal 114 of the MOSFET element 11 and the auxiliary source terminals 124, 134 of the MOSFET elements 12 and 13, and currents is1, is2, is3 flow between the auxiliary source terminals 114, 124, 134 via the common connection part. In other words, when the wiring inductances Ls1, Ls2, Ls3 of the MOSFET elements 11, 12, 13 or the di / dt of the main currents id1, id2, id3, or both, are inconsistent, voltages Vs1, Vs2, Vs3 of the wiring inductances are generated, and due to the voltage difference, currents is1, is2, is3 flow between the auxiliary source terminals 114, 124, 134 via the common connection part.

[0022] FIG. 3 shows an equivalent circuit diagram including, for example, the gate-source parasitic capacitance Cgs of the single MOSFET element 11, the wiring inductances of the gate terminal 113, and the auxiliary source terminal 114. In FIG.

[0023] Moreover, the gate terminal 113 and the auxiliary source terminal 114 are connected to a bypass capacitor Cbp in the drive circuit 31. During switching operation, the current is flowing through the auxiliary source terminal 114 may cause ringing in an LCR loop consisting of the bypass capacitor Cbp, wiring inductance, gate resistance Rg, source resistance Rs, and parasitic capacitance Cgs. The ringing may cause an overshoot or undershoot of the gate voltage, which may result in a short circuit of the upper and lower arms due to erroneous turn-on, or element destruction due to the gate terminal 113 exceeding its withstand voltage, so the current flowing through the auxiliary source terminal 114 should be suppressed.

[0024] Fig. 4 shows a comparison diagram of current waveforms is1 and is2 flowing through auxiliary source terminals 114 and 124 when there is variation in wiring inductances Ls1, Ls2, and Ls3. Fig. 4(a) shows a comparison diagram of current waveforms is1 and is2 when source resistors 51, 52, and 53 are inserted into auxiliary source terminals 114, 124, and 134. Fig. 4(b) shows a comparison diagram of current waveforms is1 and is2 when source resistors 51, 52, and 53 are not inserted into auxiliary source terminals 114, 124, and 134.

[0025] 4(a) and (b), the vertical axis indicates the amplitude of current and voltage, and the horizontal axis indicates time. In addition, in FIG. 4(a) and (b), (1) indicates the current waveform of the main current id1 flowing from the high potential supply terminal Thp to the drain terminal 111 of the MOSFET element 11, (2) indicates the difference between the voltages Vs1 and Vs2 applied to the wiring inductances Ls1 and Ls2, (3) indicates the current waveform of the current is1 flowing to the auxiliary source terminal 114, and (4) indicates the current waveform of the current is2 flowing to the auxiliary source terminal 124. In addition, the comparison is made on the assumption that the main currents id1, id2, and id3 flowing to the MOSFET elements 11, 12, and 13 are balanced.

[0026] When the source resistors 51, 52 are not inserted in the auxiliary source terminals 114, 124, a voltage difference of only about 20uV between Vs1 and Vs2 (Fig. 4(a)(2)) causes a current is1 of about 10A to flow in the auxiliary source terminal 114 (Fig. 4(a)(3)). In contrast, when the source resistors 51, 52, 53 of 0.1Ω are inserted in the auxiliary source terminals 114, 124, 134 of the MOSFET elements 11, 12, 13, it can be confirmed from the waveforms that the currents is1, is2 hardly flow in the auxiliary source terminals 114, 124 (Fig. 4(b)(3)(4)). Therefore, by inserting the source resistors 51, 52, 53 in the auxiliary source terminals 114, 124, 134 and increasing the impedance, the current caused by the variation in wiring inductance can be suppressed.

[0027] Fig. 5 shows the waveforms of currents is1 and is3 that flow through auxiliary source terminals 114 and 134 at turn-on and turn-off when main currents id1, id2, and id3 that flow through MOSFET elements 11, 12, and 13 are unbalanced. Fig. 5(a) shows the waveforms of currents is1 and is3 at turn-on, and Fig. 5(b) shows the current waveforms is1 and is3 at turn-off.

[0028] 5(a) and (b), the vertical axis indicates the amplitude of current and voltage, and the horizontal axis indicates time. Also, in Fig. 5(a) and (b), (1) indicates the current waveforms of main currents id1, id2, and id3 flowing from high potential supply terminal Thp to drain terminal 111 of MOSFET element 11, (2) indicates the difference between voltages Vs1 and Vs3 applied to wiring inductances Ls1 and Ls3, (3) indicates the current waveform of current is1 flowing to auxiliary source terminal 114, and (4) indicates the current waveform of current is3 flowing to auxiliary source terminal 134.

[0029] In this case, it is assumed that the current caused by the variation in wiring inductance is suppressed by inserting 0.1 Ω source resistors 51, 52, 53 into the auxiliary source terminals 114, 124, 134 of the MOSFET elements 11, 12, 13. When the rise of the main current id3 of the MOSFET element 13 is slower than the main currents id1, id2 of the MOSFET elements 11, 12 (FIG. 5(a)(1)), a voltage difference of several volts occurs between the auxiliary source terminal 134 of the MOSFET element 13 and the auxiliary source terminals 114, 124 of the MOSFET elements 11, 12 (FIG. 5(a)(2)), and a current flows instantaneously from other elements to the auxiliary source terminal 134 of the MOSFET element 13 (FIG. 5(a)(4)). Similarly, if the fall of the main current id3 at turn-off is slower than the main currents id1 and id2 (FIG. 5(b)(1)), a current flows from the auxiliary source terminal 134 of the MOSFET element 13 to other elements (FIG. 5(b)(4)).

[0030] Since the voltage difference at the auxiliary source terminals 114, 124, 134 caused by the imbalance of the main currents id1, id2, id3 is much larger than the voltage difference caused by variations in wiring inductance, it is extremely difficult to suppress the currents is1, is2, is3 flowing through the auxiliary source terminals 114, 124, 134 using the source resistors 51, 52, 53 inserted between the auxiliary source terminals 114, 124, 134 and the drive circuits 31, 32, 33.

[0031] However, the currents is1, is2, is3 can be suppressed by adjusting the switching timing of each of the MOSFET elements 11, 12, 13 and balancing the main currents id1, id2, id3. In the first embodiment of the present invention, the magnitudes of the currents is1, is2, is3 flowing through the auxiliary source terminals 114, 124, 134 of the MOSFET elements 11, 12, 13 are detected from the voltages Vrs1, Vrs2, Vrs3 across the source resistors 51, 52, 53 connected in series to the auxiliary source terminals 114, 124, 134, and the switching timing of each of the MOSFET elements 11, 12, 13 is corrected based on the voltage information.

[0032] 6 shows an internal configuration of a gate signal correction circuit 21 that corrects the rise and fall times of the gate signal of a MOSFET element 11 by using a voltage Vrs1 across source resistor 51 and a master gate signal in the first embodiment of the present invention. Note that the gate signal correction circuits 22 and 23 of the MOSFET elements 12 and 13 have the same configuration as the gate signal correction circuit 21 of the MOSFET element 11.

[0033] The gate signal correction circuit 21 has a turn-on time correction portion and a turn-off time correction portion, and is composed of comparator circuits 211 and 215, D latch circuits 212 and 216, counter circuits 213, 214, 217 and 218, a logical AND circuit 219, and logical OR circuits 220 and 221.

[0034] In the turn-on time correction portion, a positive current flows through the auxiliary source terminal 114. Then, voltage information output from the voltage sensor 41 is input to one input terminal of the comparator circuit 211. A turn-on threshold voltage Vref_on for current balance control is input to the other input terminal of the comparator circuit 211. The comparator circuit 211 compares the voltage information output from the voltage sensor 41 with the turn-on threshold voltage Vref_on for current balance control, and outputs an H signal to the D latch circuit 212 if the voltage Vrs1 across the source resistor 51 exceeds the turn-on threshold voltage Vref_on for current balance control.

[0035] When the D latch circuit 212 receives an H signal from the comparator circuit 211, the CLK signal changes to H and the D latch circuit 212 outputs an H signal from the output Q. The counter circuit 213 receives an H signal at the CLK input terminal, increments the output signal by 1, counts the number of delays, and stores the amount of correction. The counter circuit 214 treats the next master gate rising signal as a Load signal, subtracts the number of input delays (amount of correction) after receiving the rising signal, and outputs an L signal until the number of delays becomes 0. The output time width of the L signal corresponds to the time to be corrected, and is the number of delays x the period of the time correction clock signal. Finally, the logical AND circuit 219 corrects the turn-on signal by calculating the logical AND of the next master gate signal and the turn-on delay signal.

[0036] In the turn-off time correction portion, when the main current id1 of the MOSFET element 11 is smaller than those of the other elements, a reverse current flows through the auxiliary source terminal 114. Then, voltage information output from the voltage sensor 41 is input to one input terminal of the comparator circuit 215. A turn-off threshold voltage Vref_off for current balance control is input to the other input terminal of the comparator circuit 215. The comparator circuit 215 compares the voltage information output from the voltage sensor 41 with the turn-off threshold voltage Vref_off for current balance control, and outputs an H signal to the D latch circuit 216 when the reverse voltage of the voltage Vrs1 across the source resistor 51 exceeds the turn-off threshold voltage Vref_off for current balance control.

[0037] When the D latch circuit 216 receives an H signal from the comparator circuit 215, the CLK signal changes to H and the D latch circuit 216 outputs an H signal from the output Q. Similarly, the counter circuit 217 receives an H signal at the CLK input terminal, increments the output signal by 1, counts the number of delays, and stores the amount of correction. The counter circuit 218 treats the next falling signal of the master gate as a Load signal, subtracts the number of input delays (amount of correction) after receiving the falling signal, and outputs an H signal before the number of delays becomes 0. The logical OR circuit 220 corrects the turn-off signal by calculating the logical AND of the turn-on corrected signal and the next turn-off delay signal.

[0038] The turn-on corrected signal and the turn-off corrected signal are each selectively output as a gate signal for the MOSFET element 11. Furthermore, the logical sum circuit 221 generates a signal for correcting both turn-on and turn-off by calculating the logical sum of the turn-on corrected signal and the turn-off delay signal, and can output the signal as a gate signal.

[0039] The D latch circuit 212 and the D latch circuit 216 are reset by the falling and rising signals of the master gate signal, respectively, and output an H signal only once in one control cycle. This allows a delay time of one clock signal cycle to be added for each control cycle, gradually adjusting the switching timing of each element. Also, when the current flowing through the auxiliary source terminal 114 falls below a threshold, the number of delays counted by the counter circuits 213 and 217 is held, and a current balance state is maintained. Also, an upper limit is set for the time length of the delay signal, preventing a short circuit of the upper and lower arms due to a shortened dead time width. Also, a Down input is provided to the counter circuits 213 and 217, which allows the time width of the delay signal to be shortened.

[0040] 6, an arm short-circuit detection circuit 231 and a short-circuit detection threshold voltage Vref_st are separately provided. When the voltage Vrs1 exceeds the short-circuit detection threshold voltage Vref_st, a short-circuit detection signal is output. The short-circuit detection threshold voltage Vref_st is assumed to be higher than the current balance control threshold voltages Vref_on and Vref_off. In other words, the gate signal correction circuit 21 compares the voltage Vrs1 with the threshold voltage Vref_st in the arm short-circuit detection circuit 231, and when the voltage Vrs1 exceeds the threshold voltage Vref_st, it determines that a large current will flow in the auxiliary source terminal due to an arm short circuit or the like, and outputs a short-circuit detection signal as an alarm, allowing the administrator to be notified quickly.

[0041] Although the first embodiment has been described above, the present invention is not limited to this. For example, in order to prevent erroneous detection of the voltage sensor due to disturbance, an average calculator is added before the comparator circuits 211 and 215, and the average value of the voltage detection value for several control cycles is calculated and compared with the threshold voltage for current balance control. Alternatively, the counter circuits 213 and 217 count the delay number by one after receiving a continuous H signal for a certain period of time. Another method for adjusting the switching timing is to regard the source resistors 51, 52, and 53 connected to the auxiliary source terminals 114, 124, and 134 as part of the gate resistor, change the resistance value of the source resistors 51, 52, and 53 according to the delay number generated by the gate signal correction circuits 21, 22, and 23, and adjust the switching speed. In addition to the internal configuration of the gate signal correction circuits 21, 22, and 23 shown in FIG. 6, any circuit may be used as long as it outputs a turn-on and turn-off delay signal according to the delay number.

[0042] <Effects of the First Embodiment> As described above, according to the first embodiment, the voltage sensors 41, 42, and 43 detect the source return currents caused by variations in the operation of the MOSFET elements 11, 12, and 13, and the operation timings of the MOSFET elements 11, 12, and 13 can be made uniform.

[0043] According to the first embodiment, the voltage sensors 41, 42, 43 detect the voltages across the source resistors 51, 52, 53, respectively, to detect the source return current, thereby suppressing the source return current caused by an error in wiring inductance. Furthermore, the suppression of ringing between the auxiliary source terminals 114, 124, 134 of the MOSFET elements 11, 12, 13, the balance control of the main currents id1, id2, id3 flowing through the MOSFET elements 11, 12, 13, respectively, and the short circuit detection function are realized by the source resistors 51, 52, 53 connected in series to the auxiliary source terminals 114, 124, 134 of the MOSFET elements 11, 12, 13, respectively, and a current sensor for measuring the main currents id1, id2, id3 is not required, thereby reducing the number of components and the cost.

[0044] Furthermore, according to the first embodiment, by providing the drive circuits 31, 32, and 33 for the MOSFET elements 11, 12, and 13, respectively, it is not necessary to use a large insulated power supply, the heat generation problem due to the insulated power supply is also eliminated, and the gate wiring can be shortened. Furthermore, by forming one circuit by the MOSFET element 11, the auxiliary source terminal 124, the source resistor 51, the drive circuit 31, and the gate terminal 113, a cross current that flows through the gate wiring of the MOSFET element 11 is eliminated. Furthermore, by providing the drive circuits 31, 32, and 33 for the MOSFET elements 11, 12, and 13, respectively, even if a new MOSFET element is added, the power supplied to the added MOSFET element can be secured.

[0045] Furthermore, according to the first embodiment, balance control of the main currents id1, id2, id3 is performed while short-circuit current detection is performed by the gate signal correction circuits 21, 22, 23, so that erroneous detection of an arm short circuit due to a current imbalance can be prevented.

[0046] <Second embodiment> 7 is a schematic diagram showing the configuration of MOSFET elements 11, 12, and 13 connected in parallel and a gate drive circuit 1B in the second embodiment of the present invention. In Fig. 7, the same parts as those in Fig. 1 are given the same reference numerals and detailed explanations are omitted.

[0047] The gate drive circuit 1B has a master drive circuit (one example of a drive section) 30 connected between a master gate signal input section 20 and gate signal correction circuits 21, 22, 23. The master drive circuit 30 is a circuit that integrates the drive circuits 31, 32, 33 described above, and generates a gate drive signal for changing the gate voltage applied to the gate terminals 113, 123, 133 of the MOSFET elements 11, 12, 13 based on the master gate signal input to the master gate signal input section 20.

[0048] The gate signal correction circuits 21, 22, and 23 correct the output timing of the gate drive signals to the gate terminals 113, 123, and 133 of the MOSFET elements 11, 12, and 13, based on the voltage information detected by the voltage sensors 41, 42, and 43.

[0049] <Effects of the second embodiment> As described above, according to the second embodiment, the drive circuits 31, 32, 33 for the MOSFET elements 11, 12, 13 can be consolidated into one master drive circuit 30, so there is no need to add drive circuits 31, 32, 33 for the MOSFET elements 11, 12, 13, and this prevents the cost and size of the gate drive circuit 1B from increasing.

[0050] <Third embodiment> The third embodiment of the present invention is configured such that the difference between the reference potential of the drive circuits 31, 32, and 33 and the source potential of the MOSFET elements 11, 12, and 13 in the first embodiment is suppressed. Fig. 8 shows a schematic configuration diagram of MOSFET elements 11, 12, and 13 connected in parallel and a gate drive circuit 1C in the third embodiment of the present invention. Note that Fig. 8 will explain the MOSFET elements 11 and 12 as representatives. Also, in the gate drive circuit 1C, the drive circuits 31 and 32 will be explained as representatives.

[0051] When a high-level master gate signal is input, the drive circuit 31 generates a reference potential (gate voltage) Vg by the internal bypass capacitor 311. A current flowing from the drive circuit 31 charges a gate-source capacitance formed between the gate and source of the MOSFET element 11 via a gate resistor 71 connected in series to the gate terminal 113. When the reference potential Vg exceeds the threshold voltage between the gate and source of the MOSFET element 11, the MOSFET element 11 enters a conductive state (ON state).

[0052] Furthermore, when a high-level (turn-on) master gate signal is input to drive circuit 32, it generates a reference potential (gate voltage) Vg by means of an internal bypass capacitor 321. A current flowing from drive circuit 32 charges a gate-source capacitance formed between the gate and source of MOSFET element 12 via gate resistor 72 connected in series to gate terminal 123. When reference potential Vg exceeds a threshold voltage between the gate and source of MOSFET element 12, MOSFET element 12 enters a conductive state (ON state).

[0053] When the MOSFET elements 11 and 12 are turned on, a source return current is flows between a source resistor 51 connected in series to the auxiliary source terminal 114 of the MOSFET element 11 and a source resistor 52 connected in series to the auxiliary source terminal 124 of the MOSFET element 12. Then, a source potential (Vrs) in the direction from the auxiliary source terminal 114 to the drive circuit 31 (positive direction) is applied to the source resistor 51, and a source potential (Vrs) in the direction from the drive circuit 32 to the auxiliary source terminal 124 (negative direction) is applied to the source resistor 52.

[0054] Furthermore, when the MOSFET element 11 is turned on, one circuit is formed by the source resistor 51, the bypass capacitor 311, and the gate resistor 71. Similarly, when the MOSFET element 12 is turned on, one circuit is formed by the source resistor 52, the bypass capacitor 321, and the gate resistor 72.

[0055] A potential obtained by adding the reference potential Vg and the source potential Vrs is applied to the gate resistor 71, and a potential which is the difference between the reference potential Vg and the source potential Vrs is applied to the gate resistor 72. In such a case, there is a risk that the drive circuits 31 and 32 may malfunction due to fluctuations in the reference potential Vg.

[0056] Therefore, in the third embodiment, the resistance value of the source resistor 51 is made smaller than the resistance value required to drive the drive circuit 31. Specifically, it is made smaller than the resistance value of the gate resistor 71. Also, in the third embodiment, the resistance value of the source resistor 52 is made smaller than the resistance value required to drive the drive circuit 32. Specifically, it is made smaller than the resistance value of the gate resistor 72.

[0057] <Effects of the Third Embodiment> As described above, according to the third embodiment, the difference between the reference potential Vg of drive circuit 31 and the source potential Vrs of MOSFET element 11 and the difference between the reference potential Vg of drive circuit 32 and the source potential Vrs of MOSFET element 12 can be suppressed, thereby preventing malfunctions of drive circuits 31 and 32 due to fluctuations in the reference potential Vg.

[0058] <Modification of the third embodiment> As a modification of the third embodiment of the present invention, it is also possible to make the resistance value of the source resistors 51, 52 larger than the resistance value of the gate resistors 71, 72 of the MOSFET elements 11, 12. According to the modification of the third embodiment, the larger the resistance values ​​of the source resistors 51, 52, the more the source return current flowing between the auxiliary source terminals 114, 124 of the MOSFET elements 11, 12 can be suppressed. In addition, since the loss generated in the source resistors 51, 52 is proportional to the square of the source return current, the lower the current, the less heat the resistors generate.

[0059] <Fourth embodiment> In the fourth embodiment of the present invention, the gate signal correction circuits 21, 22, and 23 of the first embodiment are realized by one gate drive circuit 1D. FIG. 9 is a flowchart showing a control process procedure of the gate drive circuit 1D in the fourth embodiment of the present invention.

[0060] When the gate drive circuit 1D detects the master gate signal (step ST9a), it corrects the master gate signal using the stored output timing described later (step ST9b), and outputs the corrected master gate signal to the drive circuit 31 of the corresponding MOSFET element 11 to start driving the drive circuit 31 (step ST9c). After starting to drive the drive circuit 31, it detects voltage information output from the voltage sensors 41, 42, and 43 of the MOSFET elements 11, 12, and 13 (step ST9c), and determines whether the detected voltage exceeds a threshold value (step ST9d). If it is determined that the detected voltage exceeds the threshold value (step ST9d: Yes), the gate drive circuit 1D updates the stored output timing for the master gate signal to be output to the drive circuit 31 of the corresponding MOSFET element 11 (step ST9e).

[0061] On the other hand, if the detection voltage does not exceed the threshold value (step ST9d: No), the gate drive circuit 1D does not update the stored output timing of the master gate signal to be output to the drive circuit 31 of the corresponding MOSFET element 11, and waits for the next master gate signal. In this way, in the fourth embodiment, the same effects as in the first embodiment can be obtained.

[0062] <Other embodiments> As described above, the present technology has been described by the first to fourth embodiments and the modified third embodiment, but the description and drawings forming part of this disclosure should not be understood as limiting the present technology. If the gist of the technical contents disclosed in the above first to fourth embodiments is understood, it will be clear to a person skilled in the art that various alternative embodiments, examples, and operation techniques can be included in the present technology. In addition, the configurations disclosed in the first to fourth embodiments and the modified third embodiment can be appropriately combined within a range that does not cause contradictions. For example, the configurations disclosed in multiple different embodiments may be combined, and the configurations disclosed in multiple different modified versions of the same embodiment may be combined. [Explanation of symbols]

[0063] 1A, 1B, 1C, 1D Gate drive circuit 11, 12, 13 MOSFET elements 20 Master gate signal input section (an example of an input section) 21, 22, 23 Gate signal correction circuit (an example of the first and second gate signal correction units) 30 Master drive circuit (an example of a drive unit) 31, 32, 33 Drive circuit (an example of a drive unit for the first and second elements) 41, 42, 43 Voltage Sensor 51, 52, 53 Source Resistance 61, 62, 63 Freewheeling diode 71,72 Gate resistor 111,121,131 Drain terminal 112,122,132 Source terminal 113,123,133 Gate terminal 114,124,134 Auxiliary source terminals 211,215 Comparator circuit 212,216 D latch circuit 213, 214, 217, 218 Counter circuits 219 AND Circuit 220,221 OR circuit 231 Arm short circuit detection circuit 311 Bypass capacitor 321 Bypass Capacitor

Claims

1. an input section for inputting a main gate signal for controlling a switching operation of simultaneously turning on / off the first and second semiconductor switching elements connected in parallel; a driver connected to a gate terminal and a source terminal of each of the first and second semiconductor switching elements, and configured to change a gate voltage applied to each of the gate terminals of the first and second semiconductor switching elements based on the main gate signal; a first source resistor connected in series between a source terminal of the first semiconductor switching element and the drive unit, and a second source resistor connected in series between a source terminal of the second semiconductor switching element and the drive unit; a first voltage sensor that detects a voltage across the first source resistor, and a second voltage sensor that detects a voltage across the second source resistor; a correction unit that corrects timings of switching operations of the first and second semiconductor switching elements based on detection results by the first and second voltage sensors, respectively; A gate drive circuit comprising:

2. The correction unit is a first gate signal correction unit connected to a gate terminal of the first semiconductor switching element and correcting a timing of a switching operation of the first semiconductor switching element based on a detection result by the first voltage sensor; a second gate signal correction unit that is connected to a gate terminal of the second semiconductor switching element and corrects a timing of a switching operation of the second semiconductor switching element based on a detection result by the second voltage sensor; 2. The gate drive circuit of claim 1 , comprising:

3. the drive unit generates a gate drive signal for changing a gate voltage applied to a gate terminal of each of the first and second semiconductor switching elements based on the main gate signal; The correction unit corrects a timing at which the gate drive signal output from the drive unit is output to the gate terminal based on detection results by the first and second voltage sensors.

2. The gate drive circuit of claim 1.

4. The drive unit is a first element driver connected to a gate terminal and a source terminal of the first semiconductor switching element and configured to generate a gate drive signal for varying a gate voltage applied to the gate terminal of the first semiconductor switching element based on the main gate signal; a second element driver connected to a gate terminal and a source terminal of the second semiconductor switching element and configured to generate a gate drive signal for varying a gate voltage applied to the gate terminal of the second semiconductor switching element based on the main gate signal; a connection point between the first element driving unit and the first source resistor and a connection point between the second element driving unit and the second source resistor are connected to each other; The correction unit is The timing of outputting the main gate signal to the first and second element driving sections is corrected based on the detection results of the first and second voltage sensors, respectively.

2. The gate drive circuit of claim 1.

5. a resistance value of the first source resistor is smaller than a resistance value required for driving the driving unit; 2. The gate drive circuit according to claim 1, wherein a resistance value of the second source resistor is smaller than a resistance value required for driving the drive section.

6. a resistance value of the first source resistor is smaller than a resistance value of the gate resistor when a gate resistor is connected in series to a gate terminal of the first semiconductor switching element; The resistance value of the first source resistor is smaller than the resistance value of the gate resistor when the gate resistor is connected in series to the gate terminal of the first semiconductor switching element.

2. The gate drive circuit of claim 1.

7. 2. The gate drive circuit according to claim 1, wherein the correction unit compares a voltage detection value of either one of the first and second voltage sensors with a predetermined threshold voltage for current balance control, and when the voltage detection value is greater than the threshold voltage for current balance control, determines that there is an imbalance in currents flowing through main circuit terminals of a corresponding semiconductor switching element and another semiconductor switching element, and corrects a timing of a switching operation of the corresponding semiconductor switching element.

8. 2. The gate drive circuit according to claim 1, wherein the correction unit compares a voltage detection value of either one of the first and second voltage sensors with a predetermined short-circuit detection threshold voltage, and when the voltage detection value is greater than the short-circuit detection threshold voltage, determines that a short-circuit current has flowed through a corresponding semiconductor switching element, and outputs a short-circuit detection signal.

9. The gate drive circuit according to claim 8 , wherein the short circuit detection threshold voltage is greater than a current balance control threshold voltage.

10. A power conversion device including the gate drive circuit according to any one of claims 1 to 9.

11. inputting a main gate signal for controlling a switching operation of simultaneously turning on / off the first and second semiconductor switching elements connected in parallel; correcting the main gate signal with the stored output timing; changing a gate voltage applied to a gate terminal of each of the first and second semiconductor switching elements based on the corrected main gate signal; detecting a voltage across a source resistor connected in series to a source terminal of the first semiconductor switching element, and detecting a voltage across a source resistor connected in series to a source terminal of the second semiconductor switching element; determining whether a voltage across a source resistor exceeds a threshold; not updating the stored output timing when the threshold value is not exceeded; updating the stored output timing when the voltage across the source resistor exceeds a threshold; A gate driving method comprising:

Images