Multilayer wiring board, and method for designing the same

Abstract

To provide a multilayer wiring board capable of reducing warpage without changing an area and a thickness (volume) of a conductor and an insulation resin, and a designing method for the same.SOLUTION: A multilayer wiring board 100 includes: a core substrate 1 having a first side and a second side opposite the first side; a first build-up layer 51 provided on the first side of the core substrate and including first insulating resin layers 11 and first conductor layers 13 formed on the respective first insulating resin layers; and a second build-up layer 52 provided on the second side of the core substrate and including second insulating resin layers 12 and second conductor layers 14 formed on the respective second insulating resin layers 12. In the case where total volume V1 of the first conductor layers>total volume V2 of the second conductor layers, and an elastic modulus E1 of the first insulating resin layers≒an elastic modulus E2 of the second insulating resin layers, a relationship between thermal expansion coefficients of the first insulating resin layers 11 and the second insulating resin layers 12 is included within a range of ±20% of a value obtained by an expression (1).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board used for mounting electronic components such as semiconductor elements (chips) and the like, and a method for designing the same. [Background technology]

[0002] In recent years, electronic devices have become larger due to the increasing number of chips mounted on them and the need for higher integration in response to demands for higher functionality. In addition, multilayer wiring boards used in these devices are required to have reduced warpage in order to improve chip mounting reliability.

[0003] Patent Document 1 discloses a wiring board A including a core substrate 15, insulating layers 16a-16d laminated in equal numbers on the top and bottom surfaces of core substrate 15, and conductor layers 13 deposited with different occupancy rates on the top and bottom surfaces of core substrate 15 and on the surfaces of insulating layers 16a-16d. In wiring substrate A, the conductor layers 13 on the top and bottom surfaces of core substrate 15 and the conductor layers 13 positioned at the same rank on the top and bottom sides of core substrate 15 are formed so that the conductor thickness with the larger occupancy rate is thinner than the conductor thickness with the smaller occupancy rate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-139632 A Summary of the Invention [Problem to be solved by the invention]

[0005] In order to reduce warping of a multilayer wiring board, it is ideal to make the total conductor volume and the total resin volume common in the first buildup layer provided on the first surface of the core substrate and the second buildup layer provided on the second surface opposite the first surface. However, because the wiring patterns are different between the first buildup layer and the second buildup layer, it is difficult to match the remaining copper ratio (copper area), and from the standpoint of wiring connection reliability and via structure workability, it is also practically difficult to match the thickness of the conductor and resin between the first buildup layer and the second buildup layer.

[0006] The present invention has been made in consideration of these problems, and aims to provide a multilayer wiring board and a design method thereof that can reduce warping without changing the area or thickness (volume) of the conductors or insulating resin. [Means for solving the problem]

[0007] In order to solve the above problems, one representative multilayer wiring board of the present invention is: A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; A multilayer wiring board characterized in that, when V1>V2 and E1≒E2, the relationship between the thermal expansion coefficients of the first insulating resin layer and the second insulating resin layer is within a range of ±20% of the value calculated by the following formula.

number

[0008] According to the present invention, it is possible to provide a multilayer wiring board capable of reducing warpage without changing the area or thickness (volume) of the conductor or insulating resin, and a method for designing the same. Problems, configurations and effects other than those described above will become apparent from the following description of the preferred embodiment of the invention. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a multilayer wiring board according to the first embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a mounting state of the multilayer wiring board according to the first embodiment. [Diagram 3] FIG. 3 is a graph showing Table 1. [Figure 4] FIG. 4 is a graph showing Table 2. [Diagram 5] FIG. 5 is a graph showing Table 3. [Figure 6] FIG. 6 is a graph showing a regression analysis of the simulation results of the first embodiment. [Figure 7] FIG. 7 is a graph showing Table 4. [Figure 8] FIG. 8 is a graph showing Table 5. [Figure 9]FIG. 9 is a graph showing Table 6. [Figure 10] FIG. 10 is a diagram showing an example of a method for manufacturing the core substrate in the first embodiment. [Figure 11] FIG. 11 is a diagram showing a method for manufacturing the multilayer wiring board according to the first embodiment. [Figure 12] FIG. 12 is a diagram showing a method for manufacturing the multilayer wiring board according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the drawings. The dimensional ratios in the drawings may differ from the actual ratios for the convenience of explanation, and the number of layers or part of the configuration may be omitted from the drawings. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0011] In this disclosure, "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Additionally, "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-shaped member or a layer contained in the plate-shaped member is illustrated. Additionally, the "upper surface" and "lower surface" may also be referred to as the "first surface" and the "second surface".

[0012] In addition, "upward" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "upward" and its opposite, "downward," are sometimes referred to as the "Z-axis positive direction" and the "Z-axis negative direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0013] Furthermore, the term "layer" does not necessarily refer to a state in which an object is uniformly formed. It may refer to an object having a pattern with gaps, or a collection of individual objects. For example, the term "conductor layer" may refer to multiple conductors formed on the same surface among surfaces parallel to the main surface of a core substrate.

[0014] <First embodiment> A first embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing a multilayer wiring board according to the first embodiment. Here, a cross-sectional view of the multilayer wiring board is shown. Note that a semiconductor element can be mounted on the multilayer wiring board in the present disclosure by applying flip chip connection via solder bumps.

[0015] (Structure of multilayer wiring board) The multilayer wiring board 100 includes a core substrate 1 having a first surface and a second surface opposite to the first surface, a first buildup layer 51 provided on the first surface of the core substrate 1, and a second buildup layer 52 provided on the second surface of the core substrate 1. The first buildup layer 51 includes a first insulating resin layer 11 and a first conductor layer 13 formed on the first insulating resin layer 11. The first insulating resin layer 11 and the first conductor layer 13 are alternately laminated. The second buildup layer 52 includes a second insulating resin layer 12 and a second conductor layer 14 formed on the second insulating resin layer 12. The second insulating resin layer 12 and the second conductor layer 14 are alternately laminated. In FIG. 1, the number of layers in the first buildup layer 51 is two, and the number of layers in the second buildup layer 52 is two, but the number of layers is not limited to this. In addition, a solder resist layer 17 is formed on the first buildup layer 51 and the second buildup layer 52. The first pad portion 53 and the second pad portion 54 are electrically connected via an electrode that penetrates the core substrate 1.

[0016] (Composition of insulating resin layer) The first insulating resin layer 11 and the second insulating resin layer 12 can be made of a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a mixture thereof. For example, they are made of an epoxy resin, an acrylic resin, a phenolic resin, a melamine resin, a silicone resin, a polyimide resin, an acrylic resin, a polyphenylene ether resin, a maleimide resin, a liquid crystal polymer, a fluororesin, or a combination of two or more of these, and these resins may contain an inorganic filler or an organic filler.

[0017] The first insulating resin layer 11 and the second insulating resin layer 12 are made of a resin having a thermal expansion coefficient that satisfies the following relationship: The area of ​​the multilayer wiring board 100 to be completed when viewed from the Z-axis direction (i.e., the area of ​​the first surface or the second surface) is S (unit: μm 2 ), and the total volume V1 (unit: μm 3 ) and the total volume V2 (unit: μm 3 ) is V1>V2 and the relationship between the elastic modulus E1 (unit: GPa) of the first insulating resin and the elastic modulus E2 (unit: GPa) of the second resin is E1≒E2, then a resin is used in which the difference between the thermal expansion coefficient α2 (unit: ppm / °C) of the second insulating resin layer and the thermal expansion coefficient α1 (unit: ppm / °C) of the first insulating resin layer is within the range of ±20% of the value calculated by the following formula (1). That is, when a resin with a thermal expansion coefficient α1 is used for the first insulating resin layer, the thermal expansion coefficient α2 is calculated from the formula (1a), and a resin with a thermal expansion coefficient α2 is used for the second insulating resin layer.

[0018]

number

[0019]

number

[0020] The derivation of formula (1) will be described later. The first insulating resin layer 11, the second insulating resin layer 12, the first conductor layer 13, and the second conductor layer 14 are selected so as to satisfy the condition of formula (1) to design the multilayer wiring board.

[0021] The elastic modulus reflects the elastic properties of a material and is a value that indicates how difficult the material is to deform. The elastic modulus can be obtained by measuring with a dynamic mechanical analyzer (DMA). The elastic modulus at a desired temperature can be measured by measuring while heating the material.

[0022] The coefficient of thermal expansion (CTE) is a value that indicates the rate of change in length in response to an increase in temperature within a specified temperature range. The coefficient of thermal expansion is obtained by measurement using a thermomechanical analyzer (TMA). In this embodiment, the coefficient of thermal expansion used is a value equal to or lower than the glass transition point.

[0023] (Composition of Conductor Layer) As described below, the first conductor layer 13 has a seed layer 13a and a plating layer 13b formed in this order from the side closest to the core substrate 1. The conductor layer 13 may include various patterns such as wiring, vias, pads, shields, grounds, and dummy patterns, but FIG. 1 shows wiring, vias, and pads. Although not shown, the second conductor layer 14 is similar to the first conductor layer.

[0024] Seed Layer The seed layer 13a is a layer laminated on the first insulating resin layer 11. The material constituting the seed layer 13a is not particularly limited, but when it is formed by electroless plating, for example, metal materials such as Cu, Pd, Al, Sn, Ni, and Cr can be used. When it is formed by sputtering, for example, a material containing at least one of Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu3N4, and a Cu alloy can be used.

[0025] [Plating layer] The plating layer 13b is laminated on the upper surface of the seed layer 13a (the surface opposite to the first insulating resin layer 11). The material constituting the plating layer 13b is mainly a metal, and the type is not particularly limited, but for example, a material containing at least one of Cu and Cu alloys, Ag and Ag alloys, Sn, Pd, Au, Ni, Cr, Pt, and Fe can be used.

[0026] 2 is a diagram showing an example of a mounting state of the multilayer wiring board according to the first embodiment. Here, a cross-sectional view is shown of a semiconductor device in which a semiconductor element 34 (silicon chip) is mounted on a multilayer wiring board 100. In this semiconductor device, the electrode terminals of the semiconductor element 34 are electrically connected to corresponding first pads 53 on the multilayer wiring board 100 via conductive materials such as solder bumps 20, in a so-called flip-chip mounting manner. Furthermore, the gap between the mounted semiconductor element 34 and the multilayer wiring board 100 is filled with underfill resin 35 such as a thermosetting epoxy resin, and mechanical bonding between the semiconductor element 34 and the multilayer wiring board 100 is ensured by heat curing.

[0027] On the other hand, solder bumps 20 used as external connection terminals are formed on the first pad portions 53 exposed from the solder resist layer 17 on the side opposite to the mounting surface side of the semiconductor element 34 after mounting the semiconductor element 34. The multilayer wiring board 100 is mounted on a motherboard or the like via the solder bumps 20.

[0028] <Second embodiment> The second embodiment will be described with respect to the insulating resin layer, which is a difference from the first embodiment. The rest of the configuration is the same as in the first embodiment, so the description will be omitted.

[0029] (insulating resin layer) The first insulating resin layer 11 and the second insulating resin layer 12 are made of a thermosetting resin or a thermoplastic resin. For example, as the thermosetting resin, a resin containing at least one of epoxy resin, phenol resin, melamine resin, silicone resin, and polyimide resin can be used. Also, as the thermoplastic resin, a resin containing at least one of acrylic resin, polyphenylene ether resin, maleimide resin, liquid crystal polymer, and fluororesin can be used. These resins may contain an inorganic filler or an organic filler. Further, the first insulating resin layer 11 and the second insulating resin layer 12 may be formed using a photosensitive resin.

[0030] For the first insulating resin layer 11 and the second insulating resin layer 12, a resin having a coefficient of thermal expansion that satisfies the following relationship is selected as the material. That is, when the multilayer wiring board 100 is viewed from the Z-axis direction, the area of the multilayer wiring board 100 (that is, the area of the first surface or the second surface) is S (unit: μm 2 ), the total volume V1 (unit: μm 3 ) of the first conductor layers 13 of the first build-up layer 51, and the total volume V2 (unit: μm 3 ) of the second conductor layers 14 of the second build-up layer 52 satisfy the relationship V1 < V2, and when the relationship between the elastic modulus E1 (unit: GPa) of the first insulating resin layer and the elastic modulus E2 (unit: GPa) of the second insulating resin layer is E1 ≒ E2, the difference between the coefficient of thermal expansion α1 (unit: ppm / °C) of the first insulating resin layer and the coefficient of thermal expansion α2 (unit: ppm / °C) of the second insulating resin layer is within the range of ±20% of the value obtained by the following formula (2). That is, when a resin with a coefficient of thermal expansion α2 is used for the second insulating resin layer, the coefficient of thermal expansion α1 is calculated from formula (2a), and a resin with a coefficient of thermal expansion α1 is used for the first insulating resin layer.

[0031]

Equation

[0032]

Equation

[0033] The derivation of formula (2) will be described later. The first insulating resin layer 11 and the second insulating resin layer 12, the first conductor layer 13 and the second conductor layer 14 are selected so as to satisfy the condition of formula (2) to design the multilayer wiring board.

[0034] <Third embodiment> The third embodiment will be described with respect to the insulating resin layer, which is a difference from the first embodiment. The rest of the configuration is the same as the first embodiment, so the description will be omitted.

[0035] (insulating resin layer) The first insulating resin layer 11 and the second insulating resin layer 12 are made of a thermosetting resin or a thermoplastic resin. For example, the thermosetting resin may be a resin containing at least one of an epoxy resin, a phenol resin, a melamine resin, a silicone resin, and a polyimide resin. The thermoplastic resin may be a resin containing at least one of an acrylic resin, a polyphenylene ether resin, a maleimide resin, a liquid crystal polymer, and a fluororesin. These resins may contain an inorganic filler or an organic filler. The first insulating resin layer 11 and the second insulating resin layer 12 may be made of a photosensitive resin.

[0036] The first insulating resin layer 11 and the second insulating resin layer 12 are made of a resin having a thermal expansion coefficient that satisfies the following relationship: The area of ​​the multilayer wiring board 100 to be completed when viewed from the Z-axis direction (i.e., the area of ​​the first surface or the second surface) is S (unit: μm 2 ), and the total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3) has a relationship of V1>V2, and the thermal expansion coefficient α1 (unit: ppm / °C) of the first insulating resin layer, the thermal expansion coefficient α2 (unit: ppm / °C) of the second insulating resin layer, and the thermal expansion coefficient α c (Unit: ppm / ℃) The relationship is α1 ≒ α2 > α c In this case, a resin is used in which the difference between the elastic modulus E2 (unit: GPa) of the second insulating resin layer and the elastic modulus E1 (unit: GPa) of the first insulating resin layer is within the range of ±20% of the value calculated by the following formula (3). That is, when a resin with an elastic modulus E1 is used for the first insulating resin layer, the thermal expansion coefficient E2 is calculated from the formula (3a), and a resin with the thermal expansion coefficient E2 is used for the second insulating resin layer.

[0037]

number

[0038]

number

[0039] The derivation of formula (3) will be described later. The first insulating resin layer 11 and the second insulating resin layer 12, the first conductor layer 13 and the second conductor layer 14 are selected so as to satisfy the condition of formula (3) to design the multilayer wiring board.

[0040] <Fourth embodiment> The fourth embodiment will be described with respect to the insulating resin layer, which is a difference from the first embodiment. The rest of the configuration is the same as the first embodiment, so the description will be omitted.

[0041] (insulating resin layer) The first insulating resin layer 11 and the second insulating resin layer 12 are composed of a thermosetting resin or a thermoplastic resin. For example, as the thermosetting resin, a resin containing at least one of epoxy resin, phenolic resin, melamine resin, silicone resin, and polyimide resin can be used. Also, as the thermoplastic resin, a resin containing at least one of acrylic resin, polyphenylene ether resin, maleimide resin, liquid crystal polymer, and fluororesin can be used. These resins may contain an inorganic filler or an organic filler. Further, the first insulating resin layer 11 and the second insulating resin layer 12 may be formed using a photosensitive resin.

[0042] For the first insulating resin layer 11 and the second insulating resin layer 12, a resin having a coefficient of thermal expansion that satisfies the following relationship is selected as the material. That is, when the multilayer wiring board 100 is viewed from the Z-axis direction, the area of the multilayer wiring board 100 (i.e., the area of the first surface or the second surface) is denoted as S (unit: μm 2 ), the total volume V1 (unit: μm 3 ) of the first conductor layers 13 of the first build-up layer 51, and the total volume V2 (unit: μm 3 ) of the second conductor layers 14 of the second build-up layer 52 satisfy the relationship V1 < V2. When the coefficient of thermal expansion α1 (unit: ppm / °C) of the first insulating resin layer, the coefficient of thermal expansion α2 (unit: ppm / °C) of the second insulating resin layer, and the coefficient of thermal expansion α c (unit: ppm / °C) of the first conductor layer 13 and the second conductor layer 14 satisfy the relationship α1 ≈ α2 > α c , a resin is used such that the difference between the elastic modulus E1 (unit: GPa) of the first insulating resin layer and the elastic modulus E2 (unit: GPa) of the second insulating resin layer is within the range of ±20% of the value obtained by the following formula (4). That is, when a resin with an elastic modulus E1 is used for the first insulating resin layer, the coefficient of thermal expansion E2 is calculated from formula (4a), and a resin with a coefficient of thermal expansion E2 is used for the second insulating resin layer.

[0043]

Equation

[0044]

number

[0045] The derivation of formula (4) will be described later. The first insulating resin layer 11 and the second insulating resin layer 12, the first conductor layer 13 and the second conductor layer 14 are selected so as to satisfy the condition of formula (4) to design the multilayer wiring board.

[0046] [Example] <Derivation of formula (4) from formula (1)> Next, the derivation of formulas (1) to (4) will be described with reference to Examples 1 to 6. Examples 1 to 3 are simulations for calculating the thermal expansion coefficients of the first insulating resin layer 11 and the second insulating resin layer 12 when the elastic modulus of the first insulating resin layer 11 and the elastic modulus of the second insulating resin layer 12 are approximately equal. Examples 4 to 6 are simulations for calculating the elastic modulus of the first insulating resin layer 11 and the second insulating resin layer 12 when the thermal expansion coefficient of the first insulating resin layer and the thermal expansion coefficient of the second insulating resin layer are approximately equal and are larger than the thermal expansion coefficients of the first conductor layer 13 and the second conductor layer 14. A warpage simulation was performed using plate theory for the multilayer wiring board 100 shown in FIG. 1. Specifically, the multilayer wiring board 100 was rectangular, measuring 65 mm by 65 mm, and had a structure in which seven insulating resin layers and seven conductor layers were laminated on the front and back of the core board 1, and finally a solder resist was laminated. Solder, which has little effect on warpage, was excluded. The thickness of the core resin 1a was 1200 μm, the thickness of each insulating resin layer was 33 μm, and the thickness of the solder resist was 15 μm. Copper was assumed for the conductor layer, and in order to use plate theory, the thickness of each conductor layer was calculated as 15 μm and the copper remaining rate was converted into volume, and the area of ​​the board was determined as S (unit: μm 2 ) to obtain the thickness when the remaining copper ratio is 100%. The total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3), the thermal expansion coefficient and elastic modulus of the insulating resin that results in a warpage of 0 μm when the temperature at which the multilayer wiring board becomes stress-free, 180° C. (the cure temperature of the insulating resin layer) is lowered to room temperature of 23° C., when the value of (V2-V1) / S is 10 μm (approximately 8.3% in terms of residual copper difference rate), 20 μm (approximately 16.7% in terms of residual copper difference rate), and 30 μm (approximately 25.0% in terms of residual copper difference rate), were calculated by simulation. The thermal expansion coefficient used here is equal to or lower than the glass transition temperature. The method disclosed herein can be applied to any of thermosetting resin, thermoplastic resin, and photosensitive resin.

[0047] <Example 1> In the first embodiment, the total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3 ), the value of (V2-V1) / S was 10μm (approximately 8.3% calculated as the residual copper difference rate), the thermal expansion coefficient α1 of the first insulating resin was 15, 25, and 35ppm / ℃, and the elastic modulus E1 of the first insulating resin layer and the elastic modulus E2 of the second insulating resin layer were 6, 10, and 14GPa. The relationship between the thermal expansion coefficients of the first and second insulating resin layers (difference α2-α1) at which the amount of warpage of the multilayer wiring board was 0 was calculated by simulation. The results are shown in Table 1. FIG. 3 is a graph showing Table 1. [Table 1]

[0048] <Example 2> In Example 2, the total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3), the value of (V2-V1) / S was set to 20μm (approximately 16.7% calculated as the residual copper difference rate), the thermal expansion coefficient α1 of the first insulating resin layer was set to 15, 25, and 35ppm / ℃, and the elastic modulus E1 of the first insulating resin layer and the elastic modulus E2 of the second insulating resin layer were set to 6, 10, and 14GPa. The relationship between the thermal expansion coefficients of the first and second insulating resin layers (difference α2-α1) at which the amount of warpage of the multilayer wiring board was 0 was calculated by simulation. The results are shown in Table 2. FIG. 4 is a graph showing Table 2. [Table 2]

[0049] <Example 3> In the third embodiment, the total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3 ), the value of (V2-V1) / S was 30μm (approximately 25.0% calculated as the residual copper difference rate), the thermal expansion coefficient α1 of the first insulating resin was 15, 25, and 35ppm / ℃, and the elastic modulus E1 of the first insulating resin and the elastic modulus E2 of the second insulating resin were 6, 10, and 14GPa. The relationship between the thermal expansion coefficients of the first and second insulating resin layers (difference α2-α1) at which the amount of warpage of the multilayer wiring board was 0 was calculated by simulation. The results are shown in Table 3. FIG. 5 is a graph showing Table 3. [Table 3]

[0050] From the simulation results of Examples 1 to 3 and FIGS. 3 to 5, the relational expression of the coefficient of thermal expansion difference at which the warp becomes 0 was obtained. First, as shown in FIGS. 3 to 5, it is assumed that the relational expression between (α2 - α1) and α1 is linearly approximated, and the approximate expression of the result of Example 1 is calculated. Here, regarding the slope and intercept at each coefficient of thermal expansion α1 of the approximate expression, assuming that the elastic modulus E1 ≒ E2 of the insulating resin layer, a graph with E1 (or E2) as a variable is made. FIG. 6 is a diagram for regression analysis of the simulation results of Example 1. As shown in FIG. 6, the slope was approximately linearly approximated, and the intercept was approximately a quadratic function. Substituting the elastic modulus E1 of the insulating resin layer for x in the approximate function shown in FIG. 6, the approximate expression of the result of Example 1 was calculated. Finally, a correction value was calculated so as to match the simulation results of Example 2 or 3 when the value of (V2 - V1) / S was multiplied by the quadratic function showing the intercept. As a result, when expressing the relationship between the coefficient of thermal expansion α1 of the first insulating resin layer and the coefficient of thermal expansion α2 of the second insulating resin layer as an equation, it can be represented by the above formula (1).

[0051] Also, when V1 < V2, since the direction of the warp is reversed, when expressing the relationship between the coefficient of thermal expansion α1 of the first insulating resin and the coefficient of thermal expansion α2 of the second insulating resin as an equation, it can be represented by the above formula (2).

[0052] <Example 4> Referring to Examples 4 to 6, assuming that the coefficient of thermal expansion α1 of the first insulating resin layer 11, the coefficient of thermal expansion α2 of the second insulating resin layer 12, the coefficient of thermal expansion of the first conductor layer 13, and the coefficient of thermal expansion of the second conductor layer 14 are equal (here, the coefficients of thermal expansion of the first conductor layer 13 and the second conductor layer 14 are α c Let it be), and α1 ≒ α2 > α c The case will be described. In Example 4, the total volume V1 (unit: μm 3 ) of the first conductor layer 13 of the first build-up layer 51 and the total volume V2 (unit: μm 3), the value of (V2-V1) / S was 10μm (approximately 8.3% calculated as the residual copper difference rate), the thermal expansion coefficient α1 of the first insulating resin and the second thermal expansion coefficient were 25, 30, and 35ppm / ℃, and the elastic modulus E1 of the first insulating resin was 6, 10, and 14GPa. The relationship between the elastic modulus of the first and second insulating resin layers (difference E2-E1) at which the amount of warpage of the multilayer wiring board was 0 was calculated by simulation. The results are shown in Table 4. FIG. 7 is a graph showing Table 4. [Table 4]

[0053] <Example 5> In Example 5, the total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3 ), the value of (V2-V1) / S was 20μm (approximately 16.7% calculated as the residual copper difference rate), the thermal expansion coefficient α1 of the first insulating resin and the second thermal expansion coefficient were 25, 30, and 35ppm / ℃, and the elastic modulus E1 of the first insulating resin was 6, 10, and 14GPa. The relationship between the elastic modulus of the first and second insulating resin layers (difference E2-E1) at which the amount of warpage of the multilayer wiring board was 0 was calculated by simulation. The results are shown in Table 5. FIG. 8 is a graph showing Table 5. [Table 5]

[0054] <Example 6> In Example 6, the total volume V1 (unit: μm 3 ) and the sum V2 (unit: μm 3When (V2 - V1) / S is 20 μm (about 25.0% in terms of the residual copper ratio), and the coefficient of thermal expansion α1 of the first insulating resin and the second coefficient of thermal expansion are 25, 30, 35 ppm / °C, and the elastic modulus E1 of the first insulating resin is 6, 10, 14 GPa, the relationship (difference E2 - E1) between the elastic moduli of the first and second insulating resin layers at which the warp amount of the multilayer wiring board becomes 0 was calculated from the simulation. The results are shown in Table 6. Further, Fig. 9 is a diagram showing Table 6 in a graph. [Table 6]

[0055] From the simulation results of these Examples 4 to 6 and Figs. 7 to 9, the relational expression of the elastic modulus difference at which the warp becomes 0 was obtained. As shown in Figs. 7 to 9, it was assumed that the relational expression is approximated by a quadratic function, the approximation formula of the result of Example 1 was calculated, and each coefficient was calculated in the same procedure as in the case of formula (1). As a result, when the relationship between the elastic modulus E1 of the first insulating resin and the elastic modulus E2 of the second insulating resin is expressed as a formula, it can be represented by the above-mentioned formula (3).

[0056] Also, when V1 < V2, since the direction of the warp is reversed, when the relationship between the elastic modulus E1 of the first insulating resin and the elastic modulus E2 of the second insulating resin is expressed as a formula, it can be represented by the above-mentioned formula (4).

[0057] The created formulas (1) to (4) are calculated from the approximation of the simulation results. When comparing this formula with the simulation results, in formula (3), when the coefficient of thermal expansion α1 of the first insulating resin and the coefficient of thermal expansion α2 of the second are 35 ppm / °C and the elastic modulus E1 of the first insulating resin is 14 GPa, E2 - E1 is about 0.381 GPa, and in the simulation, E2 - E1 is about 0.325 GPa, and the result of formula (3) is about 17% larger and shows the largest deviation. From this result, the range of the value in the present invention is set to ±20% of the calculation formula.

[0058] <Method for Designing and Manufacturing Multilayer Wiring Board> (Fabrication of Core Substrate) A method for manufacturing the multilayer wiring board 100 according to the first embodiment and a method for designing the same will be described. First, a process for producing the core substrate 1 will be described with reference to Fig. 10. Fig. 10 is a diagram showing an example of a method for manufacturing the core substrate in the first embodiment.

[0059] First, through holes 3 are formed in the core resin 1a by using a drill or the like, penetrating from the front surface to the back surface (see FIG. 10(a)). Copper foil 2 is attached to both sides of the core resin 1a.

[0060] Next, electroless plating is performed on the surface of the copper foil 2 and the wall surface of the through-hole 3, and then electrolytic plating is performed to form the conductor layer 23 (see FIG. 10(b)). In the electroless plating, for example, metal materials such as Cu, Pd, Al, Sn, Ni, and Cr can be used. When forming by a sputtering method, for example, a material containing at least one of Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu3N4, and Cu alloy can be used. In addition, in electrolytic plating, the metal is mainly used, and the type is not particularly limited, but for example, materials containing at least one of Cu and Cu alloys, Ag and Ag alloys, Sn, Pd, Au, Ni, Cr, Pt, and Fe can be used.

[0061] Next, the through-holes 3 are filled with a filling resin 4. Any filling resin 4 that protrudes from the through-holes 3 is removed by buffing or the like (see FIG. 10(c)). Note that if the through-holes 3 are filled with plating in the step shown in FIG. 10(b), the step of FIG. 10(c) is omitted.

[0062] Next, a conductor layer 33 is formed on the entire surface of the core resin 1a by electroless plating and electrolytic plating (see FIG. 10(d)). The conductor layer 33 is formed by a method similar to that for forming the conductor layer 23. In the step shown in FIG. 10(b), if the through-hole 3 is filled with plating or if it is not necessary to provide the conductor layer 33 on the hole filling resin 4, the step of FIG. 10(d) is omitted.

[0063] Next, a resist is applied or laminated, and a resist pattern 6 is formed by photolithography on the portions of the conductor layers 23 and 33 that are to remain as conductors (see FIG. 10(e)).

[0064] Next, the portions of the conductor layers 23 and 33 where the resist pattern 6 is not formed are removed by etching to form a plurality of conductors (see FIG. 10(f)).

[0065] Next, the resist pattern 6 is removed, and the core substrate 1 having the pad portions 43 and 44 is formed (see FIG. 10(g)). The pad portions 43 and 44 are electrically connected to conductors included in the build-up layers laminated on the core substrate 1.

[0066] Although the method for producing the core substrate 1 has been described above, this is only one example and the present invention is not limited to this production method.

[0067] (Making multi-layer wiring boards) Next, a process of laminating a plurality of first insulating resin layers 11 and first conductor layers 13 alternately on the fabricated core substrate 1 to fabricate a multilayer wiring substrate 100 will be described. A second insulating resin layer 12 and a second conductor layer 14 are also laminated on the other surface of the core substrate 1. FIGS. 11 and 12 are diagrams showing a method for manufacturing a multilayer wiring substrate according to the first embodiment. In the explanatory diagrams of the manufacturing method that follow, only the first buildup layer side is shown, and the core resin 1a of the core substrate 1 and the second buildup layer are omitted, but the second buildup layer is fabricated in parallel with the first buildup layer.

[0068] First, a first insulating resin layer 11 is formed on a core substrate 1. Then, in order to expose a pad portion 43 for electrical connection in the lower layer, a via opening 8 is formed by laser processing such as UV or CO2 in the case of a thermosetting resin, or by photolithography in the case of a photosensitive resin (see FIG. 11(a)).

[0069] Next, a seed layer 13a is formed on the upper surface of the first insulating resin layer 11, the wall surface of the via opening 8, and the pad portion 43 corresponding to the bottom surface of the via opening 8 by electroless plating or sputtering (see FIG. 11(b)).

[0070] Next, a resist is applied or laminated onto the seed layer 13a, and then exposed and developed to form a resist pattern 16 corresponding to the pattern of the plating layer 13b (see FIG. 11(c)).

[0071] Next, a plating layer 13b is formed by electrolytic plating on the seed layer 13a on which the resist pattern 16 has been formed (see FIG. 11(d)). Next, the resist pattern 16 is removed (see FIG. 11(e)).

[0072] Next, the seed layer 13a exposed by removing the resist pattern 16 (ie, the seed layer 13a not covered with the plating layer 13b) is removed by etching (see FIG. 11(f)).

[0073] Next, a first insulating resin layer is laminated so as to cover the first conductor layer 13 and the underlying first insulating resin layer 11 (see FIG. 11(g)).

[0074] The above steps are repeated until a circuit having a desired number of layers is formed. In Fig. 12(g), a first buildup layer 51 includes three first insulating resin layers 11.

[0075] After forming the desired number of layers of circuits, a solder resist layer 17 is formed on the outermost layer by coating or lamination (see FIG. 12(h)).

[0076] Solder resist openings 18 are formed on the first pad portions 53 by photolithography or the like (see FIG. 12(i)). The solder resist layer 17 is, for example, a photosensitive epoxy resin, which may contain an inorganic filler. When a non-photosensitive thermosetting resin is used, the solder resist openings 18 are formed by laser processing using a UV laser or a CO2 laser, photolithography, or the like.

[0077] Next, a surface treatment layer 19 is formed on the first pad portion 53 in the solder resist opening 18 (see FIG. 12(l)).

[0078] Next, solder bumps 20 are formed in the solder resist openings 18 on the mounting side of the semiconductor element 34 (silicon chip). Through these steps, a multilayer wiring board 100 can be formed (see FIG. 12(m)). When solder paste is used, the solder bumps 20 are formed by screen printing, and when solder balls are used, the solder balls are mounted by ball transfer after screen printing of flux, and are then melted by reflow.

[0079] <Actions and Effects> Typically, when the total volume of the first conductor layers in a multilayer wiring board is greater than the total volume of the second conductor layers, and an insulating resin layer is formed using an insulating resin film of the same thickness on the first and second surfaces, warping occurs in the board due to the influence of the thermal expansion coefficient and elastic modulus of the conductor, which depend on the difference between the total volume of the first conductor layers and the total volume of the second conductor layers. In contrast, in the present disclosure, by making a difference in the thermal expansion coefficient or elastic modulus between the first insulating resin layer and the second insulating resin layer, it is possible to cancel out the effects of the thermal expansion coefficient and elastic modulus of the conductor and suppress warping of the multilayer wiring board.

[0080] Furthermore, in the present disclosure, a simulation is performed using plate theory to determine the relationship between the difference between the sum of the volumes of the first conductor layers and the sum of the volumes of the second conductor layers, the difference in the thermal expansion coefficient or elastic modulus of the first insulating resin and the second insulating resin, and warping. Based on the results obtained, a formula is derived for calculating the difference in the thermal expansion coefficient or elastic modulus of the first insulating resin and the second insulating resin required to suppress warping. In this way, by simplifying the simulation results, which include multiple parameters, into a calculation formula in which the parameters are limited to the thermal expansion coefficient and elastic modulus of the insulating resin layer, it is possible to improve convenience when designing multilayer wiring boards. [Explanation of symbols]

[0081] 1 Core Board 1a Core Resin 2 Copper foil 3 Through Hole 4. Hole filling resin 6, 16 Resist pattern 8 Via opening 11 First insulating resin layer 12 Second insulating resin layer 13 First conductor layer 13a Seed layer 13b Plating layer 14 Second conductor layer 16 Resist Pattern 17 Solder resist layer 18 Solder resist opening 19 Surface treatment layer 20 Solder Bumps 22, 33 Conductor layer 34 Semiconductor elements 35 Underfill resin 43, 44 Pad section 53 First pad section 54 Second pad section 51 First build-up layer 52 Second build-up layer 100 Multilayer wiring board

Claims

1. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; V １ >V ２ , E １ ≒E ２ In the case of the above, the relationship between the thermal expansion coefficients of the second insulating resin layer and the first insulating resin layer is within a range of ±20% of the value calculated by the following formula (1). [0010] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

2. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer being formed by alternately laminating a second insulating resin layer and a second conductor layer on the second insulating resin layer; V １ <V ２ , E １ ≒E ２ In the case of the above, the relationship between the thermal expansion coefficients of the first insulating resin layer and the second insulating resin layer is within a range of ±20% of the value calculated by the following formula (2). [0025] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

3. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; V １ >V ２ , α １ ≒α ２ >α ｃ In the case of the above, the relationship between the elastic modulus of the second insulating resin layer and the elastic modulus of the first insulating resin layer is within a range of ±20% of the value calculated by the following formula (3). [0030] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) α ｃ : Thermal expansion coefficient of the first conductor layer and the second conductor layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

4. A multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; V １ <V ２ , α １ ≒α ２ >α ｃ In the case of the above, the relationship between the elastic modulus of the first insulating resin layer and the elastic modulus of the second insulating resin layer is within a range of ±20% of the value calculated by the following formula (4). [0045] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) α ｃ : Thermal expansion coefficient of the first conductor layer and the second conductor layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

5. A method for designing a multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, comprising the steps of: The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; V １ >V ２ , E １ ≒E ２ In the case of the above, the relationship between the thermal expansion coefficients of the second insulating resin layer and the first insulating resin layer is within a range of ±20% of the value calculated by the following formula (1). [0050] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

6. A method for designing a multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, comprising the steps of: The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer being formed by alternately laminating a second insulating resin layer and a second conductor layer on the second insulating resin layer; V １ <V ２ , E １ ≒E ２ In the case of the above, the relationship between the thermal expansion coefficients of the first insulating resin layer and the second insulating resin layer is within a range of ±20% of the value calculated by the following formula (2). [006] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

7. A method for designing a multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, comprising the steps of: The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; V １ >V ２ , α １ ≒α ２ >α ｃ In the above case, the relationship between the elastic modulus of the second insulating resin layer and the elastic modulus of the first insulating resin layer is within a range of ±20% of the value calculated by the following equation (3). [0070] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) α ｃ : Thermal expansion coefficient of the first conductor layer and the second conductor layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

8. A method for designing a multilayer wiring board on which a semiconductor element can be mounted by flip chip connection via solder bumps, comprising the steps of: The multilayer wiring board has a multilayer structure in which insulating layers using an organic insulating material and wiring layers using a conductive material are alternately laminated, a core substrate having a first surface and a second surface opposite to the first surface; a first buildup layer provided on the first surface of the core substrate, the first buildup layer including a first insulating resin layer and a first conductor layer formed on the first insulating resin layer; a second buildup layer provided on the second surface of the core substrate, the second buildup layer including a second insulating resin layer and a second conductor layer formed on the second insulating resin layer; V １ <V ２ , α １ ≒α ２ >α ｃ In the above case, the relationship between the elastic modulus of the first insulating resin layer and the elastic modulus of the second insulating resin layer is within a range of ±20% of the value calculated by the following equation (4). [0080] where S is the area of ​​the multilayer wiring board (unit: μm ２ ) V １ : Total volume of the first conductor layer (unit: μm ３ ) V ２ : Total volume of the second conductor layer (unit: μm ３ ) α １ : Thermal expansion coefficient of the first insulating resin layer (unit: ppm / °C) α ２ : Thermal expansion coefficient of the second insulating resin layer (unit: ppm / °C) α ｃ : Thermal expansion coefficient of the first conductor layer and the second conductor layer (unit: ppm / °C) E １ : Elastic modulus of the first insulating resin layer (unit: GPa) E ２ : Elastic modulus of the second insulating resin layer (unit: GPa)

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