Semiconductor device

Abstract

To provide a transistor with high ON current and a semiconductor device with high productivity.SOLUTION: A semiconductor device comprises: a first insulator; a second insulator on the first insulator; a third insulator on the second insulator and a first conductor; a fourth insulator on the third insulator and the first conductor; a fifth insulator on the fourth insulator; a first oxide on the fifth insulator; a second oxide on the first oxide; a third oxide on the second oxide and a fourth oxide; a second conductor on the third oxide; a third conductor on the fourth oxide; a sixth insulator on the second conductor; a seventh insulator on the third conductor; an eighth insulator on the fifth to seventh insulators; a fifth oxide on the second oxide and arranged between the second conductor and the third conductor; a ninth insulator on the fifth oxide; and a fourth conductor on the ninth insulator. Hydrogen concentration of the first conductor is lower than hydrogen concentration of the fourth conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention relates to a semiconductor device including a first insulator, a second insulator on the first insulator, a third insulator on the second insulator, and a first conductor, a fourth insulator on the third insulator and on the first conductor, a fifth insulator on the fourth insulator, a first oxide on the fifth insulator, a second oxide on the first oxide, a third oxide on the second oxide, and a fourth oxide, a second conductor on the third oxide, a third conductor on the fourth oxide, a sixth insulator on the second conductor, a seventh insulator on the third conductor, an eighth insulator on the fifth to seventh insulators, and a fifth oxide on the second oxide and disposed between the second conductor and the third conductor. the first conductor has a region overlapping with the second oxide, the fourth conductor has a region overlapping with the second oxide, the fifth oxide has regions in contact with the first oxide to fourth oxide, the second conductor, the third conductor, and the fifth to eighth insulators, respectively, and the hydrogen concentration of the first conductor is lower than the hydrogen concentration of the fourth conductor, the hydrogen concentration of the first insulator is lower than the hydrogen concentration of the ninth insulator, the hydrogen concentration of the second insulator is lower than the hydrogen concentration of the ninth insulator, and the hydrogen concentration of the third insulator is lower than the hydrogen concentration of the ninth insulator.

[0011] In addition, in the above, it is preferable that the first oxide to the fifth oxide each contain indium, an element M (M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc.

[0012] In the above, it is preferable that the first conductor contains tantalum and nitrogen.

[0013] In one embodiment of the present invention, a first insulator, a second insulator, a third insulator, and a first conductive film are formed in the opening and on the third insulator, and the first conductive film is polished by a CMP method until it reaches the third insulator to form a first conductor in the opening. A fourth insulator, a first oxide film, a second oxide film, a third oxide film, a second conductive film, a first insulating film, and a third conductive film are formed in this order on the third insulator and on the first conductor, and the first oxide film, the second oxide film, the third oxide film, the second conductive film, the first insulating film, and the third conductive film are processed into an island shape to form a first oxide, a second oxide, a first oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer. The second conductive layer is removed, and a fourth insulating film is formed. a fifth insulator is formed on the first oxide layer, a first oxide, a second oxide, the first oxide layer, the first conductive layer, and the first insulating layer, a sixth insulator is formed on the fifth insulator, an opening reaching the second oxide is formed in the first oxide layer, the first conductive layer, the first insulating layer, the fifth insulator, and the sixth insulator, and in the formation of the opening, a third oxide and a fourth oxide are formed from the first oxide layer, a second conductor and a third conductor are formed from the first conductive layer, a seventh insulator and an eighth insulator are formed from the first insulating layer, a fifth oxide, a ninth insulator on the fifth oxide, and a third conductor on the ninth insulator are formed in the opening, and the first conductive film and the second conductive film are formed by sputtering.

[0014] In the above, the first to third insulators are preferably formed in succession under reduced pressure using an apparatus having a plurality of treatment chambers.

[0015] In the above, the first to third oxide films are preferably formed successively under reduced pressure using an apparatus having a plurality of processing chambers.

[0016] In the above, the second conductive film, the first insulating film, and the third conductive film are preferably formed successively under reduced pressure using an apparatus having a plurality of treatment chambers.

[0017] In the above, the first to third insulators, the first to third oxide films, the first to third conductive films, the first insulating film, and the fifth oxide are preferably formed by a sputtering method. Effect of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0020] [Figure 1] Fig. 1A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 2B to 2D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 3] Fig. 3A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 3B to 3D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 4] 4A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 5] Fig. 5A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 5B to 5D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 6] Fig. 6A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 6B to 6D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 9] Figure 9A is a diagram for explaining the classification of IGZO crystal structures, Figure 9B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film, and Figure 9C is a diagram for explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Figure 10] 10A to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A to 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22]22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 25] 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 25B to 25D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 26B to 26D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 27B to 27D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A and 28B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 30] FIG. 30 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 31] FIG. 31 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 32] 32A and 32B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 33 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 34 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 35] FIG. 35 is a top view illustrating an apparatus for manufacturing a semiconductor device of one embodiment of the present invention. [Diagram 36] FIG. 36 is a schematic diagram illustrating an apparatus for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 37 is a schematic diagram illustrating an apparatus for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 38] 38A and 38B are block diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 39] 39A to 39H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Diagram 40] FIG. 40 is a diagram showing various storage devices by hierarchy. [Diagram 41] 41A and 41B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Diagram 42] 42A and 42B are diagrams illustrating an example of an electronic component according to one embodiment of the present invention. [Diagram 43] 43A to 43E are schematic diagrams of a memory device according to one embodiment of the present invention. [Diagram 44] 44A to 44H are diagrams showing electronic devices according to one embodiment of the present invention. [Diagram 45] FIG. 45 shows the results of SIMS analysis of an embodiment according to one aspect of the present invention. [Figure 46] FIG. 46 shows the results of SIMS analysis of an embodiment according to one aspect of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0022] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0023] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0024] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0025] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0026] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0027] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0028] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0029] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0031] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0032] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0033] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0034] Note that impurities in a semiconductor refer to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O :oxygen vacancy) may be formed.

[0035] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. A nitride oxide is a material whose composition contains more nitrogen than oxygen. Thus, for example, a silicon oxynitride is a material whose composition contains more oxygen than nitrogen. A silicon nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0036] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0037] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0038] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0039] In this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0040] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0041] <Example of semiconductor device configuration> An example of the configuration of a semiconductor device including a transistor 200 will be described with reference to FIGS. 1A to 1D. FIG. 1A is a top view of a semiconductor device including a transistor 200. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0042] The semiconductor device of one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282. The insulators 212, 214, 280, 282, and 283 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 that functions as a plug. Moreover, a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as wiring is provided on the insulator 283 and the conductor 240. Furthermore, an insulator 286 is provided on the conductor 246 and the insulator 283.

[0043] The insulator 241a is provided in contact with the inner walls of the openings of the insulators 280, 282, and 283, the first conductor of the conductor 240a is provided in contact with the side surface of the insulator 241a, and the second conductor of the conductor 240a is provided further inside. The insulator 241b is provided in contact with the inner walls of the openings of the insulators 280, 282, and 283, the first conductor of the conductor 240b is provided in contact with the side surface of the insulator 241b, and the second conductor of the conductor 240b is provided further inside. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 283 in the region overlapping with the conductor 246 can be made approximately the same. Note that, in the transistor 200, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by giving ordinal numbers in the order of formation.

[0044] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxide 243a and oxide 243b) and an oxide 230c on the oxide 230b, a conductor 242a on the oxide 243a, an insulator 271a on the conductor 242a, The oxide 230c has a conductor 242b on the oxide 243b, an insulator 271b on the conductor 242b, an oxide 230d on the oxide 230c, an insulator 250 on the oxide 230d, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with a part of the oxide 230c, and an insulator 272 in contact with a part of the insulator 224, a side of the oxide 230a, a side of the oxide 230b, a side of the oxide 243a, a side of the conductor 242a, a side of the insulator 271a, an upper surface of the insulator 271a, a side of the insulator 271b, and a side of the conductor 242b. The oxide 230c also has a side of the oxide 243a, a side of the oxide 243b, a side of the conductor 242a, a side of the conductor 242b, and a side of the insulator 272. 1B and 1C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surface of the insulator 250, the upper surface of the oxide 230d, and the upper surface of the oxide 230c. Also, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280.

[0045] In the following, the insulator 271a and the insulator 271b may be collectively referred to as the insulator 271. Furthermore, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0046] An opening reaching the oxide 230b is provided in the insulator 280. The oxide 230d, the oxide 230c, the insulator 250, and the conductor 260 are disposed in the opening. In addition, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are provided between the conductor 242a and the oxide 243a and the conductor 242b and the oxide 243b in the channel length direction of the transistor 200. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. In addition, in the region overlapping with the oxide 230b, the oxide 230c has a region in contact with the oxide 230b, a region overlapping with the side surface of the conductor 260 via the oxide 230d and the insulator 250, and a region overlapping with the bottom surface of the conductor 260 via the oxide 230d and the insulator 250.

[0047] The oxide 230 preferably includes an oxide 230a arranged on the insulator 224, an oxide 230b arranged on the oxide 230a, an oxide 230c arranged on the oxide 230b and at least a part of which is in contact with the oxide 230b, and an oxide 230d arranged on the oxide 230c. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Also, by having the oxide 230d on the oxide 230c, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230d to the oxide 230c.

[0048] Note that, in the transistor 200, the oxide 230 has a structure in which four layers of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d are stacked, but the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, or a stacked structure of five or more layers. Alternatively, each of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may have a stacked structure.

[0049] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator. The conductor 242a functions as one of a source or a drain, and the conductor 242b functions as the other of the source or the drain. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0050] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d) including a channel formation region.

[0051] In addition, the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap in this way, the off-state current of a transistor can be reduced.

[0052] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0053] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b or oxide 230c is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a or oxide 230d.

[0054] In this manner, by arranging oxide 230a below oxide 230b or oxide 230c, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b or oxide 230c can be suppressed.

[0055] Moreover, by disposing the oxide 230d on the oxide 230b or the oxide 230c, it is possible to suppress the diffusion of impurities from a structure formed above the oxide 230d to the oxide 230b or the oxide 230c. Moreover, by disposing the oxide 230d on the oxide 230b or the oxide 230c, it is possible to suppress the upward diffusion of oxygen from the oxide 230b or the oxide 230c.

[0056] In addition, since the oxides 230a to 230d have a common element other than oxygen (as a main component), the defect state density at each interface between the oxides 230a, 230b, 230c, and 230d can be reduced. In this case, the main path of carriers is the oxide 230b, the oxide 230c, or the vicinity thereof, for example, the interface between the oxide 230b and the oxide 230c. Since the defect state density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0057] It is preferable that the oxide 230b and the oxide 230c each have crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b and the oxide 230c. Also, the oxide 230d may have crystallinity.

[0058] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0059] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. In CAAC-OS, it is difficult to confirm clear grain boundaries even near the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of dense arrangement of oxygen atoms in the ab-plane direction and the change in the bond distance between atoms due to the substitution of metal elements.

[0060] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor or a decrease in field-effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0061] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be expressed as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be expressed as an (In, M) layer.

[0062] As described above, the CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (oxygen vacancies Vo, etc.). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0063] On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility caused by grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0064] In addition, in a cross-sectional view in the channel length direction of the transistor, it is preferable to provide a groove in the oxide 230b and fill the groove with the oxide 230c. In this case, the oxide 230c is arranged so as to cover the inner wall (side surface and bottom surface) of the groove. In addition, it is preferable that the film thickness of the oxide 230c is approximately the same as the depth of the groove.

[0065] With this configuration, even if a damaged region is formed on the surface of the oxide 230b at the bottom of the opening when forming the opening for embedding the conductor 260, the damaged region can be removed, thereby suppressing defects in the electrical characteristics of the transistor 200 caused by the damaged region.

[0066] In FIG. 1 and other figures, the side of the opening in which the conductor 260 and the like are embedded is approximately perpendicular to the surface on which the oxide 230b is formed, including the groove of the oxide 230b, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped with a gentle curve. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 230b is formed.

[0067] 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0068] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the curved surface in this shape, the coverage of the groove portion by the insulator 250 and the conductor 260 formed in a later process can be improved. In addition, the length of the region not having the curved surface can be prevented from decreasing, and the on-current and mobility of the transistor 200 can be suppressed from decreasing. Therefore, a semiconductor device having good electrical characteristics can be provided.

[0069] The oxide 230 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of element M to the metal element that is the main component is preferably greater than the atomic ratio of element M to the metal element that is the main component in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a.

[0070] In order to make the oxide 230c the main path of carriers, the atomic ratio of indium to the main metal element in the oxide 230c is preferably larger than the atomic ratio of indium to the main metal element in the oxide 230b. By using a metal oxide with a high indium content in the channel formation region, the on-current of the transistor can be increased. Therefore, by making the atomic ratio of indium to the main metal element in the oxide 230c larger than the atomic ratio of indium to the main metal element in the oxide 230b, the oxide 230c can be made the main path of carriers.

[0071] In addition, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a and 230b. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinity of the oxides 230a and 230b. In this case, the main carrier path is the oxide 230c.

[0072] Specifically, the oxide 230c may be a metal oxide, indium oxide, or the like having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto.

[0073] An example of a parameter for evaluating the reliability of a transistor is the shift voltage (Vsh) measured in a +GBT (Gate Bias Temperature) stress test of the transistor. The shift voltage (Vsh) is defined as the Vg at which the tangent to the maximum slope of the drain current (Id)-gate voltage (Vg) curve of the transistor intersects with the line of Id=1pA. The amount of change in Vsh is expressed as ΔVsh.

[0074] In a +GBT stress test of a transistor, ΔVsh may shift in the negative direction over time. Also, ΔVsh may not fluctuate in one direction (e.g., the negative direction) but may exhibit behavior in which it fluctuates in both the negative and positive directions. Note that in this specification and the like, the above behavior may be referred to as the jagged behavior of ΔVsh in a +GBT stress test.

[0075] By using a metal oxide that does not contain element M as a main component or a metal oxide with a low ratio of element M for oxide 230c, for example, it is possible to reduce ΔVsh, suppress the jagged behavior of ΔVsh, and improve the reliability of the transistor.

[0076] Moreover, the oxide 230b and the oxide 230c are preferably crystalline oxides such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies) and have a dense structure with high crystallinity. This makes it possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0077] In addition, it is preferable to use a CAAC-OS as the oxide 230c, and it is preferable that the c-axis of the crystal of the oxide 230c is oriented in a direction approximately perpendicular to the surface on which the oxide 230c is formed or the upper surface of the oxide 230c. The CAAC-OS has a property of easily moving oxygen in a direction perpendicular to the c-axis. Therefore, oxygen in the oxide 230c can be efficiently supplied to the oxide 230b.

[0078] Moreover, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be In-M-Zn oxide, In-Zn oxide, or indium oxide, and the oxide 230d may be In-M-Zn oxide, M-Zn oxide, or an oxide of element M. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0079] In addition, the conduction band minimum of the oxide 230d is preferably closer to the vacuum level than the conduction band minimum of the oxide 230c. In other words, the electron affinity of the oxide 230d is preferably smaller than that of the oxide 230c. In this case, the oxide 230d is preferably made of a metal oxide that can be used for the oxide 230a or the oxide 230b. In this case, the main carrier path is the oxide 230c.

[0080] Specifically, a metal oxide or indium oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto may be used as oxide 230c, and a metal oxide or oxide of element M having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, M:Zn=2:1 [atomic ratio] or a composition close thereto, or M:Zn=2:5 [atomic ratio] or a composition close thereto may be used as oxide 230d.

[0081] Moreover, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen can be efficiently supplied to the oxide 230b via the oxide 230c.

[0082] In addition, by making the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230d smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230c, it is possible to suppress the diffusion of In to the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250, the transistor characteristics will be poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.

[0083] Here, the conduction band minimum changes gradually at the junctions of the oxides 230a, 230b, 230c, and 230d. In other words, the conduction band minimum at the junctions of the oxides 230a, 230b, 230c, and 230d can be said to change continuously or to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 230a and 230b, the interface between the oxides 230b and 230c, and the interface between the oxides 230c and 230d.

[0084] Specifically, the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as a main component, thereby forming a mixed layer with a low defect level density. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a, the oxide 230c, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0085] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. The oxide 230c may be a metal oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto, or an indium oxide. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use gallium as the element M. In addition, as the oxide 230d, a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, a composition of M:Zn=2:1 [atomic ratio] or a composition close thereto, or a composition of M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of the element M may be used.

[0086] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0087] By configuring the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d as described above, it is possible to reduce the defect state density at the interface between the oxide 230a and the oxide 230b, the interface between the oxide 230b and the oxide 230c, and the interface between the oxide 230c and the oxide 230d. As a result, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0088] Note that the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Furthermore, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, a configuration in which the oxide 230c is not provided between the transistor 200 and the transistor 200 adjacent to the transistor 200 may be used.

[0089] In a semiconductor device in which a plurality of transistors 200 are arranged in the channel width direction, the above-described structure allows the oxide 230c to be provided independently in each of the transistors 200. This makes it possible to prevent a parasitic transistor from being generated between a transistor 200 and a transistor 200 adjacent to the transistor 200, thereby preventing the above-described leakage path from being generated. This makes it possible to provide a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated.

[0090] For example, when the distance between the side end of the oxide 230c of the transistor 200 and the side end of the oxide 230c of the transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is expressed as L1, L1 is set to be larger than 0 nm. Also, when the distance between the side end of the oxide 230a of the transistor 200 and the side end of the oxide 230a of the transistor 200 adjacent to the transistor 200, which face each other in the channel width direction of the transistor 200, is expressed as L2, the value of the ratio of L1 to L2 (L1 / L2) is preferably larger than 0 and smaller than 1, more preferably 0.1 or more and 0.9 or less, and even more preferably 0.2 or more and 0.8 or less. Note that L2 may be the distance between the side end of the oxide 230b of the transistor 200 and the side end of the oxide 230b of the transistor 200 adjacent to the transistor 200, which face each other.

[0091] By reducing the ratio of L1 to L2 (L1 / L2) described above, even if a misalignment occurs in a region where oxide 230c is not located between transistor 200 and a transistor 200 adjacent to said transistor 200, oxide 230c of transistor 200 can be separated from oxide 230c of a transistor 200 adjacent to said transistor 200.

[0092] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), even if the distance between transistor 200 and the adjacent transistor 200 is narrowed, the minimum processing dimension width can be secured, thereby enabling further miniaturization or high integration of the semiconductor device.

[0093] Note that the conductor 260 and the insulator 250 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region provided contiguous with the conductor 260 of another transistor 200 adjacent to the transistor 200. The insulator 250 of one transistor 200 has a region provided contiguous with the insulator 250 of another transistor 200 adjacent to the transistor 200.

[0094] With the above structure, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and another transistor 200 adjacent to the transistor 200. Note that the oxide 230c and the oxide 230d of the transistor 200 may be separated from the oxide 230c and the oxide 230d of the transistor 200 adjacent to the transistor 200.

[0095] The insulators 212, 214, 271, 272, 282, 283, and 286 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, the insulators 212, 214, 271, 272, 282, 283, and 286 are preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (through which the above impurities are unlikely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is unlikely to permeate).

[0096] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property means a function of suppressing the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

[0097] For example, it is preferable to use silicon nitride or the like as the insulators 212, 283, and 286, and aluminum oxide or the like as the insulators 214, 271, 272, and 282. This can suppress impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulators 224 and the like to the substrate side through the insulators 212 and 214. It is also possible to suppress the diffusion of impurities such as water and hydrogen from the insulators 280, the conductor 246, and the like to the oxide 230. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 272, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0098] It may also be preferable to reduce the resistivity of the insulators 212, 283, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 283, and 286 to approximately 1×10 13 By setting the resistivity at Ωcm, the insulator 212, the insulator 283, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 283, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0099] The insulator 216 and the insulator 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as the insulator 216 and the insulator 280 as appropriate.

[0100] Note that the insulators 212, 214, and 216 are preferably formed by a sputtering method. The insulators 212, 214, and 216 formed by a sputtering method are preferable because they have a low hydrogen concentration in the film. The insulators 212, 214, and 216 are preferably formed in succession without exposure to the air environment. By forming the insulators 212, 214, and 216 without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the insulators 212, 214, and 216, and it is preferable to keep the interface between the insulators 212 and 214 and the vicinity of the interface, and the interface between the insulators 214 and 216 and the vicinity of the interface clean. An apparatus capable of forming the films in succession will be described later.

[0101] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0102] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0103] As shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of the region of the oxide 230a and the oxide 230b that does not overlap with the conductor 242a and the conductor 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to the region outside the end of the oxide 230a and the oxide 230b in the channel width direction. That is, outside the side surface of the oxide 230a and the oxide 230b in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0104] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0105] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0106] As shown in Figures 1B and 1C, the conductor 205 is configured as a single layer, but the present invention is not limited to this. For example, the conductor 205 may be configured as a laminated structure of two or more layers. When the structure has a laminated structure, the layers may be distinguished by giving ordinal numbers in the order of formation. Figures 2B and 2C show an example of a configuration in which the conductor 205 is configured as three layers (conductor 205a, conductor 205b, and conductor 205c).

[0107] When the conductor 205 has three layers, it is preferable that the conductors 205a and 205c are made of a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) or that a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms is used.

[0108] By using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, the conductor 205a and the conductor 205c may be a single layer or a multilayer of the above conductive material. For example, the conductor 205a and the conductor 205c may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide, and titanium or titanium nitride.

[0109] Moreover, it is preferable that the conductor 205b is made of a conductive material containing tantalum, tungsten, or aluminum as a main component.

[0110] When the conductor 205 is a single layer, it is preferable that the conductor 205 be a conductor similar to the conductors 205a and 205c.

[0111] The hydrogen concentration in the conductor 205 is preferably reduced. By using the conductor 205 with a reduced hydrogen concentration, the amount of hydrogen diffusing to the oxide 230 through the insulator 222 and the insulator 224 can be reduced. The hydrogen concentration in the conductor 205 is preferably 1×10 20 (atoms / cm 3 The hydrogen concentration in the conductor 205 can be measured by secondary ion mass spectrometry (SIMS).

[0112] Therefore, it is preferable to form the conductor 205 (conductor 205a, conductor 205b, and conductor 205c) by using a sputtering method. Forming the conductor 205 by a sputtering method is preferable because it is possible to reduce the hydrogen concentration in the conductor 205 more than by forming the conductor 205 by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The CVD method and the ALD method will be described later.

[0113] In addition, a first ion sputtering method and a second sputtering method can be used in a method for manufacturing a conductor or the like of a semiconductor device of one embodiment of the present invention. The details of each method will be described later. In particular, the conductor 205 can be formed by various methods including the above method. In particular, it is preferable to form the conductor 205 by using the second sputtering method.

[0114] Insulator 222 and insulator 224 function as gate insulators.

[0115] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0116] The insulator 222 may be an insulator containing one or both of aluminum and hafnium. As the insulator, an oxide, a nitride, an oxynitride, or a nitride oxide containing one or both of aluminum and hafnium may be used. For example, it is preferable to use aluminum oxide, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxynitride containing aluminum and hafnium, or a nitride oxide containing aluminum and hafnium. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses release of oxygen from the oxide 230 to the substrate side and diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress reaction of the conductor 205 with the insulator 224 or oxygen contained in the oxide 230.

[0117] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0118] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0119] It is preferable that the insulator 224 in contact with the oxide 230 release oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0120] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more than 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0121] In addition, the oxide 230 may be brought into contact with an insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, defects in which hydrogen has entered an oxygen vacancy (V O A reaction occurs in which the bond of V H is broken. O H→V O A reaction of "H + H" occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form HO, which may be removed from the oxide 230 or an insulator in the vicinity of the oxide 230. Some of the hydrogen may also diffuse or be captured (also called gettering) by the conductor 242.

[0122] The microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230 by applying RF to the substrate side. The microwave treatment may be performed under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0123] In addition, in the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 600° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230 to reduce oxygen deficiencies (VO ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0124] In addition, by subjecting the oxide 230 to an oxygen addition treatment, the oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O In addition, the reaction of the hydrogen remaining in the oxide 230 with the oxygen supplied can be promoted, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0125] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0126] An oxide 243 (oxide 243a and oxide 243b) may be provided on oxide 230b.

[0127] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0128] A metal oxide having element M may be used as the oxide 243. In particular, the element M may be one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. The oxide 243 preferably has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. A metal oxide such as In-M-Zn oxide may be used as the oxide 243. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. The thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. Moreover, it is preferable that the oxide 243 has crystallinity. When the oxide 243 has crystallinity, it is possible to suitably suppress the release of oxygen from the oxide 230. For example, when the oxide 243 has a crystal structure such as a hexagonal crystal structure, it may be possible to suppress the release of oxygen from the oxide 230.

[0129] It is preferable that the oxide film to be oxide 230a, the oxide film to be oxide 230b, and the oxide film to be oxide 243 are successively formed without exposure to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film to be oxide 230a, the oxide film to be oxide 230b, and the oxide film to be oxide 243, and it is possible to keep the interface and the vicinity of the interface between the oxide film to be oxide 230a and the oxide film to be oxide 230b, and the interface and the vicinity of the interface between the oxide film to be oxide 230b and the oxide film to be oxide 243, clean. An apparatus capable of successive film formation will be described later.

[0130] The conductor 242a is provided over the oxide 243a, and the conductor 242b is provided over the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0131] As the conductor 242 (conductor 242a and conductor 242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0132] The conductor 242 is preferably a conductor formed by a first ionization sputtering method. In this embodiment, tantalum nitride is formed as the conductor 242 by the first ionization sputtering method. The conductor 242 formed by the first ionization sputtering method can be a dense conductor with high film density and has excellent oxidation resistance. Therefore, the transistor 200 having excellent electrical characteristics and high reliability can be manufactured. The first ionization sputtering method will be described later.

[0133] If the oxide 243 is not provided, contact between the conductor 242 and the oxide 230b or the oxide 230c may cause oxygen in the oxide 230b or the oxide 230c to diffuse into the conductor 242, resulting in the oxidation of the conductor 242. The oxidation of the conductor 242 is likely to result in a decrease in the conductivity of the conductor 242. The diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230b or the oxide 230c.

[0134] In addition, oxygen in the oxide 230b or the oxide 230c may diffuse into the conductor 242a and the conductor 242b, forming layers between the conductor 242a and the oxide 230b, between the conductor 242b and the oxide 230b, or between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductor 242a or the conductor 242b, the layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and can be regarded as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0135] Note that hydrogen contained in the oxide 230b, the oxide 230c, etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, etc. may easily diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may combine with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, etc. may be absorbed by the conductor 242a or the conductor 242b.

[0136] Furthermore, there may be a curved surface between the side surface of the conductor 242 and the top surface of the conductor 242. That is, the end of the side surface and the end of the top surface may be curved. The curved surface has a radius of curvature of, for example, 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductor 242. The lack of corners at the end improves the coverage of the film in the subsequent film formation process.

[0137] The insulator 272 is provided to cover the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271, and preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 272 preferably has a function of suppressing oxygen diffusion. For example, the insulator 272 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 272, an insulator that can be used for the insulator 222 may be used.

[0138] In particular, the insulator 272 is preferably formed by forming an aluminum oxide or hafnium oxide film in an atmosphere containing oxygen by bias sputtering. Alternatively, an aluminum oxynitride or hafnium oxynitride film may be formed in an atmosphere containing oxygen and nitrogen. Bias sputtering is a method of sputtering while applying RF power to the substrate. By applying RF power to the substrate, the potential of the substrate becomes negative relative to the plasma potential (called bias potential), and positive ions in the plasma are accelerated to this bias potential and injected into the substrate. The bias potential can be controlled by the magnitude of the RF power applied to the substrate.

[0139] Therefore, by forming an aluminum oxide or hafnium oxide film in an atmosphere containing oxygen by bias sputtering, oxygen can be implanted into the insulator 224. In addition, the amount of oxygen implanted into the insulator 224 can be controlled by adjusting the RF power applied to the substrate, so that the amount of oxygen implanted into the insulator 224 can be optimized.

[0140] The insulator 271 is provided in contact with the upper surface of the conductor 242 and preferably functions as at least a barrier insulating film against oxygen, similar to the insulator 272. Therefore, the insulator 271 also preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 271, an insulator that can be used for the insulator 222 may be formed. As the insulator 271, for example, an insulator containing silicon nitride may be used.

[0141] By providing the insulator 271 and the insulator 272 as described above, the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242 can be separated from the insulator 280. Therefore, it is possible to suppress the direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242. This makes it possible to prevent the carrier density of the source region and the drain region of the oxide 230 from being reduced due to the supply of excess oxygen to the source region and the drain region. In addition, it is possible to suppress the conductor 242 from being excessively oxidized, which increases the resistivity and reduces the on-current.

[0142] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0143] The insulator 250 is preferably formed using an insulator that releases oxygen when heated, similar to the insulator 224. By providing the insulator that releases oxygen when heated as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, and oxygen vacancies in the channel formation region of the oxide 230b can be reduced. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0144] In addition, although the insulator 250 is illustrated as a single layer in FIG. 1B and FIG. 1C, it may be a laminated structure of two or more layers. When the insulator 250 is a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has a function of suppressing the diffusion of oxygen. By adopting such a configuration, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be provided using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be provided using a material similar to that of the insulator 222.

[0145] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0146] Specifically, the upper layer of the insulator 250 may be a metal oxide, a metal oxynitride, a metal oxynitride, or a metal oxide that can be used as the oxide 230, containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an oxide containing aluminum and hafnium (hafnium aluminate), an oxynitride containing aluminum and hafnium, or a oxynitride containing aluminum and hafnium.

[0147] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0148] It is preferable that the metal oxide has a function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 260a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0149] By including the metal oxide, the on-current of the transistor 200 can be improved without weakening the effect of the electric field from the conductor 260. Furthermore, by maintaining a distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, it is possible to suppress leakage current between the conductor 260 and the oxide 230. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, it is possible to easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0150] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B and FIG. 1C, the upper surface of the conductor 260 is substantially aligned with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Note that, although the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIG. 1B and FIG. 1C, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers.

[0151] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0152] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0153] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0154] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0155] As shown in FIG. 1C, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b when the bottom surface of the insulator 222 is used as a reference. The conductor 260, which functions as a gate electrode, is configured to cover the side and upper surface of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. When the bottom surface of the insulator 222 is used as a reference, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0156] The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 242, and the insulator 271. In addition, the upper surface of the insulator 280 may be planarized.

[0157] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0158] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, a material similar to that of the insulator 216. The insulator 280 may have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed by a chemical vapor deposition (CVD) method. Silicon nitride may also be stacked on top of that.

[0159] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen transmission. The insulator 282 and the insulator 283 may be, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0160] The conductor 240a and the conductor 240b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 240a and the conductor 240b may have a laminated structure. Although the conductor 240a and the conductor 240b are circular in top view in FIG. 1A, this is not limiting. For example, the conductor 240a and the conductor 240b may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0161] In addition, when the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 283, 282, 280, 272, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. In addition, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductors 240a and 240b.

[0162] The conductor 240a and the conductor 240b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 240a and the conductor 240b may have a laminated structure. Although the conductor 240a and the conductor 240b are circular in top view in FIG. 1A, this is not limiting. For example, the conductor 240a and the conductor 240b may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0163] When the conductor 240 has a laminated structure, the lower layer is preferably made of a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. By using the conductive material for the lower layer of the conductor 240, impurities such as water or hydrogen diffusing from the insulator 280 or the like can be further reduced from being mixed into the oxide 230 through the conductor 240. In addition, it is possible to prevent the oxygen added to the insulator 280 from being absorbed by the conductive material of the upper layer of the conductor 240. The upper layer is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum.

[0164] Moreover, it is preferable to use a conductor formed by a second ionization sputtering method as the conductor under the conductor 240. In this embodiment, a tantalum nitride or titanium nitride film is formed by a second ionization sputtering method as the conductor under the conductor 240. The second ionization sputtering method will be described later.

[0165] As the insulator 241a and the insulator 241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. The insulator 241a and the insulator 241b are provided in contact with the insulator 271, and therefore impurities such as water and hydrogen contained in the insulator 280 can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, it can prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0166] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surface of conductor 240a and the upper surface of conductor 240b to function as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0167] The insulator 286 is provided on the conductor 246 and on the insulator 283. As a result, the upper surface and the side surface of the conductor 246 contact the insulator 286, and the lower surface of the conductor 246 contacts the insulator 283. In other words, the conductor 246 can be configured to be surrounded by the insulators 283 and 286. With such a configuration, it is possible to suppress the permeation of oxygen from the outside and prevent the conductor 246 from being oxidized. This is also preferable because it is possible to prevent impurities such as water and hydrogen from conductor 246 from diffusing to the outside.

[0168] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0169] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0170] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0171] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0172] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, nitride oxides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, nitride oxides having silicon and hafnium, and nitrides having silicon and hafnium.

[0173] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0174] In addition, the transistor using metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0175] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0176] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0177] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0178] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0179] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0180] <<Metal oxides>> It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 230. Hereinafter, metal oxides that can be applied to the oxide 230 according to the present invention will be described.

[0181] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0182] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 9A. Fig. 9A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0183] As shown in FIG. 9A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0184] The structure in the bold frame shown in Fig. 9A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0185] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Figure 9B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 9B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 9B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 9B is 500 nm.

[0186] As shown in Figure 9B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 9B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0187] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 9C. Figure 9C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 9C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0188] As shown in FIG. 9C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0189] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 9A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0190] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0191] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0192] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0193] In addition, in an In-M-Zn oxide (wherein element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0194] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0195] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0196] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0197] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0198] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0199] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0200] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0201] <Example of oxide semiconductor configuration> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0202] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0203] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0204] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0205] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0206] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0207] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0208] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, so that the CAC-OS can be given a switching function (on / off function). In other words, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, it is possible to realize a high on-current (Ion), a high field effect mobility (μ), and good switching operation.

[0209] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0210] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0211] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0212] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0213] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0214] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0215] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0216] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0217] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0218] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0219] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0220] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0221] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0222] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0223] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0224] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0225] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0226] <Modification 1 of the semiconductor device> An example of the structure of a semiconductor device including the transistor 200 will be described below with reference to FIGS. 3A to 3D and 4A to 4D.

[0227] Fig. 3A is a top view of a semiconductor device having a transistor 200. Fig. 3B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 3A. Fig. 3C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 3A. Fig. 3D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 3A. Some elements are omitted from the top view of Fig. 3A for clarity.

[0228] FIG. 4A is a top view of a semiconductor device having a transistor 200. FIG. 4B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 4A. FIG. 4C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 4A. FIG. 4D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in FIG. 4A. Some elements are omitted from the top view of FIG. 4A for clarity.

[0229] 3A to 3D and 4A to 4D, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device> and <Modification 1 of Semiconductor Device> are denoted by the same reference numerals. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> and <Modification 1 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0230] The semiconductor device shown in Figures 3A to 3D is a modified example of the semiconductor device shown in Figures 1A to 1D. The semiconductor device shown in Figures 3A to 3D differs from the semiconductor device shown in Figures 1A to 1D in that it does not have the oxide 230c and the oxide 230d.

[0231] The structure without the oxide 230c and the oxide 230d can suppress the generation of a parasitic transistor between the transistor 200 and the transistor 200 adjacent to the transistor 200, and can suppress the generation of a leakage path along the conductor 260. Therefore, a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated can be provided.

[0232] 4A to 4D differ from the semiconductor device shown in Fig. 3A to 3D in that the conductor 205 has a three-layer structure, that is, the bottom and side surfaces of the conductor 205b contact the conductor 205a, and the top surface of the conductor 205b contacts the conductor 205c.

[0233] <Modification 2 of Semiconductor Device> An example of a semiconductor device including the transistor 200 will be described below with reference to FIGS. 5A to 5D and 6A to 6D.

[0234] Fig. 5A shows a top view of the semiconductor device. Fig. 5B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 5A. Fig. 5C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 5A. Fig. 5D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 5A. In the top view of Fig. 5A, some elements are omitted for clarity.

[0235] Fig. 6A shows a top view of the semiconductor device. Fig. 6B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 6A. Fig. 6C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 6A. Fig. 6D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 6A. In the top view of Fig. 6A, some elements are omitted for clarity.

[0236] 5A to 5D and 6A to 6D, structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device> and <Modification Example of Semiconductor Device 2> are denoted with the same reference numerals. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> and <Modification Example of Semiconductor Device 2> can be used as the materials constituting the semiconductor device.

[0237] The semiconductor device shown in Figures 5A to 5D is a modified example of the semiconductor device shown in Figures 1A to 1D. The semiconductor device shown in Figures 5A to 5D is different from the semiconductor device shown in Figures 1A to 1D in the shape of the insulator 283. Also, the semiconductor device is different in that it has an insulator 274.

[0238] In the semiconductor device shown in FIGS. 5A to 5D, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 280, and the insulator 282 are patterned. The insulator 283 is structured to cover the insulators 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 280, and the insulator 282. That is, the insulator 283 contacts the upper surface and side surface of the insulator 282 and the upper surface of the insulator 212. As a result, the insulators 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 280, and the insulator 282, including the oxide 230, are isolated from the outside by the insulator 283 and the insulator 212. In other words, the transistor 200 is disposed within a region sealed by the insulator 283 and the insulator 212 .

[0239] For example, it is preferable to form the insulators 214 and 282 using a material that has a function of capturing and fixing hydrogen, and to form the insulators 212 and 283 using a material that has a function of suppressing the diffusion of hydrogen and oxygen. Typically, the insulators 214 and 282 can be made of aluminum oxide. Typically, the insulators 212 and 283 can be made of silicon nitride.

[0240] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from entering the sealed region.

[0241] 5A to 5D show a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0242] The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 274 can be provided using, for example, a material similar to that of the insulator 280.

[0243] 6A to 6D differ from the semiconductor device shown in Fig. 5A to 5D in that the conductor 205 has a three-layer structure, that is, the bottom and side surfaces of the conductor 205b contact the conductor 205a, and the top surface of the conductor 205b contacts the conductor 205c.

[0244] <Modification 3 of the semiconductor device> Below, an example of the structure of a semiconductor device including the transistor 200 will be described with reference to FIGS. 7A to 7D and FIGS. 8A to 8D.

[0245] Fig. 7A is a top view of a semiconductor device having a transistor 200. Fig. 7B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 7A. Fig. 7C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 7A. Fig. 7D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 7A. Some elements are omitted from the top view of Fig. 7A for clarity.

[0246] FIG. 8A is a top view of a semiconductor device having a transistor 200. FIG. 8B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 8A. FIG. 8C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 8A. FIG. 8D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in FIG. 8A. Some elements are omitted from the top view of FIG. 8A for clarity.

[0247] 7A to 7D and 8A to 8D, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device> and <Modification 3 of Semiconductor Device> are denoted by the same reference numerals. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> and <Modification 3 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0248] The semiconductor device shown in Figures 7A to 7D is a modified example of the semiconductor device shown in Figures 6A to 6D. The semiconductor device shown in Figures 7A to 7D differs from the semiconductor device shown in Figures 6A to 6D in that it does not have oxide 230c and oxide 230d.

[0249] The structure without the oxide 230c and the oxide 230d can suppress the generation of a parasitic transistor between the transistor 200 and the transistor 200 adjacent to the transistor 200, and can suppress the generation of a leakage path along the conductor 260. Therefore, a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated can be provided.

[0250] 8A to 8D differ from the semiconductor device shown in Figures 7A to 7D in that the conductor 205 has a three-layer structure, that is, the bottom and side surfaces of conductor 205b contact conductor 205a, and the top surface of conductor 205b contacts conductor 205c.

[0251] <First ionization sputtering method> Hereinafter, the film formation by the first ionization sputtering method will be described with reference to Fig. 36. Fig. 36 is an example of a film formation apparatus capable of forming a film by the first ionization sputtering method, and is a cross-sectional view of a film formation apparatus 4100. Note that in the schematic cross-sectional view of the film formation apparatus 4100 shown in Fig. 36, some elements are omitted for clarity.

[0252] As shown in FIG. 36, the film forming apparatus 4100 has a film forming chamber 4102, and in the film forming chamber 4102, a backing plate 4108, a target 4110 attached to the backing plate 4108, and a substrate holder 4112 arranged to face the target 4110. The substrate holder 4112 may have a function of heating the substrate 4200. Outside the film forming chamber 4102, there are a magnet unit 4106, a DC power supply 4115 electrically connected to the backing plate, an RF power supply 4116 electrically connected to the substrate holder 4112, a coil unit 4114 arranged to surround the outer wall of the film forming chamber 4102, and an RF power supply 4117 electrically connected to the coil unit 4114. Although not shown, the film forming apparatus 4100 has an exhaust system having a vacuum pump that exhausts the inside of the film forming chamber 4102, and a gas supply system that introduces gas into the film forming chamber 4102. Also, a configuration may be adopted in which an adhesion prevention plate is arranged inside the film formation chamber 4102. In an apparatus capable of forming a film by the first ionization sputtering method, it is preferable to form a film using a film formation chamber having a high degree of vacuum. In order to reduce the hydrogen concentration in the film, it is preferable that the vacuum pump for evacuating the inside of the film formation chamber 4102 is a cryopump or a turbo molecular pump with an H2O trap.

[0253] First, the deposition chamber 4102 is kept in a low-pressure gas atmosphere, and DC power is applied from the DC power source 4115 to the target 4110 via the backing plate 4108 to generate plasma. In addition, around the target 4110, electrons in the plasma are confined by the magnetic field of the magnet unit 4106 arranged near the target 4110, increasing the probability of collision between gas molecules and electrons, resulting in high-density plasma. This high-density plasma allows metal atoms to be efficiently sputtered from the target 4110.

[0254] The sputtered metal atoms can be ionized by applying RF power from an RF power source 4117 via a coil unit 4114 to the sputtered metal atoms. RF power is also applied from an RF power source 4116 to a substrate 4200 via a substrate holder 4112. The ionized metal atoms are accelerated by a bias voltage generated on the substrate 4200 by application of the RF power. That is, energy can be imparted to the ionized metal atoms. By appropriately adjusting the energy to be imparted, the metal atoms can be diffused on the surface of the substrate 4200, and a film can be formed without gaps, so that a dense film with high film density can be formed.

[0255] In this embodiment, tantalum nitride is deposited as the conductor 242 by the first ionization sputtering method described above. The conductor 242 deposited by the first ionization sputtering method can be a dense conductor with high film density and excellent oxidation resistance. Therefore, the transistor 200 having excellent electrical characteristics and high reliability can be manufactured.

[0256] <Second ionization sputtering method> The formation of the conductor 205 will be described below with respect to the second ionization sputtering method. FIG. 37 is a cross-sectional view of a film formation apparatus 4101, which is an example of a film formation apparatus capable of forming a film by the second ionization sputtering method. Note that some elements are omitted from the cross-sectional view of the film formation apparatus 4101 shown in FIG. 37 for clarity. Also, FIGS. 10A to 10D are cross-sectional views for explaining an example of a method for forming the conductor 205 having a single-layer structure by using the second ionization sputtering method. Also, FIGS. 11A to 11D and FIGS. 12A to 12C are cross-sectional views for explaining an example of a method for forming the conductor 205 having a three-layer structure by using the second ionization sputtering method.

[0257] As shown in FIG. 37, the film forming apparatus 4101 has a film forming chamber 4102, and in the film forming chamber 4102, a backing plate 4108, a target 4110 attached to the backing plate 4108, and a substrate holder 4112 arranged to face the target 4110. The substrate holder 4112 may have a function of heating the substrate 4200. Outside the film forming chamber 4102, there are a magnet unit 4106, a DC power supply 4115 electrically connected to the backing plate, an RF power supply 4118 electrically connected to the backing plate, and an RF power supply 4116 electrically connected to the substrate holder 4112. Although not shown, the film forming apparatus 4101 has an exhaust system having a vacuum pump that exhausts the inside of the film forming chamber 4102, and a gas supply system that introduces gas into the film forming chamber 4102. Also, a configuration in which an adhesion prevention plate is arranged inside the film forming chamber 4102 may be adopted. The apparatus capable of forming a film by the second ionization sputtering method preferably uses a film formation chamber having a high degree of vacuum, as in the apparatus capable of forming a film by the first ionization sputtering method. In order to reduce the hydrogen concentration in the film, the vacuum pump for evacuating the inside of the film formation chamber 4102 is preferably a cryopump or a turbomolecular pump with an H2O trap.

[0258] First, as a first film formation step, the film formation chamber 4102 is kept in a low pressure gas atmosphere, and a first RF power is applied from an RF power source 4118 to a target 4110 via a backing plate 4108. By applying the first RF power, plasma is generated. The frequency of the first RF power is preferably 13.56 MHz or more, more preferably 40 MHz or more. The higher the frequency of the first RF power, the higher the density of the plasma that can be generated. In addition, around the target 4110, electrons in the plasma are confined by the magnetic field of the magnet unit 4106 arranged near the target 4110, and the collision probability between the gas molecules and the electrons increases, so that a more dense plasma can be obtained. In addition, by applying the first DC power from a DC power source 4115 to the target 4110 via a backing plate 4108, ionized gas atoms or many ionized gas molecules can be collided with the target 4110, so that the deposition rate of the metal atoms sputtered from the target 4110 onto the substrate 4200 can be increased.

[0259] Moreover, the sputtered metal atoms can be ionized by applying a second RF power from the RF power source 4116 to the substrate 4200 via the substrate holder 4112. The frequency of the second RF power is preferably 400 kHz or more and 30 MHz or less, typically 13.56 MHz. The ionized metal atoms are accelerated by a bias voltage generated on the substrate 4200 by the application of the second RF power, reach the substrate 4200, and form a metal film.

[0260] FIG. 10A is a cross-sectional view after the formation of an opening in insulator 216 that reaches insulator 214. FIG.

[0261] Fig. 10B is a cross-sectional view showing the state of metal film 205A being formed in the middle of the first film-forming step. As shown in Fig. 10B, metal film 205A is formed mainly on the bottom of the opening and on insulator 216, and the thickness of metal film 205A formed on the side of the opening is thinner than the thickness of metal film 205A formed on the bottom of the opening and on the upper surface of insulator 216. This is because ionized metal atoms are accelerated in a direction approximately perpendicular to the bottom of the opening.

[0262] 10C is a cross-sectional view showing a state in which the metal film 205A is formed to a depth equal to or greater than the depth of the opening in the first film-forming step. In this manner, by using the first film-forming step in the second ionization sputtering method, the metal film 205A can be embedded in the opening.

[0263] Next, the metal film 205A on the insulator 216 is polished by the CMP method until it reaches the insulator 216, thereby forming the conductor 205 embedded in the opening (see FIG. 10D). The height of the upper surface of the conductor 205 and the height of the upper surface of the insulator 216 are approximately equal. Although not shown, the CMP method may polish a part of the upper surface of the insulator 216, resulting in a thinner film thickness of the insulator 216. In this way, the conductor 205 can be formed without using lithography to process the metal film 205A, thereby improving the processing accuracy and simplifying the process.

[0264] An example of a method for forming the conductor 205 having a three-layer structure will be described below. Fig. 11A is a cross-sectional view of the insulator 216 after an opening reaching the insulator 214 is formed.

[0265] 11B is a cross-sectional view after the first deposition step in the second ionization sputtering method is performed using a deposition chamber capable of depositing the metal film 205a1. As shown in FIG. 11B, the metal film 205a1 is mainly formed on the bottom of the opening and the upper surface of the insulator 216, and the thickness of the metal film 205a1 formed on the side of the opening is thinner than the thickness of the metal film 205a1 formed on the bottom of the opening and the upper surface of the insulator 216.

[0266] Next, in the second film formation step, the RF power applied to the substrate 4200 from the RF power source 4116 via the substrate holder 4112 is changed to a third RF power greater than the second RF power, thereby causing the ionized gas atoms or ionized gas molecules to collide with the substrate side. That is, the ionized gas atoms or ionized gas molecules collide with the metal film 205a1 at the bottom of the opening formed in the first film formation step and the metal film 205a1 on the insulator 216 shown in FIG. 11B, and the metal film is sputtered and redistributed to the side of the opening. FIG. 11C shows the formed state of the metal film 205a1 after the second film formation step. The third RF power is 2 to 5 times the second RF power.

[0267] Next, as a third film formation step, the RF power applied from the RF power source 4118 to the target 4110 via the backing plate 4108 is set to a fourth RF power smaller than the first RF power. Also, the RF power applied from the RF power source 4116 to the substrate 4200 via the substrate holder 4112 is set to a fifth RF power smaller than the third RF power, thereby reducing the amount of ionized metal atoms and the amount of ionized gas atoms or ionized gas molecules heading toward the substrate 4200. On the other hand, the metal atoms sputtered from the target 4110 can be increased. Since the metal atoms are electrically neutral, they reach the substrate 4200 at random angles with almost no effect of the bias voltage generated on the substrate 4200, so that a metal film can be formed uniformly on the side of the opening. The fourth RF power is 0.5 times or more and less than 1 times the first RF power. The fifth RF power is 0.25 times or more and less than 1 times the third RF power.

[0268] As described above, by appropriately adjusting the processing time of each of the first to third film formation steps according to the size and depth of the opening, it is possible to form metal film 205a1 with excellent coverage (see FIG. 11D).

[0269] Next, a first film formation step is performed using a film formation chamber capable of forming the metal film 205b1, and the metal film 205b1 is formed so that the height of the upper surface of the metal film 205b1 in the opening is approximately 3 / 4 of the depth of the opening (see FIG. 12A).

[0270] Next, a first film formation step is performed using a film formation chamber capable of forming the metal film 205c1, and the metal film 205c1 is formed so that the height of the upper surface of the metal film 205c1 in the opening is equal to or higher than the height of the upper surface of the insulator 216 (see FIG. 12B).

[0271] Next, metal film 205b1 and metal film 205c1 are polished by CMP until they reach insulator 216, thereby forming conductors 205 (conductors 205a, 205b, and 205c) embedded in the openings (see FIG. 12C). The height of the top surface of conductor 205c and the height of the top surface of insulator 216 are approximately equal. Although not shown, a part of the top surface of insulator 216 is polished by CMP, and the film thickness of insulator 216 may become thinner.

[0272] As a result, the conductor 205 can be configured such that the highly conductive conductor 205b is disposed at the center, and the bottom, top, and side surfaces of the conductor 205b are covered with the conductor 205a and the conductor 205c, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. In this embodiment, the conductor 205b is made of tantalum, and the conductors 205a and 205b are made of tantalum nitride.

[0273] In addition, in actual film formation using the second ionization sputtering method, the effects of the second and third film formation steps may be mixed during the first film formation step. Also, the effects of the first and third film formation steps may be mixed during the second film formation step. Also, the effects of the first and second film formation steps may be mixed during the third film formation step.

[0274] The formation of the three-layered conductor 205 is preferably carried out using a so-called multi-chamber apparatus having a plurality of processing chambers capable of successively depositing different types of films. The multi-chamber apparatus will be described later.

[0275] In this embodiment, the formation of the conductor 205 has been described as an example of the second ionized sputtering method, but the present invention is not limited thereto. For example, the method can be used to form a conductor below the conductor 240. In addition, the method can be applied to the formation of a seed layer of a TSV (Through Silicon Via), for example.

[0276] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 5A to 5D will be described with reference to FIGS. 13A to 27D.

[0277] A in each figure shows a top view. B in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure. C in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure. D in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in A in each figure. Note that in the top view of A in each figure, some elements are omitted for clarity.

[0278] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate. The insulator 212 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0279] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0280] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0281] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0282] In addition, the ALD method utilizes the self-regulating nature of atoms and can deposit atoms one layer at a time, which has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD (Plasma Enhanced ALD) method, the use of plasma can enable film formation at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0283] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0284] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0285] In this embodiment, a silicon nitride film is formed as the insulator 212 by a sputtering method.

[0286] In this way, by using an insulator such as silicon nitride through which copper does not easily permeate as insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below insulator 212, it is possible to suppress the metal from diffusing upward through insulator 212. Furthermore, by using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below insulator 212.

[0287] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited as the insulator 214 by a sputtering method.

[0288] The hydrogen concentration of the insulator 214 is preferably lower than that of the insulator 212. By forming a silicon nitride film by a sputtering method as the insulator 212, silicon nitride with a low hydrogen concentration can be formed. Furthermore, by using aluminum oxide as the insulator 214, the hydrogen concentration can be lower than that of the insulator 212.

[0289] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration is placed away from the transistor 200.

[0290] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is deposited as the insulator 216 by a sputtering method.

[0291] Note that the insulators 212, 214, and 216 are preferably successively formed under reduced pressure without exposure to the air environment. By forming the films without exposure to the air, impurities or moisture from the air environment can be prevented from adhering to the insulators 212, 214, and 216, and the interface and vicinity of the interface between the insulators 212 and 214, and the interface and vicinity of the interface between the insulators 214 and 216 can be kept clean, which is preferable. For example, a multi-chamber film formation apparatus may be used for successive film formation. By forming the films successively, the manufacturing process time of the semiconductor device can be shortened, which is preferable.

[0292] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may be an area where an opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0293] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0294] After the openings are formed, the conductor 205 is formed by the manufacturing method described with reference to FIGS. 10A to 10D in the above-mentioned <second ionization sputtering method> (see FIGS. 13A to 13D).

[0295] The conductor 205 may be made of tantalum nitride, tungsten nitride, titanium nitride, or the like.

[0296] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of aluminum and hafnium. As the insulator 222, an oxide, a nitride, an oxynitride, or a nitride oxide containing one or both of aluminum and hafnium may be used. For example, an insulator such as aluminum oxide, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxynitride containing aluminum and hafnium, or a nitride oxide containing aluminum and hafnium may be formed. Such an insulator has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0297] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0298] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0299] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 222 as much as possible.

[0300] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a flow rate ratio of nitrogen gas and oxygen gas of 4 slm:1 slm at a temperature of 400° C. for one hour. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0301] Next, the insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide or silicon oxynitride film is formed by a sputtering method as the insulator 224. By using a sputtering method, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 comes into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0302] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high density plasma using, for example, microwaves. Alternatively, the apparatus may have a power source that applies RF (Radio Frequency) to the substrate side. By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment does not need to be performed.

[0303] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, a CMP process may be performed until the insulator 224 is reached. The CMP process can planarize and smooth the surface of the insulator 224. By disposing the aluminum oxide on the insulator 224 and performing the CMP process, it becomes easy to detect the end point of the CMP process. In addition, the CMP process may polish a part of the insulator 224, and the thickness of the insulator 224 may become thin, but the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage rate of the oxide to be formed later and to prevent a decrease in the yield of the semiconductor device. In addition, it is preferable to form an aluminum oxide film on the insulator 224 by a sputtering method, since oxygen can be added to the insulator 224.

[0304] Next, an oxide film 230A and an oxide film 230B are formed in this order on the insulator 224 (see FIGS. 13A to 13D).

[0305] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0306] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0307] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be set to 70% or more, preferably 80% or more, and more preferably 100%.

[0308] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0309] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0310] Next, the oxide film 243A is formed on the oxide film 230B (see FIGS. 13A to 13D). The oxide film 243A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 243A preferably has a Ga to In atomic ratio greater than the Ga to In atomic ratio of the oxide film 230B. In this embodiment, the oxide film 243A is formed by a sputtering method using an oxide target with an In:Ga:Zn=1:3:4 [atomic ratio].

[0311] It is preferable that the oxide film 230A, the oxide film 230B, and the oxide film 243A are successively formed under reduced pressure without being exposed to the air environment. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the oxide film 230A, the oxide film 230B, and the oxide film 243A, and it is preferable to keep the interface between the oxide film 230A and the oxide film 230B and the vicinity of the interface, and the interface between the oxide film 230B and the oxide film 243A and the vicinity of the interface clean. For example, a multi-chamber type film forming device may be used. By forming the films successively, it is preferable to shorten the manufacturing process time of the semiconductor device.

[0312] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A are not polycrystallized, and may be performed at 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0313] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230A, the oxide film 230B, and the oxide film 243A as much as possible.

[0314] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550° C. for 1 hour, followed by another heat treatment in an oxygen atmosphere at 550° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser and more compact structure. This can reduce the diffusion of oxygen or impurities in the oxide film 230B.

[0315] Next, the conductive film 242A is formed on the oxide film 243A (see FIGS. 13A to 13D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by a first ionization sputtering method. A conductor formed by the first ionization sputtering method can be a dense conductor with high film density, and is preferable because it has excellent oxidation resistance. Note that a heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is 200°C.

[0316] Next, the insulating film 271A is formed on the conductive film 242A (see FIGS. 13A to 13D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film having a function of suppressing oxygen permeation as the insulating film 271A. For example, an insulator that can be used for the insulator 222 may be formed as the insulating film 271A by a sputtering method or an ALD method.

[0317] Next, a conductive film 248A is formed over the insulating film 271A (see FIGS. 13A to 13D). The conductive film 248A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film 248A may be, for example, a conductive film similar to the conductive film 242A.

[0318] In this embodiment, the conductive film 242A, the insulating film 271A, and the conductive film 248A are formed by a sputtering method, with tantalum nitride as the conductive film 242A, aluminum oxide as the insulating film 271A, and tantalum nitride as the conductive film 248A.

[0319] Note that the conductive film 242A, the insulating film 271A, and the conductive film 248A are preferably successively formed under reduced pressure without exposure to the air environment. By forming the films without exposure to the air, impurities or moisture from the air environment can be prevented from adhering to the conductive film 242A, the insulating film 271A, and the conductive film 248A, and the interface and the vicinity of the interface between the conductive film 242A and the insulating film 271A, and the interface and the vicinity of the interface between the insulating film 271A and the conductive film 248A can be kept clean, which is preferable. For example, a multi-chamber type film forming apparatus may be used. By forming the films successively, the manufacturing process time of the semiconductor device can be shortened, which is preferable.

[0320] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the conductive film 248A are processed into an island shape by using a lithography method to form the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 (see FIGS. 14A to 14D). This processing can be performed using a dry etching method or a wet etching method. Processing using a dry etching method is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the conductive film 248A may be processed under different conditions. In this process, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be thin.

[0321] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0322] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that is to be a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching of the conductive film 242A and the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B and the conductive layer 248 are used as the hard mask.

[0323] Here, since the insulating layer 271B and the conductive layer 248 function as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between the side surface and the top surface, as shown in FIG. 14B to FIG. 14D. As a result, the conductors 242a and 242b shown in FIG. 5B and FIG. 5D have angular ends where the side surface and the top surface intersect. The angular end where the side surface and the top surface of the conductor 242 intersect increases the cross-sectional area of ​​the conductor 242 compared to when the end has a curved surface. This reduces the resistance of the conductor 242, and therefore the on-current of the transistor 200 can be increased.

[0324] Moreover, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are formed so as to at least partially overlap with the conductor 205. Moreover, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are approximately perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are approximately perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when providing a plurality of transistors 200. Alternatively, the angle between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 and the upper surface of the insulator 222 may be low. In this case, the angle between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 272 and the like can be improved in the subsequent steps, and defects such as porosity can be reduced.

[0325] Next, the conductive layer 248 is removed. The conductive layer 248 is removed by dry etching (see FIGS. 15A to 15D).

[0326] Next, the insulator 272 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 16A to 16D). The insulator 272 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, an aluminum oxide film is formed as the insulator 272 by sputtering. In particular, the insulator 272 is preferably formed by bias sputtering. In the bias sputtering, the amount of oxygen injected into the insulator 224, which is the base of the insulator 272, can be controlled by the magnitude of the RF power applied to the substrate. For example, the RF power is set to 0.31 W / cm. 2 More than 0.62 W / cm 2 More preferably, 1.86 W / cm 2 The above bias may be applied to the substrate. In other words, the amount of oxygen suitable for the transistor characteristics can be changed and injected by adjusting the RF power when forming the insulator 272. Also, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Also, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0327] As described above, the insulator 272 has a function of injecting oxygen into the underlying film, but the insulator 272 itself has a function of suppressing oxygen permeation. Therefore, when the insulator 280 is formed on the insulator 272 in a later process and oxygen is diffused from the insulator 280, it is possible to prevent oxygen from diffusing directly from the insulator 280 to the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B.

[0328] Next, an insulating film to be the insulator 280 is formed on the insulator 224 and the insulator 272. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed as the insulating film by a sputtering method, and a silicon oxide film may be formed thereon by a PEALD method or a thermal ALD method. The insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This can reduce the hydrogen concentration in the insulator 280. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surfaces of the insulator 224 and the insulator 272 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0329] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 17A to 17D). Note that, similarly to the insulator 224, a film of aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.

[0330] Here, a microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and the V in the oxide 230b and the oxide 230a is increased. O H is oxygen deficient (V O ) and hydrogen (H). At this time, some of the hydrogen that is separated may combine with oxygen contained in the insulator 280 and be removed as water molecules. Also, some of the hydrogen may be gettered to the conductor 242 via the insulator 272 and the insulating layer 271B.

[0331] After the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. Note that the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0332] Furthermore, by performing microwave treatment, the film quality of the insulator 280 can be modified, thereby suppressing the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 through the insulator 280 in a post-process after the formation of the insulator 280, or by heat treatment, etc.

[0333] Next, a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 18A to 18D).

[0334] When forming the opening, the upper part of the oxide 230b is removed. By removing a part of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0335] In addition, a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulator 272 and a part of the insulating layer 271B may be processed by wet etching, and a part of the oxide layer 243B, a part of the conductive layer 242B, and a part of the oxide 230b may be processed by dry etching. In addition, processing of a part of the oxide layer 243B and a part of the conductive layer 242B and processing of a part of the oxide 230b may be performed under different conditions.

[0336] Here, when a part of the oxide 230b is removed by dry etching to form a groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.02 W / cm 2 Above 0.03W / cm 2 It is preferable to set it to 0.06 W / cm or more. 2 It is more preferable that the dry etching time is set to be equal to or longer than that. The dry etching time may be appropriately set according to the depth of the groove.

[0337] Here, it is preferable to remove impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused therein. It is also preferable to remove damaged areas formed on the surface of the oxide 230b by the dry etching. The impurities include those originating from components contained in the insulator 280, part of the insulator 272, part of the insulating layer 271B, and the conductive layer 242B, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in the etching. The impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0338] In particular, impurities such as aluminum or silicon inhibit the oxide 230b or the oxide 230c formed in a later step from becoming a CAAC-OS. Therefore, it is preferable that impurity elements such as aluminum or silicon that inhibit the CAAC-OS formation are reduced or removed. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0339] In addition, the region of the metal oxide in which the CAAC-OS formation is inhibited by impurities such as aluminum or silicon and which becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so the V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC regions of the oxide 230b and the oxide 230c are reduced or removed.

[0340] In contrast, it is preferable that the oxide 230b and the oxide 230c have a layered CAAC structure. In particular, it is preferable that the CAAC structure is formed up to the drain lower end of the oxide 230b and the oxide 230c. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that either one or both of the oxide 230b and the oxide 230c near the lower end of the conductor 242a (conductor 242b) have a CAAC structure. In this way, even at the drain end that significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation of the electrical characteristics of the transistor 200 can be further suppressed. In addition, the reliability of the transistor 200 can be improved.

[0341] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning methods may be combined appropriately. Note that the above-mentioned grooves may become deeper due to the cleaning process.

[0342] For wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0343] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be called diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0344] In addition, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0345] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0346] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230c formed on the oxide 230b can be improved.

[0347] In the past, processing such as dry etching or the above-mentioned cleaning process may result in the thickness of insulator 224 in the area that overlaps with the opening but does not overlap with oxide 230b and insulator 272 being thinner than the thickness of insulator 224 in the area that overlaps with oxide 230b.

[0348] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O It is possible to reduce the amount of oxide 230c formed in the grooves of the oxide 230b. In addition, by carrying out such a heat treatment, the crystallinity of the oxide 230b can be improved, and the crystallinity of the oxide 230c formed in the grooves of the oxide 230b can also be improved. The heat treatment may be carried out under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be carried out continuously in a nitrogen atmosphere without exposure to the air.

[0349] Next, the oxide film 230C is formed (see FIGS. 19A to 19D). A heat treatment may be performed before the formation of the oxide film 230C, and the heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C.

[0350] Here, it is preferable that the oxide film 230C is provided so as to be in contact with at least the inner wall of the groove formed in the oxide 230b, a part of the side surface of the oxide 243, a part of the side surface of the conductor 242, a part of the side surface of the insulator 271, a part of the side surface of the insulator 272, and a part of the side surface of the insulator 280. By being surrounded by the oxide 243, the insulator 272, the insulator 271, and the oxide film 230C, the decrease in conductivity of the conductor 242 due to oxidation in the subsequent steps can be suppressed.

[0351] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as the oxide film 230A or the oxide film 230B according to the desired characteristics of the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with In:Ga:Zn=4:2:3 [atomic ratio], an oxide target with In:Ga:Zn=5:1:3 [atomic ratio], an oxide target with In:Ga:Zn=10:1:3 [atomic ratio], or an indium oxide target.

[0352] When the oxide film 230C is formed, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, when the oxide film 230C is formed, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%. Furthermore, by forming the oxide film 230C in an atmosphere containing a large amount of oxygen in this manner, it becomes easier to make the oxide film 230C into a CAAC-OS.

[0353] The oxide film 230C is preferably formed while heating the substrate. At this time, by setting the substrate temperature to 200° C. or higher, oxygen vacancies in the oxide film 230C and the oxide 230b can be reduced. By forming the oxide film 230C while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved.

[0354] Next, an oxide film 230D is formed (see FIGS. 19A to 19D). It is preferable that the oxide film 230D is formed continuously from the oxide film 230C without exposure to the atmosphere.

[0355] The oxide film 230D can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230D may be formed by the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230D. In this embodiment, the oxide film 230D is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0356] When the oxide film 230D is formed, some of the oxygen contained in the sputtering gas may be supplied to the oxide film 230C. Alternatively, when the oxide film 230D is formed, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.

[0357] Next, the insulating film 250A is formed (see FIGS. 19A to 19D). A heat treatment may be performed before the formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0358] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230d in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0359] When the insulator 250 has a two-layer laminated structure, it is preferable to continuously deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmospheric environment. By depositing the films without exposing them to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and it is possible to keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0360] Here, after the insulating film 250A is formed, a microwave treatment may be performed under an oxygen-containing atmosphere and reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and V in the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a is increased. O H to VO and hydrogen. At this time, some of the hydrogen separated may combine with oxygen to become H2O, which may be removed from the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a. Also, some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). In this way, by performing microwave processing, the hydrogen concentrations in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. Also, the V in the oxide 230a, the oxide 230b, the oxide film 230C, and the oxide film 230D can be reduced. O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O can be repaired or compensated for.

[0361] Also, a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed. Also, some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be more efficiently removed. The heat treatment temperature is preferably 300° C. or more and 500° C. or less.

[0362] Furthermore, by performing microwave processing to modify the film quality of the insulating film 250A, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film that becomes the conductor 260, or a post-treatment such as heat treatment.

[0363] Next, the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 20A to 20D). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is successively formed by a CVD method under reduced pressure without exposure to the atmosphere.

[0364] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 21A to 21D). As a result, the oxide 230c is arranged so as to cover the opening that reaches the oxide 230b and the inner wall (side and bottom) of the groove of the oxide 230b. The oxide 230d is arranged so as to cover the opening and the inner wall of the groove through the oxide 230c. The insulator 250 is arranged so as to cover the opening and the inner wall of the groove through the oxide 230d. The conductor 260 is arranged so as to fill the opening and the groove through the oxide 230c, the oxide 230d, and the insulator 250.

[0365] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0366] Next, the insulator 282 is formed over the oxide 230d, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 22A to 22D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form a film of aluminum oxide by a sputtering method. By forming the insulator 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 280 while forming the film. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. Moreover, it is preferable to form the insulator 282 in contact with the upper surface of the conductor 260, because this can suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in a subsequent heat treatment.

[0367] Next, a part of the insulator 282, a part of the insulator 280, a part of the insulator 272, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, and a part of the insulator 214 are processed to form an opening that reaches the insulator 212 (see FIGS. 23A to 23D). The opening may be formed so as to surround the transistor 200. Alternatively, the opening may be formed so as to surround a plurality of transistors 200. Thus, in the opening, a part of the side surface of the insulator 282, a part of the side surface of the insulator 280, a part of the side surface of the insulator 272, a part of the side surface of the insulator 224, a part of the side surface of the insulator 222, a part of the side surface of the insulator 216, and a part of the side surface of the insulator 214 are exposed.

[0368] A dry etching method or a wet etching method can be used for processing a part of the insulator 282, a part of the insulator 280, a part of the insulator 272, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, and a part of the insulator 214. Processing by the dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions.

[0369] Next, the insulator 283 is formed to cover the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 (see FIGS. 24A to 24D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed by a sputtering method. As shown in FIGS. 24B to 24D, the insulator 283 contacts the insulator 212 at the bottom surface of the opening. That is, the upper surface and side surface of the transistor 200 are surrounded by the insulator 283, and the lower surface is surrounded by the insulator 212. In this manner, the transistor 200 is surrounded by the insulator 283 and the insulator 212, which have high barrier properties, to prevent moisture and hydrogen from entering from the outside.

[0370] Next, an insulating film to become the insulator 274 is formed on the insulator 283. The insulating film to become the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed by a CVD method. In addition, the insulating film to become the insulator 274 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration in the insulating film to become the insulator 274 to be reduced.

[0371] Next, the insulating film that will become the insulator 274 is subjected to CMP processing to form the insulator 274 with a flat upper surface (see FIGS. 25A to 25D).

[0372] Next, openings are formed in the insulators 271, 272, 280, 282, and 283, reaching the conductor 242 (see FIGS. 26A to 26D). The openings may be formed by using a lithography method. Note that, although the shape of the openings is circular in top view in FIG. 26A, the shape is not limited to this. For example, the openings may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0373] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 26B). The insulating film that will become the insulator 241 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable to use an insulating film that has a function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form an aluminum oxide film by the ALD method. Alternatively, it is preferable to form a silicon nitride film by the PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0374] Moreover, for example, a dry etching method may be used as the anisotropic etching of the insulating film that becomes the insulator 241. By providing the insulator 241 on the side surface of the opening, it is possible to suppress the permeation of oxygen from the outside and to prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

[0375] Next, a conductive film that becomes the conductor 240 is formed. The conductive film that becomes the conductor 240 is desirably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. When the conductive film that becomes the conductor 240 has a laminated structure, for example, tantalum nitride, titanium nitride, or the like can be used as the lower layer film. Also, for example, tungsten, molybdenum, copper, or the like can be used as the upper layer film. The conductive film that becomes the conductor 240 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0376] In particular, it is preferable to use the second ionization sputtering method for forming the lower layer of the conductive film that becomes the conductor 240. By forming the film using the second ionization sputtering method, the film can be formed uniformly on the bottom and side surfaces of the opening.

[0377] By uniformly depositing the lower layer of the conductive film that becomes conductor 240, the lower layer of the conductive film that becomes conductor 240 preferably functions well as a seed layer for the upper layer of the conductive film that becomes conductor 240.

[0378] Next, a CMP process is performed to remove parts of the conductive film that will become conductor 240a and conductor 240b, exposing the upper surfaces of insulator 283 and insulator 274. As a result, the conductive film remains only in the openings, forming conductors 240a and 240b with flat upper surfaces (see FIG. 26B). Note that the CMP process may remove parts of the upper surfaces of insulator 283 and insulator 274.

[0379] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0380] Next, the conductive film that becomes the conductor 246 is processed by lithography to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b (see FIGS. 27A and 27B). At this time, although not shown, a part of the insulator 283 may be removed from the region where the conductor 246a and the conductor 246b do not overlap with the insulator 283.

[0381] Next, the insulator 286 is formed on the conductor 246 and the insulator 283 (see FIGS. 5B to 5D). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be multi-layered. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by a CVD method.

[0382] Through the above steps, a semiconductor device including the transistor 200 illustrated in Figures 5A to 5D can be manufactured. As illustrated in Figures 13A to 27D, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment. Note that when a semiconductor device including the transistor 200 illustrated in Figures 1A to 1D is manufactured, the semiconductor device may be manufactured without performing the steps illustrated in Figures 23 to 25.

[0383] <Applications of semiconductor devices> 28A and 28B, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those shown in the above <Structural Example of Semiconductor Device> and the above <Modification of Semiconductor Device>, will be described below. Note that in the semiconductor device shown in FIG. 28A and FIG. 28B, structures having the same functions as those of the semiconductor device shown in <Structural Example of Semiconductor Device> (see FIG. 1A to FIG. 1D) are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural Example of Semiconductor Device> and <Modification of Semiconductor Device 3> can be used as the materials for forming the transistor 200.

[0384] 28A and 28B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 28A and 28B, this is not the only possible arrangement. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0385] 28A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Thus, a plurality of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0386] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0387] In addition, although Fig. 28A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this. As shown in Fig. 28B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 28B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0388] In this manner, by using a structure in which the multiple transistors 200_1 to 200_n are surrounded by multiple sealing portions, the number of areas in contact with the insulator 283 and the insulator 212 increases, thereby improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the multiple transistors 200_1 to 200_n.

[0389] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0390] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0391] The structures, methods, and the like described in the above-described embodiment modes can be used in appropriate combination with structures, methods, and the like described in other embodiment modes, examples, and the like.

[0392] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0393] [Storage device 1] 29 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. The semiconductor device according to one embodiment of the present invention includes a transistor 200, a transistor 300, and a capacitor 100. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0394] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0395] 29, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0396] Moreover, the memory device shown in FIG. 29 can be arranged in a matrix to form a memory cell array.

[0397] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0398] Here, in the transistor 300 shown in FIG. 29, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0399] Note that the transistor 300 illustrated in FIG. 29 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0400] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

[0401] For example, the conductor 112 and the conductor 110 over the conductor 246 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0402] 29, the conductor 112 and the conductor 110 are shown to have a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0403] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0404] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0405] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, zirconium oxide, oxide having aluminum and hafnium, oxynitride having aluminum and hafnium, nitride oxide having aluminum and hafnium, oxide having silicon and hafnium, oxynitride having silicon and hafnium, nitride oxide having silicon and hafnium, and the like.

[0406] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0407] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0408] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0409] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0410] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 29, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0411] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0412] Here, similarly to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0413] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 212, the insulator 214, and the insulator 222, it is possible to prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0414] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0415] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0416] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0417] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen has been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0418] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, and 350 can be made of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0419] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0420] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0421] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0422] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0423] 29, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0424] In other words, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0425] As the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, may be used. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0426] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0427] Here, the conductor 240 penetrates the insulator 283 and the insulator 282, and the conductor 218 penetrates the insulator 214, the insulator 212, and the insulator 210, but as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 212, 214, 282, and 283 through the conductors 240 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 212, 214, 282, 283, 241, and 217, and it is possible to reduce impurities such as hydrogen contained in the insulator 274, etc. from being mixed in from the outside.

[0428] Furthermore, as described in the above embodiment, the insulators 216, 224, 280, 250, and 274 are preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0429] In this manner, the hydrogen concentration in the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0430] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0431] 29, for example, it is preferable to design the region where the insulator 283 and the insulator 212 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 282, 280, 272, 224, 222, 216, and 214 near the region that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0432] That is, the insulator 212 and the insulator 283 are in contact with each other through the openings provided in the insulators 282, 280, 272, 224, 222, 216, and 214. The insulators 212 and 283 can be made of the same material and by the same method to improve adhesion. For example, it is preferable to use silicon nitride.

[0433] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0434] This structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0435] In the memory device shown in Fig. 29, the shape of the capacitor 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Fig. 30. In the memory device shown in Fig. 30, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Fig. 29.

[0436] 30 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0437] The conductor 115 functions as the lower electrode of the capacitance element 100, the conductor 125 functions as the upper electrode of the capacitance element 100, and the insulator 145 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface in the openings of the insulators 150 and 142, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0438] The insulator 152 may be made of an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be made of an insulator that can be used for the insulator 214.

[0439] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. With such a configuration, the occupation area of ​​a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0440] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably approximately coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be, for example, a conductor that can be used for the conductor 205.

[0441] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0442] Moreover, it is preferable to use a material having a high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material having a high dielectric strength and a high dielectric constant (high-k) material may be used.

[0443] Examples of insulators made of high dielectric constant (high-k) materials include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 145 is made thick. By making the insulator 145 thick, the leakage current occurring between the conductor 115 and the conductor 125 can be suppressed.

[0444] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon nitride (SiN x ) in that order can be used. By using such an insulator having a high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0445] The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0446] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0447] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.

[0448] <Memory device configuration example> Fig. 31 is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 31 includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 1A to Fig. 1D. Fig. 31 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0449] The capacitance device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 provided to cover the insulator 272. That is, the capacitance device 292 configures a MIM (Metal-Insulator-Metal) capacitance. Note that one of a pair of electrodes included in the capacitance device 292, that is, the conductor 242b, can also serve as a source electrode of a transistor. In addition, a dielectric layer included in the capacitance device 292 can also serve as a protective layer provided in the transistor, that is, the insulator 271 and the insulator 272. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, so that a semiconductor device with high productivity can be obtained. In addition, one of a pair of electrodes of the capacitor 292, that is, the conductor 242b, also serves as a source electrode of the transistor, so that the area in which the transistor and the capacitor are arranged can be reduced.

[0450] Note that the conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0451] <Modifications of memory device> An example of a semiconductor device having a transistor 200 according to one embodiment of the present invention and a capacitor device 292, which is different from those shown in the above <Configuration Example of Memory Device>, will be described below with reference to Figs. 32A, 32B, 33, and 34. Note that in the semiconductor device shown in Figs. 32A, 32B, 33, and 34, structures having the same functions as those of the semiconductor device shown in the above embodiment and <Configuration Example of Memory Device> (see Fig. 31) are denoted by the same reference numerals. Note that in this section, the transistor 200 and the capacitor device 292 can be made of materials described in detail in the above embodiment and <Configuration Example of Memory Device>.

[0452] <<Memory Device Variation 1>> Below, an example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor device 292a, and a capacitor device 292b according to one embodiment of the present invention will be described with reference to FIG. 32A.

[0453] 32A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b. The semiconductor device 600 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with an upper surface of the insulator 271b, a side surface of the insulator 271b, and a side surface of the conductor 242b, and a conductor 294 provided to cover the insulator 272. Here, the capacitance device 292a has a conductor 242a, an insulator 271a provided on the conductor 242a, an insulator 272 provided in contact with an upper surface of the insulator 271a, a side surface of the insulator 271a, and a side surface of the conductor 242a, and a conductor 294a provided to cover the insulator 272. The capacitance device 292b has a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with an upper surface of the insulator 271b, a side surface of the insulator 271b, and a side surface of the conductor 242b, and a conductor 294b provided to cover the insulator 272.

[0454] As shown in FIG. 32A, the semiconductor device 600 has a linear symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. The conductor 242c serves as one of the source electrode or drain electrode of the transistor 200a and one of the source electrode or drain electrode of the transistor 200b. An insulator 271c is provided on the conductor 242c. The conductor 246 functions as wiring, and the conductor 240 functions as a plug to connect the transistor 200a and the transistor 200b. In this way, by configuring the two transistors, the two capacitance devices, and the wiring and the plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0455] The configuration examples of the semiconductor device illustrated in FIGS. 1A to 1D and 31 can be referred to for the configurations and effects of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b.

[0456] <<Memory Device Modification 2>> In the above, the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b are given as examples of the configuration of the semiconductor device, but the semiconductor device shown in this embodiment is not limited to this. For example, as shown in FIG. 32B, a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a similar configuration to the semiconductor device 600 are connected via a capacitance portion. In this specification, a semiconductor device having the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b is referred to as a cell. For the configurations of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b, the above description of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to.

[0457] FIG. 32B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitance portion.

[0458] As shown in FIG. 32B, the conductor 294b functioning as one electrode of the capacitance device 292b of the semiconductor device 600 is configured to also serve as one electrode of the capacitance device of the semiconductor device 601 having the same configuration as the semiconductor device 600. Although not shown, the conductor 294a functioning as one electrode of the capacitance device 292a of the semiconductor device 600 also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, that is, in FIG. 32B, in the A1 direction. The same configuration is also applied to the right side of the semiconductor device 601, that is, in FIG. 32B, in the A2 direction. That is, a cell array (also called a memory device layer) can be configured. By configuring the cell array in this way, the interval between adjacent cells can be reduced, so that the projection area of ​​the cell array can be reduced, and high integration is possible. Also, by arranging the cell array configuration shown in FIG. 32B in a matrix, a matrix-shaped cell array can be configured.

[0459] As described above, by forming transistor 200a, transistor 200b, capacitance device 292a, and capacitance device 292b in the configuration shown in this embodiment, the cell area can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0460] Moreover, the cell array may be configured not only in a plane but also in a stacked configuration. Fig. 33 shows a cross-sectional view of a configuration in which the cell array 610 is stacked in n layers. As shown in Fig. 33, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), the cells can be integrated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be configured.

[0461] <Memory Device Modification 3> FIG. 34 shows an example in which a memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0462] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420.

[0463] The memory device 420 is electrically connected to a memory device 420 in a different memory device layer 415 and a transistor 200T in a transistor layer 413 via a conductor 424 and a conductor 205.

[0464] The memory unit 470 is sealed by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 (hereinafter, for convenience, this is referred to as a sealing structure). The insulator 274 is provided around the insulator 283. Furthermore, the conductor 440 is provided on the insulator 274, the insulator 283, and the insulator 212, and is electrically connected to the element layer 411.

[0465] Further, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0466] Note that the insulators 212 and 283 are preferably made of a material having a high blocking property against hydrogen, and the insulators 214 and 282 are preferably made of a material having a function of capturing or fixing hydrogen.

[0467] For example, the material having a high blocking property against hydrogen includes silicon nitride, silicon nitride oxide, etc. Furthermore, the material having a function of capturing or fixing hydrogen includes aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0468] Note that the crystal structure of the materials used for the insulators 212, 214, 282, and 283 is not particularly limited, and may be an amorphous or crystalline structure. For example, an amorphous aluminum oxide film is preferably used as a material having a function of trapping or fixing hydrogen. Amorphous aluminum oxide may trap and fix a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0469] Here, the following model can be considered for the diffusion of excess oxygen in the insulator 280 and hydrogen in the oxide semiconductor in contact with the insulator 280.

[0470] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. In the diffusion of hydrogen, excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, and the hydrogen diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom, etc.) in the insulator 282, and is captured or fixed in the insulator 282. On the other hand, it is presumed that the oxygen atom of the excess oxygen having the OH bond remains in the insulator 280 as excess oxygen. In other words, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.

[0471] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0472] As an example, the insulator 280 containing excess oxygen is formed in an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or an atmosphere containing a mixture of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.

[0473] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0474] After the heat treatment, the insulator 283 is formed. The insulator 283 is a material having a high blocking property against hydrogen, and therefore can prevent hydrogen diffused to the outside or hydrogen present on the outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0475] Note that the above heat treatment is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, hydrogen is diffused upward or laterally of the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, hydrogen is diffused upward or laterally.

[0476] By using the above manufacturing process, the insulator 212 and the insulator 283 are bonded to each other, thereby forming the above-described sealing structure.

[0477] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor in which the hydrogen concentration is reduced can be provided. Therefore, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0478] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0479] (Embodiment 3) In this embodiment, an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0480] When manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable to use a so-called multi-chamber apparatus having a plurality of treatment chambers in which different types of films can be successively formed. In each treatment chamber, a film formation process such as sputtering, CVD, and ALD can be performed. For example, when one treatment chamber is a sputtering chamber, the sputtering chamber can be connected to a gas supply device, a gas purification device connected to the gas supply device, a vacuum pump, a target, and the like. The sputtering chamber may be configured to use an ionization sputtering method shown in FIG. 36 and FIG. 37. The sputtering chamber may be configured to use a bias sputtering method.

[0481] In each treatment chamber, a cleaning treatment, a plasma treatment, a reverse sputtering treatment, an etching treatment, an ashing treatment, a heating treatment, etc. may be performed. By appropriately performing different treatments in each treatment chamber, an insulator, a conductor, and a semiconductor film can be formed without exposure to the atmosphere.

[0482] A typical example of a semiconductor film used in one embodiment of the present invention is an oxide semiconductor film. In particular, an oxide semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) can be used to manufacture a transistor with excellent electrical characteristics. Here, a semiconductor film having a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic film or a substantially highly pure intrinsic film.

[0483] A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film can have a low carrier density because there are few carrier generation sources. Therefore, a transistor in which a channel formation region is formed in the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low. In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has an extremely small off-state current and a channel width of 1×10 6Even if the device has a channel length L of 10 μm and a width of 1 μm, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 It is possible to obtain a characteristic of A or less.

[0484] Typical examples of impurities in an oxide semiconductor film include water and hydrogen. In this specification and the like, reducing or removing water and hydrogen from an oxide semiconductor film may be referred to as dehydration or dehydrogenation. Adding oxygen to an oxide semiconductor film may be referred to as oxygen addition, and a state in which oxygen is added and the oxide semiconductor film has more oxygen than the stoichiometric composition may be referred to as an excess oxygen state.

[0485] Here, by successively depositing different types of films, that is, an oxide semiconductor, an insulator or conductor located below the oxide semiconductor, and an insulator or conductor located above the oxide semiconductor, without exposure to the air, it is possible to form a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly hydrogen and water) is reduced.

[0486] First, a structural example of an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described in detail with reference to Fig. 35. By using the apparatus shown in Fig. 35, a semiconductor film, an insulator or conductor located under the semiconductor film, and an insulator or conductor located over the semiconductor film can be successively formed. Therefore, impurities (particularly hydrogen and water) that may enter the semiconductor film can be suppressed.

[0487] FIG. 35 is a schematic top view of a single-wafer type multi-chamber apparatus 4000.

[0488] The apparatus 4000 has an atmosphere-side substrate supply chamber 4010, an atmosphere-side substrate transfer chamber 4012 for transferring substrates from the atmosphere-side substrate supply chamber 4010, a load lock chamber 4020a for transferring substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 4020b for transferring substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 4029 and a transfer chamber 4039 for transferring substrates in a vacuum, a transfer chamber 4030a and a transfer chamber 4030b connecting the transfer chamber 4029 and the transfer chamber 4039, and treatment chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e for performing film formation or heating.

[0489] The multiple processing chambers can each perform different processes in parallel. Therefore, a stacked structure of different film types can be easily fabricated. Parallel processing can be performed up to the number of processing chambers. For example, the apparatus 4000 shown in FIG. 35 has seven processing chambers. Therefore, seven film formation processes can be performed consecutively using one apparatus (also referred to as in-situ in this specification) without being exposed to the atmosphere.

[0490] On the other hand, in a laminated structure, the number of layers that can be produced without exposing to the atmosphere is not necessarily the same as the number of processing chambers. For example, if the desired laminated structure has multiple layers of the same material, the layers can be provided in one processing chamber, so that a laminated structure with a greater number of layers than the number of processing chambers installed can be produced.

[0491] The atmosphere side substrate supply chamber 4010 also includes a cassette port 4014 for accommodating substrates, and an alignment port 4016 for aligning the substrates. Note that a configuration may be provided with a plurality of cassette ports 4014 (for example, three in FIG. 35).

[0492] The atmosphere side substrate transfer chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4024a, and the processing chamber 4024b. The transfer chamber 4030a and the transfer chamber 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039. The transfer chamber 4039 is connected to the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.

[0493] A gate valve 4028 or a gate valve 4038 is provided at the connection between the chambers, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 4010 and the atmosphere side substrate transfer chamber 4012. The atmosphere side substrate transfer chamber 4012 has a transfer robot 4018. The transfer chamber 4029 has a transfer robot 4026, and the transfer chamber 4039 has a transfer robot 4036. The transfer robot 4018, the transfer robot 4026, and the transfer robot 4036 each have a plurality of movable parts and an arm that holds a substrate, and can transfer a substrate to each chamber.

[0494] The number of transfer chambers, processing chambers, load lock chambers, unload lock chambers and transport chambers is not limited to the above, and an optimum number can be provided depending on the installation space and process conditions.

[0495] In particular, when there are multiple transfer chambers, it is preferable to have two or more transfer chambers between one transfer chamber and the other transfer chambers. For example, as shown in Fig. 35, when there are transfer chambers 4029 and 4039, it is preferable to arrange transfer chambers 4030a and 4030b in parallel between transfer chambers 4029 and 4039.

[0496] By arranging the transfer chamber 4030a and the transfer chamber 4030b in parallel, for example, a step in which the transfer robot 4026 carries a substrate into the transfer chamber 4030a and a step in which the transfer robot 4036 carries a substrate into the transfer chamber 4030b can be performed simultaneously. Also, a step in which the transfer robot 4026 carries a substrate out of the transfer chamber 4030b and a step in which the transfer robot 4036 carries a substrate out of the transfer chamber 4030a can be performed simultaneously. In other words, by driving multiple transfer robots simultaneously, production efficiency is improved.

[0497] 35 shows an example in which one transfer chamber has one transfer robot and is connected to multiple processes, but this is not limited to the structure. One transfer chamber may have multiple transfer robots.

[0498] In addition, one or both of the transfer chamber 4029 and the transfer chamber 4039 are connected to a vacuum pump and a cryopump via valves. Therefore, the transfer chamber 4029 and the transfer chamber 4039 are evacuated from atmospheric pressure to a low or medium vacuum (several hundred Pa to about 0.1 Pa) using a vacuum pump, and then the valve is switched and the cryopump is used to evacuate from the medium vacuum to a high or ultra-high vacuum (0.1 Pa to 1×10 -7 It is possible to evacuate to a pressure of approximately 10 Pa.

[0499] Also, for example, two or more cryopumps may be connected in parallel to one transfer chamber. By having multiple cryopumps, even if one cryopump is in regeneration, it is possible to use the other cryopumps to pump air. Note that regeneration is the process of releasing molecules (or atoms) that have accumulated in the cryopump. If a cryopump accumulates too many molecules (or atoms), its pumping capacity will decrease, so it is a good idea to regenerate it periodically.

[0500] The processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e can each perform different processes in parallel. That is, in each processing chamber, a film formation process using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, a heat treatment, or a plasma treatment can be performed on a substrate placed therein. In addition, a film formation process may be performed in the processing chamber after a heat treatment or a plasma treatment is performed.

[0501] The apparatus 4000 has multiple processing chambers, and thus can transport the substrate between processing steps without exposing it to the atmosphere, thereby preventing impurities from being adsorbed on the substrate. In addition, since each processing chamber can perform a film formation process for different types of films, a heat treatment process, or a plasma treatment process, the order of film formation, heat treatment, etc. can be freely determined.

[0502] Each processing chamber may be connected to a vacuum pump via a valve. As the vacuum pump, for example, a dry pump, a mechanical booster pump, or the like can be used.

[0503] Each processing chamber may be connected to a power source capable of generating plasma. The power source may be a DC power source, an AC power source, or a high-frequency (RF, microwave, etc.) power source. A pulse generator may be connected to the DC power source.

[0504] The processing chamber may be connected to a gas purification device via a gas supply device. The gas supply devices and gas purification devices may be provided in the same number as the number of gas types.

[0505] For example, when a film formation process by sputtering is performed in a process chamber, the process chamber may include a target, a backing plate connected to the target, a cathode arranged facing the target via the backing plate, an adhesion prevention plate, a substrate stage, etc. Also, for example, the substrate stage may include a substrate holding mechanism for holding a substrate, a back surface heater for heating the substrate from the back surface, etc.

[0506] The substrate stage is held in a generally vertical position relative to the floor during film formation, and is held in a generally horizontal position relative to the floor during substrate transfer. By holding the substrate stage generally vertical to the floor, the probability that dust or particles that may be mixed in during film formation will adhere to the substrate can be reduced more than if the substrate stage were held horizontal. However, if the substrate stage is held vertical (90°) relative to the floor, there is a risk that the substrate will fall, so the angle of the substrate stage relative to the floor is preferably 80° or more and less than 90°.

[0507] The configuration of the substrate stage is not limited to the above. For example, the substrate stage may be configured to be approximately horizontal with respect to the floor surface. In this configuration, the target may be placed below the substrate stage, and the substrate may be placed between the target and the substrate stage. The substrate stage may also include a jig for fixing the substrate so that the substrate does not fall, or a mechanism for fixing the substrate.

[0508] Furthermore, by providing an adhesion prevention plate in the processing chamber, it is possible to prevent the particles sputtered from the target from accumulating in unnecessary areas. It is also preferable to process the adhesion prevention plate so that the accumulated sputtered particles do not peel off. For example, a blasting process may be performed to increase the surface roughness, or the surface of the adhesion prevention plate may be provided with irregularities.

[0509] The backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.

[0510] Note that the target may be a conductor, an insulator, or a semiconductor. For example, when the target is an oxide semiconductor such as a metal oxide, an oxide semiconductor film can be formed in the treatment chamber. Even when the target is a metal oxide, an oxynitride semiconductor film can be formed by using nitrogen gas as a film formation gas.

[0511] Each processing chamber may be connected to a gas supply device via a gas heating mechanism. The gas heating mechanism is connected to a gas purification device via a gas supply device. The gas introduced into the processing chamber may have a dew point of -80°C or less, preferably -100°C or less, more preferably -120°C or less, and may be, for example, oxygen gas, nitrogen gas, or a rare gas (such as argon gas). The gas heating mechanism may heat the gas introduced into the processing chamber to 40°C or more and 400°C or less. Preferably, the gas heating mechanism may heat the gas to 50°C or more and 200°C or less. The gas heating mechanism, gas supply device, and gas purification device may be provided in the same number as the number of gas types.

[0512] Each processing chamber may be connected to a turbo molecular pump and a vacuum pump via a valve, and each processing chamber may be provided with a cryotrap.

[0513] A cryotrap is a mechanism capable of adsorbing molecules (or atoms) with a relatively high melting point, such as water. A turbomolecular pump is excellent in productivity because it stably pumps large-sized molecules (or atoms) and requires little maintenance, but has a low pumping capacity for hydrogen and water. Therefore, a cryotrap can be used to improve the pumping capacity for water and the like. The temperature of the cryotrap refrigerator is 100K or less, preferably 80K or less. In addition, when a cryotrap has multiple refrigerators, it is preferable to change the temperature of each refrigerator, since this allows for efficient pumping. For example, the temperature of the first-stage refrigerator may be 100K or less, and the temperature of the second-stage refrigerator may be 20K or less.

[0514] The exhaust method of the processing chamber is not limited to this, and may be the same as the exhaust method of the connected transfer chamber (exhaust method of a cryopump and a vacuum pump). The exhaust method of the transfer chamber may be the same as the exhaust method of the processing chamber (exhaust method of a turbo molecular pump and a vacuum pump).

[0515] In particular, a combination of a vacuum pump and a cryotrap may be used as an exhaust means for the treatment chamber in which the oxide semiconductor film is formed. It is preferable that an exhaust means provided in the treatment chamber in which the oxide semiconductor film is formed has a function of adsorbing at least water molecules.

[0516] In addition, the partial pressure of hydrogen molecules in the treatment chamber for forming the oxide semiconductor film was 1×10 -2 Pa or less, and the partial pressure of water molecules is 1×10 -4 In addition, the pressure in the treatment chamber in which the oxide semiconductor film is formed in a standby state is preferably 8.0×10 Pa or less. -5 Pa or less, preferably 5.0×10 -5 Pa or less, more preferably 1.0×10 -5 The partial pressure of hydrogen molecules and the partial pressure of water molecules are values ​​when the processing chamber in which sputtering is performed is in a standby state and in a film forming state (plasma is in a discharging state) as described above.

[0517] The total pressure and partial pressure of the process chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0518] When the partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state in the treatment chamber are set to the above ranges, the impurity concentration in the oxide semiconductor film to be formed can be low.

[0519] In particular, by using each treatment chamber for a film formation process by sputtering, part of the configuration of the transistor 200 described in the above embodiment can be manufactured to have a stacked structure in which films are successively formed in situ.

[0520] In a method for manufacturing the transistor 200, the insulator 212, the insulator 214, and the insulator 216 are successively formed using an apparatus 4000. The oxide film 230A, the oxide film 230B, and the oxide film 243A are successively formed using the apparatus 4000. The conductive film 242A, the insulating film 271A, and the conductive film 248A are successively formed using the apparatus 4000.

[0521] That is, the insulator 212, the insulator 214, and the insulator 216 can be formed successively without exposure to the atmosphere. Also, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be formed successively without exposure to the atmosphere. Also, the conductive film 242A, the insulating film 271A, and the conductive film 248A can be formed successively without exposure to the atmosphere.

[0522] With the above-mentioned configuration, it is possible to form a laminated film from which impurities (typically, water, hydrogen, etc.) are thoroughly eliminated. In addition, since each interface of the laminated film is not exposed to the atmosphere, the impurity concentration is reduced.

[0523] Furthermore, for example, when heat treatment is performed in a treatment chamber, the treatment chamber may include a plurality of heating stages capable of storing substrates. The heating stages may be configured in multiple stages. By increasing the number of heating stages, a plurality of substrates can be simultaneously heat-treated, thereby improving productivity.

[0524] The heating mechanism that can be used in the processing chamber may be, for example, a heating mechanism that uses a resistance heating element for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTAs (Rapid Thermal Anneals) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTAs heat the workpiece by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. GRTAs perform heat treatment using high-temperature gas. An inert gas is used as the gas.

[0525] The load lock chamber 4020a may include a substrate transfer stage, a backside heater for heating the substrate from the backside, etc. The load lock chamber 4020a increases the pressure from a reduced pressure state to the atmosphere, and when the pressure in the load lock chamber 4020a reaches atmospheric pressure, the substrate transfer stage receives the substrate from the transfer robot 4018 provided in the atmosphere side substrate transfer chamber 4012. After that, the load lock chamber 4020a is evacuated to a reduced pressure state, and then the transfer robot 4026 provided in the transfer chamber 4029 receives the substrate from the substrate transfer stage.

[0526] The load lock chamber 4020a is connected to a vacuum pump and a cryopump via valves. The unload lock chamber 4020b may have the same configuration as the load lock chamber 4020a.

[0527] The atmosphere side substrate transfer chamber 4012 has a transfer robot 4018, so that the transfer robot 4018 can transfer substrates between the cassette port 4014 and the load lock chamber 4020a. A mechanism for suppressing the intrusion of dust or particles, such as a HEPA filter (High Efficiency Particulate Air Filter), may be provided above the atmosphere side substrate transfer chamber 4012 and the atmosphere side substrate supply chamber 4010. The cassette port 4014 can store a plurality of substrates.

[0528] By using the above-described apparatus 4000 to successively form an insulating film, a semiconductor film, and a conductive film without exposure to the atmosphere, it is possible to suitably suppress the intrusion of impurities into the semiconductor film.

[0529] As described above, by using the apparatus according to one embodiment of the present invention, a stacked structure including a semiconductor film can be manufactured by successive film formation. Therefore, impurities such as hydrogen and water that are taken into the semiconductor film can be suppressed, and a semiconductor film with a low density of defect states can be manufactured.

[0530] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes, examples, and the like.

[0531] (Embodiment 4) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter may be referred to as an OS transistor) and a memory device including a capacitor (hereinafter may be referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 38A, 38B, and 39A to 39H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0532] <Storage device configuration example> 38A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0533] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0534] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0535] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0536] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0537] 38A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 38B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0538] 39A to 39H will be used to explain examples of the configuration of a memory cell that can be applied to the above-mentioned memory cell MC.

[0539] [DOSRAM] 39A to 39C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 39A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0540] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring CAL.

[0541] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0542] Here, the memory cell 1471 shown in Fig. 39A corresponds to the memory device shown in Fig. 31. That is, the transistor M1 corresponds to the transistor 200, and the capacitive element CA corresponds to the capacitive device 292.

[0543] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 39B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 39C.

[0544] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0545] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0546] [NOSRAM] 39D to 39G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 39D has a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply called a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be called a nonvolatile oxide semiconductor RAM (NOSRAM).

[0547] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0548] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while holding data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0549] Here...

Claims

[Claim 1] A first insulator; a second insulator on the first insulator; and a third insulator on the second insulator, and a first conductor; a fourth insulator on the third insulator and on the first conductor; and a fifth insulator on the fourth insulator; and a first oxide on the fifth insulator; and a second oxide on the first oxide; and a third oxide on the second oxide, and a fourth oxide; a second conductor on the third oxide; and a third conductor on the fourth oxide; and a sixth insulator on the second conductor; and a seventh insulator on the third conductor; and an eighth insulator on the fifth to seventh insulators; a fifth oxide on the second oxide and disposed between the second conductor and the third conductor; a ninth insulator on the fifth oxide; and a fourth conductor on the ninth insulator; the first conductor has a region overlapping the second oxide, the fourth conductor has a region overlapping the second oxide, the fifth oxide has regions in contact with the first oxide to the fourth oxide, the second conductor, the third conductor, and the fifth insulator to the eighth insulator, respectively; the fifth oxide overlaps with a side surface of the fourth conductor; the eighth insulator has a region in contact with an upper surface of the fifth insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the third oxide, a side surface of the fourth oxide, a side surface of the second conductor, a side surface of the third conductor, a side surface of the sixth insulator, an upper surface of the sixth insulator, a side surface of the seventh insulator, an upper surface of the seventh insulator, and a side surface of the fifth oxide; Semiconductor device.

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