Semiconductor device

Abstract

To provide a transistor with excellent electric characteristics.SOLUTION: A semiconductor device includes a semiconductor, a first insulator provided in contact with the semiconductor, a first conductor provided in contact with the first insulator and overlapping with the semiconductor through the first insulator, and a second conductor and a third conductor provided in contact with the semiconductor. Any one or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device, and a method for manufacturing the same. Alternatively, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a camera, The present invention relates to an image device, a processor, and an electronic device. Or, a display device, a liquid crystal display device, a light emitting device, The present invention relates to a method for manufacturing a storage device, an imaging device, and an electronic device. The present invention relates to a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include a semiconductor device. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. It is known that a transistor has an extremely small leakage current when it is in a non-conducting state. For example, a low-power transistor using an oxide semiconductor is proposed, which utilizes the low leakage current of the transistor. A power CPU and the like have been disclosed (see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0006] In order to reduce impurities such as water and hydrogen in transistors using oxide semiconductors, Therefore, the gate electrode and the semiconductor device used in the transistor may be subjected to a high-temperature heat treatment. The source electrode or the drain electrode is formed of a material having heat resistance and oxidation resistance. is preferred.

[0007] In view of the above, one embodiment of the present invention is a transistor using a conductor which has heat resistance and oxidation resistance. One of the objectives is to provide the following.

[0008] Another object is to provide a transistor having stable electrical characteristics. Another object of the present invention is to provide a transistor having a small leakage current when off. Another object of the present invention is to provide a transistor having high frequency characteristics. An object of the present invention is to provide a transistor having marrow-off electrical characteristics. An object of the present invention is to provide a transistor with a small subthreshold swing value. Another object is to provide a highly reliable transistor.

[0009] Another object of the present invention is to provide a semiconductor device including the transistor. Another object of the present invention is to provide a module having the semiconductor device. Another object of the present invention is to provide a device having such a module, or an electronic device having such a module. It is an object of the present invention to provide a novel semiconductor device. Another object of the present invention is to provide a novel electronic device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device, a first insulator in contact with the semiconductor, and a second insulator in contact with the first insulator. A first conductor overlapping the semiconductor via an insulator, a second conductor in contact with the semiconductor, and and a third conductor, and at least one of the first to third conductors is made of tungsten ( W), silicon (Si), carbon (C), germanium (Ge), tin (Sn), and aluminum and one or more elements selected from aluminum (Al) and nickel (Ni), It is a semiconductor device.

[0012] In one embodiment of the present invention, at least one of the first to third conductors is a Rutherford backscattering conductor. Analysis(RBS: Rutherford Backscattering Spectrom The silicon concentration obtained by the etry is 5 atomic % or more and 70 atomic % or less. The semiconductor device has a region in which

[0013] In one embodiment of the present invention, at least one of the first to third conductors has a surface formed of silicon and an oxide. The semiconductor device according to any one of the preceding claims, further comprising a region having an element, the thickness of the region being 0.2 nm to 20 nm. It is a device.

[0014] One aspect of the present invention is a semiconductor device including a second insulator in contact with the semiconductor and a second insulator in contact with the second insulator. and a fourth conductor overlapping the semiconductor via the insulating layer, the fourth conductor being made of tungsten and silicon. One or more selected from silicon, carbon, germanium, tin, aluminum, and nickel The semiconductor device has a region having an element.

[0015] In one embodiment of the present invention, the fourth conductor is a silicon The semiconductor device having a region in which the concentration is 5 atomic % or more and 70 atomic % or less. It is located.

[0016] In one aspect of the present invention, the fourth conductor has a region having silicon and oxygen on a surface thereof, In the above semiconductor device, the thickness of the region is not less than 0.2 nm and not more than 20 nm.

[0017] One embodiment of the present invention is a semiconductor device including an oxide semiconductor. Effect of the Invention

[0018] According to one embodiment of the present invention, a transistor using a conductor having heat resistance and oxidation resistance is provided. It can be provided.

[0019] In addition, a transistor having stable electrical characteristics can be provided. It is possible to provide a transistor with low leakage current at high frequency. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor having a small subthreshold swing value can be provided. It is possible to provide a transistor with high reliability. It is possible.

[0020] Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module having the semiconductor device or the module may be provided. It is possible to provide an electronic device having a novel semiconductor device. Alternatively, a new module may be provided. Alternatively, a new electronic Equipment can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Diagram 3] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 4] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Diagram 5] Cross-sectional TEM image of a-like OS. [Figure 6] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 7] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are a schematic view and a cross-sectional view illustrating a film forming apparatus. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] FIG. 2 is a top view illustrating a manufacturing apparatus according to one embodiment of the present invention. [Figure 21] FIG. 2 is a cross-sectional view of a chamber according to one embodiment of the present invention. [Figure 22] FIG. 2 is a cross-sectional view of a chamber according to one embodiment of the present invention. [Figure 23] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 25]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 30] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 31] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 32] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 35] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 36] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 40] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 41] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 42] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 43] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 44] FIG. 1 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Diagram 45] FIG. 1 is a diagram illustrating the XPS results of a sample. [Diagram 46] Illustrative STEM results of the sample. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0024] The configurations shown in the following embodiments may be applied or combined with other configurations shown in the embodiments as appropriate. The above-mentioned embodiments can be combined or substituted to form one embodiment of the present invention.

[0025] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0026] In this specification, the terms "film" and "layer" are interchangeable. It is possible.

[0027] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". In general, potential (voltage) is relative, and the magnitude is measured relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." With respect to the potential, a positive potential and a negative potential are defined for .

[0028] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. and the ordinal numbers used to identify an aspect of the invention may not match.

[0029] Impurities in semiconductors are, for example, anything other than the main components that make up the semiconductor. For example, a concentration of 0. Elements that are less than 1 atomic % (also called atomic %) are impurities. This can result in the formation of DOS (Density of State) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, particularly hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, hydrogen, etc. In addition, if the semiconductor is a silicon layer, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of a semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0030] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode (the part of the semiconductor through which current flows) overlaps with the The source region or source potential in the region where the This refers to the distance between the drain (drain region or drain electrode) and the In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is defined as any one value, maximum value, or The minimum or average value.

[0031] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0032] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. In that case, The effective channel width of the channel is smaller than the apparent channel width. The larger the size, the larger the

[0033] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0034] In this specification, therefore, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area between the source and drain The channel width of the In this specification, it is sometimes referred to as the "channel width". In some cases, this may refer to the enclosed channel width or apparent channel width; or In this specification, when simply referring to a channel width, it may refer to an effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the inclusion channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0035] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width may be used. The value may differ from that calculated using the channel width.

[0036] In this specification, when it is stated that A has a shape protruding from B, it is to be understood that the shape is not limited to a top view. or in a cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it may be described as having a shape in which A protrudes more than B. For example, in the top view, one end of A is on the outside of one end of B. It can be read as having.

[0037] In this specification, when the term "semiconductor" is used, it can be replaced with various semiconductors. For example, Group 14 semiconductors such as silicon and germanium, and oxide semiconductors Conductors, Silicon Carbide, Germanium Silicide, Gallium Arsenide, Indium Phosphide, Selenide Can be replaced by compound semiconductors such as zinc and cadmium sulfide, and organic semiconductors .

[0038] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0040] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. I will use this to explain.

[0041] <Transistor structure> A structure of a transistor will be described below as an example of a semiconductor device according to one embodiment of the present invention. Reveal.

[0042] The structure of the transistor 10 will be described with reference to FIGS. 1B is a top view of the transistor 10. 1(C) is a cross-sectional view corresponding to the dashed line A3-A4 in FIG. 1(A). In the region indicated by the dashed line A1-A2, the channel length direction of the transistor 10 is In the region indicated by the dashed line A3-A4, the transistor 10 The channel width direction of the transistor is the same as the channel length direction of the The source (source region or source electrode) and the drain (drain region or drain electrode ) between the substrate and the substrate, the channel width direction is the direction in which the carriers move. In FIG. 1(A), the insulating film The insulating material 106a, the semiconductor material 106b, and the insulator material 106c are similar to the conductive materials 108a and 108b. However, since this would be difficult to see in a top view, the insulators 106a and 106b are not shown. The semiconductor 106b and the insulator 106c are shown by thin dashed lines slightly shifted from each other.

[0043] The transistor 10 includes an insulator 101 on a substrate 100, a conductor 102, an insulator 105, and an insulating layer. The semiconductor 103 and the insulator 104, the insulator 106a on the insulator 104, the semiconductor 106b and the and an insulator 106c, a conductor 108a and a conductor 108b on the semiconductor 106b, and an insulator The insulator 112 on the body 106c, the conductor 114 on the insulator 112, and the insulator on the conductor 114. It has an edge 116, an insulator 118, a conductor 120a and a conductor 120b.

[0044] Here, the insulator 101, the insulator 103, the insulator 104, the insulator 105, the insulator 106a, The insulators 106c, 112, 116 and 118 are insulating films or insulating The conductor 102, the conductor 108a, the conductor 108b, and the conductor 114, the conductor 120a and the conductor 120b can also be called a conductive film or a conductive layer. The semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.

[0045] Note that a configuration in which the insulator 106a and / or the insulator 106c is not provided is also possible.

[0046] In addition, one or more of the insulators 105, 103, and 104 may be provided. For example, a single-layer structure of only the insulator 104 may be used, or the insulator 103 and the insulator 104 may be used. The edge 104 may have a laminated structure of two layers.

[0047] In addition, as will be described in detail later, when the insulator 106a and the insulator 106c are used alone, Materials that can function as conductors or semiconductors may be used. When a transistor is formed by stacking the conductor 106b, the carrier is the semiconductor 106b. Near the interface between the conductor 106b and the insulator 106a, and near the interface between the semiconductor 106b and the insulator 106c The insulators 106a and 106c function as the channel of the transistor. Therefore, in this specification and the like, the insulators 106a and The insulator 106c is not described as a conductor or a semiconductor, but as an insulator.

[0048] A conductor 102 is formed on an insulator 101 formed on a substrate 100. At least a portion of the second insulating layer 106 overlaps with the insulator 106a, the semiconductor 106b, and the insulator 106c. In addition, an insulator 105 is provided on the conductor 102 so as to cover the conductor 102. An insulator 103 is formed on the insulator 105, and an insulator 104 is formed on the insulator 103. A body 104 is formed.

[0049] An insulator 106a is formed on the insulator 104, and a semiconductor 1 is formed in contact with the upper surface of the insulator 106a. In FIG. 1B, the edge of the insulator 106a and the semiconductor 106b is formed. The insulator 106a and the semiconductor 106b are formed so that their portions are roughly aligned. The configuration of the semiconductor device shown in the embodiment is not limited to this.

[0050] The conductor 108a and the conductor 108b are formed in contact with the semiconductor 106b. The conductor 108a and the conductor 108b are formed to be spaced apart from each other. It can function as a gate electrode and a drain electrode.

[0051] An insulator 106c is formed in contact with the semiconductor 106b. The insulator 106c is a conductor 108. It is preferable that the semiconductor 106b is in contact with the region between the conductor 108a and the semiconductor 106b. In FIG. 1(B), the insulator 106c is disposed approximately on the upper surfaces of the conductors 108a and 108b. However, the structure of the semiconductor device described in this embodiment is not limited to this. .

[0052] An insulator 112 is formed on the insulator 106c. A conductor 114 is formed on the insulator 112. In FIG. 1B, the ends of the insulator 112 and the insulator 106c are approximately aligned. Insulators 112 and 106c are formed so as to form the semiconductor device shown in this embodiment. The configuration of the conductor device is not limited to this. It can function as a pole.

[0053] An insulator 116 is formed on the conductor 114 and the insulator 112, and an insulating layer is formed on the insulator 116. An insulator 118 is formed. A conductor 120a and a conductor 120b are formed on the insulator 118. The conductor 120a and the conductor 120b are formed by insulating the insulator 106c and the insulator 112. The conductor 108a and the conductor 108b are electrically connected to each other through openings formed in the insulators 116 and 118. It is connected to the electric body 108b.

[0054] In addition, any one of the conductors 102, 114, 108a, and 108b The above is a combination of tungsten and silicon, carbon, germanium, tin, aluminum or nickel. and one or more elements selected from nickel.

[0055] In particular, the conductor in the present embodiment has a region containing tungsten and silicon. It is preferable to use a conductor having a silicon concentration obtained by RBS. It is preferable that the atomic percentage of the saturation region is 5 atomic % or more and 70 atomic % or less.

[0056] In addition, when a tungsten film is formed by, for example, a sputtering method, a conductor having crystallinity is formed. This may result in poor surface flatness of the conductor. By using a conductor as clearly shown, a conductor having an amorphous structure can be formed. This makes it easier to form a conductor having good surface flatness.

[0057] The conductor has a region on the surface thereof that contains silicon and oxygen, The thickness of the region is preferably 0.2 nm to 20 nm. The region may be substantially insulated, in which case the region may function as an insulator. In addition, this region functions as a barrier layer against oxygen, preventing the entire conductor from being oxidized. This can suppress the occurrence of

[0058] Conductor 102, conductor 114, conductor 108a and conductor 108b are connected as described above. By using such a conductive material, it is possible to reduce the thermal processing time during the process of fabricating the transistor 10, for example. Even if the conductor is exposed to heat or an oxidizing atmosphere, the entire conductor is prevented from being oxidized. This can suppress an increase in the resistance of the conductor, resulting in a favorable It is possible to manufacture transistors with suitable electrical characteristics (such as on-state current).

[0059] <Semiconductors> The detailed configuration of the semiconductor 106b will be described below.

[0060] The detailed configurations of the insulators 106a and 106c as well as the semiconductor 106b are also explain.

[0061] The semiconductor 106b is, for example, an oxide semiconductor containing indium. For example, the inclusion of indium increases carrier mobility (electron mobility). 106b preferably contains an element M. The element M is preferably Ti, Ga, Y, Zr, Let La, Ce, Nd, Sn or Hf be represented. However, the element M may be any of the above elements. There are cases where multiple combinations are acceptable. For example, the bond energy between element M and oxygen is For example, it has a higher bond energy with oxygen than indium. Alternatively, the element M may have a function of increasing the energy gap of the oxide semiconductor. The semiconductor 106b preferably contains zinc. If it contains, it may be prone to crystallization.

[0062] However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. 6b is a zinc-free oxide such as zinc tin oxide or gallium tin oxide. Oxide semiconductors containing lead, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. That's okay.

[0063] For example, the insulators 106a and 106c are made of a material other than oxygen that constitutes the semiconductor 106b. The semiconductor 106b is an oxide semiconductor composed of one or more elements. The insulator 106a and the insulator 106 are made of one or more elements other than oxygen. c is formed, the interface between the insulator 106a and the semiconductor 106b and the semiconductor 106b Defect levels are unlikely to be formed at the interface between the insulator 106c and the insulator 106b.

[0064] The insulator 106a, the semiconductor 106b, and the insulator 106c each contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M is preferably When 100 atomic %, In is preferably less than 50 atomic % and M is preferably less than 50 atomic %. More preferably, In is less than 25 atomic % and M is 75 atomic % or more. When the semiconductor 106b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, M is less than 75 atomic %, and more preferably In is 34 atomic % The insulator 106c is In-M-Zn In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as that of the insulator 106a may be used. In some cases, the insulator 106c does not need to contain indium. For example, The insulating material 106a and / or the insulating material 106c may be gallium oxide. The number of atoms of each element contained in the body 106a, the semiconductor 106b, and the insulator 106c is simply The ratio does not have to be an integer. The above composition can be measured by, for example, RBS. stomach.

[0065] For example, when the insulator 106a or the insulator 106c is formed by a sputtering method, A typical example of the atomic ratio of metal elements in the target used in the present invention is In:M:Zn=1:2: 4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: 3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn= 1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Z n=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M :Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, In :M:Zn=1:6:9 etc.

[0066] In addition, for example, when a film is formed by sputtering, the target used for the semiconductor 106b is Representative examples of atomic ratios of metal elements in Zn are In:M:Zn=1:1:1, In:M: Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2 .3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4 :2:4.1, In:M:Zn=5:1:7, etc. In particular, sputtering targets When the atomic ratio of In:Ga:Zn=4:2:4.1 is used, the semiconductor film is The atomic ratio of 106b may be approximately In:Ga:Zn=4:2:3.

[0067] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and Preferably, the ratio is 90% or more.

[0068] The semiconductor 106b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. The energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. The energy gap of the insulator 106c is smaller than that of the semiconductor 106b. Bigger than P.

[0069] The semiconductor 106b is an oxide having a larger electron affinity than the insulator 106a or the insulator 106c. For example, the semiconductor 106b is made of a material selected from the insulators 106a and 106c. The electron affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. It is more preferable to use an oxide having a larger molecular weight by 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. In other words, an insulator The energy level of the conduction band minimum of the insulator 106a or the insulator 106c is It is closer to the vacuum level than the energy level at the lower band edge.

[0070] At this time, when a gate voltage is applied, the insulator 106a, the semiconductor 106b and the insulator 10 A channel is formed in the semiconductor 106b having a large electron affinity among the semiconductors 106a and 106b. When a voltage is applied to the insulator 106a, the semiconductor 106b is electrically connected to the insulator 106b. Current may also flow near the interface between semiconductor 106b and 06c.

[0071] As described above, when the insulators 106a and 106c are used alone, they are not conductive or semiconductive. However, semiconductors 10 are made of materials that can function as either dielectrics or insulators. When a transistor is formed by stacking the semiconductor 106b, electrons flow through the semiconductor 106b. The flow passes near the interface between the semiconductor 106b and the insulator 106c. The insulators 106a and 106c do not function as the channel of the transistor. For this reason, in this specification and the like, the insulator 106a and the insulator 106 The insulator 106a and the insulator c are not described as semiconductors but as insulators. The body 106c is described as an insulator only because it is a transistor compared to the semiconductor 106b. Since the function is similar to that of an insulator, the insulator 106a or the insulator 106c is used. In some cases, a material that can be used for the semiconductor 106b may be used.

[0072] Here, between the insulator 106a and the semiconductor 106b, In addition, between the semiconductor 106b and the insulator 106c, The mixed region may have a semiconductor 106b and an insulator 106c. Therefore, the potential density of the insulator 106a, the semiconductor 106b, and the insulator 106c is reduced. In the laminate, the energy changes continuously near each interface (also called continuous junction). The band diagram is a band diagram of the insulator 106a and the semiconductor 106b, or the insulator 106 In some cases, the interface between the semiconductor 106c and the semiconductor 106b cannot be clearly distinguished.

[0073] At this time, the electrons flow into the semiconductor 106b, not into the insulator 106a and the insulator 106c. As described above, the electrons move mainly through the interface between the insulator 106a and the semiconductor 106b. The defect density at the interface between the semiconductor 106b and the insulator 106c is By lowering the concentration, the movement of electrons in the semiconductor 106b is less hindered, The on-state current of the transistor can be increased.

[0074] In addition, the on-current of the transistor is increased as the factors that inhibit the movement of electrons are reduced. For example, if there is no factor that inhibits the movement of electrons, electrons can move efficiently. It is estimated that the electron movement is caused by the large physical unevenness of the channel formation region. is also inhibited.

[0075] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 106b (the surface to be formed, here the upper surface of the insulator 106a) Root mean square (RMS) roughness less than 1 nm, preferably It is preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm × 1 μm is 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably 0 The maximum height difference (PV and ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, Preferably, it is less than 7 nm. RMS roughness, Ra and PV are measured by SII. Using a scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0076] In addition, in order to increase the on-state current of the transistor, the thinner the insulator 106c, the better. It is preferable that the thickness of the insulator 106c is smaller than the thickness of the insulator 106a, and the thickness of the semiconductor 106b is smaller than the thickness of the insulator 106a. For example, the thickness is less than 10 nm, preferably 5 nm or less, and The insulator 106c preferably has a region of 3 nm or less. 6c is a portion of the semiconductor 106b in which a channel is formed, which is formed by introducing an insulator other than oxygen adjacent to the semiconductor 106b. It has the function of blocking elements (hydrogen, silicon, etc.) from entering. It is preferable that the insulator 106c has a certain thickness. For example, the thickness is 0.3 nm or more. Insulator 106 having a region preferably having a thickness of 1 nm or more, more preferably 2 nm or more Let us use c.

[0077] In order to increase reliability, it is preferable that the insulator 106a is thick. nm or more, preferably 20 nm or more, more preferably 40 nm or more, and even more preferably 6 The thickness of the insulator 106a may be set to 0 nm or more. By increasing the thickness, a channel is formed from the interface between the adjacent insulator and the insulator 106a. The distance to the semiconductor 106b can be increased. However, the productivity of the semiconductor device decreases. Therefore, for example, it is set to 200 nm or less, preferably 120 nm or less, and more preferably The insulating layer 106a may have a region with a thickness of 80 nm or less.

[0078] Silicon in an oxide semiconductor can act as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the more preferable. and the insulator 106a, for example, in secondary ion mass spectrometry (SIMS), 10 16 atoms / cm3 More than 1×10 19 atoms / cm 3 Below, preferably 1x 10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 The following is more preferable: is 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 The following silicon In addition, there is a region between the semiconductor 106b and the insulator 106c, Put it, 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, good Preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 Below, More preferably, 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 Below It has a region with a lower silicon concentration.

[0079] In order to reduce the hydrogen concentration in the semiconductor 106b, the insulator 106a and the insulator 106 It is preferable to reduce the hydrogen concentration in the insulator 106a and the insulator 106c by SIMS. In, 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 below, Preferably 1 x 10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 below, More preferably, 1×1016 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below or less, and more preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / c m 3 In addition, in order to reduce the nitrogen concentration in the semiconductor 106b, To achieve this, it is preferable to reduce the nitrogen concentration in the insulators 106a and 106c. The thickness of the insulator 106a and the insulator 106c is 1×10 15 atoms / cm 3 Below Top 5×10 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 Below Top 5×10 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0080] Insulator 106a, semiconductor 106b, and insulator 106c shown in this embodiment, particularly semiconductor 106b is an oxide semiconductor having a low impurity concentration and a low density of defect states (few oxygen vacancies). and can be called a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source; The carrier density can be reduced. Therefore, a channel region is formed in the oxide semiconductor. The transistors used in this study have electrical characteristics in which the threshold voltage is negative (also called normally-on). In addition, oxide semiconductors that are high purity intrinsic or substantially high purity intrinsic are rarely The low defect density of the material may also result in a low trap density. Intrinsic or substantially highly purified intrinsic oxide semiconductors have a significantly small off-state current and a high channel density. The width W is 1×10 6 Even if the device has a channel length L of 10 μm, the source and drain electrodes When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, the off-state current is Below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 Achieved a characteristic of A or lower It is possible.

[0081] Therefore, the high purity intrinsic or substantially high purity intrinsic oxide semiconductor is provided with a channel region. The transistor in which the above-mentioned is formed has small fluctuations in electrical characteristics and is highly reliable. Note that charges trapped in the trap states of the oxide semiconductor remain trapped for a long time until they are lost. It takes a long time for the charge to be trapped, and it can behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor with a high density of dopant states has excellent electrical characteristics. The impurities that form trap states in an oxide semiconductor are water and The metals include nitrogen, alkali metals, and alkaline earth metals.

[0082] The hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c bonds with metal atoms. The oxygen reacts with the water to form water, and the lattice from which the oxygen is removed (or the part from which the oxygen is removed) When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms, forming a carrier. In particular, hydrogen trapped in oxygen vacancies can cause the band structure of semiconductors to change. Therefore, the hydrogen-containing oxide semiconductor A transistor using a conductor tends to have a normally-on characteristic. It is preferable that the semiconductor 106b and the insulator 106c have as little hydrogen as possible. Specifically, in the insulator 106a, the semiconductor 106b, and the insulator 106c, The hydrogen concentration obtained by IMS is 2×10 20 atoms / cm 3 Less than or equal to 5, preferably ×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Bottom, 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 The following applies.

[0083] In the insulator 106a, the semiconductor 106b, and the insulator 106c, one of the group 14 elements When some silicon or carbon is included, the insulator 106a, the semiconductor 106b and the insulator 106 As a result, the oxygen vacancies in the insulator 106a and the semiconductor 106c are increased, and the semiconductor 106c becomes n-type. The concentrations of silicon and carbon in the insulator 106a, the semiconductor 106b and the insulator 106c are The concentration of silicon and carbon near the interface between the insulator 106b and the insulator 106c (obtained by SIMS) The concentration at which the 18 atoms / cm 3 Less than or equal to 2×10 17 ato ms / cm 3 The following applies.

[0084] In addition, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIMS was used to The resulting concentration of alkali metal or alkaline earth metal is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 The following are the alkali metals and Alkaline earth metals can generate carriers when bonded to oxide semiconductors, which can lead to transistors. Therefore, the insulator 106a and the semiconductor 106 b and the insulator 106c. preferable.

[0085] Furthermore, when nitrogen is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, This generates electrons as carriers, increases the carrier density, and makes it easier to make the material n-type. A transistor using an oxide semiconductor film including such a semiconductor tends to be normally-on. Therefore, it is preferable that the nitrogen content in the oxide semiconductor film be reduced as much as possible. For example, the nitrogen concentration obtained by SIMS is 5×10 18 atoms / cm 3 Below It is preferable that

[0086] FIG. 1D shows an enlarged cross-sectional view of the insulator 106a and the semiconductor 106b near their centers. As shown in FIG. 1B and FIG. 1D, the conductor 108a of the semiconductor 106b and A low resistance region is formed in the region in contact with the conductor 108b (shown by the dotted line in FIG. 1B and FIG. 1D). The low resistance region 109a and the low resistance region 109b may be formed. The low resistance region 109b is formed by the conductor 108a or the conductor 108b in contact with the semiconductor 106b. or the conductive material contained in the conductor 108a or the conductor 108b. Such low resistance may be formed by bonding with elements in the semiconductor 106b. The formation of the high resistance region 109a and the low resistance region 109b allows the conductor 108a or This makes it possible to reduce the contact resistance between the conductor 108b and the semiconductor 106b. The on-current of the transistor 10 can be increased.

[0087] Although not shown, the insulator 106c and the conductor 108a or conductor 108b A low resistance region may also be formed in the contact region. Similar dotted lines indicate regions of low resistance.

[0088] As shown in FIG. 1D, the semiconductor 106b is a conductor having a conductor 108a and a conductor 108b. There is a region between the conductors 108a and 108b that is thinner than the region where the conductors 108a and 108b overlap. This is because when the conductor 108a and the conductor 108b are formed, the semiconductor 106 The upper surface of the semiconductor 106b is formed by removing a part of the upper surface of the semiconductor 106b. When the conductors that become the low resistance regions 109a and 108b are formed, In this way, a low resistance region similar to that of the semiconductor 106b may be formed. The region located between the conductors 108a and 108b on the top surface is removed to form a semiconductor This can prevent the formation of channels in the low resistance region on the top surface of the body 106b. In the following drawings, even if thin film regions are not shown in enlarged views, the same thickness is used. In some cases, thin areas may be formed.

[0089] The above-mentioned three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is just an example. For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be used. Alternatively, a single-layer structure may be used in which neither the insulator 106a nor the insulator 106c is provided. Alternatively, the insulator 106a, the semiconductor 106b, or the insulator 106c may be used. The layer structure is an n-layer structure (n is an integer of 4 or more) having either an insulating material, a semiconductor material or a conductor. It's okay.

[0090] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0091] Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned (CAAC-OS) crystalline oxide semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor and amorphous oxide semiconductor. do.

[0092] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- Examples of such materials include OS, polycrystalline oxide semiconductors, and nc-OS.

[0093] Amorphous structures are generally isotropic, have no inhomogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and the short-range order is not fixed. It is said that...

[0094] That is, the stable oxide semiconductor is transformed into a completely amorphous In addition, it is not isotropic (for example, it does not have a periodic structure in a small region). On the other hand, an oxide semiconductor having an a-li structure cannot be called a completely amorphous oxide semiconductor. The ke OS is not isotropic, but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0095] <caac-os> First, let me explain about CAAC-OS.

[0096] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0097] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. As shown in FIG. 2(A), a peak appears at a diffraction angle (2θ) of about 31°. is attributed to the (009) plane of the InGaZnO4 crystal, The crystal has a c-axis orientation, and the c-axis is a surface on which a CAAC-OS film is to be formed (also called a formation surface). ) or nearly perpendicular to the top surface. In addition to the peaks near the 2θ of 36°, a peak may also appear near the 2θ of 36°. The peak is due to the crystal structure classified into the space group Fd-3m. It is preferred that the OS does not exhibit such a peak.

[0098] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is assigned to the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. Even if the annealing is performed, no clear peak appears, as shown in Figure 2(B). When φ scanning is performed with 2θ fixed at around 56° for O4, as shown in Figure 2(C). Six peaks are observed that are attributable to the crystal plane equivalent to the (110) plane. The structure analysis using , revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed.

[0099] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the CAAC-OS surface. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (limiting) like that shown in Figure 2(D) is obtained. This diffraction pattern may show InG The electron diffraction pattern includes spots due to the (009) plane of the ZnO4 crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis extends to the surface on which the film is formed. On the other hand, for the same sample, the direction perpendicular to the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident directly on the sample is shown in Fig. 2(E). Figure 2(E) shows a ring-shaped diffraction pattern. Electron diffraction using a 300 nm electron beam also revealed that the pellets in the CAAC-OS It can be seen that the a-axis and the b-axis have no orientation. This is thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. In addition, the second ring in Fig. 2(E) is thought to be due to the (110) plane, etc. .

[0100] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. In some cases, it may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0101] Figure 3(A) shows a high-resolution TE image of the cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The M image is shown. A spherical aberration correction (SAC) was used for high-resolution TEM imaging. The spherical aberration correction function was used. A Cs-corrected high-resolution TEM image is, for example, For example, the atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed.

[0102] From Figure 3(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. It was found that the size of each pellet was 1 nm or more, and 3 nm or more. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC- It reflects the unevenness of the surface on which the OS is formed or the top surface, and the CAAC-OS surface is parallel to

[0103] In addition, Fig. 3(B) and Fig. 3(C) show the CAAC-O observed from a direction approximately perpendicular to the sample surface. Figure 3(D) and Figure 3(E) show the Cs-corrected high-resolution TEM images of the S plane. These are images obtained by processing the images of Fig. 3(B) and Fig. 3(C). The image processing method is described below. First, let us consider the case of Fig. 3(B) using the Fast Fourier Transform (FFT). Then, the FFT image is processed by the Transform process. 2.8 nm based on the origin -1 From 5.0 nm -1 Masking to leave the range between Next, the masked FFT image is transformed by inverse fast Fourier transform (IFFT). The image is then processed using Fast Fourier Transform (FFT) to obtain a processed image. The image obtained in this way is called an FFT filtered image. is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image, and shows a lattice arrangement. do.

[0104] In FIG. 3(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The dotted lines indicate the connections between the pellets. The broken line indicates the hexagonal shape, so it is clear that the pellets are hexagonal. The shape of the hole is not necessarily a regular hexagon, but is often a non-regular hexagon.

[0105] In Fig. 3(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different uniform lattice arrangement. Even in the vicinity of the dotted line, no clear grain boundaries can be seen. When you connect the surrounding lattice points around a lattice point, you get a distorted hexagon, pentagon, or / and heptagon. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction. The metal elements are substituted, and the bond distance between atoms changes, causing distortion. This is thought to be because it is possible to tolerate

[0106] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an ane-anchored crystal. do.

[0107] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. CAAC-OS is a material that can be degraded by impurities and defects ( It can also be said that the oxide semiconductor has few oxygen vacancies.

[0108] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0109] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0110] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0111] <nc-os> Next, we will explain nc-OS.

[0112] The following describes the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of the nc-OS do not have any orientation.

[0113] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region in parallel to the surface to be formed, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in A) is observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm was incident on the same sample. The electron beam diffraction pattern (EBSD pattern) is shown in Fig. 4(B). Therefore, the nc-OS was observed with an electron beam with a probe diameter of 50 nm. However, when an electron beam with a probe diameter of 1 nm is irradiated, the order is not observed. This confirms the existence of order.

[0114] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 4(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS has an ordered structure. It can be seen that the crystals are oriented in various directions. However, there are also areas where no regular electron diffraction pattern is observed.

[0115] Figure 4(D) shows a Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the deposition surface. The nc-OS is characterized by the areas indicated by auxiliary lines in the high-resolution TEM image. There are areas where crystals can be confirmed and areas where no clear crystals can be confirmed. The crystal part in the nc-OS has a size of 1 nm to 10 nm. In particular, the size of the crystals is often between 1 nm and 3 nm. Microcrystalline oxide semiconductors are oxide semiconductors with a size of more than 100 nm or less. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries may not be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, hereinafter, the crystalline parts of the nc-OS may be referred to as pellets.

[0116] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0117] In addition, since the crystal orientation between pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor can be called an oxide semiconductor.

[0118] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0119] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0120] Figure 5 shows high-resolution cross-sectional TEM images of the a-like OS. Figure 5(B) shows a high-resolution cross-sectional TEM image of the a-like OS at the start of irradiation. .3×10 8 e - / nm 2 Electrons (e - ) High resolution of a-like OS after irradiation Cross-sectional TEM images. Figures 5(A) and 5(B) show that the a-like OS is From the beginning, striped bright regions extending in the vertical direction are observed. It can be seen that the shape changes after electron irradiation. The bright areas are assumed to be voids or low-density areas. It is measured.

[0121] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0122] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0123] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0124] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that the structure has a total of nine layers, including six O layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. In the figure below, the areas where the lattice spacing is between 0.28 nm and 0.30 nm are InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0125] Figure 6 shows an example of an investigation into the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. S is the amount of crystals that grows according to the cumulative amount of electron irradiation used to obtain a TEM image. As can be seen from Figure 6, the size of the particles was about 1.2 nm at the beginning of the TEM observation. The crystal part (also called the initial nucleus) is - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 1.9 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 From Figure 6, it can be seen that there is no change in the size of the crystals in the range up to Regardless of the cumulative irradiation dose, the sizes of the crystalline parts of the nc-OS and CAAC-OS are The results show that the average particle size distribution is approximately 1.3 nm and 1.8 nm. The observation of M was performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were: Voltage: 300 kV, current density: 6.7 × 10 5 e - / (nm 2 s), the diameter of the irradiated area The wavelength was set to 230 nm.

[0126] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. That is, compared with the nc-OS and CAAC-OS, the a-like OS It is clear that this is an unstable structure.

[0127] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0128] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0129] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions. The density can be estimated by using a weighted average. It is preferable to estimate them together.

[0130] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0131] <Substrate, insulator, conductor> Each of the non-semiconductor components of transistor 10 will be described in detail below.

[0132] The substrate 100 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the solid substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. Plates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or silicon carbide. Silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Furthermore, there are semiconductor substrates having an insulating region inside the semiconductor substrate. Substrates, such as SOI (Silicon On Insulator) substrates. The conductive substrate may be a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like. , a substrate having a metal nitride, a substrate having a metal oxide, etc. A substrate having a conductor or a semiconductor provided thereon, a semiconductor substrate having a conductor or an insulator provided thereon A substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. These include elements, resistor elements, switch elements, light-emitting elements, and memory elements.

[0133] In addition, a flexible substrate that can withstand the heat treatment during transistor fabrication is used as the substrate 100. As a method for providing a transistor on a flexible substrate, a method for providing a transistor on a non-flexible substrate may be used. After the transistors are fabricated on the plate, the transistors are peeled off and the flexible substrate 10 is removed. There is also a method to transpose it to 0. In that case, a release layer is placed between the non-flexible substrate and the transistor. The substrate 100 may be a sheet, film or foil having woven fibers. The substrate 100 may be flexible. It may have the property of returning to its original shape when bending or pulling is stopped. The thickness of the substrate 100 may be, for example, 5 μm to 700 μm. Preferably, the thickness is 10 μm or more and 500 μm or less, and more preferably, the thickness is 15 μm or more and 300 μm or less. The thickness of the substrate 100 is set to be 1.5 m or less. By making the substrate 100 thinner, the weight of the semiconductor device can be reduced. By making the substrate 100 thin, it is possible to provide flexibility and foldability even when using glass or the like. It may have the property of returning to its original shape when bending or pulling is stopped. As a result, it is possible to reduce the impact or the like applied to the semiconductor device on the substrate 100. As a result, a robust semiconductor device can be provided.

[0134] The substrate 100, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or a glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of 100 mm. The lower the coefficient of thermal expansion, the more preferable it is since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester or polystyrene. Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, so it is suitable for flexible substrates. 100 is preferable.

[0135] The insulator 101 is an insulator having a function of blocking hydrogen or water. Hydrogen and water in the insulator provided near the insulator 6a, the semiconductor 106b, and the insulator 106c are 106a, semiconductor 106b, and insulator 106c. This may result in a decrease in the reliability of the transistor 10. When using a substrate on which a silicon-based semiconductor element such as a switch element is provided as 0, Hydrogen is used to terminate dangling bonds in the semiconductor device, and the hydrogen forms a transistor. There is a risk of hydrogen or water diffusing up to 10. By providing the insulator 101, hydrogen or water is prevented from diffusing from the lower layer of the transistor 10. This can suppress the breakdown voltage and improve the reliability of the transistor 10. It is preferable that the insulating layer 104 is less permeable to hydrogen or water than the insulating layer 105 or the insulating layer 104 .

[0136] In addition, the insulator 101 preferably has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 104, e.g. Oxygen can be effectively supplied to the insulator 106a, the semiconductor 106b, and the insulator 106c. do.

[0137] The insulator 101 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride or the like can be used. By using these as the insulator 101, It can function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. The insulator 101 may be made of, for example, silicon nitride or silicon oxide nitride. By using these as the insulator 101, the diffusion of hydrogen and water can be blocked. It can function as an insulating film that exhibits a blocking effect.

[0138] At least a portion of the conductor 102 is sandwiched between the conductor 108a and the conductor 108b. The conductor 102 preferably overlaps with the semiconductor 106b. By providing such a conductor 102, the transistor 1 The threshold voltage of the insulator 103 can be controlled. By controlling the threshold voltage, the gate of transistor 10 can be When the voltage applied to the conductor 114 is low, for example, when the applied voltage is below 0 V, This prevents the transistor 10 from being turned on. It becomes easier to shift the electrical characteristics of the transistor in the normally-off direction.

[0139] The conductor 102 may be made of tungsten, silicon, carbon, germanium, tin, or aluminum. and a conductor having a region having one or more elements selected from the group consisting of tungsten, nickel, and tungsten. In particular, a conductor containing tungsten and silicon is preferable. The silicon concentration obtained by BS is 5 atomic % or more and 70 atomic % or less. It is preferable that the silicon concentration is 10 atomic % or more and 60 atomic % or more. It is more preferable that the conductive material 102 has a region below the surface. The insulating film 10 may be formed as a single layer or a multilayer.

[0140] The conductor 102 also has a region having silicon and oxygen on the surface of the conductor 102, The thickness of the region is preferably 0.2 nm or more and 20 nm or less. In this case, the region can function as an insulator. In addition, the region functions as a barrier layer, preventing the entire conductor from being oxidized. This can suppress the occurrence of

[0141] The conductor 102 may be formed by sputtering. MCVD (Metal Chemical Vapor Deposition) method The film can be formed in this manner.

[0142] The insulator 105 is provided so as to cover the conductor 102. An insulator similar to 104 or insulator 112 can be used.

[0143] The insulator 103 is provided to cover the insulator 105. The insulator 103 blocks oxygen. By providing such an insulator 103, the insulator 1 This prevents the conductor 102 from extracting oxygen from the insulator 104. 04 to the insulator 106a, the semiconductor 106b, and the insulator 106c. This can be done.

[0144] The insulator 103 may be boron, aluminum, silicon, scandium, titanium, gallium, etc. tungsten, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium The oxide or nitride may be a nium or thallium oxide or nitride. Hafnium oxide or aluminum oxide is used.

[0145] In the insulators 105, 103, and 104, the insulator 103 traps electrons. It is preferable that the insulator 105 and the insulator 104 have a function of suppressing the emission of electrons. When the insulator 103 has the function of trapping electrons, the electrons trapped in the insulator 103 can behave like negative fixed charges. be.

[0146] It is preferable that the insulator 104 contains a small amount of water or hydrogen in the film. Preferably, 104 is an insulator having excess oxygen. For example, the insulator 104 may be , for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon , phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulators containing tungsten, neodymium, hafnium or tantalum are used in single or multilayer configurations. For example, the insulator 104 may be aluminum oxide, magnesium oxide, or Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Hafnium oxide or tantalum oxide may be used. Preferably, silicon oxide or oxynitride is used. Silicon carbide is used.

[0147] It is preferable that the amount of water or hydrogen contained in the insulator 104 is small. For example, 104 is a thermal desorption spectrometer (TDS). 100℃ to 700℃ or 100℃ to 500℃ In the range of surface temperatures, the number of water molecules desorbed is 1.0×10 13 molecules / cm 2 More than 1.4×10 16 molecules / cm 2 Below, 1.0×10 13 molecules / cm 2 Above 4.0×10 15 molecule / cm 2 Below, 1.0×10 13 molecules / cm 2 Above 2.0×10 15 molecules / cm 2 In addition, it is preferable that the temperature is 100°C or higher and 700°C or lower by TDS. In the surface temperature range of ℃ to 500℃, the amount of hydrogen molecules desorbed is 1.0×10 13 molecule / c m 2 More than 1.2 x 10 15 molecules / cm 2 Below, 1.0×10 13 molecules / cm 2 End 9.0×10 14 molecules / cm 2 It is preferable that the following is true: The method for measuring the amount of release will be described in detail below.

[0148] Impurities such as water and hydrogen are introduced into the insulator 106a, the semiconductor 106b and the insulator 106c, particularly A defect level is formed in the semiconductor 106b, which is a factor that changes the electrical characteristics of the transistor. For this reason, the insulating material 106a, the semiconductor 106b, and the insulating material 106c are provided below the insulating material 106a. By reducing the amount of water or hydrogen in the insulator 104, water or hydrogen can be removed from the insulator 104. This can reduce the formation of defect levels due to the supply of atoms and the like to the semiconductor 106b. By using an oxide semiconductor with a reduced density of defect states, stable electrical characteristics can be obtained. It is possible to provide a transistor having

[0149] The insulator 104 is formed by plasma enhanced CVD (PECVD), which allows high quality films to be obtained at relatively low temperatures. It is preferable to form the film by using the plasma enhanced CVD method. For example, when forming a silicon oxide film by the PECVD method, silicon is used as the raw material gas. Hydrides are often used, and hydrogen, water, etc. are introduced into the insulator 104 during film formation. Therefore, in the formation of the insulator 104 in this embodiment, a halo is used as a source gas. It is preferable to use silicon halide. Here, examples of silicon halide include For example, SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 ( Silicon trichloride), SiH2Cl2 (dichlorosilane) or SiBr4 (silicone tetrabromide) In particular, it is preferable to use SiF4 (silicon tetrafluoride). stomach.

[0150] In addition, when silicon halide is used as a source gas for forming the insulator 104, the halogen In addition to silicon hydride, silicon hydride may be added. The hydrogen and water content in the insulator 104 is reduced compared to when only hydrogen is used as the raw material gas. The film formation rate can be improved compared to when only silicon fluoride is used as the source gas. For example, In this case, the insulator 104 may be formed using SiF4 and SiH4 as raw material gases. The ratio of the flow rates of 4 and SiH4 is determined taking into consideration the water and hydrogen content in the insulator 104 and the deposition rate. It should be set appropriately.

[0151] In addition, the insulator 104 is preferably an insulator having excess oxygen. By providing 104, the insulator 104 is connected to the insulator 106a, the semiconductor 106b, and the insulator Oxygen can be supplied to the insulator 106c, which is an oxide semiconductor. The oxygen vacancies that cause defects in the semiconductor 106a, the semiconductor 106b, and the insulator 106c can be reduced. This allows the insulator 106a, the semiconductor 106b, and the insulator 106c to have low defect level densities. In this case, an oxide semiconductor having stable characteristics can be obtained.

[0152] In this specification and the like, the term "excess oxygen" refers to oxygen that is contained in excess of the stoichiometric composition. Alternatively, the excess oxygen refers to a film containing the excess oxygen, for example, by heating. Excess oxygen is oxygen released from the membrane or layer. The movement of excess oxygen can occur between atoms in a film or layer, or between oxygen atoms that compose the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0153] The insulator 104 having excess oxygen is heated to 100° C. or higher and 700° C. or lower by TDS. In the surface temperature range of ℃ to 500℃, the amount of oxygen molecules desorbed is 1.0×10 14 molecule / c m 2 Above 1.0×10 16 molecules / cm 2 Less than or equal to 1.0×10, more preferably 15 molecule / cm 2 Above 5.0×10 15 molecules / cm 2 The result is as follows.

[0154] The method for measuring the amount of released molecules using TDS is explained below using the amount of released oxygen as an example. do.

[0155] The total amount of gas released when a measurement sample is analyzed by TDS is calculated by the integral of the ion intensity of the released gas. The total amount of gas released can then be calculated by comparison with a standard sample. .

[0156] For example, the TDS results of a silicon substrate containing a given density of hydrogen as a standard sample and the measurement From the TDS results of the sample, the amount of oxygen molecules released from the measured sample (N O2 ) is calculated using the formula below. Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the molecules are oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but the possible The oxygen atom isotope with mass number 17, which is not considered here. The abundance ratio of oxygen molecules, including the oxygen atom with mass number 18, in nature is is not taken into consideration because it is an extremely small amount.

[0157] N O2 =N H2 / S H2 ×S O2 ×α

[0158] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is analyzed by TDS. Here, the reference value of the standard sample is , N H2 / S H2 Let us assume that S O2 is the ion intensity when the measurement sample was analyzed by TDS. is the integral value of the degree of concentration. α is a coefficient that affects the ion intensity in TDS. For details, please refer to Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released is The standard sample was measured using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electron Science Corporation. The measurement is performed using a silicon substrate containing a certain amount of hydrogen atoms as a constant.

[0159] In addition, some of the oxygen is detected as oxygen atoms in TDS. The ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate, by evaluating the amount of released oxygen molecules, the amount of released oxygen atoms can be calculated. can also be estimated.

[0160] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released in terms of oxygen atoms is This is twice the amount released.

[0161] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (ES R: Electron Spin Resonance, g value is near 2.01. It may also have symmetrical signals.

[0162] The insulator 104 may also have a function of preventing diffusion of impurities from the substrate 100.

[0163] As described above, it is preferable that the upper or lower surface of the semiconductor 106b is highly flat. Therefore, the upper surface of the insulator 104 is subjected to chemical mechanical polishing (CMP). The planarization process is carried out using methods such as cal polishing to improve the flatness. Good too.

[0164] Conductor 108a and conductor 108b are the source electrode or The drain electrode can function as either the first or second electrode.

[0165] The conductor 108a and the conductor 108b may be formed in a manner similar to that of the conductor 102.

[0166] In addition, in the region where the conductor 108a and the conductor 108b do not overlap with the conductor 114, It is preferable that at least a portion of the insulating material 106 overlaps with the insulating material 112 via the insulating material 106c. For example, as shown in FIG. 1B, most of the upper surfaces of the conductors 108a and 108b are insulated. By using such a configuration, the conductor 108 a and the upper surface of the conductor 108b, the extraction of oxygen from the insulator 112 can be suppressed. As a result, the insulator 112 can be removed from the insulator 106a, the semiconductor 106b, and the insulator 106c. It can effectively supply oxygen to 6c.

[0167] The insulator 112 can function as a gate insulating film for the transistor 10. The insulator 112 may be an insulator having excess oxygen, similar to the insulator 104. By providing the body 112, the insulator 112 is provided with the insulator 106a, the semiconductor 106b, and Oxygen can be supplied to the insulator 106 .

[0168] The insulator 112 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 112 may be made of aluminum oxide, oxide film, or a laminate. magnesium oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0169] Conductor 114 can function as a gate electrode of transistor 10. The conductor 4 may be formed in the same manner as the conductor 102 .

[0170] Here, as shown in FIG. 1C, the electric field generated by the conductor 102 and the conductor 114 The semiconductor 106b can be electrically surrounded by the electric field generated by the conductor. The structure of a transistor that electrically surrounds a semiconductor is called a surrounded channel. nel (s-channel) structure. Therefore, the entire semiconductor 106b (upper surface In the s-channel structure, the transistor has a channel on the top surface (the bottom surface and the side surface). A large current can flow between the source and drain of the transistor, and the current when it is conducting (on-state current) can be increased.

[0171] In addition, the s-channel structure is suitable for miniaturized transistors because it can achieve a high on-state current. Since the transistor can be miniaturized, the structure having the transistor is suitable for The semiconductor device can be a highly integrated and highly dense semiconductor device. For example, the transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. The transistor has a channel width of 0.1 nm or less, more preferably 20 nm or less. Preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has an area of.

[0172] The insulator 116 can function as a protective insulating film for the transistor 10. The thickness of the edge 116 may be, for example, 1 nm or more, or 20 nm or more. In addition, at least a portion of the insulator 116 is in contact with the upper surface of the insulator 104 or the insulator 112. It is preferable that the insulating layer is formed by the above method.

[0173] The insulator 116 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium Insulators containing tungsten, lanthanum, neodymium, hafnium or tantalum are used in single layers or The insulator 116 may be formed of oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, or the like. It is preferable that the insulating material has an effect of blocking metals and the like. Examples of such insulating materials include A nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride and oxynitride. Silicon, aluminum nitride, aluminum oxide nitride, etc. In addition, instead of nitride insulating film Instead, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, and nitridium oxide. Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Nium, etc.

[0174] Here, the insulator 116 is preferably formed by sputtering. It is more preferable to carry out the sputtering method under an atmosphere containing By forming the insulator 116, the insulator 104 or the insulator 112 is formed at the same time. (After the insulator 116 is formed, the interface between the insulator 104 or the insulator 112 and the insulator 116) Oxygen is added to the vicinity.

[0175] The insulator 116 is an insulator that is less permeable to oxygen than the insulators 104 and 112. It is preferable that the insulating material 116 has an effect of blocking oxygen. As a result, the insulator 104 and the insulator 112 are replaced by the insulator 106a, the semiconductor 106b, and the When oxygen is supplied to the insulator 106c, the oxygen is released to the outside above the insulator 116. This can prevent the problem from occurring.

[0176] Aluminum oxide is permeable to both impurities such as hydrogen and moisture, and oxygen. It is preferable to use it for the insulator 116 because it has a high blocking effect of preventing the passage of light.

[0177] In addition, the insulator 116 can be used as the insulator 106a or the insulator 106c described above. These oxides can be relatively easily deposited by sputtering. Since the insulators 104 and 112 can be easily formed, oxygen can be effectively added to the insulators 104 and 112. As the insulator 116, it is preferable to use an oxide insulator containing In. For example, In-Al oxide, In-Ga oxide, and In-Ga-Zn oxide are used. Oxide insulators containing In are prone to generate particles when they are formed by sputtering. Because they are few in number, they are well suited for use as insulators 116 .

[0178] The insulator 118 functions as an interlayer insulating film. It may be formed in the same manner as above.

[0179] Conductor 120a and conductor 120b are the source electrode and drain electrode of transistor 10. The conductor 120a and the conductor 120b function as wiring electrically connected to the electrodes. For example, a conductor that can be used as the conductor 108a and the conductor 108b may be used. This allows the wiring to function as a wiring having heat resistance and oxidation resistance.

[0180] By adopting the above-mentioned configuration, a transistor using a conductor having heat resistance and oxidation resistance can be obtained. It is possible to provide a transistor having stable electrical characteristics. Alternatively, it is possible to provide a transistor with a small leakage current when non-conducting. Alternatively, a transistor having high frequency characteristics can be provided. It is possible to provide a transistor having a constant-off electrical characteristic. It is possible to provide a transistor with a small threshold swing value. It is possible to provide a transistor with high performance.

[0181] <Modified Transistor> Modifications of the transistor 10 will be described below with reference to FIGS. 1B and 1C, the channel length direction of the transistor is The diagram shows a cross-sectional view and a cross-sectional view in the channel width direction of a transistor.

[0182] The transistor 12 shown in FIG. 7(A) and FIG. 7(B) has a silicon layer on the surface of the conductor 108a. The conductor 108b has a region 108c having silicon and oxygen, and the surface of the conductor 108b has silicon and The transistor 10 differs from the transistor 10 in that it has a region 108d containing oxygen. FIG. 7(C) is an enlarged view of the area surrounded by the dashed line in FIG. 7(A).

[0183] The regions 108c and 108d are formed by removing oxygen from the surfaces of the conductors 108a and 108b. The silicon in the conductors 108a and 108b is segregated to the surface and reacts with oxygen. The regions 108c and 108d are formed by bonding with an insulator. Therefore, as shown in FIG. 7(C), for example, A region 108c that functions as an insulator is provided between the body 114 and the conductor 108a. This reduces the parasitic capacitance between the conductor 114 and the conductor 108a. In addition, the region 108d is provided to reduce the gap between the conductor 114 and the conductor 108b. The parasitic capacitance is also reduced. By reducing the parasitic capacitance, the electrical characteristics of the transistor 12 are improved. can be improved.

[0184] In addition, the regions 108c and 108d that function as insulators are provided. In addition, the leakage current between the conductor 114 and the conductor 108a or the conductor 108b is also reduced. It is possible to do so.

[0185] Also, if the thickness of the region 108c and the region 108d is too thin, they will not function sufficiently as insulators. If the thickness is too large, the area of ​​the conductors 108a and 108b may be small. As a result, the electrical resistance of the conductors 108a and 108b increases. Therefore, the thickness of the region 108c and the region 108d is preferably 0.2 nm or more and 20 nm or less. It is nice.

[0186] Regions 108c and 108d may form naturally upon exposure to air. It can also be formed intentionally. For example, For example, the heat treatment may be performed in an oxidizing atmosphere. Alternatively, the plasma treatment may be performed in an atmosphere containing oxygen. The plasma processing may be performed using a high-density plasma processing apparatus using a power source with a frequency of, for example, 2.45 GHz. It is preferable to use Zuma treatment. In addition, oxygen is added to the semiconductor 106b at that time. The oxygen deficiency in the semiconductor 106b may be compensated for by the above.

[0187] The transistor 16 shown in FIG. 8A and FIG. 8B includes a conductor 102, an insulator 101, This transistor differs from the transistor 10 in that the insulator 105 is not formed.

[0188] The transistor 18 shown in FIG. 8C and FIG. 8D has a conductor 114 and an insulator 112. , openings formed in the insulator 106c, the insulator 104, the insulator 103, the insulator 105, etc. The transistor 10 differs from the transistor 10 in that the transistor 10 is connected to the conductor 102 via a

[0189] In the transistor 20 shown in FIG. 9(A) and FIG. 9(B), the insulator 107 is disposed on the insulator 101. The conductor 102 is embedded in an opening in the insulator 107. The transistor 10 differs from the transistor 10 in that the insulator 107 is In addition, the insulator 107 and the conductor 10 The upper surface of the substrate 2 is preferably subjected to a planarization process such as a CMP process to improve the planarization. As a result, even if the conductor 102 functioning as a back gate is provided, the semiconductor 106b Since the flatness of the surface on which the transistor is formed is not compromised, the mobility of carriers is improved and the transistor In addition, the on-current of the insulator 20 due to the shape of the conductor 102 can be increased. By eliminating the step on the surface of 104, the drain of the conductor 108a or conductor 108b can be The electric field is generated between the conductor 102 and the insulator 104 through the step portion of the insulator 104. This can reduce the leakage current of the transistor 20. It is possible.

[0190] The transistor 22 shown in FIG. 10A and FIG. 10B includes a conductor 108a, a conductor 1 An insulator 117 is provided on the semiconductor 106 and the insulator 104. An opening is provided that reaches b. The opening is provided with an insulator 106c, an insulator 112, and a conductive It differs from transistor 10 in that body 114 is embedded. In addition, the opening separates the conductor 108a and the conductor 108b. The transistor 22 has a conductor 114 that can function as a gate electrode. The opening in the edge 117 is filled in a self-aligning manner. Therefore, TGSA s-channel FET (Trench Gate S It can also be called elf Align s-channel FET.

[0191] Here, the insulator 117 may be formed using an insulator that can be used for the insulator 104. The upper surface of the insulator 117 may be planarized by a CMP method or the like.

[0192] In the transistor 22, an insulator 117 is provided between the conductor 108a and the conductor 114, and an insulator 10 6c and an insulator 112 are provided. In addition, an insulator is provided between the conductor 108b and the conductor 114. The conductor 117, the insulator 106c, and the insulator 112 are provided. The distance between the upper surface of the conductor 108b and the lower surface of the conductor 114, and the distance between the upper surface of the conductor 108b and the lower surface of the conductor 114 The distance between the surfaces can be increased by the thickness of the insulator 117. In order to reduce the parasitic capacitance generated in the region where the conductor 114 overlaps with the conductor 108a and the conductor 108b, By reducing the parasitic capacitance, the switching speed of the transistor can be increased. Therefore, it is possible to provide a transistor having high frequency characteristics. do.

[0193] The transistor 24 shown in FIG. 10C and FIG. 10D has an insulator 117 and an insulator 10. 6c, the upper surfaces of the insulator 112 and the conductor 114 are roughly flush with each other and are provided flat. In order to form the transistor in this manner, the insulator 117, The top surfaces of the insulator 106c, the insulator 112, and the conductor 114 are planarized by a CMP method or the like. Just do that.

[0194] By adopting such a structure, the conductor 114, the conductor 108a, and the conductor 108b Since the overlapping area is almost completely eliminated, the gate-source and The parasitic capacitance between the gate and drain can be reduced. This allows the transistor switching speed to be increased, making it possible to It is possible to provide a transistor having several characteristics.

[0195] In the transistor 29 shown in FIG. 11(A) and FIG. 11(B), the insulator 107 is an insulator 10 1, and the conductor 102 is embedded in the opening in the insulator 107. In addition, the insulator 106c is different from the transistor 24 in that the insulator 106a and the semiconductor The transistor 29 is also different from the transistor 24 in that the conductor 106b is covered. The insulator 106c is not provided on the side of the opening of the insulator 117. The length of the conductor 114 in the channel length direction at the mouth is set to be longer than that of the transistor 24, etc. It is possible.

[0196] In the transistor 29, the conductor 108a has a surface containing silicon and oxygen. The conductor 108b has a region 108c, and the conductor 108b has a region 108c having silicon and oxygen on its surface. The transistor 24 also differs from the transistor 24 in that the region 108c and the region 108d are It may be formed in the same manner as the transistor 12 shown in FIG.

[0197] However, in the case of the transistor 12 and the transistor 29, the region 108c and the region 108d are For example, the present invention is not limited to the case where another transistor is connected between the region 108c and the region 108d. It is okay to have it.

[0198] The transistor 26 shown in FIG. 12A and FIG. 12B includes a conductor 108a and a conductor The side ends of the conductor 114 and the insulator 112 are not provided. It differs from transistor 10 in that it is provided approximately in the same manner.

[0199] In the transistor 26, the low resistance region 109a and the low resistance region 109b are formed by insulating material 1. At least one of the elements contained in 16 may be included. Various elements may be added to the low resistance region 109b to reduce the electrical resistance. stomach.

[0200] The element added to the low resistance region 109a and the low resistance region 109b is, for example, boron. Argon, phosphorus, nitrogen, argon, helium, magnesium, aluminum, silicon, titanium , vanadium, chromium, nickel, cobalt, germanium, yttrium, zirconium Niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium For example, the low resistance region 109a and the low The above elements are present in the resistance region 109b at 1×10 14 / cm 2 More than 2×10 16 / cm 2 Included below In addition, it is preferable that the low resistance region 109a and the low resistance region 109b in the insulator 106c are The low resistance region 109b is the low resistance region 109a of the insulator 106c and the low resistance region 109b of the insulator 106c. The concentration of the above elements is higher in the non-insulating region (for example, the region where the insulator 106c overlaps with the conductor 114). High degree.

[0201] In the transistor 26, the semiconductor 106b is connected to the insulator 106a and the insulator 106c. Therefore, the side end of the semiconductor 106b, particularly the The vicinity of the side end in the channel width direction is provided in contact with the insulator 106a and the insulator 106c. As a result, the insulator 106a or the insulator 106b is in contact with the semiconductor 106b near the side end of the semiconductor 106b. A continuous junction is formed between the substrate 106c and the low-resistance region 106, and the defect density is reduced. Even if the on-current becomes easy to flow by providing the low-resistance region 109a and the low-resistance region 109b, In this case, the side edge of the semiconductor 106b in the channel width direction does not become a parasitic channel, and stable electrical characteristics are obtained. In addition, in a configuration without the insulator 106a and / or the insulator 106c, It is also possible to use the following.

[0202] The transistor 28 shown in FIG. 12C and FIG. 12D is made of an insulator 112 and a conductor The transistor 10 is different from the transistor 10 in that the transistor 114 is not provided. The transistor 28 is a so-called bottom gate type transistor.

[0203] In this embodiment, a gate electrode, a source electrode, a drain electrode, etc. of a transistor tungsten and silicon, carbon, germanium, tin, aluminum or nickel The present invention relates to a structure using a conductor having a region having one or more elements selected from the group consisting of fluorine, ...-containing fluorine, and fluorine-containing fluorine. However, the present invention is not limited to this. For example, MIM (Metal-Insulator-Metal l) The electrodes of the capacitance elements such as tungsten, silicon, carbon, germanium, and one or more elements selected from tin, aluminum, or nickel. A conductor may be used. In this case, a region having silicon and oxygen on the surface of the conductor may be formed. and a structure in which the region capable of functioning as an insulator is used as a dielectric for a capacitive element. It is also possible to use the following.

[0204] According to this embodiment, a transistor using a conductor having heat resistance and oxidation resistance is provided. It is possible.

[0205] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0206] (Embodiment 2) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 19 will be used to explain.

[0207] <Transistor manufacturing method 1> A method for manufacturing the transistor 10 will be described below with reference to FIGS.

[0208] First, a substrate 100 is prepared. The substrate 100 may be any of the above-mentioned substrates. good.

[0209] Next, the insulator 101 is formed. As the insulator 101, any of the above insulators may be used.

[0210] The insulator 101 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Vapor Deposition method, Molecular Beam Epitaxy (MBE) Laser Beam Epitaxy (PLD) or Pulsed Laser Deposition (PLD) Laser Deposition) method, Atomic Layer Deposition (ALD) method This can be done using a deposition method or the like.

[0211] Next, a film of a conductor that will become the conductor 102 is formed. The conductive film can be formed by sputtering, CVD, MBE, etc. The method can be carried out by using a PLD method, an ALD method, or the like.

[0212] Next, a resist or the like is formed on the conductor, and the conductor 102 is processed using the resist or the like. (See FIG. 13(A) and FIG. 13(B)). Note that a resist is simply formed. This also includes the case where an anti-reflection layer is formed under the resist.

[0213] The resist is removed after the object is processed by etching or other methods. In this case, plasma treatment and / or wet etching are used. Plasma ashing is suitable for this purpose. If removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% to 1% by volume Any remaining resist may be removed using water or the like.

[0214] Next, the insulator 105 is formed. The insulator 105 may be any of the above-mentioned insulators. The insulating film 105 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 105 can be reduced. For example, the substrate may be heated during deposition in order to form a thin film below the transistor 10. In the case where a semiconductor element layer is provided, a relatively low temperature range (for example, 350° C. to 445° C.) is used. Heating may be performed at a temperature range of about 100°C or less.

[0215] In addition, the insulator 104 is formed by PECVD in the same manner as the insulator 104 described later. The water or hydrogen contained in the insulator 105 may be reduced.

[0216] Next, the insulator 103 is formed. The insulator 103 may be any of the above-mentioned insulators. The insulating film 103 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, water or hydrogen contained in the insulator 103 can be reduced. For example, the substrate may be heated during deposition in order to form a thin film below the transistor 10. In the case where a semiconductor element layer is provided, a relatively low temperature range (for example, 350° C. to 445° C.) is used. Heating may be performed at a temperature range of about 100°C or less.

[0217] The CVD method is a method that uses plasma, called plasma enhanced CVD (PECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method D) method, photo CVD method, etc. Depending on the source gas, metal CVD (MCVD) method, metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0218] The PECVD method can obtain high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. The accumulated electric charge may destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of the TCVD method, which does not use plasma, such plasma damage does not occur. Therefore, the yield of semiconductor devices can be increased. Since no plasma damage occurs, a film with few defects can be obtained.

[0219] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0220] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. This is suitable for coating the surface of a high opening. However, the ALD method has a relatively slow deposition rate, so the deposition rate is In some cases, it may be preferable to use it in combination with other deposition methods such as a high-speed CVD method. .

[0221] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0222] In conventional deposition equipment using the CVD method, one or more source gases for the reaction are used for deposition. Several types of materials are supplied to the chamber at the same time. The gas that acts as a reactant (also called reactant) and the precursor gas are mixed together. The gases are introduced alternately into the chamber, and the introduction of these gases is repeated to form a film. To switch the input gas, for example, use the switching valves (also called high-speed valves) It can be switched around.

[0223] For example, the film is formed in the following procedure. First, a precursor is introduced into a chamber and then the substrate is The precursor is adsorbed onto the surface (first step). Here, the precursor is adsorbed onto the substrate surface. By this, a self-limiting mechanism of the surface chemical reaction takes effect, and the precursor layer on the substrate is formed. Furthermore, the precursor does not adsorb. The self-limiting mechanism of the surface chemical reaction works. The appropriate range of substrate temperature is also called the ALD window. It is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the laser. Next, inert gas (argon, or nitrogen) into the chamber, and excess precursors and reaction products are removed from the chamber. In addition, instead of introducing an inert gas, the gas is evacuated. Therefore, excess precursors and reaction products may be discharged from the chamber. An actant (e.g., an oxidizing agent (H2O, O3, etc.)) is introduced into the chamber and adsorbed onto the substrate surface. The film is reacted with the precursor adsorbed on the substrate, and part of the precursor is removed while the film constituent molecules are adsorbed on the substrate. (3rd step) Next, the excess is removed by introducing an inert gas or evacuating. Reactants and reaction products are discharged from the chamber (fourth step).

[0224] In addition, the introduction of reactant in the third step and the introduction of inert gas in the fourth step The introduction may be repeated several times. That is, after the first and second steps, the third step may be performed. Step, fourth step, third step, fourth step, third step and fourth step... The loop may be repeated.

[0225] For example, in the third step, O3 is introduced as an oxidant, and in the fourth step, N2 is purged. This process may be repeated multiple times.

[0226] In addition, when the third and fourth steps are repeated, the same type of reactant is not necessarily used. There is no need to repeat the introduction. For example, if H2O is used as the oxidizing agent in the first third step, In the third step from the second time onwards, O3 may be used as the oxidizing agent.

[0227] In this way, the introduction of the oxidizer and the introduction of the inert gas (or evacuation) in the chamber are performed. By repeating this process multiple times in a short period of time, excess hydrogen atoms and other impurities are removed from the precursor adsorbed on the substrate surface. The oxidizer can be removed more reliably and expelled from the chamber. By increasing the number of types to two, excess hydrogen atoms and other In this way, hydrogen atoms are not incorporated into the film during film formation. By doing so, it is possible to reduce the amount of water, hydrogen, etc. contained in the formed insulator 103. This can be done.

[0228] In this manner, a first monolayer can be formed on the substrate surface, and the first to fourth steps By repeating the above steps, a second monolayer can be laminated on the first monolayer. The fourth step is repeated multiple times while controlling the gas introduction until the film reaches the desired thickness. The thickness of the thin film increases depending on the number of times the process is repeated. This allows precise film thickness control, making it possible to fabricate fine transistors. This is suitable for manufacturing.

[0229] The ALD method is a film formation method in which precursors are reacted using thermal energy. In the reaction of the reactants, the reactants are converted into radicals using plasma. The ALD method in which the process is performed using a plasma is sometimes called the plasma ALD method. The ALD method in which the reaction of the catalyst and reactant is carried out using thermal energy is called the thermal ALD method. There is.

[0230] The ALD method can deposit extremely thin films with uniform thickness. The surface coverage is also high.

[0231] In addition, by forming the film using the plasma ALD method, the film can be formed at an even lower temperature than with the thermal ALD method. The plasma ALD method can achieve this without reducing the film formation rate even at temperatures below 100 degrees. In addition, the plasma ALD method uses not only oxidizing agents but also nitrogen gas and other gases. Many reactants can be used, including not only oxides but also nitrides, fluorides, Many types of films, including metal films, can be deposited.

[0232] In addition, when performing plasma ALD, ICP (Inductively Coupled Plasma) It is also possible to generate plasma away from the substrate, such as by using a laser-assisted plasma. By generating plasma in this way, it is possible to suppress plasma damage. Cut.

[0233] Here, as an example of an apparatus capable of forming a film by the ALD method, a film forming apparatus 1000 The configuration will be described with reference to FIG. 16(A) and FIG. 16(B). FIG. 16(A) shows a FIG. 16(B) is a schematic diagram of a multi-chamber type film forming apparatus 1000. FIG. 1 is a cross-sectional view of an ALD apparatus that can be used for

[0234] <Example of film formation equipment configuration> The film forming apparatus 1000 includes a carry-in chamber 1002, a carry-out chamber 1004, a transfer chamber 1006, and a film forming chamber. 1008, a film forming chamber 1009, a film forming chamber 1010, and a transfer arm 1014. Here, the loading chamber 1002, the unloading chamber 1004, and the film forming chambers 1008 to 1010 are a transfer chamber 10 06. This allows the deposition chambers 1008 to 1010 to be exposed to the atmosphere. This allows continuous film formation without the need for a separate process, and prevents impurities from being mixed into the film.

[0235] In addition, the loading chamber 1002, the unloading chamber 1004, the transfer chamber 1006, the film forming chambers 1008 to 1010 In order to prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferably left as it is, and it is desirable to maintain reduced pressure.

[0236] In addition, an ALD apparatus can be used for the film formation chambers 1008 to 1010. Also, a configuration may be adopted in which a film formation apparatus other than the ALD apparatus is used in any one of the film formation chambers 1008 to 1010. The film formation apparatus used for the film formation chambers 1008 to 1010 includes, for example, a sputtering apparatus, a PECVD apparatus, a TCVD apparatus, a MOCVD apparatus, and the like.

[0237] For example, by providing an ALD apparatus and a PECVD apparatus in the film formation chambers 1008 to 1010, the insulator 105 made of silicon oxide of the transistor 10 shown in FIGS. 1(B) and 1(C) can be formed by PECVD, the insulator 103 made of hafnium oxide can be formed by ALD, and the insulator 104 made of silicon oxide containing halogen can be formed by PECVD. Since a series of film formations are continuously performed without exposing the film to the atmosphere, film formation can be performed without impurities being mixed into the film.

[0238] In addition, although the film formation apparatus 1000 has a configuration including a loading chamber 1002, an unloading chamber 1004, and film formation chambers 1008 to 1010, the present invention is not limited thereto. The film formation chambers of the film formation apparatus 1000 may be configured to have four or more, or a processing chamber for performing heat treatment or plasma treatment may be added. Also, the film formation apparatus 1000 may be a single-wafer type, or may be a batch type for forming films on a plurality of substrates at once.

[0239] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used for the film formation apparatus 1000 will be described. AL The D device includes a film forming chamber (chamber 1020), raw material supply units 1021a and 1021b, and a flow The high-speed valves 1022a and 1022b are quantity controllers, and the raw material inlets 1023a and 1023 b, a raw material outlet 1024, and an exhaust device 1025. The raw material inlets 1023a and 1023b are connected to the raw material supply unit 1021 via supply pipes and valves. The raw material discharge port 1024 is connected to discharge pipes, valves, and pressure It is connected to an exhaust device 1025 via a power regulator.

[0240] In addition, as shown in FIG. 16(B), a plasma generating device 1028 is connected to the chamber 1020. This allows deposition to be performed by plasma ALD in addition to thermal ALD. In the plasma ALD method, deposition can be performed at low temperatures without decreasing the deposition rate, so deposition efficiency is low. It is suitable for use in a single-wafer deposition apparatus.

[0241] Inside the chamber is a substrate holder 1026 equipped with a heater. A substrate 1030 on which a film is to be formed is placed.

[0242] In the raw material supply units 1021a and 1021b, solid raw materials and liquid raw materials are supplied by vaporizers and heating means. The raw material supply units 1021a and 1021b generate raw material gas from the raw material. The source gas may be supplied in the above-mentioned manner.

[0243] In addition, although an example in which two raw material supply units 1021a and 1021b are provided is shown, this is not particularly limited. In addition, the high-speed valves 1022a and 1022b can be precisely controlled by the time. The gas supply system can be controlled to supply either the raw gas or the inert gas. The high-speed valves 1022a and 1022b are flow rate controllers for the source gas and inert gas. It can also be said to be a flow rate controller.

[0244] In the film forming apparatus shown in FIG. 16(B), a substrate 1030 is placed on a substrate holder 1026. After the member 1020 is sealed, the substrate 103 is heated by the heater of the substrate holder 1026. 0 is set to a desired temperature (for example, 80°C or higher, 100°C or higher, or 150°C or higher), and the raw material gas is The exhaust device 1025 supplies an inert gas and exhausts the gas. By repeating this process and exhausting the gas, a thin film is formed on the surface of the substrate.

[0245] In the film forming apparatus shown in FIG. 16(B), the raw materials (volatile By appropriately selecting the appropriate fluorine-containing compound (e.g., volatile organometallic compounds), hafnium, aluminum, tungsten, etc. Oxides (including composite oxides) containing one or more elements selected from the group consisting of tungsten, zirconium, etc. Specifically, an insulating layer containing hafnium oxide can be formed. an insulating layer including aluminum oxide; An insulating layer comprising an insulating material such as alumina or aluminium silicate. In addition, the raw materials ( By appropriately selecting the appropriate material (volatile organic metal compounds, etc.), a tungsten layer, titanium layer, etc. It is also possible to deposit thin films such as metal layers and nitride layers such as titanium nitride layers.

[0246] For example, when forming a hafnium oxide layer using an ALD apparatus, a solvent and a hafnium precursor are Liquids containing hafnium compounds (such as hafnium alkoxides and tetrakisdimethylamido hafnium The raw material gas is vaporized hafnium amide (TDMAH) and ozone is used as an oxidizer. In this case, two types of gases, 1) O2 and 2) O3, are used. The raw material gas is TDMAH, and the second raw material gas supplied from the raw material supply unit 1021b is ozone. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2 ]4. Another material liquid is tetrakis(ethylmethylamido)hafnium etc.

[0247] When forming an aluminum oxide layer using an ALD system, a solvent and an aluminum precursor are used. The raw gas is made by vaporizing a liquid containing a compound (such as TMA: trimethylaluminum) and an oxidizing agent. In this case, two types of gases are used: The first source gas is TMA, and the second source gas supplied from the source supply unit 1021b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include:

[0248] When forming a tungsten layer using an ALD system, WF6 gas and B2H6 gas are used. is introduced repeatedly in sequence to form an initial tungsten layer, and then WF6 gas and H2 gas are introduced. The tungsten layer is formed using the B2H6 gas. These gases may be controlled by a mass flow controller. .

[0249] Next, the insulator 104 is formed (see FIG. 13(C) and FIG. 13(D)). The insulator 104 may be formed by a sputtering method, a CV method, or the like. This can be carried out by using a deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0250] The insulator 104 is preferably formed by a CVD method, and more preferably by a PECVD method. It is preferable to carry out the above steps.

[0251] When the insulator 104 is formed by the PECVD method, the source gas is preferably a gas that does not contain hydrogen or It is preferable to use a substance with a low hydrogen content, for example, a halide. For example, a silicon oxide or silicon oxynitride film is formed as the insulator 104. In this case, it is preferable to use a silicon halide as the source gas, for example, SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 (silicon trichloride) ), SiH2Cl2 (dichlorosilane) or SiBr4 (silicon tetrabromide) It is possible.

[0252] When forming the insulator 104 by the PECVD method, an oxidizing gas (such as N2O) is introduced. The silicon halide is less reactive than SiH4, so it is oxidizing. The gas easily acts on the insulator 103. As a result, the water or water contained in the insulator 103 The hydrogen is desorbed by the oxidizing gas, and the amount of water and hydrogen contained in the insulator 103 is reduced. It is possible that this is possible.

[0253] In addition, when silicon halide is used as a source gas for forming the insulator 104, the halogen In addition to silicon hydride, silicon hydride may be added. The hydrogen and water content in the insulator 104 is reduced compared to when only hydrogen is used as the raw material gas. The film formation rate can be improved compared to when only silicon fluoride is used as the source gas. For example, The insulator 104 may be formed using SiF4 and SiH4 as raw material gases. The flow rate of H4 is set to be greater than 1 sccm and less than 10 sccm, and more preferably, to be greater than or equal to 2 sccm. By setting the flow rate at 4 sccm or less, both the water and hydrogen content in the insulator 104 and the deposition rate can be reduced. However, the ratio of the flow rates of SiF4 and SiH4 is This can be appropriately set in consideration of the water and hydrogen contents in the insulating body 104 and the film formation rate.

[0254] In addition, in order to reduce the amount of water or hydrogen contained in the insulator 104, the substrate is heated while being grown. It is preferable to carry out a membrane.

[0255] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later is highly flat. Therefore, a planarization process such as a CMP process is performed on the top surface of the insulator 104 to improve the planarization. This is also fine.

[0256] Next, it is preferable to perform heat treatment. By performing heat treatment, the insulator 105 and the insulator 1 The amount of water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, the insulating layer 104 can have excess oxygen. 650°C or less, preferably 450°C to 600°C, more preferably 520°C to 5 Heat treatment should be performed at 70℃ or less. Heat treatment should be performed in an inert gas atmosphere or in an oxidizing gas atmosphere of 10ppm. m or more, 1% or more, or 10% or more. Heat treatment can be performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by heating to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed to increase the crystallinity of the insulator 126a and the semiconductor 126b. The heating process can be performed by using lamp heating. It is also possible to use an RTA (Rapid Thermal Annealing) device Heat treatment with an RTA device takes less time than with a furnace, so it is ideal for increasing productivity. It is effective for this purpose.

[0257] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range For example, the temperature range is about 350°C to 445°C. For example, any one of the substrate heating temperatures during deposition of the insulators 105, 103, and 104. It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0258] Next, the insulator 126a is formed. The insulator 126a may be formed using an insulator or a semiconductor that can be used. This is done using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be done.

[0259] Next, the semiconductor 126b is formed. The semiconductor 126b may be formed by a sputtering method. The deposition can be performed by using a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 126a and the semiconductor 126b are successively formed without exposure to the atmosphere. This can reduce the amount of impurities entering the film and at the interface.

[0260] Next, it is preferable to perform heat treatment. By performing heat treatment, the insulator 126a and the semiconductor In some cases, the hydrogen concentration in the insulators 126a and 176b can be reduced. The oxygen vacancies in the semiconductor 126b may be reduced. 450°C or more and 600°C or less, more preferably 520°C or more. The heat treatment is carried out at a temperature of 570°C or less. ppm or more, 1% or more, or 10% or more. Heat treatment is performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by removing the desorbed oxygen. To compensate for this, heat treatment is performed in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The crystallinity of the insulator 126a and the semiconductor 126b can be improved by heat treatment. The heat treatment can be used to increase the temperature and remove impurities such as hydrogen and water. An RTA device can also be used. Heating with an RTA device is much faster than with a furnace. This is effective in increasing productivity since it takes a short time. When CAAC-OS is used as 6b, the peak intensity increases by heat treatment. In other words, the crystallinity of the CAAC-OS is increased by the heat treatment.

[0261] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range For example, the temperature range is about 350°C to 445°C. For example, the substrate heating temperature during deposition of the insulators 105, 103 and 104, or the insulating The temperature of the heat treatment after the deposition of the insulating layer 104 must be equal to or lower than the highest heating temperature of either of the above. By forming the insulator 104 by the above-described method, the water in the insulator 104, Since hydrogen and the like have been sufficiently removed, the insulator 126a and the semiconductor 126b are not wetted with water or water. Therefore, the amount of the supplied element can be sufficiently reduced.

[0262] The heat treatment causes oxygen to be transferred from the insulator 104 to the insulator 126a and the semiconductor 126b. By subjecting the insulator 104 to a heat treatment, Oxygen can be provided to the insulator 126a and the semiconductor 126b.

[0263] Here, the insulator 103 functions as a barrier film that blocks oxygen. By providing the insulating material 104 under the insulating material 104, oxygen diffused into the insulating material 104 is prevented from It is possible to prevent the diffusion of the fluorine-containing gas into layers below 104.

[0264] In this way, oxygen is supplied to the insulator 126a and the semiconductor 126b, and oxygen vacancies are reduced. As a result, a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor having a low density of defect states can be obtained. It can be said that:

[0265] In addition, a high-density plasma treatment may be performed. High-density plasma is generated by using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide is generated. Alternatively, a mixture of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe can be used. A combined gas may be used. In the high density plasma treatment, a bias may be applied to the substrate. This allows oxygen ions in the plasma to be drawn to the substrate. The plasma treatment may be performed while heating the substrate. When performing plasma treatment, the same effect can be obtained at a temperature lower than that of the above heat treatment. The high-density plasma treatment may be performed before the formation of the insulator 126a, or after the formation of the insulator 126b described later. The deposition may be performed before the deposition of the insulating layer 26a, after the deposition of the insulating layer 112, or after the deposition of the insulating layer 11 This may be performed after the deposition of the film 6.

[0266] Next, a conductor 128 is formed (see FIG. 13(E) and FIG. 13(F)). 8 is a conductor that can be used as the above-mentioned conductor 108a and conductor 108b. The conductor 128 can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out using a PLD method, an ALD method, or the like.

[0267] Next, a resist or the like is formed on the conductor 128, and the conductor is processed using the resist or the like. 108a and the conductor 108b are formed.

[0268] Next, a resist or the like is formed on the semiconductor 126b, and the conductor 108a and the The insulating layer 106a and the semiconductor layer 106b are formed by processing the insulating layer 106a and the semiconductor layer 106b (FIG. See Figures 13(G) and 13(H).

[0269] In addition, in the region of the semiconductor 106b that contacts the conductor 108a and the conductor 108b, In this case, low resistance regions 109a and 109b may be formed. Conductor 106b is connected between conductor 108a and conductor 108b. The conductive material 108a may have a region with a smaller thickness than the region overlapping with the conductive material 108b. In addition, when forming the conductor 108b, a part of the upper surface of the semiconductor 106b is removed. is formed.

[0270] After the conductor 128 is formed, the insulator 126a, the semiconductor 126b, and the conductor 128 are The insulator 106a, the semiconductor 106b, and the semiconductor 106b are overlapped with each other. The conductor having a shape overlapping the semiconductor 106b is further processed to form a conductor 108a and conductor 108b may be formed.

[0271] Next, the insulator 126c is formed. The insulator 126c may be formed using an insulator or a semiconductor that can be used. This is done using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Before the formation of the insulator 126c, the semiconductor 106b, the conductor 108a, and the conductor The surface of 108b may be etched. For example, the surface may be etched using plasma containing a rare gas. After that, the insulator 126c is formed continuously without being exposed to the atmosphere. By this, the semiconductor 106b, the conductors 108a and 108b, and the insulator 1 06c and can reduce the inclusion of impurities at the interface between films. Impurities that are introduced into the film may be more diffusible than impurities in the film. By reducing the amount of ZnO, the transistor can have stable electrical characteristics.

[0272] Next, the insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. The insulator 132 can be formed by a sputtering method, a CVD method, or the like. The deposition can be performed by using a deposition method such as a deposition method, an MBE method, a PLD method, or an ALD method. The deposition of the insulating film 26c and the deposition of the insulating film 132 are performed successively without exposure to the atmosphere. The incorporation of impurities into the film and at the interface can be reduced.

[0273] Next, a conductor 134 is formed (see FIG. 14(A) and FIG. 14(B)). The conductive material 4 may be any conductive material that can be used as the conductive material 114 described above. The film 134 may be formed by a method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The deposition of the insulator 132 and the deposition of the conductor 134 can be performed using a By performing the process continuously without exposing the film to the atmosphere, the incorporation of impurities into the film and at the interface is reduced. It is possible.

[0274] Next, a resist or the like is formed on the conductor 134, and the conductor is processed using the resist or the like. Form 114.

[0275] Next, a resist or the like is formed on the conductor 114 and the insulator 132, and the resist or the like is used to 14C and 14D, and the insulating body 106c and the insulating body 112 are formed. (D). At this time, the conductors 120a and 120b to be formed later The insulator 106c and the conductor 108b are removed so as to expose the areas in contact with the conductor 108a and the conductor 108b. In addition, an insulator 112 may be formed.

[0276] Next, the insulator 116 is deposited (see FIG. 14(E) and FIG. 14(F)). The insulator 116 may be formed by sputtering, C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0277] Here, the insulator 116 is made of a material such as aluminum oxide that blocks oxygen, hydrogen, water, etc. It is preferable to provide an oxide insulating film having such an effect.

[0278] The insulator 116 is preferably formed by plasma deposition, for example, by sputtering. It is more preferable to carry out the process by sputtering in an oxygen-containing atmosphere. is more preferred.

[0279] The sputtering method uses a direct current (DC) power supply for the sputtering power source. current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering method, which uses a high-frequency power source for sputtering A sputtering method may also be used. In addition, a magnetron having a magnet mechanism inside the chamber may be used. Sputtering method, bias sputtering method in which a voltage is applied to the substrate during film formation, reactive gas Alternatively, a reactive sputtering method in a gas atmosphere may be used. The flow rate of the raw gas and the deposition power may be appropriately determined depending on the amount of oxygen added, etc.

[0280] By forming the insulator 116 by a sputtering method, the insulator 10 4 or the surface of the insulator 112 (after the insulator 116 is formed, it is insulator 104 or insulator 112 Oxygen is added to the vicinity of the interface of the insulator 116. Here, the oxygen is, for example, oxygen radicals. When oxygen is added to the insulator 104 or 112, the state of the oxygen is The oxygen may be in the form of an oxygen atom or an oxygen ion, etc. The addition of oxygen may be added to the insulator 104 or the insulator 112. In some cases, the oxygen content in the insulating layer 112 exceeds the stoichiometric composition. It can also be called excess oxygen.

[0281] Next, it is preferable to carry out a heat treatment (see FIG. 15(A) and FIG. 15(B)). By carrying out the treatment, the oxygen added to the insulator 104 or the insulator 112 is diffused, and the insulating The heat treatment can be applied to the body 106a, the semiconductor 106b, and the insulator 106c. The heat treatment may be performed at a temperature of 50° C. to 650° C., preferably 350° C. to 450° C. Inert gas atmosphere or oxidizing gas is 10ppm or more, 1% or more, or 10% or more The heat treatment is carried out in an atmosphere containing the above. The heat treatment may be carried out under reduced pressure. The heat treatment is carried out by lamp heating. An RTA device that can measure the temperature can also be used.

[0282] The heat treatment is preferably performed at a temperature lower than that of the heat treatment performed after the formation of the semiconductor 126b. The temperature difference between the heat treatment after the formation of the conductor 126b is 20° C. or more and 150° C. or less, preferably 40° C. or less. The temperature is set to 100° C. or higher. This allows excess oxygen (oxygen) to escape from the insulator 104, etc. The heat treatment after the formation of the insulator 118 can be performed in the same manner as the heat treatment after the formation of the insulator 118. In the case where the heat treatment can be performed by heating each layer during film formation (for example, the heat treatment for the insulator 118), In some cases, this may not be necessary (if equivalent heating is performed during film formation).

[0283] By the heat treatment, the insulator 116 is formed, and the insulators 104 and 112 are The oxygen added to the insulator 104 or the insulator 112 (hereinafter referred to as oxygen 186) is (See FIG. 15(A) and FIG. 15(B)). The insulator 116 is or an insulator that is less permeable to oxygen than the insulator 112 and serves as a barrier film that blocks oxygen. Such an insulator 116 is formed on the insulator 104 or the insulator 112. Therefore, oxygen 186 diffusing through insulator 104 or insulator 112 is absorbed by insulator 104. Alternatively, the insulating layer 104 or the insulating layer 112 may not diffuse upward, but may extend mainly laterally through the insulating layer 104 or the insulating layer 112. or downwards.

[0284] Oxygen 186 diffusing through the insulator 104 or the insulator 112 flows through the insulator as shown by the arrows. 106a, the insulator 106c, and the semiconductor 106b. The insulating body 103 having a function of blocking the heat is provided under the insulating body 104. Therefore, the oxygen 186 diffused in the insulator 104 can be prevented from diffusing below the insulator 104. Cut.

[0285] In this manner, the insulator 106a, the insulator 106c and the semiconductor 106b, particularly the semiconductor 106b, Oxygen 186 can be effectively supplied to the region where the channel is formed in 06b. In this way, oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen vacancies are eliminated. By reducing the amount of the impurity, a high-purity intrinsic or substantially high-purity intrinsic semiconductor having a low density of defect states can be obtained. An oxide semiconductor can be used.

[0286] Note that the heat treatment after the formation of the insulator 116 may be performed at any time after the formation of the insulator 116. For example, this may be done after the formation of the insulator 118 or after the formation of the conductors 120a and 120b. You can go later.

[0287] Next, the insulator 118 is formed. The insulator 118 may be any of the above-described insulators. The insulating layer 118 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using, for example.

[0288] Next, a resist or the like is formed on the insulator 118, and the insulators 118, 116, and 117 are laminated. An opening is then formed in the conductor 120a and the insulator 106c. The conductors that will become the conductors 120a and 120b are formed. The conductive material can be formed by a sputtering method, a CVD method, or the like. The deposition can be performed by using a deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0289] Next, a resist or the like is formed on the conductor, and the conductor 120 is processed using the resist or the like. a and conductor 120b are formed (see FIG. 15(C) and FIG. 15(D)).

[0290] Through the above steps, the transistor 10 according to one embodiment of the present invention can be manufactured.

[0291] <Transistor manufacturing method 2> A method for manufacturing the transistor 29 will be described below with reference to FIGS. Regarding the method for manufacturing the transistor 29, the above-mentioned transistor manufacturing method may be referred to as appropriate. It is possible.

[0292] First, a substrate 100 is prepared. The substrate 100 may be any of the above-mentioned substrates. good.

[0293] Next, the insulator 101 is formed. As the insulator 101, any of the above insulators may be used.

[0294] Next, an insulator that will become the insulator 107 is formed. The insulator may be any of the above-mentioned insulators. The insulator film is formed by sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0295] Next, a resist or the like is formed on the insulator, and the resist or the like is used to process the insulator to form a The insulating material 107 is formed.

[0296] Next, a film of a conductor that will become the conductor 102 is formed. The conductive film can be formed by sputtering, CVD, MBE, etc. The method can be carried out by using a PLD method, an ALD method, or the like.

[0297] Next, the conductor is polished until the insulator 107 is exposed, forming the conductor 102 (FIG. 17( See FIG. 17(A) and FIG. 17(B). The polishing can be performed by a CMP process or the like.

[0298] Next, the insulator 105 is formed. The insulator 105 may be any of the above-mentioned insulators. The insulating film 105 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 105 can be reduced. For example, the substrate may be heated during deposition in order to form a thin film below the transistor 29. In the case where a semiconductor element layer is provided, a relatively low temperature range (for example, 350° C. to 445° C.) is used. Heating may be performed at a temperature range of about 100°C or less.

[0299] In addition, by forming a film by the PECVD method using the same method as the insulator 104 described above, The water or hydrogen contained in the insulator 103 may be reduced.

[0300] Next, the insulator 103 is formed. The insulator 103 may be any of the above-mentioned insulators. The insulating film 103 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, water or hydrogen contained in the insulator 103 can be reduced. For example, the substrate may be heated during deposition in order to form a thin film below the transistor 10. In the case where a semiconductor element layer is provided, a relatively low temperature range (for example, 350° C. to 445° C.) is used. Heating may be performed at a temperature range of about 100°C or less.

[0301] Next, the insulator 104 is formed (see FIG. 17(C) and FIG. 17(D)). The insulator 104 may be formed by sputtering, C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0302] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later is highly flat. Therefore, a planarization process such as a CMP process is performed on the top surface of the insulator 104 to improve the planarization. This is also fine.

[0303] Next, a heat treatment is preferably carried out.

[0304] Next, an insulator that will become the insulator 106a is formed. The insulating film may be formed by a method such as a spatula. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0305] Next, a semiconductor film that will become the semiconductor 106b is formed. The semiconductor film can be formed by sputtering, C This can be done using the VD method, MBE method, PLD method, ALD method, etc. By depositing the body film and the semiconductor film in succession without exposing them to the atmosphere, The incorporation of impurities into the interface can be reduced.

[0306] Next, it is preferable to perform heat treatment. By performing heat treatment, the insulator 105 and the insulator 1 The amount of water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, the insulating layer 104 can have excess oxygen. 650°C or less, preferably 450°C to 600°C, more preferably 520°C to 5 Heat treatment should be performed at 70℃ or less. Heat treatment should be performed in an inert gas atmosphere or in an oxidizing gas atmosphere of 10ppm. m or more, 1% or more, or 10% or more. Heat treatment can be performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by heating to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. By the heat treatment, the insulator 106a and the semiconductor 106b are formed. It is possible to improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device that uses lamp heating. The process takes less time than using a furnace, making it effective for increasing productivity.

[0307] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range For example, the temperature range is about 350°C to 445°C. For example, any one of the substrate heating temperatures during deposition of the insulators 105, 103, and 104. It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0308] Next, a resist or the like is formed on the semiconductor, and the resist or the like is used to process the semiconductor, forming an insulator 106 a and semiconductor 106b are formed (see FIG. 17(E) and FIG. 17(F)).

[0309] Next, it is preferable to perform heat treatment. By performing heat treatment, the insulator 105 and the insulator 1 The amount of water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, the insulating layer 104 can have excess oxygen. 650°C or less, preferably 450°C to 600°C, more preferably 520°C to 5 Heat treatment should be performed at 70℃ or less. Heat treatment should be performed in an inert gas atmosphere or in an oxidizing gas atmosphere of 10ppm. m or more, 1% or more, or 10% or more. Heat treatment can be performed under reduced pressure. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by heating to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. By the heat treatment, the insulator 106a and the semiconductor 106b are formed. It is possible to improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device that uses lamp heating. The process takes less time than using a furnace, making it effective for increasing productivity.

[0310] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature range For example, the temperature range is about 350°C to 445°C. For example, any one of the substrate heating temperatures during deposition of the insulators 105, 103, and 104. It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0311] Next, the insulator 106c is formed (see FIG. 17(G) and FIG. 17(H)). The insulator 106c may be an insulator or a semiconductor that can be used as the insulator 106c. The insulator 106c can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out by using a PLD method, an ALD method, or the like.

[0312] Next, a conductor that will become the conductor 108a and the conductor 108b is formed. It is preferable to use a conductor that can be used as the conductor 108a and the conductor 108b described above. Conductive films are formed by sputtering, CVD, MBE, PLD, or ALD methods. This can be done using, for example.

[0313] In addition, the semiconductor 106b and the insulator 106c are in close proximity to the conductor that will become the conductor 108. In the adjacent region, a low resistance region 109 may form.

[0314] Next, a resist or the like is formed on the conductor, and the conductor 108 is processed using the resist or the like. Form.

[0315] Next, the insulator 113 that will become the insulator 110 is formed. The insulator 113 may be formed by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0316] When the insulator 110 is formed, a region 1 having silicon and oxygen is formed on the surface of the conductor 108. In some cases, the insulating layer 11 may be formed (see Fig. 18(A) and Fig. 18(B)). In some cases, the region 111 is formed even if the insulator 110 is not formed. Depending on the film conditions, the region 111 may not be formed when the insulator 110 is deposited.

[0317] Next, a resist or the like is formed on the insulator 113, and the resist or the like is used to process the insulator. 110, forming region 108c, region 108d, conductor 108a and conductor 108b (See FIG. 18(C) and FIG. 18(D).) At this time, the low In order to remove the resistor region 109, a part of the insulator 106c and the semiconductor 106b are processed. Good too.

[0318] Next, a high-density plasma treatment may be performed. The high-density plasma treatment is performed in an atmosphere containing oxygen. The oxygen-containing atmosphere is a gas atmosphere containing oxygen atoms. , ozone or nitrogen oxides (nitric oxide, nitrogen dioxide, nitrous oxide, dinitrogen trioxide, tetranitrogen Nitrous oxide, nitrous oxide, etc.) atmosphere. Also, in an atmosphere containing oxygen, nitrogen Inert gases such as nitrogen or rare gases (helium, argon, etc.) may also be included. By performing high-density plasma treatment in an atmosphere containing oxygen, for example, carbon, hydrogen, etc. In addition, high density plasma treatment in an oxygen-containing atmosphere can be performed. This also makes it easier to desorb organic compounds such as hydrocarbons from the material to be treated.

[0319] In addition, an annealing treatment may be performed before or after the high density plasma treatment. In order to increase the efficiency, it may be preferable to flow a sufficient amount of gas. Otherwise, the deactivation rate of radicals may be faster than the generation rate of radicals. In some cases, it may be preferable to flow 00sccm or more, 300sccm or more, or 800sccm or more. be.

[0320] The high-density plasma treatment may be performed, for example, at a frequency of 0.3 GHz or more and 3.0 GHz or less, or at a frequency of 2.2 GHz or less. Generated using a high-frequency generator with a frequency of GHz or higher but not exceeding 2.8 GHz (typically 2.45 GHz) The processing pressure is preferably 10 Pa or more and 5000 Pa or less. Preferably, the pressure is 200 Pa or more and 1500 Pa or less, and more preferably, the pressure is 300 Pa or more and 1000 Pa or less. a or less, the substrate temperature is 100°C to 600°C (typically 400°C), and oxygen and aluminum are This can be done using a mixed gas of nitrile and nitridone.

[0321] The high-density plasma is generated by using, for example, 2.45 GHz microwaves. High-density plasma treatment has an electron density of 1×10 11 / cm 3 More than 1×10 13 / cm 3 below, It is preferable to carry out the treatment under conditions where the electron temperature is 2 eV or less, or the ion energy is 5 eV or less. In such high-density plasma processing, the kinetic energy of radicals is small, which is different from that of conventional plasma. Compared to conventional plasma processing, plasma damage is less. Therefore, films with fewer defects are formed. The distance between the antenna generating the microwaves and the object to be treated is 5 mm or more. 0 mm or less, and preferably 20 mm or more and 60 mm or less.

[0322] Alternatively, a plasma that applies an RF (Radio Frequency) bias to the substrate side The frequency of the RF bias may be, for example, 13.56 MHz or 27.1 By using high-density plasma, high-density oxygen ions can be generated. By applying an RF bias to the substrate, the device is generated by high-density plasma. The oxygen ions can be efficiently guided to the workpiece. This allows oxygen ions to be efficiently guided to the inside of the mouth. It is preferable to carry out a high-density plasma treatment while applying the voltage.

[0323] In addition, after the high-density plasma treatment, annealing was performed continuously without exposure to the atmosphere. In addition, the high-density plasma treatment may be performed continuously after the annealing treatment without exposing the substrate to the atmosphere. The high density plasma treatment and the annealing treatment may be performed in succession. This can prevent impurities from being mixed in during processing. After the treatment, an annealing treatment is performed to remove the oxygen from the workpiece. It is possible to eliminate unnecessary oxygen that has not been used to compensate for the oxygen vacancies. The annealing process may be performed by, for example, lamp annealing.

[0324] In addition, the processing time for high-density plasma treatment is from 30 seconds to 120 minutes, or from 1 minute to 90 minutes. , preferably from 2 to 30 minutes, or from 3 to 15 minutes.

[0325] Annealing should be performed at temperatures between 250°C and 800°C, between 300°C and 700°C, or between 400°C and 800°C. Treatment time at 00℃ to 600℃ is 30 seconds to 120 minutes, 1 minute to 90 minutes, It is preferable to set the time to between 2 and 30 minutes, or between 3 and 15 minutes.

[0326] By performing high-density plasma treatment and / or annealing treatment, the semiconductor 106b It is possible to reduce the defect level in the region that will become the channel formation region. At that time, a part of the low resistance region 109 also becomes highly resistive, The conductive material 1 may be separated into a low resistance region 109a and a low resistance region 109b. Regions 108c and 108d are also formed on the sides of the conductor 108a and the conductor 108b. (See FIG. 18(E) and FIG. 18(F)).

[0327] Next, the insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. The insulator 132 can be formed by a sputtering method, a CVD method, or the like. The deposition can be performed by using a deposition method such as a deposition method, an MBE method, a PLD method, or an ALD method. The deposition of the insulating film 26c and the deposition of the insulating film 132 are performed successively without exposure to the atmosphere. The incorporation of impurities into the film and at the interface can be reduced.

[0328] Next, a conductor 134 is formed (see FIG. 19(A) and FIG. 19(B)). The conductive material 4 may be any conductive material that can be used as the conductive material 114 described above. The film 134 may be formed by a method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The deposition of the insulator 132 and the deposition of the conductor 134 can be performed using a By performing the process continuously without exposing the film to the atmosphere, the incorporation of impurities into the film and at the interface is reduced. It is possible.

[0329] Next, the conductor 134 is polished until the insulator 113 is exposed. , and then insulators 112 and 110 are formed (see FIGS. 19(C) and 19(D)). Conductor 114 and insulator 112 are the gate electrode and gate of transistor 29, respectively. The conductor 114 and the insulator 115 function as a gate insulator. 112 can be formed in a self-aligned manner.

[0330] Next, the insulator 116 is formed (see FIG. 19(E) and FIG. 19(F)). The insulator 116 may be formed by sputtering, C This can be carried out by using a VD method, an MBE method, a PLD method, an ALD method, or the like.

[0331] Next, a heat treatment is preferably carried out.

[0332] Through the above steps, the transistor 29 of one embodiment of the present invention can be manufactured.

[0333] By manufacturing a transistor by the method described in this embodiment, heat resistance and acid resistance can be improved. It is possible to provide a transistor using a conductive material having chemical properties.

[0334] In addition, a transistor having stable electrical characteristics can be provided. It is possible to provide a transistor with a small leakage current during normal-off. Alternatively, a transistor having electrical characteristics of It is possible to provide a transistor with a small swing value or a highly reliable transistor. A register can be provided.

[0335] Furthermore, by manufacturing a transistor by the method described in this embodiment, The heat treatment in the low temperature range suppresses the supply of water, hydrogen, etc. to the semiconductor 106b, etc. Therefore, a semiconductor element layer or a wiring layer can be formed under the transistor. Even if the transistor is formed, it can be manufactured without being deteriorated at high temperatures. do.

[0336] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0337] (Embodiment 3) <Manufacturing equipment> A manufacturing apparatus for performing high density plasma processing according to one embodiment of the present invention will be described below.

[0338] First, let us consider the configuration of a manufacturing device that minimizes the inclusion of impurities during the manufacture of semiconductor devices. This will be explained using FIG.

[0339] FIG. 20 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing equipment 2700 includes a cassette port 2761 for accommodating substrates and a and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing alignment. The substrate is loaded from the supply chamber 2701 to the atmospheric substrate transfer chamber 2702, A load lock chamber 2 that switches the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 703a, the substrate is removed, and the pressure in the chamber is reduced from reduced pressure to atmospheric pressure, or reduced from atmospheric pressure to atmospheric pressure. and a transfer chamber 2703b for transferring substrates in a vacuum. 04, chamber 2706a, chamber 2706b, and chamber 2706c, and a chamber 2706d.

[0340] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock The load lock chamber 2703a and the unload lock chamber 2703b are connected to each other. b is connected to the transfer chamber 2704, which is connected to the chamber 2706a, the chamber -2706b, connected to chamber 2706c and chamber 2706d.

[0341] In addition, a gate valve GV is provided at the connection between each chamber, and the atmosphere side substrate supply chamber 2701 Each chamber can be independently maintained in a vacuum state except for the atmospheric substrate transfer chamber 2702. In addition, a transfer robot 2763a is provided in the atmospheric substrate transfer chamber 2702. The chamber 2704 is provided with a transport robot 2763b. The substrate can be transported within the manufacturing apparatus 2700 by the transport robot 2763b. .

[0342] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Below Pa, Preferably 3 x 10 -5 Pa or less, more preferably 1×10 -5 Pa or less. Also, The transfer chamber 2704 and each chamber are filled with gas molecules (atoms) having a mass-to-charge ratio (m / z) of 18. The partial pressure of the electrons is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, Preferably 3 x 10 -6 In addition, the transfer chamber 2704 and each chamber The partial pressure of a gas molecule (atom) with m / z of 28 is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less. The partial pressure of gas molecules (atoms) with m / z of 44 in the chamber 2704 and each chamber is, for example, , 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0343] The total pressure and partial pressure in the transfer chamber 2704 and each chamber were measured using a mass spectrometer. For example, a quadrupole mass spectrometer (Q-mass (Also known as Qulee CGM-051) can be used.

[0344] In addition, the transfer chamber 2704 and each chamber are configured to have little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is preferably set as follows: 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. For example, m / z 28 gas molecule (atom) leak rate is 1×10 -5 Pa·m 3 / s or less, Preferably 1 x 10 -6 Pa·m 3 / s or less. For example, if the m / z is 44, The leak rate of gas molecules (atoms) is 3×10 -6 Pa·m 3 / s or less, preferably 1×1 0 -6 Pa·m 3 / s or less.

[0345] The leak rate was calculated from the total and partial pressures measured using the mass spectrometer mentioned above. The leak rate depends on the external leak and the internal leak. The reason is that gas enters from outside the vacuum system due to a small hole or a defective seal. The gas leak is caused by leakage from valves and other partitions in the vacuum system or by gas released from internal components. In order to keep the leak rate below the above values, both external and internal leaks must be prevented. Therefore, measures need to be taken.

[0346] For example, the opening and closing parts of the transfer chamber 2704 and each chamber are sealed with metal gaskets. Metal gaskets are protected by iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use a coated metal. Metal gaskets have a higher adhesion than O-rings, It can reduce external leakage. In addition, iron fluoride, aluminum oxide, chromium oxide, etc. By using a passivation coating, the metal gasket is protected from impurities The released gas is suppressed, and internal leakage can be reduced.

[0347] In addition, the components constituting the manufacturing apparatus 2700 are aluminum, which emits less gas including impurities. Cr, Ti, Zr, Ni or Vanadium is used. The above members may be coated with an alloy containing iron, chromium, nickel, etc. The alloys containing copper, nickel, etc. are strong, heat resistant, and easy to machine. In order to reduce the surface area, the surface irregularities of the component can be reduced by polishing, etc. Gas can be reduced.

[0348] Alternatively, the components of the manufacturing apparatus 2700 may be made of iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with

[0349] It is preferable that the members of the manufacturing apparatus 2700 are made of metal as much as possible, for example, quartz. When installing a viewing window, the surface is treated with iron fluoride or acid to suppress gas emission. It is advisable to thinly coat the surface with aluminum oxide or chromium oxide.

[0350] The adsorbents present in the transfer chamber 2704 and each chamber are adsorbed to the inner walls, etc. It does not affect the pressure in the transfer chamber 2704 and each chamber, but This causes gas emission when exhausting the nozzle. Therefore, there is a correlation between the leak rate and the pumping speed. Although there is no exhaust gas, the transfer chamber 2704 and each chamber are filled with the gas using a pump with high exhaust capacity. It is important to remove as much of the adsorbed matter as possible and evacuate the air in advance. To facilitate the removal of adhesions, the transfer chamber 2704 and each of the chambers may be baked. Baking can increase the desorption rate of adsorbed substances by about 10 times. The heating may be performed at a temperature of 100° C. or more and 450° C. or less. By removing the adsorbed substances while introducing them into each chamber, it is difficult to remove them by simply evacuating the gas. The desorption rate of water and the like can be further increased. By heating the catalyst to a temperature similar to that of the catalyst, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a rare gas as the inert gas.

[0351] Alternatively, an inert gas such as a heated rare gas or oxygen may be introduced into the transfer chamber 270 The pressure in the transfer chamber 2704 and each chamber is increased, and after a certain period of time, the transfer chamber 2704 and each chamber are It is preferable to perform a process of evacuating the chamber. The adsorbed substances in the transfer chamber 2704 and each chamber can be desorbed. This treatment can be repeated 2 to 30 times to reduce impurities present in the water. It is effective to repeat the process 5 to 15 times. or an inert gas having a temperature of 40° C. or higher and 400° C. or lower, preferably 50° C. or higher and 200° C. or lower; By introducing oxygen, etc., the pressure in the transfer chamber 2704 and each chamber is kept at 0.1 Pa or more. 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, and more preferably 5 Pa or more and 10 0 Pa or less, and the pressure is maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the transfer chamber 2704 and each chamber are cooled for 5 minutes to 300 minutes. The evacuation is preferably performed for a period of 10 minutes or more and 120 minutes or less.

[0352] Next, the chamber 2706b and the chamber 2706c are shown in a cross-sectional schematic diagram in FIG. The following explains using the diagram.

[0353] The chambers 2706b and 2706c are, for example, for applying high-density plasma to a workpiece. The chambers 2706b and 2706c are chambers in which the laser processing can be performed. The only difference between the 2706c and the 2706c is the atmosphere during high-density plasma treatment. Since the configurations of the above are the same, they will be described together below.

[0354] The chambers 2706b and 2706c each include a slot antenna plate 2808; The device includes a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Outside the chambers 2706b and 2706c, a gas supply source 2801 and A valve 2802, a high frequency generator 2803, a waveguide 2804, and a mode converter 2805. , a gas pipe 2806, a waveguide 2807, a matching box 2815, and a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0355] The high frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with the dielectric plate 2809. The gas source 2801 is connected to the mode converter 2805 via a valve 2802. Then, a gas tube passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. 2806 delivers gas to chamber 2706b and chamber 2706c. The vacuum pump 2817 also supplies the chamber with air via a valve 2818 and an exhaust port 2819. It has a function of exhausting gases and the like from the bar 2706b and the chamber 2706c. A high frequency power supply 2816 is connected to the substrate stage 2812 via a matching box 2815. Connected.

[0356] The substrate stage 2812 has a function of holding the substrate 2811. For example, The device has the function of electrostatically or mechanically chucking the object. It also has a heating mechanism 2813 inside, It has a function of heating the substrate 2811 .

[0357] The vacuum pump 2817 may be, for example, a dry pump, a mechanical booster pump, an On-pump, titanium sublimation pump, cryopump or turbomolecular pump In addition to the vacuum pump 2817, a cryotrap can be used. Cryopumps and cryotraps can be used to efficiently pump out water. Particularly preferred.

[0358] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like. Alternatively, the heat can be transferred by heat conduction or radiation from a medium such as a heated gas. A heating mechanism that heats the gas may be used. For example, GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) RTAs such as nealing can be used. GRTAs use high-temperature gas Heat treatment is performed using an inert gas.

[0359] In addition, the gas supply source 2801 is connected to a refiner via a mass flow controller. The gas used has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) are used. That's good.

[0360] The dielectric plate 2809 is made of, for example, silicon oxide (quartz), aluminum oxide, or oxide. Yttrium oxide (yttria) or the like may be used. A separate protective layer may be formed. The protective layer may be formed of magnesium oxide, titanium oxide, or the like. Tantalum, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, Aluminum oxide or yttrium oxide may be used. Since the device is exposed to a particularly high-density region of the high-density plasma 2810 described below, a protective layer is provided. As a result, the damage can be mitigated by reducing the number of particles during processing. It can be suppressed.

[0361] The high frequency generator 2803 may be, for example, 0.3 GHz or more and 3.0 GHz or less, or 2.2 GHz. It has the function of generating microwaves from 280 Hz to 2.8 GHz. The microwaves generated in 3 are transmitted to the mode converter 2805 via a waveguide 2804 . In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then guided through a waveguide 2807 to a slot antenna plate 2808. The slot antenna plate 2808 has a number of slot holes, The wave passes through the slot hole and the dielectric plate 2809. Then, under the dielectric plate 2809 By generating an electric field, a high density plasma 2810 can be generated. In the gas supply source 2801, ions and radicals corresponding to the gas species are supplied. For example, oxygen radicals or nitrogen radicals exist.

[0362] At this time, the ions and radicals generated by the high density plasma 2810 cause the substrate 2 The film on the substrate 811 can be modified. It may be preferable to apply a bias to the 811 side. RF (Radio Frequency) By applying a bias to the substrate, a high density plasma 28 The ions in the nozzle 10 can be efficiently guided to the depth of the opening in the film on the substrate 2811. Cut.

[0363] For example, in the chamber 2706b, oxygen is introduced from the gas supply source 2801 to form a high density The oxygen radical treatment is performed using the high-temperature plasma 2810, and the gas Nitrogen radicals using high-density plasma 2810 by introducing nitrogen from a supply source 2801 Processing can be performed.

[0364] Next, the chamber 2706a and the chamber 2706d are shown in a cross-sectional schematic diagram in FIG. The following explains using the diagram.

[0365] The chambers 2706a and 2706d are used for, for example, irradiating the object to be treated with electromagnetic waves. In addition, the chamber 2706a and the chamber 27 The only difference between the 06d and the 06i is the type of electromagnetic wave. The rest of the configuration is the same. Because there are many, we will explain them together below.

[0366] Chamber 2706a and chamber 2706d may include one or more lamps 2820. , a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. , outside chamber 2706a and chamber 2706d, a gas supply source 2821 , a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0367] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The air pump 2828 is connected to an exhaust port 2830 via a valve 2829. The substrate stage 2825 is disposed opposite the substrate stage 2820. The substrate stage 2825 has a function of holding the substrate 2824. It has a mechanism 2826 and has a function of heating the substrate 2824 .

[0368] The lamp 2820 has a function of emitting electromagnetic waves such as visible light or ultraviolet light. For example, a light source having a wavelength of 10 nm or more and 2500 nm or less, or a light source having a wavelength of 500 nm or more and 2500 nm or less, may be used. Emitting electromagnetic waves with a peak of 2000 nm or less, or between 40 nm and 340 nm It is sufficient to use a light source having such a function.

[0369] For example, the lamp 2820 may be a halogen lamp, a metal halide lamp, a xenon lamp, or a -lamp, carbon arc lamp, high pressure sodium lamp or high pressure mercury lamp A light source may be used.

[0370] For example, electromagnetic waves emitted from the lamp 2820 may be partially or completely transmitted to the substrate 2824. The absorption can modify the film on the substrate 2824. For example, the generation of defects The substrate 2824 is heated while the process is performed. By using this method, defects can be efficiently generated or reduced, or impurities can be efficiently removed.

[0371] Alternatively, for example, the substrate stage 2825 may be moved by electromagnetic waves emitted from the lamp 2820. In this case, the inside of the substrate stage 2825 may be heated. The heating mechanism 2826 may not be included.

[0372] The vacuum pump 2828 is the same as that described for the vacuum pump 2817. 2826 refers to the description of the heating mechanism 2813. Also, the gas supply source 2821 , see the description of gas source 2801.

[0373] By using the above manufacturing equipment, it is possible to suppress the inclusion of impurities in the processed object while modifying the film, etc. This becomes possible.

[0374] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0375] (Embodiment 4) In this embodiment, a semiconductor device including a transistor according to one embodiment of the present invention is An example of the circuit will be described.

[0376] <Circuit> An example of a circuit of a semiconductor device using a transistor according to one embodiment of the present invention will be described below. We will explain about this.

[0377] <CMOSインバータ> The circuit diagram shown in FIG. 23A includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected. 4 shows the configuration of an S inverter.

[0378] <Semiconductor device structure 1> 24 is a cross-sectional view of the semiconductor device corresponding to FIG. 23(A). The transistor 2200 includes a transistor 2100. The transistor 2100 is disposed above the transistor 2200. The transistor 2100 is The description of the transistor 20 shown in FIGS. 9(A) and 9(B) may be appropriately referred to. The semiconductor device according to one aspect of the present invention is not limited to the above embodiment. The transistor described in can be used as the transistor 2100. For the transistor 2100, the above-mentioned description of the transistor may be referred to as appropriate. do.

[0379] A transistor 2200 shown in FIG. 24 is a transistor using a semiconductor substrate 450 . The transistor 2200 includes a region 472 a in the semiconductor substrate 450 and a The conductive material 454 includes a region 472b, an insulator 462, and a conductive material 454. The conductive material 454 includes a tongue. Stainless steel and silicon, carbon, germanium, tin, aluminum or nickel. It is preferable to use a conductor having a region having one or more elements selected from the group consisting of .

[0380] In transistor 2200, regions 472a and 472b are source and The insulator 462 functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by applying a potential to the body 454. That is, the electric potential applied to the conductor 454 causes a conduction line between the region 472a and the region 472b. The non-conduction can be controlled.

[0381] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A semiconductor substrate such as a gallium oxide substrate may be used. A single crystal silicon substrate is used.

[0382] The semiconductor substrate 450 is a semiconductor substrate having impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate having an impurity that imparts p-type conductivity. In that case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, That's fine.

[0383] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-characteristics of the transistor 2200 can be improved.

[0384] Regions 472a and 472b are regions having impurities that impart p-type conductivity. In this manner, transistor 2200 constitutes a p-channel transistor.

[0385] Note that transistor 2200 is isolated from adjacent transistors by regions 460, etc. The region 460 is an insulating region.

[0386] The semiconductor device shown in FIG. 24 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b. , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator An insulator 489, an insulator 490, an insulator 491, an insulator 492, an insulator 493, and an insulator The conductor 480a, the conductor 480b, and the conductor 480c are , tungsten and silicon, carbon, germanium, tin, aluminum or nickel It is preferable to use a conductor having a region having one or more elements selected from the above.

[0387] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 89 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 489. Also, an insulator 493 is disposed on the transistor 2100. Also, an insulator 4 94 is disposed on the insulator 493 .

[0388] The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0389] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0390] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0391] The insulator 489 has an opening overlapping with a channel formation region of the transistor 2100 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. is.

[0392] The conductor 474a may function as a gate electrode of the transistor 2100. Alternatively, for example, a constant potential may be applied to the conductor 474a to turn on the transistor 210. Alternatively, the electrical properties of the conductor 474 may be controlled, such as the threshold voltage of 0. a and the conductor 504 functioning as the gate electrode of the transistor 2100 are electrically This can increase the on-state current of the transistor 2100. In addition, since the punch-through phenomenon can be suppressed, the transistor 210 The electrical characteristics in the saturated region of 0 can be stabilized. Since this corresponds to the conductor 102 in the embodiment, please refer to the description of the conductor 102 for details. It is possible.

[0393] In addition, the insulator 490 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. The insulator 490 corresponds to the insulator 103 in the above embodiment, For details, the description of the insulator 103 can be referred to. In this manner, an insulator 490 is provided to cover the conductors 474a to 474c except for the openings. By this, the conductors 474a to 474c can extract oxygen from the insulator 491. As a result, the oxide semiconductor of the transistor 2100 can be prevented from being separated from the insulator 491. can effectively supply oxygen to

[0394] Further, the insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. Since the insulator 491 corresponds to the insulator 104 in the above embodiment, For details, the description of the insulator 104 can be referred to.

[0395] As shown in the above embodiment, by reducing the water and hydrogen content of the insulator 491, In this way, formation of defect states in the oxide semiconductor of the transistor 2100 can be suppressed. This makes it possible to stabilize the electrical characteristics of the transistor 2100.

[0396] In addition, such an insulator with reduced water and hydrogen is not only insulator 491 but also other insulators. For example, the insulator 466, the insulator 468, the insulator 489, the insulator 493, etc. It can be used in any way.

[0397] In addition, in FIG. 24, the insulator 105 corresponds to the insulator 101 in the transistor 20. Although the insulators are not shown, they may be provided. An insulator equivalent to the insulator 101 may be provided between the edge 468 and the insulator 489. An insulator equivalent to the insulator 105 may be provided between the insulator 489 and the insulator 490. Between the edge 468 and the insulator 489, there is an insulator 101 that blocks water, hydrogen, etc. By providing an insulator having the above-mentioned function, the water and hydrogen content of the insulator 491 can be reduced. This further suppresses the formation of defect states in the oxide semiconductor of the transistor 2100. It is possible.

[0398] Also, the insulator 492 is connected to one of the source and drain electrodes of the transistor 2100. An opening through one conductor 516b to conductor 474b and a transistor 2100 An opening reaching the conductor 516a, which is the other of the source electrode or drain electrode of the transistor, An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c The insulator 492 corresponds to the insulator 116 in the above embodiment. For details, the description of the insulator 116 can be referred to.

[0399] The insulator 493 is connected to one of the source and drain electrodes of the transistor 2100. An opening through one conductor 516b to conductor 474b and a transistor 2100 An opening reaching the conductor 516a, which is the other of the source electrode or drain electrode of the transistor, An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c The openings are provided with a conductor 496a and a conductor 496b. , a conductor 496c or a conductor 496d is embedded in each opening. may be transmitted through an opening in any of the components such as the transistor 2100. There is.

[0400] The insulator 494 has an opening that reaches the conductor 496a, and a conductor 496b and a The opening reaches the conductor 496d, and the opening reaches the conductor 496c. The conductive body 498a, the conductive body 498b, and the conductive body 498c are embedded in the conductive body 498a, the conductive body 498b, and the conductive body 498c, respectively. do.

[0401] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 and Insulator Examples of 494 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in Alternatively, the film may be used in a laminated form.

[0402] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of 494 has an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 2100. By disposing an insulator having a locking function, the electrical characteristics of the transistor 2100 are It can stabilize the sex.

[0403] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0404] Conductor 454, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor Conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, The conductor 496d, the conductor 498a, the conductor 498b, and the conductor 498c are each a tongue. Stainless steel and silicon, carbon, germanium, tin, aluminum or nickel. In particular, a conductor having a region containing one or more elements selected from the group consisting of tungsten and tungsten is used. A conductor containing boron, nitrogen, oxygen, fluorine, silicon, etc. is preferable. Copper, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc , Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Conductors containing one or more of tin, tantalum and tungsten are used in a single layer or multilayer. For example, the material may be an alloy or a compound, such as a conductor containing aluminum, copper, Conductors containing titanium, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0405] The semiconductor device shown in FIG. 25 is the same as the transistor 2200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. As a result, the effective channel width is increased, improving the on-characteristics of the transistor 2200. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0406] 26 is a semiconductor device in which the transistor 2200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450 which is an SOI substrate. 1 shows a structure in which region 456 is separated from semiconductor substrate 450 by insulator 452. By using an SOI substrate as the conductive substrate 450, punch-through phenomenon and the like can be suppressed. Therefore, the off-state characteristics of the transistor 2200 can be improved. The insulator 452 can be formed by insulating the semiconductor substrate 450. For example, the insulator 452 can be silicon oxide.

[0407] The semiconductor device shown in FIG. 24 to FIG. 26 is a p-channel transistor formed on a semiconductor substrate. By fabricating a MOSFET and fabricating an n-channel transistor above it, the area occupied by the device is reduced. In other words, the integration density of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor were fabricated using the same semiconductor substrate. Since the process can be simplified compared to the conventional method, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. The transistor is in the LDD (Lightly Doped Drain) region, shallow trench In some cases, complex processes such as ch-structure and distortion design can be omitted. Compared to manufacturing transistors using a semiconductor substrate, the productivity and yield are improved. It may be possible to reduce the

[0408] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 23B is that of a transistor 2100 and a transistor 2200. The source and drain of each transistor are connected. It can function as a so-called CMOS analog switch.

[0409] <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied FIG. 27 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0410] The semiconductor device shown in FIG. 27A includes a transistor 3200 using a first semiconductor and a The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 is the same as the transistor 2100 described above. It is possible.

[0411] The transistor 3300 is preferably a transistor having a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. The contents of the memory can be retained, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in a semiconductor with low power consumption. It becomes a body device.

[0412] In FIG. 27A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0413] The semiconductor device shown in FIG. 27A can hold a gate potential of the transistor 3200. This property makes it possible to write, hold, and read information, as shown below. do.

[0414] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the The signal is applied to a node FG that is electrically connected to one of the electrodes of the capacitance element 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. By setting the potential at which the transistor 3300 is in a non-conducting state, the transistor 3300 is in a non-conducting state. As a result, charge is held at the node FG (retention).

[0415] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long period of time. It will be held.

[0416] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, 3002 takes a potential according to the amount of charge held in the node FG. This is the transistor If 3200 is an n-channel type, a high-level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it in a "conductive state." Then, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential between For example, in a write, the charge applied to node FG can be determined. When a high-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." On the other hand, the node FG When a low-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. It can be put out.

[0417] When memory cells are arranged in an array, the information of a desired memory cell is read. In memory cells where information is not to be read, The potential at which the transistor 3200 is in a "non-conducting state" regardless of the charge applied, i.e. V th_H By applying a lower potential to the fifth wiring 3005, the information of the desired memory cell is Alternatively, in a memory cell from which information is not read, Therefore, the transistor 3200 is in a "conducting state" regardless of the charge applied to the node FG. Such a potential, that is, V th_L By applying a higher potential to the fifth wiring 3005, a desired It is only necessary to have a configuration in which only the information in the memory cells can be read.

[0418] In the above, an example in which two types of charges are held in the node FG is shown. The semiconductor device according to the present invention is not limited to this. For example, It may be configured to hold three or more types of charges. The semiconductor device can be made multi-valued to increase the memory capacity.

[0419] <Memory device structure 1> 28 is a cross-sectional view of the semiconductor device corresponding to FIG. 27(A). The semiconductor memory device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are disposed above the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100 described above. In addition, the transistor 3200 may be the transistor shown in FIG. Please refer to the description of transistor 2200 in FIG. The case where the transistor 3200 is an n-channel transistor has been described. A transistor of a channel type may also be used.

[0420] A transistor 3200 shown in FIG. 28 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472 a in the semiconductor substrate 450 and a It has a region 472b, an insulator 462, and a conductor 454.

[0421] The semiconductor device shown in FIG. 28 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b. , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator An insulator 489, an insulator 490, an insulator 491, an insulator 492, an insulator 493, and an insulator and an edge body 494.

[0422] An insulator 464 is disposed on the transistor 3200. Also, an insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 89 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 489. Also, an insulator 493 is disposed on the transistor 3300. Also, an insulator 4 94 is disposed on the insulator 493 .

[0423] The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0424] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0425] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0426] The insulator 489 has an opening overlapping with a channel formation region of the transistor 3300 and a conductor The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. is.

[0427] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a may cause the transistor It is also possible to control electrical properties such as the threshold voltage of 3300. 474a is electrically connected to the conductor 504 which is the top gate electrode of the transistor 3300. This can increase the on-current of the transistor 3300. In addition, the punch-through phenomenon can be suppressed, so the transistor 3300 The electrical characteristics in the saturation region can be stabilized.

[0428] In addition, the insulator 490 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. The insulator 490 corresponds to the insulator 103 in the above embodiment, For details, the description of the insulator 103 can be referred to. In this manner, an insulator 490 is provided to cover the conductors 474a to 474c except for the openings. By this, the conductors 474a to 474c can extract oxygen from the insulator 491. This can prevent the oxide semiconductor of the transistor 3300 from being damaged by the insulator 491. can effectively supply oxygen to

[0429] Further, the insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. Since the insulator 491 corresponds to the insulator 104 in the above embodiment, For details, the description of the insulator 104 can be referred to.

[0430] As shown in the above embodiment, by reducing the water and hydrogen content of the insulator 491, In this way, formation of defect states in the oxide semiconductor of the transistor 2100 can be suppressed. This makes it possible to stabilize the electrical characteristics of the transistor 2100.

[0431] In addition, such an insulator with reduced water and hydrogen is not only insulator 491 but also other insulators. For example, the insulator 466, the insulator 468, the insulator 489, the insulator 493, etc. It can be used in any way.

[0432] In addition, in FIG. 24, the insulator 105 corresponds to the insulator 101 in the transistor 20. Although the insulators are not shown, they may be provided. An insulator equivalent to the insulator 101 may be provided between the edge 468 and the insulator 489. An insulator equivalent to the insulator 105 may be provided between the insulator 489 and the insulator 490. Between the edge 468 and the insulator 489, there is an insulator 101 that blocks water, hydrogen, etc. By providing an insulator having the above-mentioned function, the water and hydrogen content of the insulator 491 can be reduced. This further suppresses the formation of defect states in the oxide semiconductor of the transistor 3300. It is possible.

[0433] Also, the insulator 492 is connected to one of the source and drain electrodes of the transistor 3300. An opening through one conductor 516b to conductor 474b and transistor 3300 The other of the source electrode or drain electrode is overlapped with a conductor 516a via an insulator 511. 514, which is the gate electrode of transistor 3300; and 04 and the other of the source electrode or drain electrode of the transistor 3300. An opening that passes through a certain conductor 516a and reaches the conductor 474c. The insulator 492 corresponds to the insulator 116 in the above embodiment, and therefore the details thereof will be described with reference to the insulator 116. The above description may be taken into consideration.

[0434] The insulator 493 is connected to one of the source and drain electrodes of the transistor 3300. An opening through one conductor 516b to conductor 474b and transistor 3300 The other of the source electrode or drain electrode is overlapped with a conductor 516a via an insulator 511. 514, which is the gate electrode of transistor 3300; and 04 and the other of the source electrode or drain electrode of the transistor 3300. An opening extending through a certain conductor 516a to a certain conductor 474c. The section is embedded with a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496 d. However, each opening may further pass through an opening of any of the components such as the transistor 3300 .

[0435] Also, the insulator 494 has an opening reaching the conductor 496a, an opening reaching the conductor 496b , an opening reaching the conductor 496c, and an opening reaching the conductor 496d . Also, the openings are each embedded with a conductor 498a, a conductor 498b, a conductor 498c, and a conductor 498d

[0436] One or more of the insulators 464, 466, 468, 489, 493, or 494 preferably have an insulator function of blocking impurities such as hydrogen and oxygen . By disposing an insulator having a function of blocking impurities such as hydrogen and oxygen near the transistor 3300, the electrical characteristics of the transistor 3300 can be stabilized . .

[0437] The source or drain of the transistor 3200 is electrically connected to a conductor 516b, which is one of the source electrode or drain electrode of the transistor 3300, via the conductor 480b, the conductor 478b , the conductor 476a, the conductor 474b, and the conductor 496c . Also, the conductor 454, which is the gate electrode of the transistor 3200, is electrically connected to a conductor 516a, which is the other of the source electrode or drain electrode of the transistor 3300, via the conductor 480c, the conductor 478c , the conductor 476b, the conductor 474c, and the conductor 496d . .

[0438] ​​ The capacitor 3400 is the other of the source electrode and the drain electrode of the transistor 3300. The insulating material 511 includes a conductor 516a, a conductor 514, and an insulator 511. The insulator can be formed in the same process as the insulator that functions as the gate insulator of the transistor 3300. This can be preferable because it can increase productivity. 3300. The conductor 504 that functions as the gate electrode of the transistor 3300 is formed in the same process. The use of such a layer may be preferable in some cases because it can increase productivity.

[0439] For other structures, please refer to the descriptions in Figure 24 etc. as appropriate.

[0440] The semiconductor device shown in FIG. 29 is the same as the transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The figure shows a case where the transistor 200 is a fin type. For details, refer to the description of the transistor 2200 shown in FIG. The transistor 2200 is a p-channel transistor. The transistor 3200 may be an n-channel transistor.

[0441] 30 is a semiconductor device having a transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450 which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. The case where the transistor 3200 is an n-channel transistor has been described. A transistor of a channel type may also be used.

[0442] <Storage device 2> The semiconductor device shown in FIG. 27B differs from the semiconductor device shown in FIG. 27A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information more easily.

[0443] The reading of data in the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and electric charges are redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is expressed by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0444] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+CV) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of 3400 can take two states, V1 and V0 (V1>V0), then The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+CV1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=(C B×VB0+CV0) / (CB+C)).

[0445] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0446] In this case, the transistor in which the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the driving circuit.

[0447] The above-described semiconductor device uses a transistor including an oxide semiconductor and has low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the potential for a long period of time. It is possible to maintain the capacity.

[0448] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the problem of a conventional nonvolatile memory. A semiconductor device with dramatically improved reliability, without the problematic limit on the number of times it can be rewritten Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This enables high-speed operation.

[0449] <Storage device 3> Regarding a modification of the semiconductor device (memory device) shown in FIG. 27(A), a circuit diagram shown in FIG. I will explain it below.

[0450] The semiconductor device illustrated in FIG. 31 includes transistors 4100 to 4400 and a capacitor. The transistor 4100 has a capacitance element 4500 and a capacitance element 4600. A transistor similar to the transistor 3200 in the embodiment can be used, and the transistor 420 0 to 4400 can be transistors similar to the transistor 3300 described above. The semiconductor device shown in FIG. 31 can be implemented in a matrix form, although this is not shown in FIG. The semiconductor device shown in FIG. 5 to 4009, the writing and reading of the data voltage is controlled according to the signal or potential applied to It can be controlled.

[0451] One of the source and the drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to a wiring 4001. In FIG. 31, the conductivity type of the transistor 4100 is shown as a p-channel type. That's fine too.

[0452] The semiconductor device shown in FIG. 31 has two data storage units. For example, the first data storage unit is , one of the source and drain of the transistor 4400 connected to the node FG1, One electrode of the element 4600 and one of the source and drain of the transistor 4200 The second data storage unit stores a charge between the transistor connected to the node FG1 and the transistor connected to the node FG2. The gate of the transistor 4100, the other of the source or drain of the transistor 4200, One of the source or drain of the transistor 4300 and one of the electrodes of the capacitor element 4500 A charge is maintained between the

[0453] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and the drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4300 is connected to a wiring 4006. The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to a wiring 4008. The other electrode of element 4000 is connected to wiring 4009.

[0454] The transistors 4200 to 4400 are transistors that control writing of data voltages and retention of electric charges. Note that the transistors 4200 to 4400 are in a non-conducting state. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, a transistor having an oxidized layer in a channel formation region is preferably used. Preferably, the transistor is an OS transistor having an organic semiconductor. The advantage of a transistor is that it has a low off-state current and can be stacked with a silicon-containing transistor. In FIG. 31, the conductivity type of the transistors 4200 to 4400 is an n-channel type. However, a p-channel type may also be used.

[0455] The transistors 4200, 4300, and 4400 are oxidized. Even if the transistor is made of a semiconductor, it is preferable to provide the transistor in a separate layer. The semiconductor device shown in FIG. 1 includes a first layer 4 having a transistor 4100 as shown in FIG. 021 and a second layer 4022 having a transistor 4200 and a transistor 4300. and a third layer 4023 having a transistor 4400. By stacking layers having transistors, the circuit area can be reduced. This allows the body device to be made smaller.

[0456] Next, the operation of writing information into the semiconductor device shown in FIG. 31 will be described.

[0457] First, a data voltage is written to the data storage unit connected to node FG1 (hereinafter, In the following, the write operation 1 will be described. The data voltage to be written to the data storage unit is V D1 The threshold voltage of the transistor 4100 is The voltage is Vth.

[0458] In write operation 1, the line 4003 is connected to V D1 Then, after setting the wiring 4001 to the ground potential, The wirings 4005 and 4006 are set to a high level. 007 to 4009 are set to a low level. Then, the node FG2, which is in an electrically floating state, The potential of the wiring 40 increases, and a current flows through the transistor 4100. The potential of the transistor 4400 and the transistor 4200 are turned on. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 also increase. The potential of the node FG2 rises, and a potential difference between the gate and source of the transistor 4100 increases. When the voltage (Vgs) reaches the threshold voltage Vth of the transistor 4100, the transistor 410 Therefore, the potential of the wiring 4001, the nodes FG1 and FG2 The rise stopped, and V D1 Vth has dropped from D1 -Vth".

[0459] In other words, the V given to wire 4003 D1 When a current flows through the transistor 4100, The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. , the potential of node FG2 is "V D1 -Vth", the Vgs of transistor 4100 is Vth is reached and the current stops.

[0460] Next, a data voltage is written to the data storage unit connected to node FG2 (hereinafter, “write”). The data retention operation connected to node FG2 is called write operation 2. The data voltage written to the section is V D2 This is explained as follows.

[0461] In write operation 2, the line 4001 is connected to V D2 Then, after setting the wiring 4003 to the ground potential, The wiring 4007 is set to a high level. 006, 4008, and 4009 are set to low level. Transistor 4300 is set to a conductive state. Therefore, the potential of the node FG2 is also set to a low level. The voltage Vcc of the wiring 4003 decreases, and a current flows through the transistor 4100. The potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. As the potential rises, the potential at node FG2 rises. When Vgs of transistor 4100 becomes Vth of transistor 4100, The current flowing through 100 becomes smaller. Therefore, the potential of wiring 4003 and FG2 does not stop rising. V D2 Vth has dropped from D2 -Vth".

[0462] In other words, the V given to wire 4001 D2 When a current flows through the transistor 4100, The potential of the node FG2 is increased by the increase in the potential. The potential of FG2 is "V D2 -Vth", the Vgs of transistor 4100 is Vth. At this time, the potential of the node FG1 is the same as that of the transistors 4200 and 4201. 400 are in a non-conducting state, and the "V D1 -Vth" is maintained can be.

[0463] In the semiconductor device shown in FIG. 31, after writing data voltages to a plurality of data holding units, By setting 4009 to a high level, the potentials of the nodes FG1 and FG2 are raised. The transistor is put into a non-conductive state, preventing the movement of charge and retaining the written data voltage. .

[0464] By the above-described data voltage write operation to the nodes FG1 and FG2, multiple data The data voltage can be stored in the data storage section. D 1-Vth" or "V D2 -Vth" was used as an example, but these are multi-value data. Therefore, each data storage section stores 4 bits of data. When holding, 16 values ​​of "V D1 -Vth" or "V D2 -Vth".

[0465] Next, the operation of reading information from the semiconductor device shown in FIG. 31 will be described.

[0466] First, a data voltage is read from the data storage unit connected to node FG2 (hereinafter, This operation is called read operation 1.

[0467] In the read operation 1, the wiring 4003, which is precharged and then put into an electrically floating state, The wirings 4005 to 4008 are set to a low level. The potential of the electrically floating node FG2 is set to "V D2 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The current flows, and the potential of the wiring 4003, which is in an electrically floating state, drops. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When Vgs becomes the Vth of the transistor 4100, the current flowing through the transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D2 -Vth” Vth is larger than V D2 The potential of the wiring 4003 is The data voltage of the data storage section connected to G2 corresponds to the data of the analog value that is read out. The voltage of the capacitor is converted into digital data and the data is acquired from the data storage section connected to node FG2. .

[0468] In other words, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. By switching the input from high to low, current flows through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D2 " Tran In register 4100, the "V D2 -Vth" is Vth. The current stops. Then, the wiring 4003 is connected to the "V D2 " is read out.

[0469] After acquiring the data of the data storage section connected to the node FG2, the transistor 4300 is In the conductive state, the "V D2 -Vth" is discharged.

[0470] Next, the charge held at node FG1 is distributed to node FG2, and the The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. Then, the wirings 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. , the wiring 4005 and the wirings 4007 to 4009 are set to low level. When the node FG1 is turned on, the charge of the node FG1 is shared with the node FG2.

[0471] Here, the potential after the charge distribution is the written potential "V D1 -Vth". Therefore, the capacitance value of the capacitance element 4600 is set to be larger than the capacitance value of the capacitance element 4500. Alternatively, the potential "V D1 -Vth" is the same data The potential "V D2 It is preferable to set the capacitance value to be larger than "-Vth". By changing the ratio of the potential and increasing the potential to be written in advance, the potential after the charge distribution can be reduced. The change in potential due to the distribution of charge will be described later.

[0472] Next, a data voltage is read from the data storage unit connected to the node FG1 (hereinafter, read This is called read-out operation 2.

[0473] In the read operation 2, the wiring 4003, which is precharged and then put into an electrically floating state, The wirings 4005 to 4008 are set to a low level. The signal is set to high level during precharge and then to low level. By making the node FG2 in an electrically floating state into a potential of "V D1 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. As a result, the potential of the wiring 4003, which is in an electrically floating state, is reduced. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When gs becomes the Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D1 -Vth" or Vth is larger than the D1 The potential of the wiring 4003 is the node FG The analog value data read out corresponds to the data voltage of the data storage section connected to 1. The voltage undergoes A / D conversion, and data is acquired from a data storage section connected to node FG1. The above is the operation of reading out the data voltage to the data holding unit connected to node FG1.

[0474] In other words, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. By switching the input from high to low, current flows through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D1 " Tran In register 4100, the "V D1 -Vth" is Vth. The current stops. And the wiring 4003 is connected to the "V D1 " is read out.

[0475] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, multiple data For example, the data voltage can be read from the data storage unit. FG2 stores 4 bits (16 values) of data each, for a total of 8 bits (256 values) In FIG. 31, the first layer 4021 to the third layer 4022 can hold data. The semiconductor device is configured with the layer 4023, but by forming further layers, It is possible to increase the storage capacity without increasing the product.

[0476] The potential that is read out is a voltage that is Vth higher than the written data voltage. Therefore, the "V D1 -Vth" or "V D2 - As a result, the Vth of the memory cell can be offset. This improves the memory capacity per memory and makes the read data closer to the correct data. This makes it possible to obtain data with excellent reliability.

[0477] 32 is a cross-sectional view of the semiconductor device corresponding to FIG. 31. The semiconductor device shown in FIG. , transistor 4100, transistor 4200, transistor 4300, transistor 4400, a capacitor 4500, and a capacitor 4600. 100 is formed in a first layer 4021, a transistor 4200, a transistor 4300, The capacitor 4500 is formed in the second layer 4022. The capacitor 4600 is formed in the third layer 4023 .

[0478] Here, the description of the transistor 3300 is used as the transistors 4200 to 4400. The transistor 4100 can be described with reference to the description of the transistor 3200. The description in Figure 28 can also be taken into consideration as appropriate for other wiring, insulators, etc.

[0479] In the capacitance element 3400 of the semiconductor device shown in FIG. 28, the conductive layer is provided parallel to the substrate. In the capacitor elements 4500 and 4600, a conductive layer is formed in a trench shape. By using such a configuration, the occupied area is the same. Even if the capacitance is large, a large capacitance value can be ensured.

[0480] <Storage device 4> The semiconductor device shown in FIG. 27C includes a transistor 3500 and a sixth wiring 3006. This is different from the semiconductor device shown in FIG. It is possible to write and hold information by the same operation as the device. The transistor 3500 may be the same as the transistor 3200 described above.

[0481] The sixth wiring 3006 is electrically connected to the gate of the transistor 3500. One of the source and drain of the transistor 3500 is electrically connected to the drain of the transistor 3200. The other of the source and drain of the transistor 3500 is electrically connected to a third wiring 3003. Connected.

[0482] FIG. 33 is a cross-sectional view of the semiconductor device shown in FIG. 33 and 34 show an example of a cross section approximately perpendicular to the A1-A2 direction. The semiconductor device shown in C) has five layers, ie, layers 1627 to 1631. The layer 1627 is The transistors 3200 to 3600 are included. The layers 1628 and 1629 are It has a transistor 3300.

[0483] Layer 1627 is a layer that connects substrate 1400 and transistors 3200 to 3200 on substrate 1400. 3600, an insulator 1464 on the transistor 3200, etc., and plugs such as plug 1541. The plugs 1541 and the like are, for example, gate electrodes and source electrodes of the transistors 3200 and the like. The plug 1541 is connected to the insulator 1464 so as to fill the insulator 1464. It is preferable that the ion exchange film is formed in the above-mentioned manner.

[0484] The transistors 3200 to 3600 are the same as those of the transistor 2200. Please refer to the above for further information.

[0485] The insulator 1464 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitrogen. Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride Aluminum or the like may be used.

[0486] Insulator 1464 is made by sputtering, CVD (thermal CVD, MOCVD, PECVD The thin film can be formed by a method such as a GaN thin film deposition method, an MBE method, an ALD method, or a PLD method. In particular, when the insulator is formed into a film by a CVD method, preferably a plasma CVD method, the coating property is excellent. In addition, in order to reduce damage caused by plasma, The CVD method, the MOCVD method or the ALD method is preferred.

[0487] As the insulator 1464, silicon carbonitride is used. Silicon oxycarbide, silicon oxycarbide, etc. In addition, USG (Undoped Silicate Glass), BPS G(Boron Phosphorus Silicate Glass), BSG(B orosilicate glass) can be used. USG, BPSG, etc. The film may be formed by atmospheric pressure CVD. For example, HSQ (hydrogen silsesquioxane) may be used. The insulating layer 11 may be formed by using a coating method.

[0488] The insulator 1464 may be a single layer, or may be a laminate of multiple materials.

[0489] Here, in FIG. 33, the insulator 1464 is insulator 1464a and the insulator on the insulator 1464a. An example of two layers with 1464b is shown below.

[0490] The insulator 1464a is disposed between the region 1476 of the transistor 3200, the transistor 3200, etc. It is preferable that the insulating layer has good adhesion and coverage with the conductor 1454 functioning as a gate.

[0491] An example of the insulator 1464a is silicon nitride formed by a CVD method. Here, it may be preferable that the insulator 1464a contains hydrogen. By having such a material, defects in the substrate 1400 can be reduced, and the transistors 3200, etc. For example, the substrate 1400 may be made of a material having silicon. In this case, defects such as dangling bonds of silicon can be terminated by hydrogen. .

[0492] Here, the conductor under the insulator 1464a, such as the conductor 1454, and the insulator, such as the conductor 1511, It is preferable that the parasitic capacitance formed between 1464b and the conductor formed on it is small. Therefore, it is preferable that the insulator 1464b has a low dielectric constant. It has a lower dielectric constant than the insulator 1462 that serves as the gate insulator, such as Transistor 3200. It is preferable that the insulator 1464b has a lower dielectric constant than the insulator 1464a. For example, the relative dielectric constant of the insulator 1464b is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of insulator 1464b is 0.5 times that of insulator 1464a. It is preferably 7 times or less, and more preferably 0.6 times or less.

[0493] As an example, silicon nitride is used for the insulator 1464a and USG is used for the insulator 1464b. There can be.

[0494] Here, the insulator 1464a and the insulator 1581a are made of silicon nitride or silicon carbonitride. By using materials with low copper permeability such as fluorine, when copper is used for conductor 1511, etc. In addition, when the diffusion of copper into the upper and lower layers of the insulator 1464a and the insulator 1581a can be suppressed, There is a match.

[0495] In addition, for example, impurities such as copper may be present in the upper layer from the upper surface of the conductor 1511 through the insulator 1584 or the like. Therefore, the insulator 1584 on the conductor 1511 is made of non-ferrous metal such as copper. It is preferable to use a material with low pure permeability. For example, the insulator 1584 is A layered structure may be used, such as the layered structure of 581a and the insulator 1581b.

[0496] Layer 1628 includes insulator 1581, insulator 1584 on insulator 1581, and insulator 158 4 and an insulator 1585 on the insulator 1571. Conductors 1511 etc. on the body 1464, plugs 1543 etc. connecting to the conductors 1511 etc., The conductor 1511 is disposed on the insulator 1571. It is preferable that the plug 1543 is formed so as to fill the opening. It is preferable that the conductor 1513 is formed so as to fill the opening of the insulator 1571. , preferably formed to fill the opening in the insulator 1585.

[0497] The layer 1628 may also include a conductor 1413. The conductor 1413 may be formed by insulating the insulator 158. It is preferable that the insulating layer 5 is formed so as to fill the opening of the insulating layer 5 .

[0498] The insulators 1584 and 1585 may be, for example, silicon oxide, silicon oxynitride, Silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, oxynitride Aluminum, aluminum nitride, or the like may be used.

[0499] The insulators 1584 and 1585 are formed by sputtering, CVD (thermal CVD, M OCVD, PECVD, etc.), MBE, ALD, or PLD methods In particular, the insulator can be formed by a CVD method, preferably a plasma CVD method. It is preferable to form a film by plasma since it is possible to improve the covering property. To reduce the image, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0500] In addition, silicon carbide, silicon carbonitride ( Silicon carbonitride, silicon carbide oxide xycarbide, etc. can be used. USG (Undoped Si licate Glass), BPSG (Boron Phosphorus Sili cate Glass), BSG (Borosilicate Glass), etc. USG, BPSG, etc. can be formed by using the atmospheric pressure CVD method. For example, HSQ (hydrogen silsesquioxane) or the like may be formed by using a coating method.

[0501] The insulators 1584 and 1585 may be single-layered or may be laminated with a plurality of materials. stomach.

[0502] The insulator 1581 may be formed by stacking multiple layers. For example, as shown in FIG. The body 1581 is made up of two layers: an insulator 1581a and an insulator 1581b on the insulator 1581a. Good too.

[0503] The plug 1543 also has a protrusion on the insulator 1571 .

[0504] Metal materials as the conductor 1511, the conductor 1513, the conductor 1413, the plug 1543, etc. Conductive materials such as metal oxide materials, alloy materials, or metal oxide materials can be used. Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, niobium, molybdenum Metals such as lithium, silver, tantalum, or tungsten, or alloys that contain these as their main components. Gold can be used as a single layer or a multilayer structure. Tungsten nitride, nitride Metal nitrides such as molybdenum and titanium nitride can be used.

[0505] Here, the conductors such as the conductor 1511 and the conductor 1513 are the same as those of the semiconductor device shown in FIG. It is preferable that the conductor functions as a wiring. Therefore, the conductor is used as a wiring or a wiring layer. These conductors are connected by plugs such as plug 1543. It is preferable.

[0506] The insulator 1581 may be the same as that of the insulator 1464. A layer may be used, or multiple materials may be laminated. An example of two layers, an insulator 1581a and an insulator 1581b on the insulator 1581a, is shown. Regarding materials that can be used for the insulators 1581a and 1581b and methods of forming them, The materials and shapes that can be used for the insulator 1464a and the insulator 1464b are shown in FIG. The description of the synthesis method can be found in the literature.

[0507] As an example of the insulator 1581a, silicon nitride formed by a CVD method can be used. Here, a semiconductor element included in the semiconductor device shown in FIG. 00, etc., hydrogen diffuses into the semiconductor element, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferable to use a film that releases less hydrogen as the insulator 1581a. The amount of desorption of hydrogen can be analyzed, for example, by TDS. The amount of hydrogen desorption from 81a was 100% in the range of 50°C to 500°C in TDS. The amount of desorption converted into atoms is, for example, 5 × 10 20 atoms / cm 3 Less than or equal to 2 x 10 20 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 Below Alternatively, the amount of desorption of the insulator 1581a converted into hydrogen atoms is For example, 5×10 15 atoms / cm 2 Less than or equal to 2 x 10 15 atoms / cm 2 Less than or equal to 1×10 15 atoms / cm 2 The following is acceptable.

[0508] In addition, silicon nitride, which has a small amount of hydrogen desorption, can be used not only in the insulator 1581a, but also in the following cases: It may be used for the insulator layer above the insulator 1581a shown in FIG. Instead of the capacitor, an insulator similar to the insulator 104 with reduced hydrogen and water content shown in the above embodiment is used. The body may also be used.

[0509] Moreover, it is preferable that the insulator 1581b has a lower dielectric constant than the insulator 1581a. For example, The relative dielectric constant of the insulator 1581b is preferably less than 4, and more preferably less than 3. The relative dielectric constant of the insulator 1581b is preferably 0.7 times or less than the relative dielectric constant of the insulator 1581a. The ratio is preferably 0.6 or less, and more preferably 0.6 or less.

[0510] The insulator 1571 is preferably formed using an insulating material that has low impurity permeability. For example, it is preferable that the insulator 1571 has low oxygen permeability. It is preferable that the insulator 1571 has low hydrogen permeability. It is preferable that

[0511] The insulator 1571 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or Zirconium, lead zirconate titanate (PZT), strontium titanate (SrTiO 3) Or (Ba,Sr)TiO3 (BST), silicon nitride, etc. are used in a single layer or multilayer. Alternatively, these insulators may be made of, for example, aluminum oxide, bismuth oxide, or Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide Sodium oxide, zirconium oxide, or gallium oxide may be added. The above insulator may be treated with a silicon oxide, a silicon oxynitride, or the like. In particular, aluminum oxide has high resistance to water and hydrogen. This is preferred because of its excellent barrier properties.

[0512] The insulator 1571 may be, for example, silicon carbide, silicon carbonitride, or silicon carbide oxide. etc. may also be used.

[0513] The insulator 1571 is made by laminating a layer of a material with low water and hydrogen permeability with a layer containing another insulating material. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing metal oxide, etc. may be laminated and used.

[0514] For example, the semiconductor device shown in FIG. 27C has an insulator 1571. The elements contained in the conductor 1513, the conductor 1413, etc. are included in the insulator 1571 and the layer thereunder (insulator This can suppress diffusion into the layers (eg, layer 1584, insulator 1581, layer 1627, etc.).

[0515] Here, when the dielectric constant of the insulator 1571 is higher than that of the insulator 1584, the dielectric constant of the insulator 1571 is The thickness of the film is preferably smaller than that of the insulator 1584. The dielectric constant is preferably 0.7 times or less, more preferably 0. For example, the thickness of the insulator 1571 is preferably 5 nm or more and 200 nm or less. The thickness of the insulator 1584 is preferably 5 nm or more and more preferably 60 nm or less. The thickness is preferably 30 nm or more and 800 nm or less, and more preferably 50 nm or more and 500 nm or less. Also, for example, the thickness of the insulator 1571 is one-third or less of the thickness of the insulator 1584. preferable.

[0516] FIG. 33 is a cross-sectional view showing a part of the components of the semiconductor device shown in FIG. The insulator 1464b and the plug 15 formed to be embedded in the insulator 1464b are 41, an insulator 1581 on the insulator 1464b, and a plug 1541 and an insulator 1464 conductor 1511 on b, insulator 1584 on insulator 1481, and insulator 1584 on insulator 1584. The edge 1571, the insulator 1584 and the insulator 1571 are formed so as to be embedded therein. a plug 1543 located on the conductor 1511, an insulator 1585 on the insulator 1571, 33. The conductor 1513 on the plug 1543 and the insulator 1571 is shown. In the cross section, the height of the highest region of the upper surface of the plug 1543 is the height of the insulator 1571. It is preferable that the height of the upper surface of the insulating film is higher than the height of the highest region of the upper surface of the insulating film.

[0517] In addition, the opening for forming the conductor 1513 is formed by removing a part of the insulator 1571. There is.

[0518] Here, as an example, silicon nitride is used as the insulator 1464a and carbon is used as the insulator 1581a. Silicon nitride is used. Here, at least one of the insulator 1571a and the insulator 1571 is A material with low hydrogen permeability is used for the conductor 1513b. By using silicon nitride or silicon carbonitride, hydrogen in the silicon nitride or silicon carbonitride is converted into transistor 3. This can prevent the spread to 300.

[0519] Layer 1629 includes transistor 3300 and plugs such as plug 1544 and plug 1544b. The plugs, such as plug 1544 and plug 1544b, are formed by arranging the layer 1628 in a groove. The conductor 1513, the gate electrode, the source electrode, or the like of the transistor 3300 The transistor 3300 is configured in the same manner as the transistor 20. The descriptions in Jista 2100 and other models can be taken into consideration.

[0520] The transistor 3300 includes a conductor 1413, an insulator 1571a, an insulator 1402, and a conductor 1416a, conductor 1416b, conductor 1404, insulator 1408, and insulator 591. The configuration of the transistor 3300 can be understood by taking into consideration the configuration of the transistor 20. The conductor 1413 is the conductor 102, the insulator 1571a is the insulator 103, and the insulator 14 102 is an insulator 104, conductor 1416a is a conductor 108a, and conductor 1416b is a conductor 108b. 08b, the conductor 1404 is the conductor 114, the insulator 1408 is the insulator 116, and the insulator 591 In addition, in FIG. Although an insulator corresponding to the insulator 105 in the figure is not shown, it is of course possible to provide such an insulator. For example, a layer corresponding to the insulator 105 may be provided between the insulator 1585 and the insulator 1571a. An insulator may be provided.

[0521] As in the above embodiment, the insulator 1571 corresponds to the insulator 106a of the transistor 20. A laminate of insulators (insulator 1585 in this embodiment) is provided between the insulators. The amount of water or hydrogen contained in the laminate of the insulator 1571a and the insulator 1402 is small. As described above, the insulator 1571 is preferably an insulator having a function of blocking water and hydrogen. As an insulator, the oxide that becomes the insulator 106a and the semiconductor 106b of the transistor 20 is When the film is formed, water and hydrogen are supplied to the oxide. a, which is included in the insulator 1402. Therefore, when the oxide is formed into a film, the insulator A laminate of the edge 1585, the insulator 1571a and the insulator 1402, particularly the insulator If the amount of water or hydrogen contained in 1402 is small enough, the oxide will not contain water or hydrogen. The amount of electricity supplied can be reduced.

[0522] The conductor 1416a and the conductor 1416b are plugs formed in contact with their upper surfaces. It is preferable that 1544b be made of a material that has low permeability to the elements contained therein.

[0523] The conductor 1416a and the conductor 1416b may be a laminated film. Thus, conductor 1416a and conductor 1416b form a stack of a first layer and a second layer. Here, a first layer is formed on the oxide layer 406b, and a second layer is formed on the first layer. The first layer is made of, for example, tungsten, and the second layer is made of, for example, tantalum nitride. For example, copper is used for the plugs 1544b. Copper has a low resistance and is suitable for plugs, wiring, etc. It is preferable to use copper as a conductor. On the other hand, copper is easily diffused and is used in the semiconductor layer of a transistor. The diffusion of these elements into the gate insulating film or other parts may degrade the transistor characteristics. The conductor 1416a and the conductor 1416b are made of tantalum nitride, so that the plug In some cases, it may be possible to suppress the copper contained in 1544b etc. from diffusing into the oxide layer 406b.

[0524] In the semiconductor device shown in FIG. 27C of one embodiment of the present invention, plugs, wirings, and the like are used to improve the characteristics of semiconductor elements. When the semiconductor device contains elements and compounds that cause degradation, the elements and compounds may diffuse into the semiconductor device. It is preferable that the structure suppresses the above.

[0525] Layer 1630 includes insulator 1592, conductors such as conductor 1514, and plugs such as plug 1545. The plugs, such as 1545, connect to electrical conductors, such as conductor 1514.

[0526] The layer 1631 includes a capacitor 3400. The capacitor 3400 includes a conductor 1516 and , a conductor 1517, and an insulator 1571. The insulator 1571 is The layer 1631 has a region sandwiched between the insulator 1594 and the conductor 1517. It is preferable to have a plug 1547 on the insulator 1517. The plug 1547 is connected to the insulator 15 It is preferable that the layer 1631 is formed so as to fill the opening of the layer 163. conductor 1516b that connects to a plug having conductor 1516b; and plug 1547 on conductor 1516b. It is preferred that b.

[0527] The layer 1631 may also have a wiring layer connected to the plug 1547 and the plug 1547b. In the example shown in FIG. 33, the wiring layer is a conductor connected to the plug 1547 and the plug 1547b. 1518, etc., plug 1548 on conductor 1518, insulator 1595, and plug 154 8 and an insulator 1599 on the conductor 1519. It is preferable that the insulating material 1595 is formed so as to fill the opening of the insulating material 1595. 599 has an opening over the conductor 1519 .

[0528] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0529] (Embodiment 5) In this embodiment, an imaging device using a transistor according to one embodiment of the present invention An example will be described.

[0530] <Imaging device> An imaging device according to an aspect of the present invention will be described below.

[0531] FIG. 35A is a plan view showing an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) have a plurality of pixels 211 arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 each include a plurality of The pixel 211 is connected to the pixel 211 and has a function of supplying a signal for driving the pixel 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0532] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0533] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuits. The peripheral circuits are a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. Any one or more of these may be omitted.

[0534] As shown in FIG. 35B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0535] <Pixel configuration example 1> The imaging device 200 has a pixel 211 that is composed of a plurality of sub-pixels 212. By combining a filter (color filter) that transmits light of a specific wavelength range with the pixel 212, In this way, information required to realize a color image display can be obtained.

[0536] FIG. 36A is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 36(A) is provided with a color filter that transmits light in the red (R) wavelength range. The subpixel 212 (hereinafter also referred to as "subpixel 212R") transmits light in the green (G) wavelength range. A subpixel 212 (hereinafter also referred to as "subpixel 212G") is provided with a color filter that transmits light through the and a subpixel 212 (hereinafter referred to as The subpixel 212 functions as a photosensor. It is possible to do so.

[0537] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, The wiring 248 and the wiring 249 are respectively represented as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 36A, the sub-pixel 212R of the pixel 211 in the m-th column is written as follows: The wiring 253 connected to the subpixel 212G is disposed as wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as a wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0538] In addition, the imaging device 200 has color filters that transmit light of the same wavelength range for adjacent pixels 211. The sub-pixels 212 in which the filters are provided are electrically connected to each other via the switches. In Figure 36(B), the matrix is ​​arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). A sub-pixel 212 of a pixel 211 arranged in the n+1th row and the mth column adjacent to the pixel 211 is arranged in the n+1th row and the mth column. 36B shows an example of a connection of the sub-pixels 212 of the pixel 211 arranged in the nth row. The sub-pixel 212R arranged in the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are switched. In addition, the sub-pixels 212G arranged in the nth row and the mth column are connected via the n+ The sub-pixels 212G arranged in the first row and the mth column are connected via the switches 202. The sub-pixels 212B arranged in the nth row and the mth column and the sub-pixels 212B arranged in the n+1th row and the mth column are 203.

[0539] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have sub-pixels 211 for detecting light of three different wavelength ranges. By providing 12, a full color image can be obtained.

[0540] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A pixel 211 may include sub-pixels 21 that detect light in four different wavelength ranges. By providing 2, the color reproducibility of the captured image can be further improved.

[0541] Also, for example, in FIG. 36A, a sub-pixel 212 detects light in the red wavelength range, A pixel of the subpixel 212 that detects light in the long wavelength range and a pixel of the subpixel 212 that detects light in the blue wavelength range. The ratio of the number of pixels (or the ratio of the light receiving areas) does not have to be 1:1:1. The area ratio may be a Bayer array with red:green:blue=1:2:1. The ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0542] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy is increased and imaging The reliability of the device 200 can be improved.

[0543] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0544] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0545] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 37A, a lens 255 and a filter 25 formed in a pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0546] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 37(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0547] As the photoelectric conversion element 220 shown in FIG. 37, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0548] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0549] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 22 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 0 can be achieved.

[0550] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0551] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the above will be described.

[0552] 38(A) and 38(B) are cross-sectional views of elements constituting an imaging device. The imaging device shown in A) has a silicon-based transistor provided on a silicon substrate 300. 351, a transistor using an oxide semiconductor stacked on the transistor 351 352 and a transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 3 70 and a wiring 371. The lead 361 has an electrical connection with the plug 370 through the low resistance region 363 .

[0553] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and in contact with layer 320, and includes transistors 352 and 353. A layer 330 is provided in contact with the layer 330 and has wiring 372 and wiring 373. It has 40.

[0554] In the example of the cross-sectional view of FIG. 38(A), the transistor 35 is disposed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the surface opposite to the surface on which the photodiode 1 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. This makes it possible to form pixels with a high aperture ratio. The light receiving surface of 360 may be the same as the surface on which the transistor 351 is formed.

[0555] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 31 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0556] If the pixel is constructed using only silicon transistors, layer 330 can be omitted. An example of a cross-sectional view in which the layer 330 is omitted is shown in FIG.

[0557] The silicon substrate 300 may be an SOI substrate. Instead, germanium, silicon germanium, silicon carbide, gallium arsenide, and aluminum arsenide The substrate has a gallium nitride, indium phosphide, gallium nitride or organic semiconductor. You can also be there.

[0558] Here, a layer 310 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 330 having the resistor 352 and the transistor 353. However, the position of the insulator 380 is not limited.

[0559] The hydrogen in the insulator provided near the channel forming region of the transistor 351 is converted into silicon diaphragm. This has the effect of terminating the ring bond and improving the reliability of the transistor 351. , hydrogen in an insulator provided near the transistor 352 and the transistor 353, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 52 and the transistor 353. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 380 having a function of blocking hydrogen is provided between them. It is preferable to provide the insulator 380. By confining hydrogen below the insulator 380, the transistor The reliability of the insulator 351 can be improved. Since hydrogen diffusion to layers above 380 can be suppressed, the transistors 352 and This can improve the reliability of the transistor 353 and the like.

[0560] As the insulator 380, for example, an insulator having a function of blocking oxygen or hydrogen is used. There are.

[0561] In the cross-sectional view of FIG. 38(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0562] Also, as shown in FIGS. 39(A1) and 39(B1), part or all of the imaging device may be curved. FIG. 39(A1) shows the state where the imaging device is curved in the direction of the dashed-dotted line X1-X2 in the figure. FIG. 39(A2) is a cross-sectional view of the part indicated by the dashed-dotted line X1-X 2 in FIG. 39(A1). FIG. 39(A3) is a cross-sectional view of the part indicated by the dashed-dotted line Y1- Y2 in FIG. 39(A1).

[0563] FIG. 39(B1) shows the state where the imaging device is curved in the direction of the dashed-dotted line X3-X4 in the figure and is also curved in the direction of the dashed-dotted line Y3-Y4 in the figure. FIG. 39(B2) is a cross-sectional view of the part indicated by the dashed-dotted line X3-X4 in FIG. 39(B1). FIG. 39(B3) is a cross-sectional view of the part indicated by the dashed-dotted line Y3-Y4 in FIG. 39(B1).

[0564] By curving the imaging device, curvature of field and aberration can be reduced. Therefore, the optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lens elements for aberration correction can be reduced, miniaturization and weight reduction of an electronic device or the like using the imaging device can be achieved. Also, the quality of the captured image can be improved .

[0565] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0566] (Embodiment 6) In this embodiment, an example of a CPU including a semiconductor device such as a transistor according to an aspect of the present invention and the above-described memory device will be described.

[0567] <Configuration of CPU> FIG. 40 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0568] The CPU shown in FIG. 40 includes an ALU 1191 (ALU: Arithmetic logic unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on a separate chip. The CPU shown in FIG. 40 is merely an example showing a simplified configuration. There are many different configurations depending on the application. For example, the CPU or arithmetic circuit shown in FIG. A configuration including the above is considered as one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is as follows: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0569] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0570] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0571] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0572] In the CPU shown in FIG. 40, a memory cell is provided in a register 1196. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0573] In the CPU shown in FIG. 40, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of the Select whether to hold data by flip-flops. If the power supply voltage is set to 0, the power supply voltage is supplied to the memory cells in the register 1196. If data retention is selected for the capacitive element, data is rewritten to the capacitive element. This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped.

[0574] FIG. 41 is a circuit diagram of an example of a storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a A circuit 1202 that prevents stored data from volatilizing when the circuit is turned off, a switch 1203, and a switch 1204. 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0575] Here, the above-mentioned memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential at which the transistor 1209 is turned off is continuously input. For example, the gate of the transistor 1209 is grounded via a load such as a resistor. .

[0576] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conductive or non-conductive state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The conductive or non-conductive state of transistor 1214 is selected.

[0577] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0578] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0579] A control signal WE is input to the gate of the transistor 1209. and the switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first and second terminals of one switch is selected. When the terminals of the switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. It becomes.

[0580] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 41, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. The signal is then input to the circuit 1201.

[0581] In FIG. 41, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0582] In addition, in FIG. 41, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed at 0 can be used. The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements besides the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor having a capacitance of 100 .mu.m.

[0583] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0584] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0585] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor The off-current is significantly lower than that of transistors with a channel formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitance element 1208 is maintained for a long period of time even while the power supply voltage is not supplied to the In this way, the memory element 1200 can retain its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0586] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0587] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the state of the transistor 1210 is changed according to the signal held by the capacitor 1208. The state (conducting or non-conducting) of the transistor 1202 can be determined and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original The signal can be read out accurately.

[0588] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0589] Although the memory element 1200 has been described as being used as a CPU, the memory element 1200 can also be used as a DSP ( Digital Signal Processor), Custom LSI, PLD (Pr LSIs such as grammable logic devices, RF (Radio Frequency It can also be applied to low-requency devices.

[0590] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0591] (Embodiment 7) In this embodiment, a display device including a transistor according to one embodiment of the present invention will be described. This will be described with reference to FIG. 42 and FIG.

[0592] <Display device configuration> Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, etc. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose luminance can be controlled, specifically inorganic EL (Electroluminescent) The following is an example of a display device. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0593] The display device described below is a panel in which a display element is sealed, and a control circuit is attached to the panel. This includes modules in which ICs including controllers are mounted.

[0594] The display device described below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and TCP with printers A module or display element with a printed wiring board has an IC (integrated circuit) mounted on it by the COG method. The display device also includes all modules mounted on the display device.

[0595] FIG. 42 illustrates an example of an EL display device according to one embodiment of the present invention. FIG. 42(B) is a top view showing the entire EL display device. FIG. 42(C) is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 42(B). .

[0596] FIG. 42A is an example of a circuit diagram of a pixel used in an EL display device.

[0597] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple When multiple locations are anticipated, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements) By specifying the connection destinations of only some of the terminals on It may be possible to configure a clear embodiment.

[0598] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if the function is specified, one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0599] The EL display device shown in FIG. 42(A) includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitance element 742 and a light emitting element 719 .

[0600] Note that FIG. 42(A) is an example of a circuit configuration, and therefore, if a transistor is added, Conversely, at each node in FIG. It is also possible to avoid adding passive elements.

[0601] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and is electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0602] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switch element 743 is a transistor manufactured through the same process as the transistor 741. By using the transistor 74, the productivity of the EL display device can be improved. As the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0603] FIG. 42B is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealant 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 includes the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively / and the driving circuit 736 may be disposed outside the sealing material 734 .

[0604] FIG. 42(C) is a cross-sectional view of an EL display device corresponding to a part of the dashed line MN in FIG. 42(B). It is.

[0605] In FIG. 42C, a conductor 704 a on a substrate 700 and a conductor An insulator 712a on the body 704a, an insulator 712b on the insulator 712a, and an insulator 712 Semiconductor 706a and semiconductor 706b are located on conductor 704a and overlap with semiconductor 706b. Conductors 716a and 716b in contact with semiconductor 706a and semiconductor 706b, respectively. 6b, an insulator 718a on the conductor 716a and on the conductor 716b, and an insulator 718a an insulator 718b on the insulator 718b; an insulator 718c on the insulator 718c; The semiconductor 706b and the conductor 714a overlap each other. The structure of 41 is just an example, and the structure may be different from that shown in FIG.

[0606] Therefore, in the transistor 741 shown in FIG. The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as gate electrodes. The conductor 714a functions as a gate insulator, and the conductor 714b functions as a gate electrode. The electrical characteristics of the semiconductors 706a and 706b may vary when exposed to light. Therefore, any of the conductors 704a, 716a, 716b, and 714a It is preferable that one or more of them has a light-shielding property.

[0607] The interface between the insulator 718a and the insulator 718b is shown by a dashed line. For example, insulators 718a and 718b may not be clearly defined. Th...

Claims

[Claim 1] Semiconductors and a first insulator having a region in contact with the semiconductor; a first conductor having a region in contact with the first insulator and a region overlapping with the semiconductor via the first insulator; a second conductor and a third conductor having a region in contact with the semiconductor; A semiconductor device, wherein any one or more of the first to third conductors contains tungsten and one or more elements selected from the group consisting of silicon, carbon, germanium, tin, aluminum, and nickel.

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