Printed wiring board

Abstract

To provide a printed wiring board that can reduce the difference in cross-sectional area between a portion of a wiring near a power feed position and a portion of the wiring away from the power feed position.SOLUTION: A printed wiring board 100 includes a base film 10 having a main surface, a wiring 20 disposed on the main surface, a first plating lead 60 branching off from a first position P1 of the wiring 20, and a second plating lead 70 branching off from a second position P2 of the wiring 20. The cross-sectional area of the wiring at a third position P3 of the wiring 20, which is an intermediate position between the first position P1 and the second position P2, is 95 percent or more of the cross-sectional area of the wiring at the first position P1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a printed wiring board. This application claims priority based on Japanese Patent Application No. 2021-106969, filed on June 28, 2021. All contents of the Japanese patent application are incorporated herein by reference. [Background technology]

[0002] For example, JP 2016-9854 A (Patent Document 1) describes a printed wiring board. The printed wiring board described in Patent Document 1 has a base film and wiring arranged on a main surface of the base film. The wiring has a seed layer arranged on the main surface of the base film, a core body arranged on the seed layer, and a shrink layer covering the core body. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-9854 A Summary of the Invention

[0004] The printed wiring board of the present disclosure includes a base film having a main surface, a wiring disposed on the main surface, a first plated lead connected to a first position of the wiring, and a second plated lead connected to a second position of the wiring, the cross-sectional area of ​​the wiring at a third position of the wiring, which is an intermediate position between the first position and the second position, is 95 percent or more of the cross-sectional area of ​​the wiring at the first position. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view of a printed wiring board 100. FIG. [Diagram 2] FIG. 2 is a bottom view of the printed wiring board 100. FIG. [Diagram 3]FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a process diagram showing a method for manufacturing printed wiring board 100. [Diagram 5] FIG. 5 is a cross-sectional view of the base film 10 after the seed layer forming step S21 has been performed. [Figure 6] FIG. 6 is a cross-sectional view of the base film 10 after the resist formation step S22 has been performed. [Figure 7] FIG. 7 is a cross-sectional view of the base film 10 after the first electrolytic plating step S23 has been performed. [Figure 8] FIG. 8 is a cross-sectional view of the base film 10 after the resist removal step S24 has been performed. [Figure 9] FIG. 9 is a cross-sectional view of the base film 10 after the seed layer removal step S25 has been performed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Problem that this disclosure aims to solve] In forming wiring for a printed wiring board described in Patent Document 1, first, a seed layer is formed on the main surface of a base film. Second, a resist having openings is formed on the seed layer. Third, an electric current is passed through the seed layer, thereby performing electrolytic plating (first electrolytic plating) on ​​the seed layer exposed from the openings in the resist. This forms a core body. Third, the seed layer between the resist and the core body is removed, and then an electric current is passed through the core body, thereby performing electrolytic plating (second electrolytic plating) so as to cover the core body. This forms a shrink layer.

[0007] In the second electrolytic plating process, the voltage applied to the portion of the core far from the power feed position is lower than the voltage applied to the portion of the core near the power feed position. Therefore, the thickness of the shrink layer is smaller in the portion of the wiring far from the power feed position. In other words, the cross-sectional area of ​​the portion of the wiring far from the power feed position is smaller, and the electrical resistance value is increased.

[0008] The present disclosure has been made in consideration of the problems of the conventional techniques as described above. More specifically, the present disclosure provides a printed wiring board capable of reducing the difference in cross-sectional area between a portion of a wiring near a power feed position and a portion of a wiring far from the power feed position.

[0009] [Effects of this disclosure] According to the printed wiring board of the present disclosure, it is possible to reduce the difference in cross-sectional area between the portion of the wiring near the power feed position and the portion of the wiring away from the power feed position.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] (1) A printed wiring board according to an embodiment includes a base film having a main surface, wiring disposed on the main surface, a first plated lead connected to a first position of the wiring, and a second plated lead connected to a second position of the wiring. A cross-sectional area of ​​the wiring at a third position of the wiring, which is an intermediate position between the first position and the second position, is 95 percent or more of a cross-sectional area of ​​the wiring at the first position.

[0012] According to the printed wiring board of (1) above, it is possible to reduce the difference in cross-sectional area between the portion of the wiring near the power feed position and the portion of the wiring away from the power feed position.

[0013] (2) In the printed wiring board of (1) above, the wiring may have a seed layer disposed on a main surface, a first electrolytic plating layer disposed on the seed layer, and a second electrolytic plating layer covering the seed layer and the first electrolytic plating layer. The thickness of the second electrolytic plating layer at the third position may be 8 μm or less.

[0014] (3) In the printed wiring board of (1) or (2) above, the electrical resistance value of the first plating lead between the end of the first plating lead opposite the wiring and the first position may be 1 Ω or less, and the electrical resistance value of the wiring and the first plating lead between the end of the first plating lead opposite the wiring and the third position may be 5 Ω or more and 6 Ω or less.

[0015] (4) In the printed wiring boards according to (1) to (3) above, the wiring may have at least one coil formed by winding the wiring in a spiral shape on the main surface.

[0016] (5) In the printed wiring boards of (1) to (4) above, the end of the first plated lead opposite the wiring and the end of the second plated lead opposite the wiring may reach an end of the base film.

[0017] [Details of the embodiment of the present disclosure] Next, details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0018] (Configuration of the printed wiring board according to the embodiment) The configuration of a printed wiring board according to an embodiment (referred to as "printed wiring board 100") will be described below.

[0019] Fig. 1 is a plan view of the printed wiring board 100. Fig. 2 is a bottom view of the printed wiring board 100. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. As shown in Figs. 1, 2, and 3, the printed wiring board 100 has a base film 10, wiring 20, a first plated lead 60, and a second plated lead 70.

[0020] The base film 10 is made of a flexible insulating material. In other words, the printed wiring board 100 is a flexible printed wiring board. Specific examples of materials constituting the base film 10 include polyimide, polyethylene terephthalate, and fluororesin.

[0021] The base film 10 has a first main surface 10a and a second main surface 10b. The second main surface 10b is the surface opposite to the first main surface 10a. The direction from the first main surface 10a to the second main surface 10b is sometimes referred to as the thickness direction of the base film 10.

[0022] The wiring 20 is disposed on the main surface of the base film 10. The wiring 20 has, for example, a first wiring 30, a second wiring 40, and a third wiring 50. The first wiring 30 and the second wiring 40 are disposed on the first main surface 10a. The third wiring 50 is disposed on the second main surface 10b.

[0023] The first wiring 30 has a first end 30a and a second end 30b. The second end 30b is the end opposite to the first end 30a. The first wiring 30 is provided with a terminal 31 and a land 32. The terminal 31 is provided on the first end 30a side of the first wiring 30. The land 32 is provided on the second end 30b side of the first wiring 30.

[0024] The first wiring 30 has a coil 33. The coil 33 is configured by winding the first wiring 30 in a spiral shape on the first main surface 10a. The first end 30a is located outside the coil 33 in a plan view (when viewed from a direction perpendicular to the first main surface 10a). The second end 30b is located inside the coil 33 in a plan view.

[0025] The second wiring 40 has a first end 40a and a second end 40b. The second end 40b is the end opposite to the first end 40a. The second wiring 40 is provided with a terminal 41 and a land 42. The terminal 41 is provided on the first end 40a side of the second wiring 40. The land 42 is provided on the second end 40b side of the second wiring 40.

[0026] The third wiring 50 has a first end 50a and a second end 50b. The second end 50b is the end opposite to the first end 50a. The third wiring 50 is provided with a land 51 and a land 52. The land 51 is provided on the first end 50a side of the third wiring 50. The land 52 is provided on the second end 50b side of the third wiring 50.

[0027] The third wiring 50 has a coil 53. The coil 53 is configured by winding the third wiring 50 in a spiral shape on the second main surface 10b. The first end 50a is located outside the coil 53 in a plan view (when viewed from a direction perpendicular to the second main surface 10b). The second end 50b is located inside the coil 53 in a plan view. The coil 53 overlaps with the coil 33 in the thickness direction of the base film 10.

[0028] Through holes 10c and 10d are formed in the base film 10. The through holes 10c and 10d penetrate the base film 10 in the thickness direction. The through hole 10c overlaps with the land 32 and the land 52 in a plan view. The through hole 10d overlaps with the land 42 and the land 51 in a plan view.

[0029] The land 32 and the land 52 are electrically connected by a conductor (not shown) arranged on the inner wall surface of the through hole 10c. The land 42 and the land 51 are electrically connected by a conductor (not shown) arranged on the inner wall surface of the through hole 10d. The first wiring 30, the second wiring 40, and the third wiring 50 are thus integrated as wiring arranged on the base film 10.

[0030] The wiring 20 (first wiring 30, second wiring 40, and third wiring 50) has a seed layer 21, a first electrolytically plated layer 22, and a second electrolytically plated layer .

[0031] The seed layer 21 is disposed on the main surfaces (first main surface 10a and second main surface 10b) of the base film 10. The seed layer 21 has, for example, a first layer and a second layer. The first layer of the seed layer 21 is disposed on the main surfaces (first main surface 10a and second main surface 10b) of the base film 10. The second layer of the seed layer 21 is disposed on the first layer of the seed layer 21.

[0032] The first layer of the seed layer 21 is, for example, a sputtered layer (a layer formed by sputtering). The seed layer 21 is formed of, for example, a nickel-chromium alloy. The second layer of the seed layer 21 is, for example, an electroless plating layer (a layer formed by electroless plating). The second layer of the seed layer 21 is formed of, for example, copper.

[0033] First electrolytic plating layer 22 is a layer formed by electrolytic plating. First electrolytic plating layer 22 is formed of, for example, copper. That is, first electrolytic plating layer 22 is formed of the same material as the second layer of seed layer 21. First electrolytic plating layer 22 is disposed on seed layer 21.

[0034] Second electrolytic plating layer 23 is a layer formed by electrolytic plating. Second electrolytic plating layer 23 is formed of, for example, copper. Second electrolytic plating layer 23 covers seed layer 21 and first electrolytic plating layer 22. More specifically, second electrolytic plating layer 23 is disposed on the side surfaces of seed layer 21 and first electrolytic plating layer 22 and on the upper surface of first electrolytic plating layer 22. The thickness of second electrolytic plating layer 23 is defined as thickness T.

[0035] The first plating lead 60 is connected to a first position P1 of the wiring 20. More specifically, the first plating lead 60 is connected to the first wiring 30. The first position P1 is, for example, on the first end 30a side. The first plating lead 60 is connected to the first end 30a side of the first wiring 30 via a terminal 31. The end of the first plating lead 60 opposite the wiring 20 (first wiring 30) reaches the end of the base film 10. The first plating lead 60 is disposed on the first main surface 10a.

[0036] The second plating lead 70 is connected to a second position P2 of the wiring 20. More specifically, the second plating lead 70 is connected to the second wiring 40. The second position P2 is, for example, on the first end 40a side. The second plating lead 70 is connected to the first end 40a side of the second wiring 40 via a terminal 41. The end of the second plating lead 70 opposite the wiring 20 (second wiring 40) reaches the end of the base film 10. The second plating lead 70 is disposed on the first main surface 10a.

[0037] Although not shown, the first plating lead 60 and the second plating lead 70 have a structure similar to that of the wiring 20 (the first wiring 30, the second wiring 40, and the third wiring 50). That is, the first plating lead 60 and the second plating lead 70 have a seed layer 21, a first electrolytic plating layer 22, and a second electrolytic plating layer 23.

[0038] The position of the wiring 20, which is an intermediate position between the first position P1 and the second position P2, is defined as the third position P3. The third position P3 is farther from the power supply position than the first position P1 and the second position P2. From another perspective, the first position P1 and the second position P2 are closer to the power supply position than the third position. The electrical resistance value of the first plating lead 60 between the end of the first plating lead 60 opposite the wiring 20 and the first position P1 is, for example, 1Ω or less. The electrical resistance value of the wiring 20 and the first plating lead 60 between the end of the first plating lead 60 opposite the wiring 20 and the third position P3 is, for example, 5Ω or more and 6Ω or less. The electrical resistance value of the wiring 20 and the electrical resistance value of the first plating lead 60 are measured by contacting the measurement points with a tester probe.

[0039] The cross-sectional area of ​​the wiring 20 at the third position P3 is 95 percent or more of the cross-sectional area of ​​the wiring 20 at the first position P1. That is, the value obtained by subtracting the cross-sectional area of ​​the wiring 20 at the third position P3 from the cross-sectional area of ​​the wiring 20 at the first position P1 is 5 percent or less of the cross-sectional area of ​​the wiring 20 at the first position P1. The cross-sectional area of ​​the wiring 20 at the third position P3 is 100 percent or less of the cross-sectional area of ​​the wiring 20 at the first position P1. The cross-sectional area of ​​the wiring 20 is measured by the following method. First, an image of a cross section perpendicular to the length direction of the wiring 20 is obtained at the measurement position. This image is obtained using a microscope. This cross section is exposed using a cross-section processing device such as a microtome. Second, the cross-sectional area of ​​the wiring 20 is calculated based on the image of the cross section of the wiring 20 obtained as described above.

[0040] The thickness T at the third position P3 is preferably 8 μm or less. The third position P3 is located on the first wiring 30, for example.

[0041] (Method of Manufacturing Printed Wiring Board 100 According to the Embodiment) A method for manufacturing the printed wiring board 100 will now be described.

[0042] Fig. 4 is a process diagram showing a method for manufacturing printed wiring board 100. As shown in Fig. 4, the method for manufacturing printed wiring board 100 includes a preparation step S1 and a wiring formation step S2. The wiring formation step S2 is performed after the preparation step S1.

[0043] In the preparation step S1, a base film 10 is prepared. In the base film prepared in the preparation step S1, the first wiring 30, the second wiring 40, the first plating lead 60, and the second plating lead 70 are not formed on the first main surface 10a, and the third wiring 50 is not formed on the second main surface 10b. In addition, the base film prepared in the preparation step S1 is not divided into individual pieces.

[0044] In the wiring formation step S2, the wiring 20 is formed. Furthermore, in the wiring formation step S2, a first plating lead 60 and a second plating lead 70 are formed. The wiring formation step S2 is performed using a semi-additive process.

[0045] More specifically, the wiring formation step S2 includes a seed layer formation step S21, a resist formation step S22, a first electrolytic plating step S23, a resist removal step S24, a seed layer removal step S25, and a second electrolytic plating step S26. The resist formation step S22 is performed after the seed layer formation step S21. The first electrolytic plating step S23 is performed after the resist formation step S22. The resist removal step S24 is performed after the first electrolytic plating step S23. The seed layer removal step S25 is performed after the resist removal step S24. The second electrolytic plating step S26 is performed after the seed layer removal step S25.

[0046] Fig. 5 is a cross-sectional view of the base film 10 after the seed layer formation step S21 has been performed. As shown in Fig. 5, in the seed layer formation step S21, a seed layer 21 is formed. The seed layer 21 is formed by sequentially performing sputtering and electroless plating on the main surfaces (the first main surface 10a and the second main surface 10b) of the base film 10.

[0047] FIG. 6 is a cross-sectional view of the base film 10 after the resist formation step S22 has been performed. As shown in FIG. 6, in the resist formation step S22, a resist 80 is formed. The resist 80 is formed by applying a photosensitive organic material onto the seed layer 21 and patterning the applied photosensitive organic material by exposing and developing it. The resist 80 has an opening. The seed layer 21 is exposed from the opening of the resist 80. FIG. 7 is a cross-sectional view of the base film 10 after the first electrolytic plating step S23 has been performed. As shown in FIG. 7, in the first electrolytic plating step S23, a first electrolytic plating layer 22 is formed. The first electrolytic plating layer 22 is formed by passing a current through the seed layer 21 and performing electrolytic plating on the seed layer 21 exposed from the opening of the resist 80.

[0048] Fig. 8 is a cross-sectional view of the base film 10 after the resist removal step S24 has been performed. As shown in Fig. 8, in the resist removal step S24, the resist 80 is peeled off and removed from the seed layer 21. As a result of the removal of the resist 80, the seed layer 21 is exposed between the first electrolytic plating layer 22.

[0049] Fig. 9 is a cross-sectional view of base film 10 after seed layer removal step S25 has been performed. As shown in Fig. 9, in seed layer removal step S25, seed layer 21 exposed between first electrolytic plated layer 22 is removed. Seed layer 21 exposed between first electrolytic plated layer 22 is removed by etching.

[0050] Etching is performed by supplying an etching solution between the first electrolytic plating layer 22. The etching solution is selected so that the etching rate is determined by the reaction between the reactive species in the etching solution and the target to be etched, rather than by the diffusion of reactive species in the etching solution to the vicinity of the target to be etched.

[0051] More specifically, the etching solution used has a dissolution reaction rate of 0.5 μm / min or less with respect to the material (i.e., copper) constituting the second layer of seed layer 21 and first electrolytic plating layer 22. A specific example of such an etching solution is a sulfuric acid / hydrogen peroxide solution.

[0052] After etching of the second layer of seed layer 21 is completed, the etching solution is switched. As the etching solution after the switch, an etching solution having a high selectivity to the material (i.e., nickel-chromium alloy) constituting the first layer of seed layer 21 is used. Therefore, after the switch of the etching solution, etching of first electrolytic plating layer 22 does not progress easily.

[0053] In the second electrolytic plating step S26, the second electrolytic plated layer 23 is formed. The second electrolytic plated layer 23 is formed by electrolytic plating. Power is supplied in the electrolytic plating in the second electrolytic plating step S26 via the seed layer 21 and the first electrolytic plated layer 22 in the portions that will become the first plating lead 60 and the second plating lead 70 after the second electrolytic plating step S26. As a result, the wiring 20 (the first wiring 30, the second wiring 40, and the third wiring 50) having the structure shown in FIGS. 1, 2, and 3 is formed.

[0054] The seed layer 21 and the first electrolytic plating layer 22 included in the first plating lead 60 and the second plating lead 70 extend to the power supply terminals at the ends of the base film 10 before it is singulated. After the second electrolytic plating step S26 is performed, the base film 10 is cut and singulated. Therefore, the first plating lead 60 and the second plating lead 70 extend to reach the ends of the base film 10 after it is singulated.

[0055] (Effects of the Printed Wiring Board According to the Embodiment) The effects of the printed wiring board 100 will be described below.

[0056] The third position P3 is farther from the power supply position in the second electrolytic plating process S26 than the first position P1. Therefore, the thickness T at the third position P3 is likely to be smaller than the thickness T at the first position P1, and as a result, the cross-sectional area of ​​the wiring 20 at the third position P3 is likely to be smaller than the cross-sectional area of ​​the wiring 20 at the first position P1.

[0057] According to intensive studies by the present inventors, in order to reduce the difference between thickness T of the portion of wiring 20 near the power supply position and thickness T of the portion of wiring 20 away from the power supply position, it is effective to reduce the current density of the current flowing through seed layer 21 and first electrolytic plating layer 22 in second electrolytic plating step S26. However, if the current density of the current flowing through seed layer 21 and first electrolytic plating layer 22 in second electrolytic plating step S26 is reduced, the formation rate of second electrolytic plating layer 23 decreases, and the time required for second electrolytic plating step S26 increases.

[0058] In seed layer removal step S25, first electrolytic plating layer 22 is also partially removed when removing the second layer of seed layer 21. Second electrolytic plating layer 23 is formed to compensate for the thinning of first electrolytic plating layer 22 in seed layer removal step S25, so if the amount of first electrolytic plating layer 22 removed in seed layer removal step S25 is small, it is not necessary to form second electrolytic plating layer 23 thick.

[0059] In the seed layer removal step S25, it is difficult to supply an etching solution between the first electrolytic plating layer 22. Therefore, if an etching solution having a high dissolution reaction rate with respect to the material constituting the seed layer 21 (i.e., an etching solution in which the diffusion of reactive species in the etching solution to the vicinity of the etching target determines the etching rate) is used for the etching in the seed layer removal step S25, the etching of the seed layer 21 varies widely. As a result, the amount of etching must be increased in order to reliably remove the seed layer 21, and the first electrolytic plating layer 22 becomes thinner.

[0060] However, if an etching solution having a low dissolution reaction rate with respect to the material constituting the seed layer 21 is used for the etching in the seed layer removal process S25 (i.e., if the etching in the seed layer removal process S25 becomes rate-limited by the reaction between the reactive species in the etching solution and the etching target), even if it is difficult to supply the etching solution between the first electrolytic plating layer 22, variation in the etching of the seed layer 21 is unlikely to occur.

[0061] As a result, in printed wiring board 100, excessive etching of first electrolytic plated layer 22 in seed layer removal step S25 is suppressed, and the thickness of first electrolytic plated layer 22 is maintained. Therefore, in printed wiring board 100, there is no need to form second electrolytic plated layer 23 thick, and the current density of the current flowing through seed layer 21 and first electrolytic plated layer 22 can be reduced without increasing the time required for second electrolytic plating step S26. In this way, printed wiring board 100 can reduce the difference in cross-sectional area between the portion of wiring 20 near the power supply position and the portion of wiring 20 away from the power supply position.

[0062] The embodiments disclosed herein are illustrative in all respects and should not be considered as limiting. The scope of the present invention is defined by the claims, not the above-described embodiments, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0063] 100 printed wiring board, 10 base film, 10a first main surface, 10b second main surface, 10c, 10d through hole, 20 wiring, 21 seed layer, 22 first electrolytic plating layer, 23 second electrolytic plating layer, 30 first wiring, 30a first end, 30b second end, 31 terminal, 32 land, 33 coil, 40 second wiring, 40a first end, 40b second end, 41 terminal, 42 land, 50 third wiring, 50a first end, 50b second end, 51, 52 land, 53 coil, 60 first plating lead, 70 second plating lead, 80 resist, P1 first position, P2 second position, P3 third position, S1 preparation step, S2 wiring formation step, S21 seed layer formation step, S22 resist formation step, S23 first electrolytic plating step, S24 S25 resist removal step, S25 seed layer removal step, S26 second electrolytic plating step, T thickness.

Claims

1. A base film having a main surface; Wiring disposed on the main surface; a first plating lead connected to a first location of the wiring; a second plating lead connected to a second location of the wiring; A printed wiring board, wherein a cross-sectional area of ​​the wiring at a third position, which is an intermediate position between the first position and the second position, is 95 percent or more of the cross-sectional area of ​​the wiring at the first position.

2. the wiring has a seed layer disposed on the main surface, a first electrolytic plating layer disposed on the seed layer, and a second electrolytic plating layer covering the seed layer and the first electrolytic plating layer, The printed wiring board according to claim 1 , wherein the second electrolytic plating layer at the third location has a thickness of 8 μm or less.

3. an electrical resistance value of the first plating lead between an end of the first plating lead opposite to the wiring and the first position is 1 Ω or less; The printed wiring board according to claim 1 , wherein an electrical resistance value of the wiring and the first plating lead between an end of the first plating lead opposite the wiring and the third position is 5Ω or more and 6Ω or less.

4. 2. The printed wiring board according to claim 1, wherein the wiring has at least one coil configured by winding the wiring in a spiral shape on the main surface.

5. The printed wiring board according to claim 1 , wherein an end of the first plated lead opposite the wiring and an end of the second plated lead opposite the wiring reach an end of the base film.

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