Printed wiring board

Abstract

To provide a high quality printed wiring board.SOLUTION: A printed wiring board includes a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component, a connecting conductor layer located under the mounting conductor layer and having a connecting wiring that electrically connects the first electrode and the second electrode, a resin insulating layer disposed between the mounting conductor layer and the connecting conductor layer and having a plurality of openings including a first opening and a second opening, a first connecting via conductor formed in the first opening and electrically connecting the first electrode and the connecting wiring, and a second connecting via conductor formed in the second opening and electrically connecting the second electrode and the connecting wiring. The mounting conductor layer, the first connecting via conductor, and the second connecting via conductor are formed of a seed layer and an electrolytic plating layer on the seed layer. The seed layer has a first portion on the resin insulating layer, a second portion on the inner wall surface of the opening, and a third portion on the connecting conductor layer exposed from the opening, and the thickness of the first portion is thicker than the thicknesses of the second portion and the third portion.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a printed wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board having a first conductor layer, an insulating layer formed on the first conductor layer, and a second conductor layer formed on the insulating layer. The insulating layer has a through hole for a via conductor that exposes the first conductor layer. A via conductor that connects the first conductor layer and the second conductor layer is formed in the through hole. The via conductor is formed of an electroless plating layer and an electrolytic plating layer. The insulating layer contains a resin and inorganic particles. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-126103 A Summary of the Invention

[0004] [Problem of Patent Document 1] As shown in FIG. 17 of Patent Document 1, Patent Document 1 has an intermediate layer on the wall surface (inner peripheral surface) of the through hole. The intermediate layer has a complex uneven surface due to gaps formed between inorganic particles. The inorganic particles contained in the intermediate layer are the same as the inorganic particles contained in the insulating layer. As shown in FIG. 18 of Patent Document 1, Patent Document 1 forms an electroless plating film in the through hole. However, if the unevenness is complex, it is considered difficult to completely fill the gap with the electroless plating film. It is considered that when the electroless plating film is deposited, gas generated by the reaction inhibits filling the gap. According to the technology of Patent Document 1, it is considered that the via conductor contains voids. The sidewall of the via conductor of Patent Document 1 is formed on a complex uneven surface. Therefore, it is considered that the via conductor of Patent Document 1 cannot transmit high-speed signals. [Means for solving the problem]

[0005] The printed wiring board of the present invention includes a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component, a connecting conductor layer located under the mounting conductor layer and having a connecting wiring electrically connecting the first electrode and the second electrode, a resin insulating layer disposed between the mounting conductor layer and the connecting conductor layer and having a plurality of openings including a first opening and a second opening, a first connecting via conductor formed in the first opening and electrically connecting the first electrode and the connecting wiring, and a second connecting via conductor formed in the second opening and electrically connecting the second electrode and the connecting wiring. The mounting conductor layer, the first connecting via conductor, and the second connecting via conductor are formed of a seed layer and an electrolytic plating layer on the seed layer. The seed layer has a first portion on the resin insulating layer, a second portion on the inner wall surface of the opening, and a third portion on the connecting conductor layer exposed from the opening, and the thickness of the first portion is thicker than the thickness of the second portion and the thickness of the third portion.

[0006] In the printed wiring board of the embodiment of the present invention, the thickness of the second portion is smaller than the thickness of the first portion. The volume of the opening for the via conductor (first connection via conductor, second connection via conductor, etc.) after the seed layer is formed can be increased. Even if the diameter of the opening for the via conductor is small, the opening for the via conductor can be filled with the electrolytic plating layer. The connecting conductor layer and the via conductor (first connection via conductor, second connection via conductor, etc.) are connected via the third portion. The thickness of the third portion is smaller than the thickness of the first portion. The embodiment can reduce the influence of the third portion. The connection resistance via the third portion is unlikely to be high. A high-quality printed wiring board is provided. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating a printed wiring board according to an embodiment. [Diagram 2] Cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III of FIG. 1. [Figure 4] FIG. 2 is an enlarged cross-sectional view illustrating a portion of the printed wiring board according to the embodiment. [Diagram 5] FIG. 2 is an enlarged cross-sectional view illustrating a portion of the printed wiring board according to the embodiment. [Figure 6] FIG. 4 is an enlarged cross-sectional view illustrating a schematic view of a portion of a seed layer. [Figure 7] FIG. 11 is a cross-sectional view illustrating a printed wiring board according to a modified example of the embodiment. [Figure 8A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8D] 1A to 1C are enlarged cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8E] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8F] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8G] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 8H] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a printed wiring board according to an embodiment. [Figure 9] FIG. 1 is a cross-sectional view showing a schematic diagram of a printed wiring board having three internal conductor layers for connection. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Embodiment] FIG. 1 is a plan view showing a printed wiring board 2 of an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 and FIG. 5 are enlarged cross-sectional views showing a part of the printed wiring board 2 of an embodiment. As shown in FIG. 1 and FIG. 2, the printed wiring board 2 has an upper surface 2a and a lower surface 2b opposite to the upper surface 2a. The printed wiring board 2 has a first mounting area A1 for mounting a first electronic component E1 and a second mounting area A2 for mounting a second electronic component E2. The first mounting area A1 is located directly below the first electronic component E1. The second mounting area A2 is located directly below the second electronic component E2. The circles shown by solid lines in FIG. 1 indicate bumps (metal posts) 241, 242, 243, and 244 for mounting electronic components. The wiring drawn by dotted lines indicates the connection wiring 36 embedded in the printed wiring board 2. Examples of the first electronic component E1 and the second electronic component E2 are electronic components such as logic ICs and memories.

[0009] As shown in Figs. 1 to 3, the printed wiring board 2 has a conductor layer 10, a resin insulating layer (first resin insulating layer) 20, a connecting conductor layer 30, via conductors 41, 42, 141, 142, 143, 144, a resin insulating layer (second resin insulating layer) 120, a mounting conductor layer 130, and bumps 241, 242, 243, 244. As shown in Fig. 2, the via conductors 41, 141, 143 are disposed directly below the first mounting area A1. The bumps 241, 243 are disposed directly above the first mounting area A1. The via conductors 42, 142, 144 are disposed directly below the second mounting area A2. The bumps 242, 244 are disposed directly above the second mounting area A2.

[0010] The connection conductor layer 30 includes a connection wiring 36. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the connection wiring 36. The connection wiring 36 is a part of a path for sending data from the first electronic component E1 to the second electronic component E2. The mounting conductor layer 130 includes electrodes 131, 132, 133, and 134. A bump 241, an electrode 131, and a via conductor 141 are arranged in a path (first path) between the first electronic component E1 and the connection wiring 36. The first path is located directly below the first electronic component E1. A bump 242, an electrode 132, and a via conductor 142 are arranged in a path (second path) between the second electronic component E2 and the connection wiring 36. The second path is located directly below the second electronic component E2. The bump 241, the electrode 131, the via conductor 141, the bump 242, the electrode 132, and the via conductor 142 are also part of the path. The bumps 241 and 242 can be called connection bumps (connection metal posts). The connection bump 241 located directly under the first electronic component E1 is a first connection bump (first connection metal post), and the connection bump 242 located directly under the second electronic component E2 is a second connection bump (second connection metal post). The electrodes 131 and 132 can be called connection electrodes. The connection electrode 131 located directly under the first electronic component E1 is a first connection electrode, and the connection electrode 132 located directly under the second electronic component E2 is a second connection electrode. The via conductors 141 and 142 can be called connection via conductors. The connection via conductor 141 located directly under the first electronic component E1 is a first connection via conductor, and the connection via conductor 142 located directly under the second electronic component E2 is a second connection via conductor. The first connection bump may be called a first bump (first metal post). The first connection electrode may be called a first electrode. The first connection via conductor may be called a first via conductor. The second connection bump may be called a second bump (second metal post). The second connection electrode may be called a second electrode. The second connection via conductor may be called a second via conductor. The first bump, the first electrode, and the first via conductor located directly below the first electronic component E1 and electrically connected to the connection wiring 36 form a first path. The second bump, the second electrode, and the second via conductor located directly below the second electronic component E2 and electrically connected to the connection wiring 36 form a second path.

[0011] The via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 do not form a path. These via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 are electrically connected to a power line or a ground line in the electronic component. These via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 are independent of the connection wiring 36. These via conductors 41, 42, 143, 144, the electrodes 133, 134, and the bumps 243, 244 are not electrically connected to the connection wiring 36.

[0012] 2, the conductor layer 10 includes pads 12 and 14. The pads 12 and 14 are exposed from the lower surface 2b of the printed wiring board 2. The pads 12 and 14 are used for connecting to another printed wiring board or electronic components. The conductor layer 10 is mainly formed of copper.

[0013] The resin insulating layer (first resin insulating layer) 20 is formed on the conductor layer 10. The resin insulating layer 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The second surface 20b of the resin insulating layer 20 forms the lower surface 2b of the printed wiring board 2. The second surface 20b of the resin insulating layer 20 faces the conductor layer 10. The resin insulating layer 20 has openings (openings for via conductors) 21 and 22 that expose the conductor layer 10. The opening 21 is located directly below the first mounting area A1 and exposes the pad 12. The opening 21 extends from the first surface 20a of the resin insulating layer 20 to the pad 12. The opening 22 is located directly below the second mounting area A2 and exposes the pad 14. The opening 22 extends from the first surface 20a of the resin insulating layer 20 to the pad 14. The resin insulating layer 20 is formed of a resin 80 and a large number of inorganic particles 90 dispersed in the resin 80. The resin 80 is an epoxy resin. Examples of the resin are a thermosetting resin and a photosetting resin. The inorganic particles 90 are glass particles. The inorganic particles 90 may be alumina.

[0014] As shown in Figures 2 and 4, the inorganic particles 90 include first inorganic particles 91 and second inorganic particles 92. The second inorganic particles 92 are embedded in the resin insulation layer (first resin insulation layer 20, second resin insulation layer 120, etc.). The first inorganic particles 91 form the inner wall surface of the opening (opening for via conductor). The second inorganic particles 92 have a spherical shape. The shape of the first inorganic particles 91 is obtained by cutting a sphere on a plane. The shape of the first inorganic particles 91 is obtained by cutting the second inorganic particles 92 on a plane. The shapes of the first inorganic particles 91 and the second inorganic particles 92 are different.

[0015] The first surface 20a of the resin insulation layer 20 is formed only from resin 80. The inorganic particles 90 (second inorganic particles 92) are not exposed from the first surface 20a. The first surface 20a does not include the surfaces of the second inorganic particles 92. The first surface 20a of the resin insulation layer 20 does not have any irregularities. The first surface 20a is not roughened. The first surface 20a is formed smoothly.

[0016] As shown in FIG. 4, inner wall surface 23 of an opening (opening for a via conductor) is formed of resin 80 and first inorganic particles 91. FIG. 4 shows opening 21 as a representative example of an opening. First inorganic particles 91 have flat portion 91a. Flat portion 91a forms inner wall surface 23. Inner wall surface 23 is formed of resin 80 and flat portion 91a. Flat portion 91a and the surface of resin 80 forming inner wall surface 23 form a substantially common surface. No irregularities are formed on resin 80 forming inner wall surface 23. The surface of resin 80 forming inner wall surface 23 is smooth. No irregularities are formed on exposed surface 91b of flat portion 91a (surface forming inner wall surface 23). Exposed surface 91b of flat portion 91a is smooth. Inner wall surface 23 is formed smoothly. Arithmetic mean roughness (Ra) of inner wall surface 23 is 1.0 μm or less.

[0017] The flat portion 91a of the first inorganic particle 91 approximately coincides with a surface obtained by extending the surface 80a (the surface forming the inner wall surface 23) of the resin 80 formed around the first inorganic particle 91. The flat portion 91a depicted as a substantially straight line in Figures 2 and 4 means a flat surface. In the cross sections shown in Figures 2 and 4, the flat portion 91a is a flat surface. The flat portion 91a does not have to be a perfect flat surface. The flat portion 91a is a substantially flat surface, which is an approximately smooth surface.

[0018] 4, the inner wall surface 23 of the opening 21 is inclined. The angle (inclination angle) θ1 between the upper surface of the pad 12 and the inner wall surface 23 is not less than 70° and not more than 85°. The upper surface of the pad 12 is included in the upper surface of the conductor layer 10. The angle (inclination angle) θ2 between the first surface 20a of the resin insulating layer 20 and the inner wall surface 23 is not less than 95° and not more than 110°.

[0019] 2 and 4, the shape of the openings for via conductors, such as opening 21, is shown as a substantially inverted trapezoid. However, the shape of the actual openings for via conductors is substantially an inverted truncated cone. Therefore, the inner wall surface (side wall) of the actual openings for via conductors is substantially curved. In other words, the common surface formed by flat portion 91a and resin 80 includes the inner wall surface (side wall) formed as a substantially curved surface.

[0020] The inner wall surface may have a step between the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80 surrounding the first inorganic particle 91 having the exposed surface 91b. The exposed surface 91b is recessed from the surface 80a of the resin 80. Alternatively, the exposed surface 91b protrudes from the surface 80a of the resin 80. For example, a step exists between the exposed surface 91b and the surface 80a of the resin 80. The amount of the step (the distance between the exposed surface 91b and the surface 80a of the resin 80) is 5 μm or less. The amount of the step is preferably 3 μm or less. The amount of the step is more preferably 1.5 μm or less. Even if a step is formed, the step is small, so that the exposed surface 91b and the surface 80a of the resin 80 form an almost common surface.

[0021] The openings 21, 22 formed in the resin insulating layer 20 are similar to each other. The openings 21, 22 formed in the resin insulating layer 20 have similar inner wall surfaces 23, 24. The inner wall surfaces 23, 24 of each of the openings 21, 22 are formed by the surface 80a of the resin 80 and the exposed surfaces 91b of the first inorganic particles 91.

[0022] As shown in FIG. 2 and FIG. 3, the connecting conductor layer (first connecting conductor layer) 30 is formed on the first surface 20a of the resin insulating layer 20. As shown in FIG. 2, the connecting conductor layer 30 includes pads 32, 34 and a connecting wire 36. The connecting wire 36 has one end and the other end opposite to the one end. The pad 32 is a first pad 32 and is directly connected to one end of the connecting wire 36. The pad 34 is a second pad 34 and is directly connected to the other end of the connecting wire 36. The first pad 32 is formed directly below the first mounting area A1. The second pad 34 is formed directly below the second mounting area A2. As shown in FIG. 3, one connecting conductor layer 30 includes a plurality of connecting wires 36. Although not shown, one connecting conductor layer 30 includes a plurality of first pads 32 and a plurality of second pads 34. One first pad 32 and one second pad 34 are connected to both ends of each connecting wire 36. The connection wiring 36 in the connecting conductor layer 30 may include a first pad 32 and a second pad 34. The first pad 32 is included in a first path. The second pad 34 is included in a second path. The pads (first pad 32, second pad 34, etc.) directly connected to the connection wiring 36 may be called connection pads. The first pad 32 may be called a first connection pad. The second pad 34 may be called a second connection pad. The first pad 32 located directly under the first electronic component E1 and directly connected to the connection wiring 36 forms the first path. The second pad 34 located directly under the second electronic component E2 and directly connected to the connection wiring 36 forms the second path.

[0023] The connection wirings 36 are arranged approximately parallel to each other. Among the multiple connection wirings 36, the connection wiring 36 having the smallest width W1 is the smallest connection wiring 36a. The width W1 of the smallest connection wiring 36a is 1 μm or more and 3 μm or less. A space 37 is present between adjacent connection wirings 36. Among the multiple spaces 37, the space 37 having the smallest width G1 is the smallest space 37a. The width G1 of the smallest space 37a is 1 μm or more and 3 μm or less.

[0024] Of the multiple connection wirings 36, the connection wiring 36 having the largest width W2 is the largest connection wiring 36b. The width W2 of the largest connection wiring 36b is 5 μm or less. It is preferable that the width W2 of the largest connection wiring 36b is 3 μm or less. Of the multiple spaces 37, the space having the largest width G2 is the largest space 37b. The width G2 of the largest space 37b is 5 μm or less. It is preferable that the width G2 of the largest space 37b is 3 μm or less.

[0025] The width of each of the connection wires 36 is preferably 1 μm or more and 3 μm or less. The width of each of the spaces 37 is preferably 1 μm or more and 3 μm or less.

[0026] Each of the connection wires 36 has an aspect ratio (thickness / width) of 2.0 or more and 4.0 or less.

[0027] The connecting conductor layer 30 is mainly made of copper. The connecting conductor layer 30 is formed of a seed layer 30a on the first surface 20a of the resin insulating layer 20 and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a is formed by sputtering. The seed layer 30a is formed of a first layer 31a on the first surface 20a of the resin insulating layer 20 and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the first surface 20a of the resin insulating layer 20. For example, the seed layer 30a and the first layer 31a are formed of a copper alloy, and the second layer 31b is formed of copper. The second layer 31b is not essential. The first layer 31a and the second layer 31b are formed by sputtering. Both are sputtering films.

[0028] The first layer 31a is made of an alloy containing copper, aluminum, and a specific metal. Examples of the specific metal are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one type of specific metal, two types of specific metals, or three types of specific metals. The content of aluminum in the alloy is 1.0 at% or more and 15.0 at% or less. An example of the specific metal is silicon. The content of the specific metal in the alloy is 0.5 at% or more and 10.0 at% or less. The first layer 31a may contain impurities. Examples of the impurities are oxygen and carbon. The first layer 31a may contain oxygen or carbon. The first layer 31a may contain oxygen and carbon. In the embodiment, the alloy further contains carbon. The content of carbon in the alloy is 50 ppm or less. The alloy further contains oxygen. The content of oxygen in the alloy is 100 ppm or less. The above content values ​​of each element are examples. The amount of copper is the largest among the elements forming the first layer 31a. The amount of aluminum is next largest. The amount of the specific metal is less than the amount of aluminum. Therefore, copper is the major metal, aluminum is the first minor metal, and the specific metal is the second minor metal. The amount of impurities is less than the amount of the specific metal.

[0029] Second layer 31b is formed of copper. The copper content forming second layer 31b is 99.9 at% or more. It is preferable that the copper content in second layer 31b is 99.95 at% or more. Electrolytically plated layer 30b is formed of copper. The copper content forming electrolytically plated layer 30b is 99.9 at% or more. It is preferable that the copper content in electrolytically plated layer 30b is 99.9 at% or more.

[0030] 4, the seed layer 30a has a first portion P1 on the first surface 20a, a second portion P2 on the inner wall surface 23 of the opening 21, and a third portion P3 on the pad 12 exposed from the opening 21. The third portion P3 is formed on the conductive layer 10 exposed by the opening 21. The seed layer 30a forming the third portion P3 closes the bottom opening of the opening 21. The first layer 31a forming the third portion P3 closes the bottom opening of the opening 21. The bottom opening is located on the upper surface of the pad 12.

[0031] FIG. 6 is an enlarged cross-sectional view showing a portion of the seed layer 30a. FIG. 6(a) shows the portion indicated by reference character VI-1 in FIG. 4 (first portion P1). FIG. 6(b) shows the portion indicated by reference character VI-2 in FIG. 4 (second portion P2). FIG. 6(c) shows the portion indicated by reference character VI-3 in FIG. 4 (third portion P3). As shown in FIG. 6, the thickness T1 of the first portion P1 is thicker than the thickness T2 of the second portion P2 and the thickness T3 of the third portion P3. The thickness T3 of the third portion P3 is thicker than the thickness T2 of the second portion P2.

[0032] When the seed layer 30a is formed of a plurality of layers, the thickness T1, the thickness T2, and the thickness T3 are the sum of the thicknesses of the layers. The thickness T1a of the first portion P1 of the first layer 31a is thicker than the thickness T2a of the second portion P2 of the first layer 31a and the thickness T3a of the third portion P3 of the first layer 31a. The thickness T3a of the third portion P3 of the first layer 31a is thicker than the thickness T2a of the second portion P2 of the first layer 31a. The thicknesses of the other layers have a similar relationship to the thickness of the first layer 31a. Therefore, when the seed layer 30a is formed of two layers, the thickness T1b of the first portion P1 of the second layer 31b is thicker than the thickness T2b of the second portion P2 of the second layer 31b and the thickness T3b of the third portion P3 of the second layer 31b. The thickness T3b of the third portion P3 of the second layer 31b is thicker than the thickness T2b of the second portion P2 of the second layer 31b.

[0033] The ratio of the thickness T2 of the second portion P2 to the thickness T1 of the first portion P1 (thickness T2 of the second portion P2 / thickness T1 of the first portion P1) is 0.2 or more and 0.6 or less. The ratio of the thickness T3 of the third portion P3 to the thickness T1 of the first portion P1 (thickness T3 of the third portion P3 / thickness T1 of the first portion P1) is 0.5 or more and 0.9 or less. The ratio of the thickness T2a to the thickness T1a (thickness T2a / thickness T1a) and the ratio of the thickness T2b to the thickness T1b (thickness T2b / thickness T1b) are 0.2 or more and 0.6 or less. The ratio of the thickness T3a to the thickness T1a (thickness T3a / thickness T1a) and the ratio of the thickness T3b to the thickness T1b (thickness T3b / thickness T1b) are 0.5 or more and 0.9 or less.

[0034] The second layer 31b has a thickness greater than that of the first layer 31a. The thickness T1b is greater than the thickness T1a. The thickness T2b is greater than the thickness T2a. The thickness T3b is greater than the thickness T3a.

[0035] When the seed layer 30a is formed of only the first layer 31a, the thickness T1a of the first portion P1 of the first layer 31a is greater than the thickness T2a of the second portion P2 of the first layer 31a and the thickness T3a of the third portion P3 of the first layer 31a. The thickness T3a of the third portion P3 of the first layer 31a is greater than the thickness T2a of the second portion P2 of the first layer 31a.

[0036] The thickness T1 of the first portion P1 of the seed layer 30a is 0.02 μm or more and 1.0 μm or less. The thickness T1a of the first portion P1 of the first layer 31a is 0.01 μm or more and 0.5 μm or less. The thickness T1b of the first portion P1 of the second layer 31b is 0.01 μm or more and 0.9 μm or less. If the thickness T1 of the first portion P1 of the seed layer 30a is less than 0.02 μm, the adhesion strength between the resin insulating layer 20 and the seed layer 30a is low. If the thickness T1 of the first portion P1 exceeds 1.0 μm, the amount of etching required to remove the seed layer 30a is large. It is difficult to control the wiring width.

[0037] The thickness T2 of the second portion P2 of the seed layer 30a is 0.004 μm or more and 0.6 μm or less. The thickness T2a of the second portion P2 of the first layer 31a is 0.002 μm or more and 0.3 μm or less. The thickness T2b of the second portion P2 of the second layer 31b is 0.002 μm or more and 0.54 μm or less.

[0038] The thickness T3 of the third portion P3 of the seed layer 30a is 0.01 μm or more and 0.9 μm or less. The thickness T3a of the third portion P3 of the first layer 31a is 0.005 μm or more and 0.45 μm or less. The thickness T3b of the third portion P3 of the second layer 31b is 0.005 μm or more and 0.81 μm or less.

[0039] In the embodiment, an adhesive layer 100 can be formed on the surface (upper surface and side surface) of the connecting conductor layer 30. The adhesive layer 100 is not essential. The surface of the connecting conductor layer 30 is formed of a first surface and a second surface. Of the surfaces, the first surface is a portion exposed by an opening for a via conductor. The second surface is a portion other than the first surface. The first surface is not covered with the adhesive layer 100, and the second surface is covered with the adhesive layer 100. The adhesive layer 100 is in contact with the connecting conductor layer 30. The adhesive layer 100 is in contact with the second surface of the connecting conductor layer 30. The adhesive layer 100 is formed of a resin. The adhesive layer 100 is formed of an organic material (organic resin). An example of the organic material is a nitrogen-based organic compound. An example of the nitrogen-based organic compound is a tetrazole compound. An example of the nitrogen-based organic compound is disclosed in JP 2015-54987 A. The adhesive layer 100 does not cover the first surface 20a of the resin insulating layer 20 exposed from the connecting conductor layer 30. The adhesive layer 100 is formed between the connecting conductor layer 30 and the second resin insulating layer 120. The adhesive layer 100 is sandwiched between the connecting conductor layer 30 and the resin insulating layer (second resin insulating layer) 120. The adhesive layer 100 bonds the connecting conductor layer 30 and the resin insulating layer 120. The connecting wiring 36 may have only a second surface.

[0040] Fig. 5 is an enlarged cross-sectional view showing a part of the adhesive layer 100 formed on the second surface of the connection wiring 36. As shown in Fig. 5, the adhesive layer 100 is formed of a substantially smooth film 102 and a plurality of protrusions 104 protruding from the smooth film 102. The adhesive layer 100 formed on the second surface of the pad (pads 32, 34, etc.) is formed of a smooth film 102 and a plurality of protrusions 104 similar to those in Fig. 5. The shape is also the same.

[0041] The smooth film 102 has a substantially uniform thickness T. The thickness T of the smooth film 102 is 10 nm or more and 120 nm or less. The ratio (S1 / S2) of the area (S1) of the smooth film 102 exposed from the protrusion 104 to the area (S2) of the adhesive layer 100 is 0.1 or more and 0.5 or less. The smooth film 102 on the second surface of the connecting conductor layer 30 is formed to substantially conform to the shape of the second surface of the connecting conductor layer 30. When undulations are formed on the top and side surfaces of the connecting conductor layer 30, the smooth film 102 follows the undulations.

[0042] The protruding portion 104 is formed of a plurality of protrusions 106. The plurality of protrusions 106 form unevenness on the upper surface of the protruding portion 104. 2 The number of protrusions 106 per unit area is 5 or more and 15 or less. The protrusions 104 have heights H1, H2 between the upper surface of the smooth film 102 and the tops of the protrusions 104. The maximum values ​​of the heights H1, H2 are 10 times or more and 30 times or less the thickness T of the smooth film 102. The heights H1, H2 are 200 nm or more and 450 nm or less.

[0043] As shown in FIG. 2, via conductors 41 and 42 are formed in the openings (openings 21 and 22 for via conductors). The via conductors 41 and 42 electrically connect the conductor layer 10 and the connecting conductor layer 30. The via conductors 41 and 42 and the connecting conductor layer 30 are formed at the same time. The via conductors 41 and 42 are formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductors 41 and 42 and the seed layer 30a forming the connecting conductor layer 30 are common. The electrolytic plating layer 30b forming the via conductors 41 and 42 and the electrolytic plating layer 30b forming the connecting conductor layer 30 are common. The seed layer 30a forming the via conductors 41 and 42 is formed of a first layer 31a formed on the inner wall surfaces 23 and 24 of the openings 21 and 22 for via conductors and on the pads 12 and 14 exposed from the openings 21 and 22 for via conductors, and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the pads 12, 14 and the inner wall surfaces 23, 24. The resin insulating layer (first resin insulating layer) 20 supports the connecting conductor layer (first connecting conductor layer) 30. The connecting conductor layer (first connecting conductor layer) 30 in contact with the first surface 20a of the resin insulating layer (first resin insulating layer) 20 and the via conductors 41, 42 penetrating the resin insulating layer (first resin insulating layer) 20 are formed simultaneously. In the embodiment, the thickness of the seed layer 30a forming the via conductors 41, 42 can be reduced. In the embodiment, the thickness of the first layer 31a forming the via conductors 41, 42 can be reduced. In the embodiment, the thickness of the second layer 31b forming the via conductors 41, 42 can be reduced. Therefore, in the embodiment, the connecting conductor layer 30 having the fine connecting wiring 36 can be formed.

[0044] As shown in FIG. 2, a resin insulating layer (second resin insulating layer) 120 having a first surface 120a and a second surface 120b opposite to the first surface 120a is formed on the connecting conductor layer 30 and the resin insulating layer 20 via an adhesive layer 100. The resin insulating layer 120 is bonded to the connecting conductor layer 30 by the adhesive layer 100. The resin insulating layer 120 is in contact with the adhesive layer 100. The second surface 120b of the resin insulating layer 120 faces the connecting conductor layer 30. The resin insulating layer 120 is formed of a resin 80 and inorganic particles 90 (first inorganic particles 91, second inorganic particles 92) like the resin insulating layer 20. Therefore, the material of the resin insulating layer (second resin insulating layer) 120 is the same as the material of the resin insulating layer (first resin insulating layer) 20. The first surface 120a of the resin insulating layer 120 is the same as the first surface 20a of the resin insulating layer 20.

[0045] The resin insulating layer 120 has openings (openings for via conductors) 121, 122, 123, and 124. The opening 121 is a first opening 121 that exposes the first pad 32. The opening 122 is a second opening 122 that exposes the second pad 34. The first opening 121 and the opening 123 are formed directly below the first mounting area A1. The second opening 122 and the opening 124 are formed directly below the second mounting area A2. The first opening 121 and the second opening 122 reach the pads 32 and 34 that are directly connected to the connection wiring 36. Such openings (the first opening 121, the second opening 122, etc.) may be called openings for connection via conductors. The first opening 121 located directly below the first electronic component E1 is an opening for the first connection via conductor, and the second opening 122 located directly below the second electronic component E2 is an opening for the second connection via conductor. First opening 121, second opening 122, openings 123, 124 are similar to opening 21 shown in Fig. 4. Accordingly, inner wall surface 125 of first opening 121, inner wall surface 126 of second opening 122, and inner wall surfaces of openings 123, 124 are similar to inner wall surface 23 of opening 21 shown in Fig. 4. The inner wall surface of an opening for a via conductor penetrating resin insulation layer (second resin insulation layer) 120 is similar to the inner wall surface of an opening for a via conductor penetrating resin insulation layer (first resin insulation layer) 20. Each of the openings for a via conductor penetrating each resin insulation layer has a substantially similar inner wall surface.

[0046] The mounting conductor layer 130 is formed on the first surface 120a of the resin insulating layer 120. The resin insulating layer 120 supporting the mounting conductor layer 130 is the uppermost resin insulating layer. The mounting conductor layer 130 is in contact with the first surface of the uppermost resin insulating layer. The mounting conductor layer 130 includes a plurality of first electrodes 131 and a plurality of second electrodes 132. The mounting conductor layer 130 includes electrodes 133 and 134 other than the first electrode 131 and the second electrode 132. The first electrodes 131 and 133 are formed in the first mounting area A1. The first electronic component E1 is mounted on the printed wiring board 2 via the first electrodes 131 and 133. The second electrodes 132 and 134 are formed in the second mounting area A2. The second electronic component E2 is mounted on the printed wiring board 2 via the second electrodes 132 and 134. The mounting conductor layer 130 may further have a plurality of connection wirings (second connection wirings). In this case, the second connection wirings have one end and the other end opposite to the one end. One end of the second connection wirings is directly connected to one first electrode 131. The other end of the second connection wirings is directly connected to one second electrode 132. The second connection wirings electrically connect the first electrode 131 and the second electrode 132. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the second connection wirings. The connection wirings in the mounting conductor layer 130 are not essential. The connection wirings in the mounting conductor layer 130 may include the first electrode 131 and the second electrode 132.

[0047] The mounting conductor layer 130 and the connecting conductor layer 30 are similar. Therefore, the mounting conductor layer 130 is formed of a seed layer 130a and an electrolytic plating layer 130b on the seed layer 130a. The seed layer 130a is formed of a first layer 131a and a second layer 131b on the first layer 131a. The seed layer 130a forming the mounting conductor layer 130 and the seed layer 30a forming the connecting conductor layer 30 are similar. The first layer 131a forming the mounting conductor layer 130 and the first layer 31a forming the connecting conductor layer 30 are similar. The second layer 131b forming the mounting conductor layer 130 and the second layer 31b forming the connecting conductor layer 30 are similar. The electrolytic plating layer 130b forming the mounting conductor layer 130 and the electrolytic plating layer 30b forming the connecting conductor layer 30 are similar.

[0048] When the mounting conductor layer 130 includes connection wiring, the connection wiring in the mounting conductor layer 130 is similar to the connection wiring 36 in the connection conductor layer 30. Therefore, the widths W1, G1, W2, and G2 of the connection wiring in the mounting conductor layer 130 are similar to the widths W1, G1, W2, and G2 of the connection wiring 36 in the connection conductor layer 30. The aspect ratio (thickness / width) of the connection wiring in the mounting conductor layer 130 is 2.0 or more and 4.0 or less.

[0049] In the embodiment, an adhesive layer 150 can be formed on the surface (upper surface and side surface) of the mounting conductor layer 130. The adhesive layer 150 is not essential. The surface of the mounting conductor layer 130 is formed of a third surface and a fourth surface. Of the surfaces, the third surface is a portion exposed by an opening. An example of an opening is an opening for forming a bump. The fourth surface is a portion other than the third surface. The third surface is not covered with the adhesive layer 150, and the fourth surface is covered with the adhesive layer 150. The adhesive layer 150 covering the fourth surface of the mounting conductor layer 130 is similar to the adhesive layer 100 covering the second surface of the connecting conductor layer 30. Therefore, the adhesive layer 150 is formed of a substantially smooth smooth film 102 and a protruding portion 104 protruding from the smooth film 102 (see FIG. 5). The adhesive layer 150 does not cover the first surface 120a of the resin insulating layer 120 exposed from the mounting conductor layer 130. The adhesive layer 150 bonds the mounting conductor layer 130 and the insulating layer 220. If the mounting conductor layer 130 includes a connecting wire, the connecting wire may only have a fourth surface.

[0050] Via conductors 141, 142, 143, and 144 are formed in the openings (openings for via conductors) 121, 122, 123, and 124 penetrating the resin insulating layer 120. The via conductor 141 formed in the first opening 121 is the first connection via conductor 141. The first connection via conductor 141 is connected to the first pad 32 extending from one end of the connection wiring 36. The via conductor 142 formed in the second opening 122 is the second connection via conductor 142. The second connection via conductor 142 is connected to the second pad 34 extending from the other end of the connection wiring 36. The first connection via conductor 141 and the second connection via conductor 142 electrically connect the connection conductor layer 30 and the mounting conductor layer 130. The first connection via conductor 141 electrically connects the first pad 32 and the first electrode 131. The second connection via conductor 142 electrically connects the second pad 34 and the second electrode 132. The first connection via conductor 141 electrically connects the first electrode 131 and the connection wiring 36. The second connection via conductor 142 electrically connects the second electrode 132 and the connection wiring 36. The inner wall surfaces 125, 126 of the openings 121, 122 for the connection via conductors 141, 142 are formed by the exposed surface 91b of the first inorganic particles 91 and the surface 80a of the resin 80. The exposed surface 91b of the first inorganic particles 91 and the surface 80a of the resin 80 form an almost common surface. The inner wall surface of the opening for the connection via conductor is almost flat. Therefore, when data from the first electrode 131 to the second electrode 132 passes through the connection via conductors 141, 142, the data is unlikely to deteriorate. The connection via conductor of the embodiment is suitable as a via conductor for transmitting high-speed data. The printed wiring board 2 of the embodiment can transmit a large amount of data through the connection via conductor.

[0051] The connection via conductor is formed by a seed layer 130a and an electrolytic plating layer 130b on the seed layer 130a. The first connection via conductor 141 and the second connection via conductor 142 are examples of connection via conductors. The seed layer 130a forming the connection via conductors 141, 142 and the seed layer 130a forming the mounting conductor layer 130 are common. The first layer 131a forming the connection via conductors 141, 142 and the first layer 131a forming the mounting conductor layer 130 are common. The second layer 131b forming the connection via conductors 141, 142 and the second layer 131b forming the mounting conductor layer 130 are common. The electrolytic plating layer 130b forming the connection via conductors 141, 142 and the electrolytic plating layer 130b forming the mounting conductor layer 130 are common. The seed layer 130a forming the connection via conductors 141, 142 is composed of a first layer 131a formed on inner wall surfaces 125, 126 of the openings 121, 122 for the connection via conductor and on the pads 32, 34 exposed from the openings 121, 122 for the connection via conductor, and a second layer 131b on the first layer 131a. The first layer 131a is in contact with the inner wall surfaces 125, 126 and the pads 32, 34. Via conductors 143, 144 are formed in the openings 123, 124 other than the openings 121, 122 for the connection via conductor.

[0052] The seed layer 130a which forms the connection via conductors 141, 142 and the via conductors 143, 144, and the seed layer 30a which forms the via conductors 41, 42 are similar. The first layer 131a which forms the connection via conductors 141, 142 and the via conductors 143, 144, and the first layer 31a which forms the via conductors 41, 42 are similar. The second layer 131b which forms the connection via conductors 141, 142 and the via conductors 143, 144, and the second layer 31b which forms the via conductors 41, 42 are similar. The electrolytic plating layer 130b which forms the connection via conductors 141, 142 and the via conductors 143, 144, and the electrolytic plating layer 30b which forms the via conductors 41, 42 are similar.

[0053] The seed layer 130a and the seed layer 30a are similar, each having a first portion P1 on the first surface 120a, a second portion P2 on the inner wall surfaces 125, 126 of the openings 121, 122, and a third portion P3 on the pads 32, 34 exposed from the openings 121, 122. Therefore, the seed layer 130a and the seed layer 30a have a similar thickness relationship with respect to the first portion P1, the second portion P2, and the third portion P3. The first layer 131a and the first layer 31a have a similar thickness relationship with respect to the first portion P1, the second portion P2, and the third portion P3. The second layer 131b and the second layer 31b have a similar thickness relationship with respect to the first portion P1, the second portion P2, and the third portion P3. Therefore, the seed layer 130a and the first layer 131a and the second layer 131b have the following relationship with respect to the first portion P1, the second portion P2, and the third portion P3. The thickness of the first portion P1 is greater than the thickness of the second portion P2 and the thickness of the third portion P3. The thickness of the third portion P3 is greater than the thickness of the second portion P2. The thickness of the second layer 131b is greater than the thickness of the first layer 131a. The thickness of each portion (first portion P1, second portion P2, third portion P3) forming the second layer 131b is greater than the thickness of each portion (first portion P1, second portion P2, third portion P3) forming the first layer 131a. Similar thickness relationships include the thickness ranges and thickness ratios (thickness of the second portion P2 / thickness of the first portion P1, thickness of the third portion P3 / thickness of the first portion P1, etc.) of each portion (first portion P1, second portion P2, third portion P3).

[0054] The mounting conductor layer is formed directly on the resin insulation layer (mounting resin insulation layer) that supports the mounting conductor layer. The mounting conductor layer contacts the mounting resin insulation layer. The seed layer that forms the mounting conductor layer and the seed layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The first layer that forms the mounting conductor layer and the first layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The second layer that forms the mounting conductor layer and the second layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The first layer and the second layer form a seed layer. The electrolytic plating layer that forms the mounting conductor layer and the electrolytic plating layer that forms the via conductor penetrating the mounting resin insulation layer are common. Both are formed at the same time. The inner wall surface of the opening for the via conductor penetrating the mounting resin insulation layer and the inner wall surface 23 of the opening 21 shown in FIG. 4 are similar. Therefore, the embodiment can reduce the thickness of the seed layer that forms the mounting conductor layer. The mounting conductor layer may have fine connecting wiring.

[0055] An insulating layer 220 having a first surface 220a and a second surface 220b opposite to the first surface 220a is formed on the mounting conductor layer 130 and the first surface 120a of the resin insulating layer 120. In the embodiment, an adhesive layer 150 can be formed on the mounting conductor layer 130. In that case, the insulating layer 220 is formed on the mounting conductor layer 130 via the adhesive layer 150. The adhesive layer 150 formed on the mounting conductor layer 130 and the adhesive layer 100 on the connecting conductor layer 30 are the same. The insulating layer 220 is bonded to the mounting conductor layer 130 by the adhesive layer 150. The second surface 220b of the insulating layer 220 faces the mounting conductor layer 130. The insulating layer 220 functions as a solder resist layer. It is preferable that the material of the insulating layer 220 is different from the material of the resin insulating layers 20 and 120. The insulating layer 220 is formed using, for example, an epoxy resin or a polyimide resin containing a photosensitive agent.

[0056] The insulating layer 220 has openings (bump openings) 221, 222, 223, 224 that expose the electrodes 131, 132, 133, 134. The opening 221 is a first opening (first bump opening) 221 that exposes the first electrode 131. The opening 222 is a second opening (second bump opening) 222 that exposes the second electrode 132. The first opening 221 and the opening 223 are formed directly above the first mounting area A1. The second opening 222 and the opening 224 are formed directly above the second mounting area A2.

[0057] Bumps 241, 242, 243, and 244 are formed on the electrodes 131, 132, 133, and 134 exposed from the openings (openings for bumps) 221, 222, 223, and 224. The bump 241 formed on the first electrode 131 exposed from the first opening (first opening for bumps) 221 is the first bump 241. The bump 242 formed on the second electrode 132 exposed from the second opening (second opening for bumps) 222 is the second bump 242. The bumps 241, 242, 243, and 244 are examples of bumps for mounting electronic components (first electronic component E1, second electronic component E2, etc.) on the printed wiring board 2. The first bump 241 and the bump 243 are located on the first mounting area A1, and the first electronic component E1 is mounted on the printed wiring board 2 via these bumps 241 and 243. The second bumps 242 and 244 are located on the second mounting area A2, and the second electronic component E2 is mounted on the printed wiring board 2 via these bumps 242, 244.

[0058] Each of the bumps 241, 242, 243, 244 is formed by a portion (first portion) filling the openings 221, 222, 223, 224 and a second portion (land) on the first portion. The second portion is formed on the first surface 220a of the insulating layer 220 directly above the first portion and around the openings 221, 222, 223, 224. The second portion protrudes from the first surface 220a of the insulating layer 220. The first portion and the second portion are continuous. Both are formed integrally. The first bump 241 electrically connects the first electronic component E1 and the first electrode 131. The second bump 242 electrically connects the second electronic component E2 and the second electrode 132. The first electronic component E1 and the second electronic component E2 are connected via the first bump 241, the first connection via conductor 141, the connection wiring 36, the second connection via conductor 142, and the second bump 242. When data is sent from the first electronic component E1 to the second electronic component E2, the data is transmitted through a path including the connection via conductors and the connection wiring. Since the connection via conductors and the connection wiring include a sputtered seed layer formed on a substantially flat surface, the printed wiring board 2 of the embodiment can transmit a large amount of data at high speed from the first electronic component E1 to the second electronic component E2. When the data is transmitted, degradation of the data is unlikely to occur.

[0059] The bumps 241, 242, 243, and 244 are formed of a seed layer 230a and an electrolytic plating layer 230b on the seed layer 230a. The seed layer 230a is formed of a first layer 231a and a second layer 231b on the first layer 231a. The seed layer 230a forming the bumps (first bump 241, second bump 242, etc.) and the seed layer 30a forming the connecting conductor layer 30 are the same. The first layer 231a forming the bumps and the first layer 31a forming the connecting conductor layer 30 are the same. The second layer 231b forming the bumps and the second layer 31b forming the connecting conductor layer 30 are the same. The electrolytic plating layer 230b forming the bumps and the electrolytic plating layer 30b forming the connecting conductor layer 30 are the same. In the modified example, the bumps 241, 242, 243, and 244 may be formed of solder.

[0060] A functional layer 260 is formed on the tops of the bumps 241, 242, 243, and 244. The functional layer 260 is, for example, a plating film of nickel, tin, palladium, gold, or the like. The functional layer 260 is not essential.

[0061] [Modifications of the embodiment] Fig. 7 is a cross-sectional view showing a printed wiring board 3 according to a modified example of the embodiment. As shown in Fig. 7, the printed wiring board 3 has the printed wiring board 2 according to the embodiment and a support 4. The support 4 is attached to the lower surface 2b of the printed wiring board 2 according to the embodiment. The support 4 includes a base material 5, a first metal layer 6 laminated on both sides of the base material 5, a release layer 7 formed on the first metal layer 6, and a second metal layer 8 laminated on the release layer 7. The printed wiring board 2 according to the embodiment is laminated on the second metal layer 8.

[0062] An example of the base material 5 is a substrate containing a reinforcing material such as glass, silicon, or glass fiber. The rigidity of the base material 5 is higher than the rigidity of the printed wiring board 2. Therefore, in the modified printed wiring board 3, it is possible to increase the connection reliability between the printed wiring board and the electronic components (the first electronic component E1, the second electronic component E2, etc.).

[0063] [Method of manufacturing printed wiring board 2 according to embodiment] 8A to 8H show a method for manufacturing a printed wiring board 2 according to an embodiment. FIGS. 8A to 8C and 8E to 8H are cross-sectional views. FIG. 8D is an enlarged cross-sectional view. FIG. 8A shows a support 4 and a conductor layer 10 formed on the support 4. The support 4 is the same as the support 4 in FIG. 7. A plating resist is formed on the second metal layer 8. A conductor layer 10 including pads 12, 14 is formed on the second metal layer 8 exposed from the plating resist. The second metal layer 8 serves as a seed layer for forming the conductor layer 10. The plating resist is then removed. In an embodiment, the upper surface of the conductor layer 10 can be polished by, for example, CMP (Chemical Mechanical Polishing) before removing the plating resist.

[0064] As shown in FIG. 8B, a resin insulation layer (first resin insulation layer) 20 and a protective film 50 are formed on the second metal layer 8 and the conductor layer 10. The second surface 20b of the resin insulation layer 20 faces the second metal layer 8. The protective film 50 is formed on the first surface 20a of the resin insulation layer 20. The resin insulation layer 20 has resin 80 and inorganic particles 90 (second inorganic particles 92). The inorganic particles 90 are embedded in the resin 80. The first surface 20a of the resin insulation layer 20 is formed only from the resin 80. The inorganic particles 90 are not exposed from the first surface 20a of the resin insulation layer 20. The first surface 20a of the resin insulation layer 20 does not include the surfaces of the inorganic particles 90. No irregularities are formed on the first surface 20a of the resin insulation layer 20.

[0065] As shown in FIG. 8C, laser light L is irradiated from above the protective film 50. The laser light L penetrates the protective film 50 and the resin insulating layer 20 at the same time. Openings 21, 22 for via conductors are formed, leading to the pads 12, 14 of the conductor layer 10. The laser light L is, for example, a UV laser light or a CO2 laser light. The pads 12, 14 are exposed by the openings 21, 22. When the openings 21, 22 for the via conductors are formed, the first surface 20a of the resin insulating layer 20 is covered with the protective film 50. Therefore, even if resin scatters when the openings 21, 22 for the via conductors are formed, the resin is prevented from adhering to the first surface 20a of the resin insulating layer 20.

[0066] FIG. 8D shows the inner wall surface 23b of the opening (opening for via conductor) after the laser light irradiation. The opening 21 is depicted as a representative example of the opening for the via conductor. The opening 22 and the opening 21 are similar. The inner wall surface 24b of the opening 22 and the inner wall surface 23b of the opening 21 are similar. The inner wall surface 23b is formed of the resin 80 and the inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 23b after the laser light irradiation is treated. It is preferable to selectively remove the inorganic particles 90 protruding from the resin 80. As a result, the first inorganic particles 91 are formed from the inorganic particles 90. For example, the inorganic particles 90 protruding from the resin 80 are selectively removed by treating the inner wall surface 23b after the laser light irradiation with a chemical. Alternatively, the inorganic particles 90 protruding from the resin 80 are selectively removed by treating the inner wall surface 23b after the laser light irradiation with plasma. Selectively removing includes that the etching rate of the inorganic particles 90 is greater than the etching rate of the resin 80. For example, the difference in etching rate between the two is 10 times or more. Alternatively, the difference in etching rate between the two is 50 times or more. Alternatively, the difference in etching rate between the two is 100 times or more. By processing the inner wall surface 23b after the laser light irradiation, the first inorganic particles 91 having the flat portion 91a are obtained. By controlling the conditions for processing the inner wall surface 23b after the laser light irradiation, the embodiment can control the shape of the inner wall surface 23. Examples of the conditions are temperature, concentration, time, and type and pressure of gas. The etching rate of the inorganic particles 90 and the etching rate of the resin are controlled.

[0067] By irradiating the resin insulating layer 20 with laser light L, a part of the second inorganic particles 92 embedded in the resin 80 forms the inner wall surface 23b after the laser light irradiation. The second inorganic particles 92 forming the inner wall surface 23b after the laser light irradiation are formed by a protruding portion P protruding from the resin 80 and a portion E embedded in the resin 80. The inner wall surface 23b after the laser light irradiation is treated. For example, the inner wall surface 23b is treated with plasma of a gas containing tetrafluoromethane. The protruding portion P is selectively removed to form the inner wall surface 23 of the embodiment. The first inorganic particles 91 are formed from the second inorganic particles 92. The protruding portion P is selectively removed to form the first inorganic particles 91 having a flat portion 91a. The flat portion 91a is a flat surface. When the second inorganic particles 92 having a spherical shape are cut by a flat surface, the shape of the first inorganic particles 91 is obtained. The inner wall surface 23 is formed by the flat portion 91a and the surface 80a of the resin 80, and the exposed surface 91b of the flat portion 91a and the surface 80a of the resin 80 are located on approximately the same plane. For example, when the seed layer 30a is formed on the inner wall surface 23b by sputtering, the protruding portion P inhibits the growth of the sputtered film (sputtering film formation). For example, the seed layer 30a is not formed continuously on the inner wall surface 23b. Alternatively, it is necessary to increase the thickness of the seed layer 30a. A fine conductor circuit cannot be formed. In the embodiment, the protruding portion P is removed. In the embodiment, the thickness of the seed layer 30a formed by sputtering can be reduced. Even if the thickness of the seed layer 30a formed by sputtering is thin, a continuous seed layer 30a can be obtained. The width of the connection wiring 36 satisfies the target value. The width of the space 37 between adjacent connection wirings 36 satisfies the target value. The via conductor formed on the inner wall surface 23b having the protruding portion P is the via conductor of the reference example. If the via conductor of the reference example is present in the path, data moving from the first electronic component E1 to the second electronic component E2 must pass through the via conductor of the reference example. In that case, it is considered that the data will be deteriorated due to the influence of the protruding portion P. In the embodiment, the protruding portion P is removed. The embodiment can suppress the deterioration of the data.

[0068] Forming an opening (opening for a via conductor) includes forming inorganic particles (second inorganic particles 92) 90 having protruding portions P. An opening 21 is a representative example of an opening (opening for a via conductor). The protruding portions P protrude from the resin 80 forming the inner wall surface 23b of the opening 21. The first inorganic particles 91 are formed by removing the protruding portions P of the inorganic particles (second inorganic particles 92) 90. The inner wall surface 23 of the opening 21 includes the exposed surfaces 91b of the first inorganic particles 91. The exposed surfaces 91b of the first inorganic particles 91 are formed by removing the protruding portions P.

[0069] Obtaining the shape of the first inorganic particle 91 by cutting the spherical second inorganic particle 92 on a plane includes removing the protruding portion P of the inorganic particle 90. The inner wall surface 23 of the actual opening 21 is a substantially curved surface. Since the flat portion 91a is formed by removing the protruding portion P, the exposed surface 91b of the flat portion 91a includes a curved surface. In other words, forming a common surface between the flat portion 91a and the resin 80 includes forming the inner wall surface 23 that is substantially formed as a curved surface.

[0070] No irregularities are formed on the inner wall surface 23. The inner wall surface 23 is formed smoothly. The size of the irregularities is controlled by controlling the conditions for processing the inner wall surface 23b after the laser light irradiation.

[0071] The inside of the opening 21 is cleaned. By cleaning the inside of the opening 21, resin residue generated when the opening 21 is formed is removed. The inside of the opening 21 is cleaned by plasma. That is, the cleaning is performed by a dry process. The cleaning includes a desmear process.

[0072] When the inside of the opening 21 is cleaned, the first surface 20a of the resin insulating layer 20 is covered with the protective film 50. The first surface 20a is not affected by the plasma. The first surface 20a is formed only of the resin 80. The inorganic particles 90 are not exposed from the first surface 20a. The first surface 20a does not include the surfaces of the inorganic particles 90. The first surface 20a does not have any irregularities. The first surface 20a is formed to be smooth.

[0073] In the case where processing the inner wall surface 23b after the laser light irradiation includes cleaning the inside of the opening 21, the embodiment can omit cleaning the inside of the opening 21.

[0074] As shown in Fig. 8E, after cleaning the insides of the via conductor openings 21, 22, the protective film 50 is removed from the resin insulating layer 20. When processing the inner wall surfaces 23b, 24b after the laser light irradiation includes cleaning the insides of the via conductor openings, the protective film 50 is removed from the resin insulating layer 20 after processing the inner wall surfaces 23b, 24b after the laser light irradiation. When the inner wall surfaces 23b, 24b after the laser light irradiation are processed, the protective film 50 covers the first surface 20a of the resin insulating layer 20. After the protective film 50 is removed, the first surface 20a is not roughened.

[0075] As shown in FIG. 8F, a seed layer 30a is formed on the first surface 20a. The seed layer 30a is formed by sputtering. The seed layer 30a is formed by a dry process. The seed layer 30a is also formed on the inner wall surfaces 23 and 24 of the openings for the via conductors and on the pads 12 and 14 exposed from the openings 21 and 22 for the via conductors.

[0076] For example, sputtering is performed through a mask. First, a first mask covering the openings 21, 22 for each via conductor is placed on the resin insulating layer 20. The first mask exposes only the first surface 20a of the resin insulating layer 20. A first portion P1 having a thickness T1a is formed on the first surface 20a of the resin insulating layer 20 through the first mask. The first mask is removed. A second mask exposing only the inner wall surfaces 23, 24 of the openings 21, 22 for the via conductors 41, 42 is placed on the resin insulating layer 20. A second portion P2 having a thickness T2a is formed on the inner wall surfaces 23, 24 through the second mask. The inner wall surfaces 23, 24 have a step between the surface of the resin and the flat portion. The second mask is removed. A third mask exposing only the pads 12, 14 exposed from the openings 21, 22 is placed on the resin insulating layer 20. A third portion P3 having a thickness T3a is formed on the pads 12, 14 through the third mask. The third mask is removed. As a result, the first layer 31a is formed on the first surface 20a. The first layer 31a is formed on the inner wall surfaces 23, 24 exposed from the openings 21, 22 and on the pads 12, 14. Thereafter, the second layer 31b is formed on the first layer 31a. The method of forming the first layer 31a and the method of forming the second layer 31b are the same. The first layer 31a is formed of an alloy containing copper, aluminum, and a specific metal (e.g., silicon). The second layer 31b is formed of copper.

[0077] The first layer 31a and the second layer 31b are formed by sputtering. Examples of sputtering conditions are as follows: The distance between the target and the first surface 20a of the resin insulating layer 20 is 50 mm or more and 250 mm or less; The voltage is 15 eV or more and 50 eV or less; The gas concentration is 0.1 Pa or more and 1.0 Pa or less. For example, the thickness T1 of the first portion P1, the thickness T2 of the second portion P2, and the thickness T3 of the third portion P3 of the seed layer 30a are adjusted by changing the processing time. The thickness T1a of the first portion P1 of the first layer 31a is thicker than the thickness T2a of the second portion P2 of the first layer 31a and the thickness T3a of the third portion P3 of the first layer 31a. The thickness T3a of the third portion P3 of the first layer 31a is thicker than the thickness T2a of the second portion P2 of the first layer 31a. The thickness T1b of the first portion P1 of the second layer 31b is thicker than the thickness T2b of the second portion P2 of the second layer 31b and the thickness T3b of the third portion P3 of the second layer 31b. The thickness T3b of the third portion P3 of the second layer 31b is thicker than the thickness T2b of the second portion P2 of the second layer 31b. As a result, the thickness T1 of the first portion P1 of the seed layer 30a is thicker than the thickness T2 of the second portion P2 and the thickness T3 of the third portion P3. The thickness T3 of the third portion P3 of the seed layer 30a is thicker than the thickness T2 of the second portion P2.

[0078] The ratio of the thickness of the second layer 31b to the thickness of the first layer 31a (thickness of the second layer 31b / thickness of the first layer 31a) is not less than 1.2 and not more than 2. The ratio (thickness T1b / thickness T1a), the ratio (thickness T2b / thickness T2a), and the ratio (thickness T3b / thickness T3a) are not less than 1.2 and not more than 2.

[0079] The first portion P1 is formed on the first surface 20a of the resin insulating layer 20, and the second portion P2 is formed on the inner wall surfaces 23, 24 of the resin insulating layer 20. Both the first portion P1 and the second portion P2 are formed on the resin insulating layer 20. The first portion P1 forms the seed layer 30a of the pads 32, 34 and the connection wiring 36. The second portion P2 forms the seed layer 30a of the via conductors 41, 42. The thermal expansion coefficient of the resin insulating layer 20 and the thermal expansion coefficient of the seed layer 30a are different. Therefore, when the printed wiring board 2 is subjected to a thermal shock, it is considered that stress acts on the seed layer 30a. Normally, the connection wiring 36 includes a curved portion that is much longer than the via conductors 41, 42. Therefore, large stress should be concentrated in the curved portion in the connection wiring 36. In contrast, the via conductors 41, 42 are short and formed almost straight. Therefore, stress concentration is unlikely to occur in the via conductors 41, 42. Therefore, in order to avoid breakage of the seed layer 30a on the first surface 20a of the resin insulating layer 20, it is preferable that the seed layer 30a forming the connection wiring 36 has a large thickness. In contrast, the seed layer 30a on the inner wall surfaces 23, 24 forming the via conductors 41, 42 may have a small thickness. Therefore, in the embodiment, the thickness T1 is made larger than the thickness T2.

[0080] By reducing the thickness T2 of the second portion P2, embodiments may reduce the time required to form the seed layer 30a.

[0081] The first surface 20a has excellent flatness. When the seed layer 30a is formed on the first surface 20a by sputtering, the distance between the target and the first surface 20a is almost constant. The embodiment can form the seed layer 30a having an almost uniform thickness. The embodiment can reduce the variation in the thickness of the first layer 31a and the second layer 31b on the first surface 20a of the resin insulating layer 20. The width of the connection wiring 36 on the first surface 20a of the resin insulating layer 20 satisfies the target value. The width of the space 37 between the adjacent connection wirings 36 satisfies the target value. The embodiment can reduce the variation in the width of the connection wiring 36. The embodiment can reduce the variation in the width of the space 37. Even if a plurality of connection wirings 36 are formed on the first surface 20a of the resin insulating layer 20, data transmitted through each connection wiring 36 reaches the electronic component with almost no delay.

[0082] For example, the first layer 31a is formed of a copper alloy. The first layer 31a of the seed layer 30a is formed of an alloy containing copper, aluminum, and silicon. Aluminum has high ductility and high malleability. Therefore, the adhesive strength between the resin insulating layer 20 and the first layer 31a is high. Even if the resin insulating layer 20 expands and contracts due to heat cycles, it is considered that the seed layer 30a containing aluminum can follow the expansion and contraction. Even if the first surface 20a of the resin insulating layer 20 is smooth, the seed layer 30a is difficult to peel off from the resin insulating layer 20. It is considered that aluminum is easily oxidized. If the first inorganic particles 91 are inorganic particles 90 containing oxygen (oxygen element), it is considered that the first layer 31a formed on the inner wall surfaces 23, 24 adheres to the first inorganic particles 91 through the oxygen in the inorganic particles 90 forming the inner wall surfaces 23, 24. The first layer 31a and the inner wall surfaces 23, 24 are strongly bonded. The embodiment can increase the adhesive strength between the inner wall surfaces 23, 24 and the first layer 31a. The seed layer 30a is unlikely to peel off from the inner wall surfaces 23, 24. The inorganic particles 90 forming the inner wall surfaces 23, 24 preferably contain oxygen elements.

[0083] A plating resist is formed on the seed layer 30a. The plating resist has openings for forming the via conductors 41, 42, the connection wiring 36, and the pads 32, 34 extending from the connection wiring 36.

[0084] An electrolytic plating layer 30b is formed on the seed layer 30a exposed from the plating resist. The electrolytic plating layer 30b fills the openings in the plating resist. The electrolytic plating layer 30b fills the openings 21 and 22. A portion of the electrolytic plating layer 30b protrudes above the top surface of the plating resist. In this case, the electrolytic plating layer 30b partially covers the top surface of the plating resist. Alternatively, the electrolytic plating layer 30b completely covers the top surface of the plating resist.

[0085] The electrolytic plating layer 30b is polished. The thickness of the electrolytic plating layer 30b is reduced by polishing. The sum of the thickness of the electrolytic plating layer 30b and the thickness of the seed layer 30a reaches a predetermined value. The plating resist is also polished together with the electrolytic plating layer 30b. An example of a polishing method is CMP. The arithmetic mean roughness (Ra) of the upper surface of the electrolytic plating layer 30b after polishing is 0.3 μm or less.

[0086] After polishing the electrolytic plating layer 30b, the plating resist is removed. The seed layer 30a exposed from the electrolytic plating layer 30b is removed. As shown in FIG. 8G, the pads 32, 34 and the connection wiring 36 are formed by the seed layer 30a and the electrolytic plating layer 30b on the resin insulating layer 20. The connecting conductor layer 30 is formed. The seed layer 30a and the electrolytic plating layer 30b in the openings 21, 22 for the via conductors form the via conductors 41, 42. The connecting conductor layer 30 and the via conductors 41, 42 are formed simultaneously.

[0087] An example of the openings 210, 211 after the seed layer is formed is shown in FIG. 8F. When the thickness T2 is thin, the volume of the openings 210, 211 for the via conductors after the seed layer 30a is formed can be increased. Therefore, the electrolytic plating solution easily enters the openings 210, 211. Voids are less likely to form in the electrolytic plating layer 30b forming the via conductors 41, 42. The embodiment can form the via conductors 41, 42 with low resistance. Even if the opening diameter (diameter on the pads 12, 14) D (see FIG. 8E) of the openings 21, 22 is 30 μm or less, the embodiment can form the via conductors 41, 42 that do not include voids. Even if the opening diameter D is 10 μm or more and 25 μm or less, the connection reliability through the via conductors 41, 42 is stable for a long period of time. In this way, by reducing the thickness T2 of the second portion P2, the embodiment can improve the cost, productivity, and reliability. Therefore, it is preferable that the thickness T2 is smaller than the thickness T1.

[0088] As shown in FIG. 8H, an adhesive layer 100 is formed on the upper surface and side surface of the connecting conductor layer 30. The adhesive layer 100 is formed by immersing the intermediate substrate shown in FIG. 8G in a chemical solution containing a nitrogen-based organic compound. The pH of the chemical solution is 7 or less. By immersing the intermediate substrate in the chemical solution, an adhesive layer 100 having a smooth film 102 and a protruding portion 104 is formed on the upper surface and side surface of the connecting conductor layer 30. Before the intermediate substrate is immersed in the chemical solution, the oxide film covering the upper surface and side surface of the connecting conductor layer 30 is removed. In the modified example, the adhesive layer 100 is formed by applying a chemical solution onto the connecting conductor layer 30. After the adhesive layer 100 is formed, the intermediate substrate is removed from the chemical solution. The adhesive layer 100 is dried. The upper surface of the adhesive layer 100 before drying may be smooth. In that case, a part of the adhesive layer is coagulated by drying. By coagulation, an adhesive layer 100 including the smooth film 102 and the protruding portion 104 is formed.

[0089] A resin insulating layer (second resin insulating layer) 120, a mounting conductor layer 130, and via conductors 141, 142, 143, and 144 are formed on the connecting conductor layer 30 and the resin insulating layer 20. The via conductors include connecting via conductors. Examples of the connecting via conductors are the first connecting via conductor 141 and the second connecting via conductor 142. The resin insulating layer 120 and the resin insulating layer 20 are formed in a similar manner. The mounting conductor layer 130 and the connecting conductor layer 30 are formed in a similar manner. The via conductors 141, 142, 143, and 144 and the via conductors 41 and 42 are formed in a similar manner. When the openings 121, 122, 123, and 124 for the via conductors are formed in the resin insulating layer 120 by the laser light L, the laser light L removes the adhesive layer 100 covering the connecting conductor layer 30. Alternatively, the adhesive layer 100 is not completely removed by the laser light L. In this case, the adhesive layer 100 at the bottom of the openings 121, 122, 123, 124 for the via conductor is removed by cleaning the insides of the openings 121, 122, 123, 124 for the via conductor. The openings 121, 122, 123, 124 for the via conductor expose the connecting conductor layer 30. The openings for the via conductor include openings for the connecting via conductor. Examples of the openings for the connecting via conductor are the first opening (opening for the first connecting via conductor) 121 and the second opening (opening for the second connecting via conductor) 122.

[0090] In the embodiment, the thickness of the first layer forming the connection via conductor can be reduced. In the embodiment, the thickness of the second layer forming the connection via conductor can be reduced. The first layer and the second layer form a seed layer. In the embodiment, the volume of the opening for the connection via conductor after the seed layer is formed can be increased. The opening for the connection via conductor after the seed layer is formed can be called the opening after the seed layer is formed. By forming an electrolytic plating layer in the opening after the seed layer is formed, a connection via conductor consisting of the seed layer and the electrolytic plating layer is formed. Even if the diameter of the opening for the connection via conductor is small, the electrolytic plating solution easily enters the opening for the connection via conductor after the seed layer is formed. The electrolytic plating layer forming the connection via conductor is unlikely to include voids. A low-resistance connection via conductor is formed. Even if the path includes the connection via conductor, the printed wiring board 2 of the embodiment can transmit high-speed data. An example of the openings 210 and 211 after the seed layer is formed is shown in FIG. 8F. The openings 210 and 211 after the seed layer is formed are surrounded by the seed layer. The bottom and side of the openings 210 and 211 are in contact with the seed layer.

[0091] An adhesive layer 150 is formed on the upper and side surfaces of the mounting conductor layer 130. The adhesive layer 150 and the adhesive layer 100 are similar. An insulating layer 220 is formed on the mounting conductor layer 130 and the resin insulating layer 120. The insulating layer 220 has openings 221, 222, 223, 224 that expose the electrodes (first electrode 131, second electrode 132, etc.). Bumps (first bump 241, second bump 242, etc.) are formed on the electrodes 131, 132, 133, 134 exposed by the openings 221, 222, 223, 224. A functional layer 260 is formed on the bumps 241, 242, 243, 244. A modified printed wiring board 3 is obtained.

[0092] The support 4 is removed. The release layer 7 of the support 4 is softened or weakened, for example, by heating or ultraviolet light irradiation. The first metal layer 6 and the second metal layer 8 are separated from each other. The second metal layer 8 is then removed by etching. The lower surface 2b of the printed wiring board 2 is exposed. The printed wiring board 2 of the embodiment is obtained.

[0093] In the printed wiring board 2 of the embodiment, the inner wall surface of the opening for the via conductor is formed by the flat portion 91a of the first inorganic particles 91 and the resin 80. The flat portion 91a and the surface 80a of the resin 80 forming the inner wall surface form a substantially common surface. The inner wall surface is formed smoothly. Therefore, a seed layer 30a of uniform thickness is formed on the inner wall surface of the opening. The seed layer 30a is formed thin. When the seed layer 30a is removed, the amount of etching is small. Therefore, the amount of etching of the electrolytic plating layer 30b is small. Each conductor circuit in the connecting conductor layer 30 and the mounting conductor layer 130 has a width according to the design value. A printed wiring board 2 having high quality is provided.

[0094] Data is transmitted from the first electronic component E1 to the second electronic component E2 through the connection wiring 36. When data is transmitted, low loss is preferable. When the connection conductor layer is an inner layer conductor layer, the path for data transmission between the first electronic component E1 and the second electronic component E2 includes a via conductor connected to the connection wiring. The via conductor forming the path is a connection via conductor. Even if the path includes a via conductor (connection via conductor), the inner wall surface of the opening for the connection via conductor of the printed wiring board 2 of the embodiment is formed by the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80. The inner wall surface is almost flat. According to the embodiment, when data passes through the via conductor, the printed wiring board 2 of the embodiment can suppress loss. The inner layer conductor layer is sandwiched between adjacent resin insulating layers. When there are multiple connection conductor layers (connection internal conductor layers) formed by the inner layer conductor layers, the number of connection internal conductor layers CI is preferably 3 or more. The number of connection internal conductor layers CI is preferably 7 or less. Furthermore, the number of connection internal conductor layers CI is preferably 5 or less. An example of a printed wiring board 200 having three connection internal conductor layers CI is shown in FIG. 9. As shown in FIG. 9, when the path connecting the first connection pad Pa1 and the first connection electrode D1 has a plurality of via conductors V1, V2, and V3, all of the via conductors V1, V2, and V3 in the path are formed in openings for via conductors similar to the opening 21 shown in FIG. 4. The via conductors V1, V2, and V3 are first connection via conductors and form a first path. The via conductors V1, V2, and V3 are formed in different resin insulating layers. When the path connecting the second connection pad Pa2 and the second connection electrode D2 has a plurality of via conductors V4, V5, and V6, all of the via conductors V4, V5, and V6 in the path are formed in openings for via conductors similar to the opening 21 shown in FIG. 4. The via conductors V4, V5, and V6 are second connection via conductors and form a second path. The via conductors V4, V5, and V6 are formed in different resin insulating layers.

[0095] The connecting internal conductor layer is preferably sandwiched between resin insulating layers containing first inorganic particles 91 and second inorganic particles 92. Both resin insulating layers sandwiching the connecting internal conductor layer have openings for via conductors. The inner wall surface of the opening for the via conductor is formed by the exposed surface 91b of the first inorganic particles 91 and the surface 80a of the resin 80. Each connecting wire forming the connecting internal conductor layer has a width close to the design value. The embodiment can form a high-density group of connecting wires.

[0096] Since the inner wall surface of the opening for each via conductor is formed by the exposed surface 91b of the first inorganic particles 91 and the surface 80a of the resin 80, the shape of the inner wall surface of each via conductor is approximately the same. Even if there are multiple paths including connecting via conductors, the embodiment can reduce the difference in transmission speed between the paths.

[0097] In the printed wiring board 2 of the embodiment, the electrolytic plating layers forming the pads 12, 14, 32, 34 and the electrolytic plating layers forming the via conductors 41, 42, 141, 142 sandwich the seed layers 30a, 130a forming the third portion P3. The pads are an example of a conductor circuit exposed by an opening for the via conductor. The seed layers 30a, 130a are formed by sputtering. Since electrolytic plating and sputtering are different techniques, it is considered that the contraction amount and expansion amount of the two are different when the printed wiring board 2 is subjected to a thermal shock. Therefore, the connection reliability via the via conductors 41, 42, 141, 142 is likely to decrease between the seed layers 30a, 130a and the electrolytic plating layers forming the pads 12, 14, 32, 34. Alternatively, the connection reliability is likely to decrease between the seed layers 30a, 130a and the electrolytic plating layers forming the via conductors 41, 42, 141, 142. The connection reliability is likely to decrease between the electrolytic plating film (electrolytic plating layer 30b, 130b, etc.) and the sputtered seed layer. In order to reduce the influence of the sputtered seed layer 30a, 130a on the connection reliability, it is preferable that the thickness of the sputtered seed layer 30a, 130a on the pads 12, 14, 32, 34 is thin. Therefore, in the embodiment, the thickness T3 of the third portion P3 is made thin. Specifically, in the embodiment, the thickness T3 is made smaller than the thickness T1. As a result, even if the via conductors 41, 42, 141, 142 have the sputtered seed layer 30a, 130a and the electrolytic plating layer 30b, 130b, the embodiment can provide a printed wiring board 2 having high connection reliability.

[0098] The thickness T1 of the first portion P1 of the seed layer 30a, 130a is thicker than the thickness T2 of the second portion P2 and the thickness T3 of the third portion P3. Therefore, the seed layer 30a, 130a on the first surface 20a, 120a is difficult to break. The first portion P1 is difficult to break. The connection wiring 36 is difficult to break. The connection wiring 36 is difficult to include microcracks. Even if the embodiment has multiple connection wirings, the resistance of each connection wiring is approximately equal. The embodiment can transmit high-speed data simultaneously via the multiple connection wirings 36. Large amounts of data are transmitted via the connection wirings 36. A high-quality printed wiring board 2 is provided.

[0099] When a signal or power moves from the pads 12, 14, 32, 34 to the via conductors 41, 42, 141, 142, the signal or power passes through the first layers 31a, 131a of the seed layers 30a, 130a. The resistivity of aluminum contained in the alloy forming the first layers 31a, 131a is greater than the resistivity of copper. Therefore, when the signal or power flows through the first layers 31a, 131a, it is preferable that the distance traveled through the first layers 31a, 131a is short. In the embodiment, the thickness T1a of the first portion P1 of the first layers 31a, 131a is thicker than the thickness T2a of the second portion P2 and the thickness T3a of the third portion P3. Therefore, when the signal or power moves from the pads 12, 14, 32, 34 to the via conductors 41, 42, 141, 142, the distance traveled through the third portion P3 of the first layers 31a, 131a is short. Signals and power are likely to move directly from the third portion P3 of the seed layer 30a, 130a to the electrolytic plating layer 30b, 130b. It is preferable that signals and power move from the third portion P3 to the electrolytic plating layer 30b, 130b forming the via conductors 41, 42, 141, 142 without moving from the third portion P3 to the second portion P2. In the embodiment, the thickness T2 of the second portion P2 is smaller than the thickness T1 of the first portion P1 and the thickness T3 of the third portion P3. Therefore, the embodiment can increase the resistance of the second portion P2. Since the current flows through a portion having a low resistance, signals and power are likely to move directly from the third portion P3 to the electrolytic plating layer 30b, 130b forming the via conductors 41, 42, 141, 142. The seed layer 30a, 130a is unlikely to adversely affect the signal transmission speed and power supply through the via conductors 41, 42, 141, 142. Even if a logic IC is mounted on the printed wiring board 2, the logic IC is unlikely to malfunction.

[0100] In the printed wiring board 2 of the embodiment, the first surface 20a of the resin insulating layer 20 is formed of the resin 80. The inorganic particles 90 are not exposed on the first surface 20a. The first surface 20a does not have any unevenness. The standard deviation of the relative dielectric constant of the portion of the resin insulating layer 20 near the first surface 20a is suppressed from increasing. The relative dielectric constant of the first surface 20a of the resin insulating layer 20 does not vary significantly depending on the location. Even if a plurality of connection wirings 36 are in contact with the first surface 20a of the resin insulating layer 20, the embodiment can reduce the difference in the propagation speed of the electric signal between the connection wirings 36. Therefore, the printed wiring board 2 of the embodiment suppresses noise. Even if a logic IC is mounted on the printed wiring board 2 of the embodiment, data transmitted through each connection wiring 36 reaches the logic IC almost simultaneously. The embodiment can suppress malfunction of the logic IC. Even if the length of each connection wiring 36 is 5 mm or more, the difference in the propagation speed can be reduced. Even if the length of each connection wiring 36 is 10 mm or more and 20 mm or less, the embodiment can suppress malfunction of the logic IC. First surface 120a of resin insulating layer 120 is similar to first surface 20a of resin insulating layer 20. Therefore, the connection wiring in mounting conductor layer 130 has the same effect as connection wiring 36 in connecting conductor layer 30. A high-quality printed wiring board 2 is provided.

[0101] The printed wiring board 2 of the embodiment has an adhesive layer 100 between the connecting conductor layer 30 and the resin insulating layer 120. The adhesive layer 100 bonds the connecting conductor layer 30 and the resin insulating layer 120. Therefore, even if the upper surface and side surface of the connection wiring 36 are smooth, the resin insulating layer 120 is unlikely to peel off from the connection wiring 36. It is preferable not to roughen the upper surface and side surface of the connection wiring 36. The adhesive layer 100 is formed of a substantially smooth smooth film 102 and a protruding portion 104 protruding from the smooth film 102. The adhesive layer 100 has unevenness formed by the protruding portion 104 and the smooth film 102. The adhesive layer 100 has unevenness formed by a plurality of protrusions 106. Therefore, the connecting conductor layer 30 and the resin insulating layer 120 are sufficiently adhered to each other via the adhesive layer 100. A printed wiring board 2 having high quality is provided. For example, even if the length of each side of the printed wiring board 2 is 50 mm or more, the resin insulating layer 120 is unlikely to peel off from the connecting conductor layer 30. Even if the length of each side of the printed wiring board 2 is 100 mm or more, cracks caused by the adhesive layer 100 are unlikely to occur in the resin insulating layer 120. Even if the connecting conductor layer 30 includes a conductor circuit having a width of 5 μm or less, the resin insulating layer 120 is unlikely to peel off from the connecting conductor layer 30. Even if the connecting conductor layer 30 includes a conductor circuit having a width of 3 μm or less, cracks caused by the adhesive layer 100 are unlikely to occur in the resin insulating layer 120. The adhesive layer 150 formed between the mounting conductor layer 130 and the insulating layer 220 has the same effect as the adhesive layer 100. A high-quality printed wiring board 2 is provided.

[0102] When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer on the inner wall surface and the first inorganic particles contain silicon. It is considered that the two are strongly bonded via silicon. The seed layer is difficult to peel off from the inner wall surface.

[0103] When the first layer contains aluminum and the inorganic particles contain oxygen, it is believed that the first layer and the first inorganic particles (inorganic particles containing oxygen, such as glass particles) are strongly bonded. When the first layer contains aluminum and the inorganic particles contain oxygen, the first layer does not need to contain the specific metal. In this case, the first layer is formed of copper, aluminum, and impurities.

[0104] [Example 1 of the embodiment] In another embodiment, the specific metal contained in the alloy forming the first layer is at least one of nickel, zinc, gallium, silicon, and magnesium.

[0105] [Another Example 2 of the embodiment] In another embodiment, the alloy forming the first layer does not contain carbon.

[0106] [Example 3 of the embodiment] In another embodiment, the alloy forming the first layer does not contain oxygen.

[0107] In this specification, the term "plane" is used for the shape of the inner wall surface, the shape of the flat portion 91a, and the shape of the first inorganic particle 91. The meaning of the plane used for these is shown in Fig. 2 and Fig. 4. That is, in Fig. 2 and Fig. 4, the inner wall surface is drawn almost straight. The shape of the inner wall surface in Fig. 2 and Fig. 4 is almost straight. In this specification, the plane includes a substantially straight line shown in the cross section. As shown in the cross section of the first inorganic particle 91 in Fig. 2 and Fig. 4, in the cross section, cutting with a plane includes cutting with a straight line. In this specification, the plane does not mean a perfect plane but includes a substantially flat plane. The substantially flat plane may include small irregularities. [Explanation of symbols]

[0108] 2: Printed wiring board 30: Conductive layer for connection 30a: seed layer 30b: electrolytic plating layer 31a: 1st layer 31b: 2nd layer 36: Connection wiring 37: Space 90: Inorganic particles 91: 1st inorganic particle 91a: Flat part 91b: Exposed surface 92:Second inorganic particle 100: Adhesive layer 102: Smooth film 104:Protrusion 120: Resin insulation layer 121: First opening 122: Second opening 125: Inner wall surface 126: Inner wall surface 130: Conductive layer for mounting 130a: seed layer 130b: electrolytic plating layer 131a: 1st layer 131b: 2nd layer 131: 1st electrode 132:Second electrode 141: First connecting via conductor 142: Second connecting via conductor 150: Adhesive layer 241: First Bump 242: 2nd Bump E1: First electronic component E2: 2nd electronic component P1: 1st part P2 :Second part P3: 3rd part

Claims

1. a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component; a connection conductor layer located under the mounting conductor layer and having a connection wiring that electrically connects the first electrode and the second electrode; a resin insulating layer disposed between the mounting conductor layer and the connecting conductor layer, the resin insulating layer having a plurality of openings including a first opening and a second opening; a first connection via conductor formed in the first opening and electrically connecting the first electrode and the connection wiring; a second connection via conductor formed in the second opening and electrically connecting the second electrode and the connection wiring, the mounting conductor layer, the first connection via conductor, and the second connection via conductor are formed of a seed layer and an electrolytic plating layer on the seed layer, The seed layer has a first portion on the resin insulation layer, a second portion on the inner wall surface of the opening, and a third portion on the connecting conductor layer exposed from the opening, and the thickness of the first portion is thicker than the thicknesses of the second portion and the third portion.

2. 2. The printed wiring board of claim 1, wherein the third portion has a thickness greater than a thickness of the second portion.

3. 2. The printed wiring board of claim 1, wherein the seed layer has a first layer and a second layer formed on the first layer, A thickness of the first portion of the first layer is greater than a thickness of the second portion of the first layer and a thickness of the third portion of the first layer, and a thickness of the third portion of the first layer is greater than a thickness of the second portion of the first layer.

4. 4. The printed wiring board of claim 3, wherein a thickness of the first portion of the second layer is greater than a thickness of the second portion of the second layer and a thickness of the third portion of the second layer, and a thickness of the third portion of the second layer is greater than a thickness of the second portion of the second layer.

5. 3. The printed wiring board of claim 2, wherein a ratio of a thickness of the second portion to a thickness of the first portion (thickness of the second portion / thickness of the first portion) is 0.2 or more and 0.6 or less, and a ratio of a thickness of the third portion to a thickness of the first portion (thickness of the third portion / thickness of the first portion) is 0.5 or more and 0.9 or less.

6. 2. The printed wiring board of claim 1, wherein the resin insulating layer contains resin, first inorganic particles and second inorganic particles, the first inorganic particles have flat portions, and the inner wall surface is formed by the resin and the flat portions.

7. 7. The printed wiring board according to claim 6, wherein a step is formed between the flat portion and a surface of the resin that forms the inner wall surface.

8. A printed wiring board according to claim 6, wherein forming the opening includes forming inorganic particles having protruding portions protruding from the resin forming the inner wall surface of the opening, and the first inorganic particles are formed by removing the protruding portions of the inorganic particles.

9. 7. The printed wiring board of claim 6, wherein forming the opening includes forming inorganic particles having protruding portions from the second inorganic particles, and the inner wall surface of the opening includes an exposed surface of the first inorganic particle formed by removing the protruding portion.

10. 2. The printed wiring board according to claim 1, further comprising an adhesive layer between said connecting conductor layer and said resin insulating layer, said adhesive layer being in contact with said connecting conductor layer and said resin insulating layer being in contact with said adhesive layer.

11. 11. The printed wiring board according to claim 10, wherein the adhesive layer is formed of a substantially flat smooth film and a protruding portion protruding from the flat smooth film.

12. 2. The printed wiring board of claim 1, wherein the number of the first electrodes, the number of the second electrodes, and the number of the connection wirings are multiple, each of the connection wirings is arranged approximately in parallel, the connection wiring having the smallest width among the multiple connection wirings is the smallest connection wiring, the width of the smallest connection wiring is 1 μm or more and 3 μm or less, there is a space between adjacent connection wirings, and the space having the smallest width among the multiple spaces is the smallest space, the width of the smallest space is 1 μm or more and 3 μm or less.

13. 2. The printed wiring board of claim 1, wherein the seed layer has a first layer and a second layer formed on the first layer, the first layer and the second layer are formed by sputtering, the first layer is made of an alloy containing copper, aluminum and a specific metal, and the second layer is formed of copper.

14. 14. The printed wiring board according to claim 13, wherein the specific metal is silicon.

15. 7. The printed wiring board according to claim 6, wherein the first inorganic particles contain oxygen elements.

16. 2. The printed wiring board of claim 1, further comprising a first bump formed on the first electrode and a second bump formed on the second electrode, the first bump and the second bump being formed by solder or plating.

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